W78C438C40FL

W78C438C Data Sheet 8-BIT MICROCONTROLLER Table of Contents1. GENERAL DESCRIPTION.......................................................................................................... 2 2. FEATURES ................................................................................................................................. 2 3. PIN CONFIGURATIONS ............................................................................................................. 3 4. PIN DESCRIPTION ..................................................................................................................... 4 5. FUNCTIONAL DESCRIPTION .................................................................................................... 6 6. 7. 8. 5.1 Dedicated Data and Address Port .................................................................................. 6 5.2 Additional I/O Port ........................................................................................................... 8 5.3 Additional External Interrupt ............................................................................................ 8 5.4 Newly Added Special Function Registers ..................................................................... 10 5.5 Power Reduction Function ............................................................................................ 10 5.6 Programming Difference ............................................................................................... 11 ELECRICAL CHARACTERISTICS ........................................................................................... 12 6.1 Absolute Maximum Ratings .......................................................................................... 12 6.2 D.C. Characteristics ...................................................................................................... 12 6.3 A.C. Characteristics ...................................................................................................... 13 6.3.2 Program Fetch Cycle...................................................................................................... 13 6.3.3 Data Memory Read/Write Cycle ..................................................................................... 14 7.1 Program Fetch Cycle .................................................................................................... 15 7.2 Data Memory Read/Write Cycle ................................................................................... 16 TYPICAL APPLICATION CIRCUITS......................................................................................... 17 Using 128K × 8 bit External EPROM (W27E010) ......................................................... 17 PACKAGE DIMENSIONS ......................................................................................................... 19 9.1 10. Clock Input Waveform .................................................................................................... 13 TIMING WAVEFORMS ............................................................................................................. 15 8.1 9. 6.3.1 100-pin QFP .................................................................................................................. 19 REVISION HISTORY ................................................................................................................ 20 -1- Publication Release Date: March 10, 2010 Revision A7 W78C438C 1. GENERAL DESCRIPTION The W78C438C is a high-performance single-chip CMOS 8-bit microcontroller that is a derivative of the W78C58 microcontroller family. The W78C438C is functionally compatible with the W78C32, except that it provides either a 64 KB program/1 MB data memory address or memory-mapped chip select logic, five general I/O ports, and four external interrupts. In the W78C32, two I/O ports, Port 1 and Port 3, are available for general-purpose use (Port 3 also supports alternative functions), and Port 2 and Port 0 are used as the address bus and data bus, respectively. To enable Port 0 and Port 2 to also be used as general purpose I/O ports, the W78C438C provides two dedicated address ports (AP5 and AP6) that serve as address output for 64 KB of memory and one address/data port (DP4) that serves as ROM code input and external RAM data input/output. Unlike the W78C32, this product does not require an external latch device for multiplexing low byte addresses. The W78C438C also provides four pins (AP7.0−AP7.3) to support either 64 KB program/1 MB data memory space or memory-mapped chip select logic, one parallel I/O port (Port 8) without bit addressing mode, and two additional external interrupts ( INT2 , INT3 ) . The W78C438C is programmed in a manner fully compatible with that used to program the W78C32, except that the external data RAM is accessed by the "MOVX @Ri" instruction. Address paging is performed by loading page addresses into the HB (high byte) register, which is not a standard register in the W78C32, before execution of the "MOVX @Ri" instruction. 2. FEATURES                8-bit CMOS microcontroller Fully static design DC to 40 MHz operation ROM-less operation 256-byte on-chip scratchpad RAM Either 64 KB program/1 MB data memory address space or 4 memory-mapped chip select pins One 8-bit data/address port Two 8-bit and one 4-bit (optional) address ports Five 8-bit bidirectional I/O ports − Four 8-bit bit-addressable I/O ports and one 8-bit parallel I/O port Eight-source, two-level interrupt capability Three 16-bit timer/counters Four external interrupts One full-duplex serial channel Built-in power management − Idle mode − Power-down mode Packages: − Lead Free (RoHS) PQFP 100: W78C438C40FL -2- W78C438C 3. PIN CONFIGURATIONS N C NC NC 1 2 NC NC P1.5 P1.6 P1.7 3 4 RESET P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 INT3 INT2 P 1 . 3 P 1 . 2 P 1 . 1 P 1 . 0 D P 4 . 7 D P 4 . 6 D P 4 . 5 D P 4 . 4 D P 4 . 3 D P 4 . 2 D P 4 . 1 D P 4 V . D 0 D P 0 . 0 P 0 . 1 P 0 . 2 P 0 . 3 N C 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 5 8 4 8 3 8 2 8 1 1 0 0 8 6 10 11 12 13 14 15 W78C438CF 16 100-pin PQFP 17 18 TXD, P3.1 INT0, P3.2 21 22 INT1, P3.3 23 24 WR, P3.6 NC NC NC NC P 1 . 4 7 8 9 19 20 T1, P3.5 T 2 , 5 6 RXD, P3.0 VDD T0, P3.4 T 2 E X , 25 26 27 28 29 30 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 P 3. 7, / R D X T A L 2 X T A L 1 V S S N C A P 7 . 3 , / C S 3 A P 7 . 2 , / C S 2 A P 7 . 1 , / C S 1 A P 7 . 0 , / C S 0 A P 6 . 7 A P 6 . 6 A P 6 . 5 A P 6 . 4 A P 6 . 3 A P 6 . 2 A P 6 . 1 A P 6. 0 P 2 . 0 P 2 . 1 P 2 . 2 -3- 80 NC 79 78 77 76 75 NC NC 74 73 72 71 70 69 P0.6 P0.7 AP5.2 68 67 66 AP5.3 AP5.4 AP5.5 65 64 63 62 61 60 59 58 AP5.6 AP5.7 V DD V SS ALE NC P0.4 P0.5 EA AP5.0 AP5.1 PSEN P2.7 P2.6 57 56 55 54 53 52 P2.5 51 P2.3 P2.4 NC NC NC NC Publication Release Date: March 10, 2010 Revision A7 W78C438C 4. PIN DESCRIPTION P0.0−P0.7 I/O Port 0 These pins function the same as those in the W78C32, except that a multiplexed address/data bus is not provided during accesses to external memory. P1.0−P1.7 I/O Port 1 Functions are the same as in the W78C32. P2.0−P2.7 I/O Port 2 Functions are the same as in the W78C32, except that an upper address bus is not provided during accesses to external memory. P3.0−P3.7 I/O Port 3 Functions are the same as in the W78C32. DP4.0−DP4.7 Data/Address Bus DP4 provides multiplexed low-byte address/data during access to external memory. AP5.0−AP5.7 Address Bus AP5 outputs the address of the external ROM multiplexed with the address of the external data RAM. AP6.0−AP6.7 Address Bus AP6 outputs the address of the external ROM multiplexed with the address of the external data RAM. During the execution of "MOVX @Ri," the output of AP6 comes from the HB register, which is the page register for the high byte address, and its address is 0A1H. AP7.0−AP7.3 Address Bus/Chip Select Pins Set bit 7 of the EPMA (Extended Program Memory Address) register to determine the functions of port 7. When this bit is "0" (default value), AP7 allows the external memory data to be accessed by outputting the address of the external memory from bits of the EPMA register during the execution of "MOVC A, @A+DPTR" or "MOVX dest, src." At all other times, AP7 will output 0H. When this bit is "1," AP7 (CS3−0) are the chip select pins, which support memory-mapped peripheral device select, and only one pin is active low at any one time. These pins are decoded by AP6. For details, see the table below. AP6.7 AP6.6 DESCRIPTION 0 0 AP70: low; others: high 0 1 AP71: low; others: high 1 0 AP72: low; others: high 1 1 AP73: low; others: high -4- W78C438C P8.0−P8.7 I/O Port Functions are the same as those of Port 1 in the W78C31, except that they are mapped by the P8 register and not bit-addressable. The P8 register is not a standard register in the W78C32. Its address is at 0A6H. INT2 , INT3 External Interrupt, Input Functions are similar to those of external INT0 , INT1 in the W78C32, except that the functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the W78C32. Its address is at 0C0H. For details, see the Functional Description below. EA External Address, Input Functions same as W78C32. RST, XTAL1, XTAL2, PSEN , ALE Functions same as W78C32. -5- Publication Release Date: March 10, 2010 Revision A7 W78C438C 5. FUNCTIONAL DESCRIPTION The W78C438C is a functional extension of the W78C58 microcontroller. It contains a 256 × 8 RAM, 64 KB program/1 MB data memory address or memory-mapped chip select logic, two 8-bit address ports, one 8-bit data port, five general I/O ports, four external interrupts, three timers/counters, and one serial port. 5.1 Dedicated Data and Address Port The W78C438C provides four general-purpose I/O ports for W78C32 applications; the address and data bus are separated from Port 0 and Port 2 so that these ports can be used as general-purpose I/O ports. In this product, DP4 is the data bus for external ROM and RAM, AP5 are the low byte address, AP6 are the high byte address, PSEN enables the external ROM to DP4, and P3.6 ( WR ) and P3.7 ( RD ) are the write/read control signals for the external RAM. The external latch for multiplexing the low byte address is no longer needed in this product. The W78C438C uses AP5 and AP6 to support 64 KB external program memory and 64 KB external data memory, just as a standard W78C32 does. The W78C438C provides four pins, AP7.3−AP7.0 (CS3−CS0), to support either 64 KB program/1 MB data memory space or memory-mapped chip select logic. Bit 7 of the EPMA (Extended Program Memory Address) register, which is described in Table 1 below, determines the functions of these pins. When this bit is "0" (the default value), AP7 support external program/data memory addresses up to 64 KB/1 MB for applications which need additional external memory to store large amounts of data. Although there is 1M bytes memory space, instructions stored here can not be run at full range of this area except the first 64 Kbytes. It is owing to the fact that during the instruction fetch cycle, AP7 always output 0s to address lines A19−A16. This limits the program code to store at address 0−0FFFFH (64K). The rest of the area (10000H−FFFFFH) can be treated as ROM data storage which can be read by "MOVC A, @A+DPTR" instruction. When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is executed to access the external RAM data, AP7 output address from bits of the EPMA (Extended Program Memory Address) register. At other times, AP7 always output 0H to ensure the instruction fetch is within the 64K program memory address. Different banks can be selected by modifying the content of the EPMA register before the execution of "MOVC A, @A+DPTR" or "MOVX dest, src." [Example]. Access the external ROM/RAM data from external memory space. CLR A ; Clear Accumulator. MOV DPTR, #0H ; Clear DPTR. MOV 0A2H, #02 ; Initialize EPMA(0A2H). EPMA.7 = 0: extended memory space ; EPMA. = 0010B, the address range: 20000−2FFFFH. MOVC A, @A+DPTR ; Read the external ROM data from location 20000H. MOVX A, @DPTR ; Read the external RAM data from location 20000H. CLR A MOV 0A2H, #03H ; EPMA. = 0011B, the address range: 30000H−3FFFFH. MOVC A, @A+DPTR ; Read the external ROM data from location 30000H. MOVX @DPTR, A ; Write the contents of Accumulator to external RAM data. ; location 30000H. -6- W78C438C (A) EPMA.7 = 0 EPROM ADDR (20-bit) W78C438 P0 AP5 P1 AP7 64K PROGRAM \8 \8 \4 AP6 DATA AREA \8 DP4 P2 OE PSEN P8 INT0 INT1 INT2 RAM ADDR 1MB (20-bit) INT3 RD WR DATA P3 WE OE When bit 7 of the EPMA is "1," AP7 are the output pins that support memory-mapped peripheral chip select logic, which eliminates the need for glue logic. These pins are decoded by AP6. Only one pin is active low at any time. That is, they are active individually with 16K address resolution. For example, CS0 is active low in the address range from 0000H to 3FFFH, CS1 is active low in the address range from 4000H to 7FFFH, and so forth. (B) EPMA.7 = 1 W78C438 64K PROGRAM \8 \8 AP5 P0 EPROM ADDR (16-bit) AP6 P1 DP4 DATA AREA \8 P2 OE PSEN P8 INT0 INT1 INT2 \8 INT3 \6 RD 0000h DATA P3 WR RAM Device Device ADDR (14-bit) AP7.0 AP7.1 AP7.2 AP7.3 3FFFh (16k) Device 4000h 7FFFh 8000h C000h BFFFh FFFFh (16k) (16k) (16k) WE OE -7- Publication Release Date: March 10, 2010 Revision A7 W78C438C The EPMA register is a nonstandard 8-bit SFR at address 0A2H in the standard W78C32. To read/write the EPMA register, one can use the "MOV direct" instruction or "read-modify-write" instructions. Bits of the EPMA register are reserved bits, and their output values are 111B if they are read. The content of EPMA is 70H after a reset. The EPMA register does not support bitaddressable instructions. BIT NAME FUNCTION 7 EPMA7 EPMA7 = 0: 64 KB program/1 MB data memory space mode EPMA7 = 1: memory-mapped chip select mode 6 EPMA6 Reserved 5 EPMA5 Reserved 4 EPMA4 Reserved 3 EPMA3 Value of AP7.3 2 EPMA2 Value of AP7.2 1 EPMA1 Value of AP7.1 0 EPMA0 Value of AP7.0 Table 1. Functional Description of EPMA Register 5.2 Additional I/O Port The W78C438C provides one parallel I/O port, Port 8. Its function is the same as that of Port 1 in the W78C31, except that it is mapped by the P8 register and is not bit-addressable. The P8 register is not a standard register in the standard W78C32. Its address is at 0A6H. To read/write the P8 register, one can use the "MOV direct" instruction or "read-modify-write" instructions. [Example]: MOV 0A6H, A ; Output data via Port 8. MOV A, 0A6H ; Input data via Port 8. 5.3 Additional External Interrupt The W78C438C provides two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupts 0 and 1 in the W78C32. The functions (or the status) of these interrupts are determined by (or shown by) the bits in the XICON (External Interrupt Control) register. For details, see Table 2. The XICON register is bit-addressable but is not a standard register in the standard 80C32. Its address is at 0C0H. To set/clear the bit of the XICON register, one can use the "SETB( CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. The interrupt vector addresses and the priority polling sequence within the same level are shown in Table 3. [Example]. SETB 0C0H ; INT2 is falling-edge triggered. SETB 0C3H ; INT2 is high-priority. SETB 0C2H ; Enable INT2 . CLR 0C4H ; INT3 is low-level triggered. -8- W78C438C BIT ADDR. NAME FUNCTION 7 0C7H PX3 High/low priority level for INT3 is specified when this bit is set/cleared by software. 6 0C6H EX3 Enable/disable interrupt from INT3 when this bit is set/cleared by software. 5 0C5H IE3 If IT3 is "1," IE3 is set/cleared automatically by hardware when interrupt is detected/serviced. 4 0C4H IT3 INT3 is falling-edge/low-level triggered when this bit is set/cleared by software. 3 0C3H PX2 High/low priority level for INT2 is specified when this bit is set/cleared by software. 2 0C2H EX2 Enable/disable interrupt from INT2 when this bit is set/cleared by software. 1 0C1H IE2 If IT2 is "1," IE2 is set/cleared automatically by hardware when interrupt is detected/serviced. 0 0C0H IT2 INT2 is falling-edge/low-level triggered when this bit is set/cleared by software. Table 2. Functions of XICON Register INTERRUPT SOURCE VECTOR ADDRESS PRIORITY SEQUENCE External Interrupt 0 03H 0 (Highest) Timer/Counter 0 0BH 1 External Interrupt 1 13H 2 Timer/Counter 1 1BH 3 Serial Port 23H 4 Timer/Counter 2 2BH 5 External Interrupt 2 33H 6 External Interrupt 3 3BH 7 (Lowest) Table 3. Priority of Interrupts -9- Publication Release Date: March 10, 2010 Revision A7 W78C438C 5.4 Newly Added Special Function Registers The W78C438C uses four newly defined special function registers, which are described in Table 4. To read/write these registers, use the "MOV direct" or "read-modify-write" instructions. REGISTER ADDR. 1 HB A1H 2 EPMA A2H 3 P8 A6H 4 XICON C0H FUNCTION LENGTH R/W TYPE VALUE AFTER RESET 8 R/W 00H 8 R/W 70H 8 R/W 0FFH 8 R/W 00H During the execution of "MOVX @Ri," the content of HB is output to AP6. EPMA.7 determines functions of AP7. EPMA.3−EPMA.0 determine values of AP7 when EPMA.7 is "0." The content of P8 is output to port 8. The bits of XICON determine/show the functions/status of INT2 − INT3 . Bitaddressable. Table 4. Newly Added Special Function Registers of the W78C438C Notes: 1. The instructions used to access these nonstandard registers may cause assembling errors with respect to the 2500 A. D. assembler, but these errors can be ignored by adding directive ".RAMCHK OFF" ahead these instructions. 2. In the newly added SFR of W78C438C, only XICON register is bit-addressable. 5.5 Power Reduction Function The W78C438C supports power reduction just as the W78C32 does. The following table shows the status of the external pins during the idle and power-down modes. FUNCTION ALE, PSEN P0−P3, P8 DP4 AP5, AP6 AP7 Idle 1 1 Port Data Floating Address Note Power Down 0 0 Port Data Floating Address Note Note: AP7 is either 0 or a value decoded by AP6, depending on the value of EPMA.7. - 10 - W78C438C 5.6 Programming Difference The W78C438C is programmed in the same way as the W78C32, except that the external data RAM is accessed by a "MOVX @Ri" instruction. To support address paging, there is an additional 8-bit SFR "HB" (high byte), which is a nonstandard register, at address 0A1H. During execution of the "MOVX @Ri" instruction, the contents of HB are output to AP6. The page address is modified by loading the HB register with a new value before execution of the "MOVX @Ri" instruction. To read/write the HB register, one can use the "MOV direct" instruction or "read-modify-write" instructions. The HB register does not support bit-addressable instructions. [Example]. MOV R1, #0H ; R1 = 0. MOV 0A1H, #0FFH ; HB contents MOVX A, @R1 ; Read the contents of external RAM location FF00H into FFH. ; Accumulator. MOV 0A1H, #12H ; HB contents 12H. MOVX @R1, A ; Copies the contents of Accumulator into external RAM ; location 1200H. - 11 - Publication Release Date: March 10, 2010 Revision A7 W78C438C 6. ELECRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX. UNIT VDD−VSS -0.3 +7.0 V VIN VSS -0.3 VDD +0.3 V Operating Temperature TOPR 0 70 °C Storage Temperature TSTG -55 +150 °C DC Power Supply Input Voltage Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 6.2 D.C. Characteristics (VDD − VSS = 5V ±10%, TA = 25° C, FOSC = 20 MHz, unless otherwise specified.) PARAMETER SYM. Oper. Voltage VDD Oper. Current IDD Idle Current IIDLE Pwdn Current IPWDN Input Leakage Current ILK1 Input Leakage Current ILK2 Input Leakage Current TEST CONDITIONS MIN. TYP. MAX. UNIT 4.5 5 5.5 V * No load - - 20 mA Program idle mode - - 7 mA Program power-down mode - - 50 µA -300 - +10 µA -10 - +300 µA INT2 , INT3 Internal pull-high Notes 1, 2 RESET Internal pull-low Notes 1, 2 ILK3 EA , Port 0, DP4 Note 1 -10 - +10 µA Input Leakage Current ILK4 P1, P2, P3, P8 Note 1 -50 - +10 µA Output Low Voltage VOL1 IOL1 = 2 mA - - 0.45 V Output High Voltage VOH1 IOH1 = -100 µA (Port 1, 2, 3, 8) 2.4 - - V Output Low Voltage VOL2 IOL2 = 4mA Note 3 (ALE, PSEN , P0, DP4) - - 0.45 V Output High Voltage VOH2 IOH2 = -400 µA Note 3 (ALE, PSEN , P0, DP4) 2.4 - - V Output Low Voltage VOL3 IOL2 = 2 mA - - 0.45 V Output High Voltage VOH3 IOH2 = -100 µA (AP5, AP6, AP7) 2.4 - - V Input Voltage VILT VDD = 5V ±10% 0 - 0.8 V Input Voltage VIHT VDD = 5V ±10% 2.4 - Note 4 V (Port 1, 2, 3, 8) (AP5, AP6, AP7) - 12 - W78C438C D.C. Characteristics, continued PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Input Voltage VILC VDD = 5V ±10%, XTAL1 Note 5 0 - 0.8 V Input Voltage VIHC VDD = 5V ±10%, XTAL1 3.5 - Note 4 V Input Voltage VILR VDD = 5V ±10%, RESET Note 5 0 - 0.8 V Input Voltage VIHR VDD = 5V ±10%, RESET Note 5 2.4 - Note 4 V Note 5 Notes: 1. 0 < VIN < VDD, for INT2 , INT3 , RESET, EA , Port 0, DP4, P1, P2, P3 and P8 inputs in leakage. 2. Using an internal pull low/high resistor (approx. 30K). 3. ALE, PSEN , P0 and DP4 in external program or data access mode. 4. The maximum input voltage is VDD +0.2V. 5. XTAL1 is a CMOS input and RESET is a Schmitt trigger input. 6.3 A.C. Characteristics AC specifications are a function of the particular process used to manufacture the product, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. 6.3.1 Clock Input Waveform PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed FOP 0 - 40 MHz 1 Clock Period TCP 25 - - nS 2 Clock High TCH 10 - - nS 3 Clock Low TCL 10 - - nS 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. 6.3.2 Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Valid to PSEN Low TAPL 2 TCP - - nS PSEN Low to Data Valid TPDV - - 2 TCP nS - 13 - Publication Release Date: March 10, 2010 Revision A7 W78C438C 6.3.3 Data Memory Read/Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Valid to RD Low TARL 4 TCP - 4 TCP +∆ nS RD Low to Data Valid TRDV - - 4 TCP nS Data Hold After RD High TRDQ 0 - 2 TCP nS TRS 6 TCP -∆ 6 TCP - nS Address Valid to WR Low TAWL 4 TCP - 4 TCP +∆ nS Data Valid to WR Low TDWL 1 TCP - - nS Data Hold After WR High TWDQ 1 TCP - - nS TWS 6 TCP -∆ 6 TCP - nS RD Pulse Width WR Pulse Width Note: "∆" (due to buffer driving delay and wire loading) is 20 nS. - 14 - W78C438C 7. TIMING WAVEFORMS 7.1 Program Fetch Cycle S1 S3 S2 S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 PSEN TAPL AP6 AP5 address TPDV DP4 address code - 15 - Publication Release Date: March 10, 2010 Revision A7 W78C438C 7.2 Data Memory Read/Write Cycle S4 S5 S6 S7 S8 S9 S10 S11 S12 S1 XTAL1 PSEN AP7 addr out (When bit7 of EPMA is 0.) AP6 DPH or HB SFR out PGM address AP5 DPL or Ri out PGM address TARL TRS RD TRDQ TRDV DP4 addr. WR data addr. TWS TAWL DP4 addr. DATA OUT TDWL TWDQ - 16 - S2 S3 W78C438C 8. TYPICAL APPLICATION CIRCUITS 8.1 Using 128K × 8 bit External EPROM (W27E010) 1 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 N P P C 1 1 . . 4 3 1 NC 2 NC P 1 . 2 P 1 . 1 P 1 . 0 D P 4 . 7 D P 4 . 6 D P 4 . 5 D P 4 . 4 D P 4 . 3 D P 4 . 2 D P 4 . 1 D V P P P D 0 0 4 D . . . 0 1 0 P 0 . 2 P N 0 C . 3 NC NC NC NC P0.4 3 NC 4 NC 5V 10 U 8.2 K 5 P1.5 6 P1.6 7 P1.7 8 RESET 9 P8.0 P0.5 P0.6 P0.7 EA AP5.0 10 P8.1 11 P8.2 12 P8.3 13 P8.4 AP5.1 AP5.2 AP5.3 14 P8.5 15 P8.6 16 P8.7 17 INT3 18 INT2 AP5.4 AP5.5 W78C438C AP5.6 AP5.7 VDD VSS 19 P3.0, RXD 20 VDD 21 P3.1, TXD 22 P3.2, INT0 ALE 61 PSEN 60 P2.7 59 P2.6 58 P2.5 57 23 P3.3, INT1 24 P3.4, T0 25 P3.5, T1 26 P3.6, WR 27 NC 28 NC 29 NC 30 NC P 3 . 7 X , T / A R L D 2 3 3 1 2 X T A L 1 3 3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 GND 22 24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 O0 O1 O2 O3 O4 O5 O6 O7 13 14 15 17 18 19 20 21 W27E010 Vpp Vcc PGM 1 32 31 CE OE Vss 16 P2.4 56 NC 55 NC 54 A P 7 . 3 , / C V S N S S C 3 3 3 3 4 5 6 A P 7 . 2 , / C S 2 A P 7 . 1 , / C S 1 A P 7 . 0 , / C S 0 A P 6 . 7 3 3 3 4 7 8 9 0 NC 53 NC 52 P2.3 51 A P 6 . 6 4 1 A P 6 . 5 A P 6 . 4 4 4 2 3 A P 6 . 3 4 4 A P 6 . 2 4 5 A P 6 . 1 4 6 A P 6 . 0 P 2 . 0 4 4 7 8 P 2 . 1 4 9 P 2 . 2 5 0 R C1 C2 - 17 - Publication Release Date: March 10, 2010 Revision A7 W78C438C Figure A CRYSTAL C1 C2 R 16 MHz 30P 30P − 24 MHz 15P 15P − 33 MHz 10P 10P 6.8K 40 MHz 5P 5P 6.8K Above table shows the reference values for crystal applications. Notes: 1. For C1, C2, R components refer to Figure A. 2. It is recommended that the crystals be replaced with oscillators for applications above 35 MHz. - 18 - W78C438C 9. PACKAGE DIMENSIONS 9.1 100-pin QFP HD D 100 81 Symbol 80 1 A A1 A2 b c D E e HD HE L L1 y θ E HE 51 30 31 e b 50 Dimension in mm Min. Nom. Max. 0.130 0.004 3.30 0.10 0.107 0.112 0.117 2.718 2.845 2.972 0.010 0.012 0.016 0.254 0.305 0.407 0.004 0.006 0.010 0.101 0.152 0.254 0.546 0.551 0.556 13.87 14.00 14.13 0.782 0.787 0.792 19.87 20.00 20.13 0.020 0.026 0.032 0.498 0.65 0.802 0.728 0.740 0.752 18.49 18.80 19.10 0.964 0.976 0.988 24.49 24.80 25.10 0.039 0.047 0.055 0.991 1.194 1.397 0.087 0.095 0.103 2.21 2.413 0.004 0 12 2.616 0.102 0 12 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. A2 A See Detail F Min. Nom. Max. Notes: c Seating Plane Dimension in inches A1 y θ L L 1 Detail F - 19 - Publication Release Date: March 10, 2010 Revision A7 W78C438C 10. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A1 July, 1998 - Initial issued A2 June, 2004 2 Revise part number in the item of packages A3 April 19, 2005 19 Add Important Notice A4 July 27, 2005 2 Add Lead free (RoHS) part number A5 October 3, 2006 A6 December 4, 2006 2 Remove all Leaded package parts A7 March 10, 2010 2 Remove the package parts of “Lead Free (RoHS) PLCC 84 W78C438C40PL” Remove block diagram Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. - 20 -