W78E858 Data Sheet
8-BIT MICROCONTROLLER
Table of Contents1.
GENERAL DESCRIPTION .......................................................................................................... 3
2.
FEATURES.................................................................................................................................. 3
3.
PIN CONFIGURATIONS ............................................................................................................. 4
4.
PIN DESCRIPTION ..................................................................................................................... 5
5.
FUNCTIONAL DESCRIPTION .................................................................................................... 6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
RAM................................................................................................................................. 6
EEPROM ......................................................................................................................... 6
5.2.1
Byte Write Mode................................................................................................................ 6
5.2.2
Page Write Mode .............................................................................................................. 6
5.2.3
Software Protected Data Write .......................................................................................... 7
5.2.4
Command Codes for Software Data Protection Enable/Disable and Software Erase ....... 7
Demo Code: .................................................................................................................... 7
On-chip Flash EPROM .................................................................................................. 10
Timers 0, 1, and 2 ......................................................................................................... 11
Clock ............................................................................................................................. 11
Crystal Oscillator ........................................................................................................... 11
External Clock ............................................................................................................... 11
Power Management ...................................................................................................... 11
5.9.1
Idle Mode ........................................................................................................................ 11
5.9.2
Power-down Mode .......................................................................................................... 11
5.9.3
Wake-up Via External Interrupts INT0 to INT9 ................................................................ 12
Reset ............................................................................................................................. 14
Pulse Width Modulator System ..................................................................................... 15
5.11.1
PWMCON (91H) ........................................................................................................... 15
5.11.2
PWMP (92H) ................................................................................................................. 15
In-system Programming System ................................................................................... 16
5.12.1
SFRAL (C4H) ................................................................................................................ 16
5.12.2
SFRAH (C5H) ............................................................................................................... 16
5.12.3
SFRFD (C6H) ............................................................................................................... 16
5.12.4
SFRCN (C7H) ............................................................................................................... 17
In-system Programming Mode Operating Table ........................................................... 17
5.13.1
5.14
5.15
5.16
CHPCON (BFH) ............................................................................................................ 18
MXPSR (A2H) ............................................................................................................... 18
Interrupt System ............................................................................................................ 18
External Interrupts INT2 to INT9 ................................................................................... 19
5.16.1
IE_1 (E8H) .................................................................................................................... 19
-1-
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.17
5.16.2
IP1 (F8H) ...................................................................................................................... 19
5.16.3
IX1 (E9H) ...................................................................................................................... 20
5.16.4
IRQ1 (C0H) ................................................................................................................... 20
5.16.5
Interrupt Priority and Vector Address ............................................................................ 20
F04KBOOT Mode (Boot From 4K Bytes LDROM)........................................................ 21
5.17.1
5.18
5.19
5.18.1
Lock Bit (Bit0) ................................................................................................................ 22
5.18.2
MOVC Lock (Bit1) ......................................................................................................... 22
5.18.3
Scramble Enable (Bit2) ................................................................................................. 22
5.18.4
Oscillator Gain Select (Bit7) .......................................................................................... 22
Watch Dog Timer .......................................................................................................... 23
5.19.1
5.20
5.21
6.
6.3.1
Clock Input Waveform ..................................................................................................... 27
6.3.2
Program Fetch Cycle ...................................................................................................... 27
6.3.3
Data Read Cycle ............................................................................................................. 28
6.3.4
Data Write Cycle ............................................................................................................. 28
6.3.5
Port Access Cycle ........................................................................................................... 28
6.3.6
Flash Mode Timing.......................................................................................................... 28
Program Fetch Cycle .................................................................................................... 29
Data Read Cycle ........................................................................................................... 29
Data Write Cycle ........................................................................................................... 30
Port Access Cycle ......................................................................................................... 30
Expanded External Program Memory and Crystal........................................................ 31
Expanded External Data Memory and Oscillator .......................................................... 32
PACKAGE DIMENSIONS ......................................................................................................... 33
9.1
9.2
9.3
10.
Absolute Maximum Ratings .......................................................................................... 25
D.C. Characteristics ...................................................................................................... 25
A.C. Characteristics ...................................................................................................... 27
TYPICAL APPLICATION CIRCUITS ......................................................................................... 31
8.1
8.2
9.
Programmable Clock-out .............................................................................................. 24
Reduce EMI Emission ................................................................................................... 24
TIMING WAVEFORMS ............................................................................................................. 29
7.1
7.2
7.3
7.4
8.
WDTC (8FH) ................................................................................................................. 23
ELECTRICAL CHARACTERISTICS ......................................................................................... 25
6.1
6.2
6.3
7.
F04KBOOT Mode ......................................................................................................... 21
Security ......................................................................................................................... 21
40-pin DIP ..................................................................................................................... 33
44-pin PLCC .................................................................................................................. 33
44-pin PQFP.................................................................................................................. 34
VERSION HISTORY ................................................................................................................. 35
-2-
Publication Release Date: April 22, 2008
Revision A8
W78E858
1. GENERAL DESCRIPTION
The W78E858 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E858 is fully compatible with the standard 8052. The
W78E858 contains a 32K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM
which allows the contents of the 32KB main Flash EPROM to be updated by the loader program
located at the 4KB auxiliary Flash EPROM ROM; 768 bytes of on-chip RAM; 128 bytes of EEPROM, 8
extra power down wake-up through INT2 to INT9; 4 channel 8-bit PWM; four 8-bit bi-directional and
bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters where the TIMER2
with programmable clock output and 17-bit watchdog timer are built in this device; a serial port. These
peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming
and verification, the Flash EPROM inside the W78E858 allows the program memory to be
programmed and read electronically. Once the code is confirmed, the user can protect the code for
security.
2. FEATURES
Fully static design 8-bit CMOS micro-controller up to 40 MHz
32K bytes of in-system programmable FLASH EPROM for Application Program (APROM)
4K bytes of auxiliary FLASH EPROM for Loader Program (LDROM)
Low standby current at full supply voltage
256 + 512 bytes of on-chip RAM
128 bytes on-chip EEPROM memory
64K bytes program memory address space and 64K bytes data memory address space
Four 8-bit bi-directional ports
One 4-bit bi-directional port
Extra interrupts INT2 to INT9 at PORT1
Wake-up via external interrupts INT0 INT9
Three 16-bit timer/counters
One full duplex serial port
Fourteen-sources, two-level interrupt capability
Programmable Timer2 clock output via P1.0
17-bits watchdog timer
Four channels 8-bit PWM
Built-in power management
Code protection
Packaged in PDIP 40 / PLCC 44 / PQFP 44
-3-
Publication Release Date: April 22, 2008
Revision A8
W78E858
3. PIN CONFIGURATIONS
P
1
.
4
P
1
.
3
P
1
.
2
T
2
E
X
.
P
1
.
1
6
5
4
3
T
2
.
P
1
.
0
2
A
D
0
.
P
0
.
0
P V
4 D
. D
2
A
D
1
.
P
0
.
1
A
D
3
.
P
0
.
3
A
D
2
.
P
0
.
2
P0.4, AD 4
8
1 44 43 42 41 40
39
38
P1.7
9
37
P0.6, AD 6
RST
10
36
P0.7, AD 7
RXD, P3.0
P4.3
11
35
EA
TXD, P3.1
P1.5
7
P1.6
44-pin
PLCC
12
P0.5, AD 5
34
P4.1
13
33
ALE
INT0, P3.2
14
32
INT1, P3.3
15
31
PSEN
P2.7, A15
T0, P3.4
T1, P3.5
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
P1.0
1
40
VCC
P1.1
2
39
P0.0, AD0
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V P
S 4
S .
0
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P2.6, A14
P2.5, A13
P
2
.
4
,
A
1
2
P
1
.
4
P1.2
3
38
P0.1, AD1
P1.3
4
37
P0.2, AD2
P1.4
5
36
P0.3, AD3
P1.5
1
P1.5
6
35
P0.4, AD4
P1.6
P1.6
7
34
P0.5, AD5
P1.7
8
33
RST
9
40-pin
DIP
T
2
E
X
.
P P P
1 1 1
. . .
3 2 1
T
2
.
P
1
.
0
P
4
.
2
V
D
D
A
D
3
.
P
0
.
3
A
D
2
.
P
0
.
2
A
D
1
.
P
0
.
1
A
D
0
.
P
0
.
0
P0.4, AD4
2
44 43 42 41 40 39 38 37 36 35 34
33
32
P1.7
3
31
P0.6, AD6
P0.6, AD6
RST
4
30
P0.7, AD7
32
P0.7, AD7
RXD, P3.0
5
29
EA
31
EA
P4.3
6
28
P4.1
30
ALE
TXD, P3.1
7
27
ALE
INT0, P3.2
8
26
INT1, P3.3
9
25
PSEN
P2.7, A15
T0, P3.4
10
24
P2.6, A14
T1, P3.5
11
23
P2.5, A13
RXD , P3.0
10
TXD , P3.1
11
INT0, P3.2
12
29
PSEN
INT1, P3.3
13
28
P2.7, A15
T0, P3.4
14
27
P2.6, A14
T1, P3.5
15
26
P2.5, A13
W R , P3.6
16
25
P2.4, A12
R D, P3.7
17
24
P2.3, A11
XTAL2
18
23
P2.2, A10
XTAL1
19
22
P2.1, A9
VSS
20
21
P2.0, A8
44-pin PQFP
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
-4-
P
3
.
7
,
/
R
D
X
T
A
L
2
X
T
A
L
1
V P
S 4
S .
0
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P0.5, AD5
P
2
.
4
,
A
1
2
Publication Release Date: April 22, 2008
Revision A8
W78E858
4. PIN DESCRIPTION
SYMBOL
EA
TYPE
I
DESCRIPTIONS
External Access Enable: EA low forces the processor to execute the
external ROM. The ROM address and data will not be present on the bus if
the EA pin is high and the program counter is within the 32 KB area.
Otherwise they will be present on the bus.
O/H
Program Strobe Enable: PSEN enables the external ROM data in the Port 0
address/data bus. When internal ROM access is performed, no PSEN strobe
signal outputs originate from this pin.
ALE
O/H
Address Latch Enable: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency. An ALE pulse is omitted during external data memory
accesses.
RST
I/L
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device. RST has a Schmitt trigger input stage to provide
additional noise immunity with a slow rising input voltage.
XTAL1
I
Crystal 1: This is the crystal oscillator input. This pin may be driven by an
external clock
XTAL2
O
Crystal 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS
I
Ground: Ground potential.
VDD
I
Power Supply: Supply voltage for operation.
PSEN
P0.0 P0.7
I/O D
Port 0: Function is the same as that of the standard 8052.
P1.0 P1.7
I/O H
Port 1: Function is the same as that of the standard 8052. Port1 also service
the alternative function INT2 INT9. P1.0 provide a timer2 programmable
clock output. Four channel PWM clock output via P1.4 P1.7
P2.0 P2.7
I/O H
Port 2: Port 2 is a bi-directional I/O port with internal pull-ups and emits the
high-order address byte during accesses external memory
P3.0 P3.7
I/O H
Port 3: Function is the same as that of the standard 8052
P4.0 P4.3
I/O H
Port 4: Function is the same as Port1
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
-5-
Publication Release Date: April 22, 2008
Revision A8
W78E858
5. FUNCTIONAL DESCRIPTION
The W78E858 architecture consists of a core controller surrounded by various registers, four 8-bit
general purpose I/O ports, one 4-bits general purpose I/O port, 256 bytes data RAM and 512 bytes
auxiliary RAM, 128 bytes embedded EEPROM memory, three timer/counters, one serial port, 17-bit
watch-dog timer, 8-bit four channels PWM, programmable timer2 clock output, extra external interrupts
INT2 to INT9, power-down wake up via external interrupts INT0 INT9. The CPU supports 111
different op-codes and references both a 64K program address space and a 64 K data storage space.
5.1 RAM
The internal data RAM in W78E858 is 768 bytes. It is divided into two banks: 256 bytes of data RAM
and 512 bytes of auxiliary RAM. These RAM are addressed by different ways.
RAM 00H 7FH can be addressed directly and indirectly as the same as in 80C51. Address
pointers are R0 and R1 of the selected register bank.
RAM 80H FFH can only be addressed indirectly as the same as in 80C51. Address pointers are
R0, R1 of the selected registers bank.
Auxiliary RAM 0000H 01FFH is addressed indirectly as the same way to access external data
memory with the MOVX instruction. Address pointers are R0 and R1 of the selected register bank
and DPTR register. By setting ENAUXRAM flag in CHPCON register bit4 to enable on-chip
auxiliary RAM 512 bytes. When the auxiliary RAM is enabled, the data and address will not appear
on P0 and P2, they will keep their previous status that before the MOVX instruction be executed.
Write the page select 00H or 01H to MXPSR register if R0 and R1 are used as address pointer.
When the address of external data memory locations higher than 01FFH or disable auxiliary RAM
512 bytes micro-controller will be performed with the MOVX instruction in the same way as in the
80C51. The auxiliary RAM 512 bytes default is disabled after chip reset.
5.2 EEPROM
The 128 bytes EEPROM is defined in external data memory space that located in FF80H-FFFFH in
standard 8-bit series. It is accessed the same as auxiliary RAM512 bytes, the ENEEPROM flag in
CHPCON register bit5 is set. Write the page select 02H to MXPSR register, R0 and R1are used as
address pointer. The EEPROM provided byte write, page write mode and software write protection is
used to protect the data lose when power on or noise. They are described as below:
5.2.1
Byte Write Mode
Once a byte write has been started, it will automatically time itself to completion. A BUSY signal
(MXPSR.7) will be used to detect the end of write operation.
5.2.2
Page Write Mode
The EEPROM is divided into 2 pages and each page contains 64 bytes. The page write allows one to
64 bytes of data to be written into the memory during a single internal programming cycle. Page write
is initiated in the same manner as byte write mode. After the first byte is written, it can then be followed
by one to 63 additional bytes. If a second byte is written within a byte-load cycle time (TBLC) of 150us,
the EEPROM will stay at page load cycle. Additional bytes can then be loaded consecutively. The
page load cycle will be terminated and the internal programming cycle will start if no additional byte is
load within 300us from the last byte be loaded. The address bit6 specify the page address. All bytes
that are loaded to the buffer must have the same page address. The data for page write may be
loaded in any order, the sequential loading is not required.
-6-
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.2.3
Software Protected Data Write
The EEPROM provides a JEDED-approved optional software-protected data write. Once this scheme
is enabled, any write operation requires a series of three-byte program commands (with specific data
to a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up or power-down. Once enabled, the software data protection will remain
enabled unless the disable commands are issued. To reset the device to unprotected mode, a six-byte
command sequence is required.
The address mapping of the external memory is given as following, if ENAUXRAM or ENEEPROM
flags in CHPCON is not set, the CPU will access external memory instead of the on-chip memory. The
data, address and read/write strobe signal will appear on relative IO port just like standard 80C52.
5.2.4
Command Codes for Software Data Protection Enable/Disable and Software Erase
BYTE
ENABLE WRITE PROTECT
SEQUENCE
ADDRESS
DATA
0 Write
FFD5H
1 Write
FFAAH
2 Write
3 Write
DISABLE WRITE PROTECT
ADDRESS
DATA
AAH
FFD5H
55H
FFAAH
FFD5H
A0H
-
-
SOFTWARE ERASE
ADDRESS
DATA
AAH
FFD5H
AAH
55H
FFAAH
55H
FFD5H
80H
FFD5H
80H
FFD5H
AAH
FFD5H
AAH
4 Write
-
-
FFAAH
55H
FFAAH
55H
5 Write
-
-
FFD5H
20H
FFD5H
10H
0000H
Auiliary RAM 512 Bytes
01FFH
0200H
External M em ory
FF80H
EEPROM 128 Bytes
FFFFH
(a) Standard 51 Series
Fig. On-Chip External Mem ory Addressed Mapping
5.3 Demo Code:
EEPROM_BASE EQU
FF80H
-7-
Publication Release Date: April 22, 2008
Revision A8
W78E858
org
0000h
jmp
start
org
500h
start:
mov
chpenr,#87h
mov
chpenr,#59h
orl
chpcon,#00100000b
mov
chpenr,#00h
call
enable_protect
mov
dptr,#EEPROM_BASE
mov
r0,#40h
byte/page. Write from FF80h to FFBFh.
mov
r1,#55h
call
write_eeprom_block
call
enable_protect
mov
dptr,#EEPROM_BASE+40h
mov
r0,#40h
address.
mov
r1,#55h
call
write_eeprom_block
mov
mov
mov
call
jc
dptr,#EEPROM_BASE
r0,#80h
r1,#55h
read_eeprom_block
$error
mov
mov
anl
mov
clr
jmp
chpenr,#87h
chpenr,#59h
chpcon,#11011111b
chpenr,#00h
c
$end
mov
mov
anl
mov
setb
chpenr,#87h
chpenr,#59h
chpcon,#11011111b
chpenr,#00h
c
; enable eeprom
; only write up to 64
; write 55 data.
; Call it before writing
; Write from FFC0h to FFFFh
; disable eeprom
$error:
; disable eeprom
$end:
sjmp
$
;----------------------------------------------------------------disable_protect:
mov
dptr,#EEPROM_BASE+55h
mov
a,#aah
movx
@dptr,a
mov
dptr,#EEPROM_BASE+2ah
mov
a,#55h
movx
@dptr,a
mov
dptr,#EEPROM_BASE+55h
mov
a,#80h
movx
@dptr,a
mov
dptr,#EEPROM_BASE+55h
-8-
Publication Release Date: April 22, 2008
Revision A8
W78E858
mov
a,#aah
movx
@dptr,a
mov
dptr,#EEPROM_BASE+2ah
mov
a,#55h
movx
@dptr,a
mov
dptr,#EEPROM_BASE+55h
mov
a,#20h
movx
@dptr,a
call
busy_waiting
ret
;----------------------------------------------------------------eeprom_erase:
mov
dptr,#EEPROM_BASE+55h
mov
a,#aah
movx
@dptr,a
mov
dptr,#EEPROM_BASE+2ah
mov
a,#55h
movx
@dptr,a
mov
dptr,#EEPROM_BASE+55h
mov
a,#80h
movx
@dptr,a
mov
dptr,#EEPROM_BASE+55h
mov
a,#aah
movx
@dptr,a
mov
dptr,#EEPROM_BASE+2ah
;a5~a0
mov
a,#55h
movx
@dptr,a
mov
dptr,#EEPROM_BASE+55h
mov
a,#10h
movx
@dptr,a
call
busy_waiting
ret
;----------------------------------------------------------------enable_protect:
mov
dptr,#EEPROM_BASE+55h
mov
a,#aah
movx
@dptr,a
mov
dptr,#EEPROM_BASE+2ah
mov
a,#55h
movx
@dptr,a
mov
dptr,#EEPROM_BASE+55h
mov
a,#a0h
movx
@dptr,a
ret
;----------------------------------------------------------------busy_waiting:
$wait1:
mov
a,mxpsr
jnb
acc.7,$wait1
$wait0:
mov
a,mxpsr
jb
acc.7,$wait0
ret
;----------------------------------------------------------------
-9-
Publication Release Date: April 22, 2008
Revision A8
W78E858
write_eeprom_block:
;input r0:counter
;input r1:pattern form
;input dptr:eeprom base address
$write_loop:
mov
a,r1
movx
@dptr,a
inc
dpl
djnz
r0,$write_loop
call
busy_waiting
ret
;---------------------------------------------------------------read_eeprom_block:
;input r0:counter
;input r1:pattern form
;input dptr:eeprom base address
;output setb c --> fail
push
b
$read_loop:
movx
a,@dptr
mov
b,a
mov
a,r1
cjne
a,b,$error
inc
dpl
djnz
r0,$read_loop
clr
c
jmp
$end
$error:
setb
c
$end:
pop
b
ret
.end
5.4 On-chip Flash EPROM
The W78E858 includes two banks of FLASH EPROM. One is 32K bytes of main FLASH EPROM for
application program (APROM) and another 4K bytes of FLASH EPROM for loader program (LDROM)
when operating the in-system programming feature. In normal operation, the micro-controller will
execute the code from the 32K bytes of APROM. By setting program registers, user can force CPU to
switch to the programming mode which will execute the code (loader program) from the 4K bytes of
auxiliary LDROM, and this loader program is going to update the contents of the 32K bytes of
APROM. After chip reset, the micro-controller executes the new application program in the APROM.
This in-system programming feature makes the job easy and efficient in which the application needs to
update firmware frequently. In some applications, the in-system programming feature make it possible
that
end-user is able to easily update the system firmware by themselves without opening the
chassis.
- 10 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.5 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit
timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2
can operate as either an external event counter or as an internal timer, depending on the setting of bit
C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator.
The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
5.6 Clock
The W78E858 is designed to use with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used by default. This makes the W78E858 relatively insensitive to
duty cycle variations in the clock.
5.7 Crystal Oscillator
The W78E858 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
5.8 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
5.9 Power Management
5.9.1 Idle Mode
The CPU will enter to idle by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
5.9.2 Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks, including the oscillator are stopped. There are two ways to exit power-down mode,
one is by a chip reset and another is via external interrupts wake up if the related control flags are
enabled.
- 11 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.9.3
Wake-up Via External Interrupts INT0 to INT9
If the external interrupts INT0 to INT9 are enabled, the W78E858 can be awakened from power down
mode with the external interrupts if the EA flag in IE register and related interrupt enable is set before
enter power down mode. To ensure that the oscillator is stable before the controller starts, the internal
clock will remain inactive for some oscillator periods. This is controlled by a on-chip delay counter. The
delay time is software selectable and the reset default value is 1536 periods. By setting the PS2 PS0
bits in AUXR register the delay periods is given as below:
PS2
PS1
PS0
DELAY PERIODS
DELAY TIME (20 MHZ)
0
0
0
192
0.0096 mS
0
0
1
384
0.0192 mS
0
1
0
768
0.0384 mS
0
1
1
1536
0.0768 mS
1
0
0
3072
0.1536 mS
1
0
1
6144
0.372 mS
1
1
0
12288
0.6144 mS
1
1
1
24576
1.2288 mS
Power-Down
RESET-Pin
Internal Clock
...
....
Interrupt IN0~INT9
Oscillator
> 24 x Tosc
delay counter x Tosc
Fig. Power-Down W ake Up Operation
- 12 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
P1.7
X9
P1.6
X8
P1.5
X7
P1.4
X6
P1.3
X5
P1.2
X4
P1.1
X3
P1.0
X2
OR8
IX1
IEN1
IRQ 1
W ake Up
Fig. Port1 External Interrupt Configuration
- 13 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.10 Reset
The external RST signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the RA80xx is used with an external RC network. The reset logic also has
a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
W78E858 Special Function Registers and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
+IP1
0000000
+B
00000000
+IE_1
00000000
+ACC
00000000
+P4
11111111
+PSW
00000000
+T2CON
00000000
+IRQ1
00000000
+IP
000000
+P3
11111111
+IE
01000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
11111111
FF
CHPENR
00000000
F7
IX1
00000000
EF
E7
DF
D7
T2MOD
Xxxxxx0x
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
SFRAL
00000000
TH2
00000000
SFRAH
00000000
CF
SFRFD
00000000
SFRCN
00000000
CHPCON
0xx00000
C7
BF
B7
AF
MXPSR
0xxxxx00
SBUF
xxxxxxxx
PWMCON
PWMP
xxxx0000
00000000
TMOD
TL0
00000000
00000000
SP
DPL
00000111
00000000
A7
9F
DAC0
00000000
TL1
00000000
DPH
00000000
DAC1
00000000
TH0
00000000
DAC2
00000000
TH1
00000000
DAC3
00000000
AUXR
xxxx0110
97
WDTC
000xx000
PCON
00110000
8F
87
Note: the SFRs marked with a plus sign(+) are both byte and bit-addressable.
- 14 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.11 Pulse Width Modulator System
The pulse width modulator system of W78E858 contains four PWM output channels with a common 8bit counter. These channels generate pulses of programmable length and interval. The prescaler and
counter are common to four PWM channels.
5.11.1 PWMCON (91H)
BIT
74
3
2
1
0
NAME
-
Reverse
FUNCTION
PWM3
PWM2
PWM1
PWM0
Enable P1.7 as PWM clock output.
Enable P1.6 as PWM clock output.
Enable P1.5 as PWM clock output.
Enable P1.4 as PWM clock output.
5.11.2 PWMP (92H)
The prescaler is loaded with the complement of the PWMP register during counter overflow. The
repetition frequency is defined by 8-bit prescaler which clocks the counter. The prescaler division
factor = (PWMP + 1). Reading the PWMP gives the current reload value. The actual count of the
prescaler can’t be read.
The PWM counter is enabled with any bit PWMENn (n = 0, 1, 2, 3) of the PWMCON register. Output to
the port pin is separately enabled by setting the PWMENn bits in the PWMCON register. The PWM
function is reset by a chip reset. In idle mode, the PWM will function as configurated in PWMCON. In
power-down state of the PWM will freeze when the internal clock stops. If the chip is awakened with
an external interrupt, the PWM will continue to function its state when power-down was entered.
The repetition frequency is given by:
Fpwm =
Fosc
[255 x (1+PWMP)]
An oscillator frequency of 24 MHz results in a repetition range of 367.65 Hz to 94.12 KHz. The
high/low ratio of PWMn is DACn/(255-DACn) for DACn values except 255. A DACn value 255 results
in a high PWMn output.
- 15 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
Fosc
PW MEN0
PW MEN1
OR
ENDAC
PW MEN2
AND
PW MEN3
INTERNAL
PW MP SFR
8-BIT PRESCALER
8-BIT UP CO UNTER
BUS
DAC0
8-BIT DETECT
O UTPUT
BUFFER
P1.4
DAC1
8-BIT DETECT
O UTPUT
BUFFER
P1.5
DAC2
8-BIT DETECT
OUTPUT
BUFFER
P1.6
DAC3
8-BIT DETECT
O UTPUT
BUFFER
P1.7
Fig. Four Channels 8-Bit PW M Function Block Diagram
5.12 In-system Programming System
The W78E858 provided in-system programming function for new firmware updated. After the related
register and flags are set, user can start timer and force the CPU enter idle mode, then W78E858 will
perform the in-system program mode function specify in SFRCN register, the destination data and
address will come from the related SFR.
The CHPCON is read only by default. Firmware designer must write 87H, 59H sequentially to this
special register CHPENR to enable the CHPCON write attribute, and write other value to disable
CHPCON write attribute. This register protects from writing to the CHPCON register carelessly.
5.12.1 SFRAL (C4H)
The programming low-order byte address of FLASH EPROM in-system programming mode
5.12.2 SFRAH (C5H)
The programming high-order byte address of FLASH EPROM in-system programming mode
5.12.3 SFRFD (C6H)
The programming data for on-chip FLASH EPROM in-system programming mode
- 16 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.12.4 SFRCN (C7H)
BIT
NAME
7
-
FUNCTION
Reserve.
On-chip FLASH EPROM bank select for in-system programming.
6
WFWIN
= 0: 32K bytes FLASH EPROM bank is selected as destination for reprogramming.
= 1: 4K bytes FLASH EPROM bank is selected as destination for reprogramming.
5
OEN
FLASH EPROM output enable.
4
CEN
FLASH EPROM chip enable.
30
CTRL[3:0]
The flash control signals
5.13 In-system Programming Mode Operating Table
MODE
CTRL
WFWIN
OEN
CEN
SFRAL
SFRAH
SFRFD
Erase 32K APROM
0010
0
1
0
X
X
X
Erase 4K LDROM
0010
1
1
0
X
X
X
Program 32K
APROM
0001
0
1
0
Address
Address
Data In
Program 4K LDROM
0001
1
1
0
Address
Address
Data In
Read 32K APROM
0000
0
0
0
Address
Address
Data Out
Read 4K LDROM
0000
1
0
0
Address
Address
Data Out
- 17 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.13.1 CHPCON (BFH)
BIT
7
6
5
4
NAME
FUNCTION
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
SWRESET will enforce microcontroller reset to initial condition just like power on reset.
(F04KMODE) This action will re-boot the microcontroller and start to normal operation.
To read this bit can determine that the F04KBOOT mode is running.
Reserve.
ENEEPROM Enable on-chip 128 bytes EEPROM.
ENAUXRAM Enable on-chip 512 bytes auxiliary RAM.
32
-
1
FBOOTSL
0
FPROGEN
The loader program location selection.
= 0: loader program in 32K memory bank.
= 1: loader program in 4K memory bank.
In system programming enable flag.
= 1: enable. The CPU switches to the programming flash mode after
entering the idle mode and waken up from interrupt. The CPU will
execute the loader program while in on-chip programming mode.
= 0: disable. The on-chip FLASH EPROM read-only. In-system
programmability is inhibit.
5.14 MXPSR (A2H)
BIT
NAME
7
BUSY
6-2
-
1-0
ADDRPNT
FUNCTION
EEPROM BUSY signal.
1: EEPROM is writing.
Reserved.
Address pointer by MOVX instruction
0: read or write lower 256 byte Auxiliary RAM by pointer of R0 or R1 register
1: read or write Higher 256 byte Auxiliary RAM by pointer of R0 or R1
register
2: 128 byte EEPROM by pointer of R0 or R1 register
5.15 Interrupt System
External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous
to do execution of any particular section of code. To tie the asynchronous actives of these functions to
normal program execution, a multiple-source, two-priority-level, nested interrupt system is provided.
The W78E858 acknowledges interrupt requests from fourteen sources as below:
INT0 and INT1
Timer0 and Timer1
UART serial I/O
INT2 to INT9 (at Port1)
- 18 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.16 External Interrupts INT2 to INT9
Port1 lines serve an alternative purpose at eight additional interrupts INT2 to INT9. When enabled,
each of these lines may "wake-up" the device from power-down mode. Using the IX1 register, the
each pin may be initialized to either active HIGH or LOW. IRQ1 is the interrupt request flag register.
Each flag, if the interrupt is enabled will be set on an interrupt request but must be cleared by
software, i.e. via the interrupt software or when the interrupt is disable.
The Port1 interrupts are level sensitive. A Port1 interrupt will be recognized when a level (HIGH or
LOW depending on Interrupt Polarity Register IX1) on P1.x is held active for at least one machine
cycle. The interrupt request is not served until the next machine cycle.
5.16.1 IE_1 (E8H)
BIT
NAME
FUNCTION
7
EX9
Enable external interrupt 9
6
EX8
Enable external interrupt 8
5
EX7
Enable external interrupt 7
4
EX6
Enable external interrupt 6
3
EX5
Enable external interrupt 5
2
EX4
Enable external interrupt 4
1
EX3
Enable external interrupt 3
0
EX2
Enable external interrupt 2
5.16.2 IP1 (F8H)
BIT
NAME
FUNCTION
7
PX9
External interrupt 9 priority level
6
PX8
External interrupt 8 priority level
5
PX7
External interrupt 7 priority level
4
PX6
External interrupt 6 priority level
3
PX5
External interrupt 5 priority level
2
PX4
External interrupt 4 priority level
1
PX3
External interrupt 3 priority level
0
PX2
External interrupt 2 priority level
- 19 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.16.3 IX1 (E9H)
BIT
NAME
FUNCTION
7
IL9
External interrupt 9 polarity level
6
IL8
External interrupt 8 polarity level
5
IL7
External interrupt 7 polarity level
4
IL6
External interrupt 6 polarity level
3
IL5
External interrupt 5 polarity level
2
IL4
External interrupt 4 polarity level
1
IL3
External interrupt 3 polarity level
0
IL2
External interrupt 2 polarity level
5.16.4 IRQ1 (C0H)
BIT
NAME
FUNCTION
7
IQ9
External interrupt 9 request flag
6
IQ8
External interrupt 8 request flag
5
IQ7
External interrupt 7 request flag
4
IQ6
External interrupt 6 request flag
3
IQ5
External interrupt 5 request flag
2
IQ4
External interrupt 4 request flag
1
IQ3
External interrupt 3 request flag
0
IQ2
External interrupt 2 request flag
5.16.5 Interrupt Priority and Vector Address
PRIORITY
INTERRUPT
VECTOR
SOURCE
PRIORITY
INTERRUPT
VECTOR
SOURCE
1
INT0
0003H
External 0
8
TF1
001BH
Timer 1
2
INT5
0053H
External 5
9
SINT
0023H
UART
3
TF0
000BH
Timer 0
10
TF2
002BH
Timer 2
4
INT6
005BH
External 6
11
INT3
0043H
External 3
5
INT1
0013H
External 1
12
INT8
006BH
External 8
6
INT2
003BH
External 2
13
INT4
004BH
External 4
7
INT7
0063H
External 7
14
INT9
0073H
External 9
- 20 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.17 F04KBOOT Mode (Boot From 4K Bytes LDROM)
The W78E858 boots from APROM program (32K bytes bank) by default after chip reset. On some
occasions, user can force the W78E858 to boot from the LDROM program (4K bank) after chip reset.
The setting for this special mode is as follow.
5.17.1 F04KBOOT Mode
RST
P4.3
P2.7
P2.6
MODE
H
X
L
L
FO4KBOOT
H
L
X
X
FO4KBOOT
Note: In application system design, user must take care the P2, P3, ALE, EA and PSEN pin status at reset to avoid
W78E858 entering the programming mode or F04KBOOT mode in normal operation.
Enter 4K Reboot M ode Tim ing
P2.6
X
P2.7
X
Ts=1us
RESET
Th > 24 clocks
5.18 Security
During the on-chip FLASH EPROM programming mode, the FLASH EPROM can be programmed and
verified repeatedly. Until the code inside the FLASH EPROM is confirmed OK, the code can be
protected. The protection of FLASH EPROM and those operations on it are described below:
The W78E858 has several special setting registers in FLASH EPROM block. Those bits of the security
register can’t be changed once they have been programmed from high to low. They can only be reset
through erase-all operation. The security register is located at the FFFFH on the same bank with 4K
LDROM i.e., P3.6 must set high at writer mode.
- 21 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
0000H
On-Chip
4KB LDROM
0FFEH
Reversed
FFFFH
Security Register
5.18.1 Lock Bit (Bit0)
This bit is used to protect the customer's program code in the W78E858. It may be set after the
programmer finishes the programming and verifies sequence. Once these bits are set to logic 0, both
the FLASH EPROM data and all data in FLASH EPROM block can’t be accessed again.
5.18.2 MOVC Lock (Bit1)
When this bit is program to "0", the MOVC instruction will be disable when the program counter more
than 7FFFh or EA pin is forced low.
5.18.3 Scramble Enable (Bit2)
This bit is used to protect the customer's program code in the W78E858. If this bit is set to logic 0, the
dump ROM code are scrambled by a scramble circuit and the dump ROM code will become a random
ROM code.
5.18.4 Oscillator Gain Select (Bit7)
If this bit is set to logic 0 (for 24 MHz), the EMI effect will be reduce. If this bit is set to logic 1 (for 40
MHz), the W78E858 could to use 40 MHz crystal, but the EMI effect is major. So we provide the option
bit which could be chose by customer.
- 22 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.19 Watch Dog Timer
For more system reliability, W78E858 provides a programmable watch-dog time-out reset function.
From programming prescaler select, user can choose a variable prescaler from divided by 2 to divided
by 256 to get a suitable time-out period. The time-out period is given by:
Ttim e-out
=
1
Fosc
x 2
14
x PRESCALER x 1000 x 12 (mS)
(Note: Fosc unit = Hz)
5.19.1 WDTC (8FH)
BIT
NAME
FUNCTION
7
ENW
6
CLRW
Clear watch-dog timer and prescaler if set. This flag will be cleared automatically.
5
WIDL
If this bit is set, watch-dog is enabled under idle mode. If cleared, watch-dog
is disable under idle mode. Default is cleared.
43
-
2
PS2
Watch-dog prescaler timer select.
1
PS1
Watch-dog prescaler timer select.
0
PS0
Watch-dog prescaler timer select.
Enable watch-dog timer if set.
Reversed.
PS2
PS1
PS0
PRESCALER SELCET
WATCH-DOG TIME-OUT PERIOD (FOSC = 20 MHz)
0
0
0
2
19.66 mS
0
1
0
4
39.32 mS
0
0
1
8
78.64 mS
0
1
1
16
157.28 mS
1
0
0
32
314.57 mS
1
0
1
64
629.14 mS
1
1
0
128
1.25 mS
1
1
1
256
2.52 mS
- 23 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
5.20 Programmable Clock-out
A 50% duty cycle clock can be programmed to come out on P1.0. To configure the timer/counter2 as a
clock generator, bit C/T2 in T2CON register must be cleared and bit T2OE in T2MOD register must be
set. Bit TR2 (T2CON.2) also must be set to start timer. The clock-out frequency depends on the
oscillator frequency and reload value of Timer2 capture register (RCAP2H, RCAP2L) as shown in this
equation:
oscillatotr frequency
4 (65536 ( RCAP 2 H , RCAP 2 L))
In the clock-out mode, timer2 roll-overs will not generate an interrupt. This is similar to when it is used
as a baud-rate generator. It is possible to use Timer2 as a baud-rate generator and a clock and a
clock generator simultaneously.
5.21 Reduce EMI Emission
The transition of ALE will cause noise, so it cab be turned off to reduce the EMI emission if it is
useless. Turn off the ALE signal transition only need too set the ALEOFF flag in the AUXR register
When ALE is turned off, it will be reactived when program access external ROM or RAM data or jump
to execute external ROM code. After access completely or program returns to internal ROM code, ALE
signal will turn off again.
W IDL
IDLE
Fosc
EXTERNAL RESET
1/12
PRESCALER
ENW
14-BIT TIMER
SYSTEM RESET
CLRW
Fig. 17-BIT W atch-Dog Tim er Function Block Diagram
- 24 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
6. ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VDD VSS
-0.3
+6.0
V
Input Voltage
Vin
VSS -0.3
VDD +0.3
V
Operating Temperature
Ta
0
70
C
Storage Temperature
Tst
-55
+150
C
DC Power Supply
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
6.2 D.C. Characteristics
(VDD VSS = 5V 10%, TA = 25 C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
SPECIFICATION
MIN.
MAX.
UNIT
TEST CONDITIONS
Operating Voltage
VDD
4.5
5.5
V
Operating Current
IDD
-
20
mA
IIDLE
-
6
mA
IPWDN
-
50
A
IIN1
-50
+10
A
IIN2
-10
+300
A
ILK
-10
+10
A
ITL[*4]
-500
-
A
VIL1
0
0.8
V
VDD = 4.5V
VIL2
0
0.8
V
VDD = 4.5V
VIL3
0
0.8
V
VDD = 4.5V
Idle Current
Power Down Current
Input Current
P1, P2, P3, P4
Input Current
RST
Input Leakage Current
P0, EA
Logic 1 to 0 Transition Current
P1, P2, P3, P4
RST = 1, P0 = VDD
No load
VDD = 5.5V
Idle mode
VDD = 5.5V
Power-down mode
VDD = 5.5V
VDD = 5.5V
VIN = 0V or VDD
VDD = 5.5V
0 < VIN < VDD
VDD = 5.5V
0 < VIN < VDD
VDD = 5.5V
VIN = 2.0V
Input Low Voltage
P0, P1, P2, P3, P4, EA
Input Low Voltage
RST
Input Low Voltage
XTAL1[*4]
- 25 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
D.C. Characteristics, continued
PARAMETER
SYM.
SPECIFICATION
MIN.
MAX.
UNIT
Input High Voltage
VIH1
2.4
VDD
+0.2
V
VDD = 5.5V
VIH2
3.5
VDD
+0.2
V
VDD = 5.5V
VIH3
3.5
VDD
+0.2
V
VDD = 5.5V
VOL1
-
0.45
V
VOL2
-
0.45
V
ISK1
4
12
mA
I SK2
10
20
mA
VOH1
2.4
-
V
VOH2
2.4
-
V
ISR1
-120
-250
A
ISR2
-8
-20
mA
P0, P1, P2, P3, P4, EA
Input High Voltage
RST
Input High Voltage
XTAL1[*4]
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
P0, ALE, PSEN
[*3]
Sink Current
P1, P3, P4
Sink Current
P0, P2, ALE, PSEN
Output High Voltage
P1, P2, P3, P4
Output High Voltage
P0, ALE, PSEN [*3]
Source Current
P1, P2, P3, P4
Source Current
P0, P2, ALE, PSEN
TEST CONDITIONS
VDD = 4.5V
IOL = +2 mA
VDD = 4.5V
IOL = +4 mA
VDD = 4.5V
VIN = 0.45V
VDD = 4.5V
VIN = 0.45V
VDD = 4.5V
IOH = -100 A
VDD = 4.5V
IOH = -400 A
VDD = 4.5V
VIN = 2.4V (latch)
VDD = 4.5V
VIN = 2.4V
Notes:
*1. RST pin is a Schmitt trigger input.
*3. P0, ALE and PSEN are tested in the external access mode.
*4. XTAL1 is a CMOS input.
*5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN approximates to 2V.
- 26 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
6.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a 20 nS variation. The numbers below represent the performance expected
from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
6.3.1
Clock Input Waveform
XTAL1
T CH
T CL
F OP,
PARAMETER
SYMBOL
TCP
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
FOP
0
-
40
MHz
1
Clock Period
TCP
25
-
-
nS
2
Clock High
TCH
10
-
-
nS
3
Clock Low
TCL
10
-
-
nS
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
6.3.2
Program Fetch Cycle
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
PARAMETER
SYMBOL
TAAS
1 TCP-
-
-
nS
4
Address Hold from ALE Low
TAAH
1 TCP-
-
-
nS
1, 4
ALE Low to PSEN Low
TAPL
1 TCP-
-
-
nS
4
PSEN Low to Data Valid
TPDA
-
-
2 TCP
nS
2
Data Hold after PSEN High
TPDH
0
-
1 TCP
nS
3
Data Float after PSEN High
TPDZ
0
-
1 TCP
nS
ALE Pulse Width
TALW
2 TCP-
2 TCP
-
nS
4
PSEN Pulse Width
TPSW
3 TCP-
3 TCP
-
nS
4
Notes:
1. P0.0 P0.7, P2.0 P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "" (due to buffer driving delay and wire loading) is 20 nS.
- 27 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
6.3.3
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to RD Low
Tdar
3 TCP-
-
3 TCP+
nS
1, 2
RD Low to Data Valid
Tdda
-
-
4 TCP
nS
1
Data Hold from RD High
Tddh
0
-
2 TCP
nS
Data Float from RD High
Tddz
0
-
2 TCP
nS
RD Pulse Width
Tdrd
6 TCP-
6 TCP
-
nS
2
Notes:
1. Data memory access time is 8 TCP.
2. "" (due to buffer driving delay and wire loading) is 20 nS.
6.3.4
Data Write Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
ALE Low to WR Low
TDAW
3 TCP-
-
3 TCP+
nS
Data Valid to WR Low
TDAD
1 TCP-
-
-
nS
Data Hold from WR High
TDWD
1 TCP-
-
-
nS
WR Pulse Width
TDWR
6 TCP-
6 TCP
-
nS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Port Input Setup to ALE Low
TPDS
1 TCP
-
-
nS
Port Input Hold from ALE Low
TPDH
0
-
-
nS
Port Output to ALE
TPDA
1 TCP
-
-
nS
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
6.3.5
Port Access Cycle
PARAMETER
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
6.3.6
Flash Mode Timing
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
TRV
9
10
11
S
-
Enter Flash Mode Reset Low
TEFRL
9
10
11
S
-
Program Pulse High
TPPH
18
20
22
S
-
Program Pulse Low
TPPL
40
50
60
S
-
Erase Pulse Low
TEPL
25
30
50
mS
-
Read Pulse Low
TRPL
1.35
1.5
1.65
S
-
Address PreFix
TAPF
45
50
55
nS
-
Data Remain
TDR
81
90
99
nS
-
Reset Valid
- 28 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
7. TIMING WAVEFORMS
7.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
T ALW
ALE
T APL
PSEN
T PSW
T AAS
PORT 2
T PDA
T AAH
T PDH,
T PDZ
PORT 0
A0-A7
Code
A0-A7
Data
A0-A7
Code
Data
A0-A7
7.2 Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
T DAR
T DDA
T DDH, T DDZ
RD
T DRD
- 29 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
7.3
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
PORT 0
A8-A15
A0-A7
DATA OUT
T DW D
TDAD
WR
T DW R
T DAW
7.4 Port Access Cycle
S5
S6
S1
XTAL1
ALE
T PDS
T PDA
T PDH
DATA OUT
PORT
INPUT
SAMPLE
- 30 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
8. TYPICAL APPLICATION CIRCUITS
8.1 Expanded External Program Memory and Crystal
V DD
V DD
35
21
10 u
R 22
CRYSTAL
8.2 K
10
C1
EA
XTAL1
XTAL2
RST
C2
INT0
14
15
16
17
INT1
T0
T1
2
3
4
5
6
7
8
9
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
43
42
41
40
39
38
37
36
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE
TXD
RXD
19
18
32
33
13
11
AD0 3
AD1 4
AD2 7
AD3 8
AD4 13
AD5 14
AD6 17
AD7 18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A0 10
A1 9
A2 8
A3 7
A4 6
A5 5
A6 4
A7 3
A8 25
A9 24
A10 21
A11 23
A12 2
A13 26
A14 27
A15 1
2 A0
5 A1
6 A2
9 A3
12 A4
15 A5
16 A6
19 A7
GND 1 OC
11 G
74LS373
GND 20
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
CE
OE
2764
W78E858
Figure A
CRYSTAL
C1
C2
R
6 MHz
68P 100P
68P 100P
6.8K
16 MHz
20P 100P
20P 100P
6.8K
24 MHz
10P 68P
10P 68P
6.8K
32 MHz
5P 20P
5P 20P
6.8K
40 MHz
5P
5P
3.3K
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A
2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
- 31 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
8.2
Expanded External Data Memory and Oscillator
VDD
VDD
35
EA
21
XTAL1
20
XTAL2
10 u OSCILLATOR
8.2 K
10 RST
14
15
16
17
2
3
4
5
6
7
8
9
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
43
42
41
40
39
38
37
36
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
A13
A14
RD
19
18
32
33
13
11
WR
PSEN
ALE
TXD
RXD
AD0 3
AD1 4
AD2 7
AD3 8
AD4 13
AD5 14
AD6 17
AD7 18
GND 1
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
OC
11 G
74LS373
A0
A1
A2
A3
A4
A5
A6
A7
A0 10
A1 9
A2 8
A3 7
A4 6
A5 5
A6 4
A7 3
A8 25
A9 24
A10 21
A11 23
A12 2
A13 26
A14 1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
GND 20
22
27
CE
OE
D0 11
D1 12
D2 13
D3 15
D4 16
D5 17
D6 18
D7 19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
WR
20256
W78E858
Figure B
- 32 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
9. PACKAGE DIMENSIONS
9.1 40-pin DIP
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
E1
0.155
0.160
3.81
3.937
4.064
0.016
0.018
0.022
0.406
0.457
0.559
0.048
0.050
0.054
1.219
1.27
1.372
0.008
0.010
0.014
0.203
0.254
0.356
2.055
2.070
52.20
52.58
15.494
0.590
0.600
0.610 14.986
15.24
0.540
0.545
0.550
13.72
13.84
13.97
0.090
0.100
0.110
2.286
2.54
2.794
0.120
0.130
0.140
3.048
3.302
3.556
15
0
0.670
16.00
16.51
17.01
0
eA
S
20
0.254
0.150
a
1
5.334
0.210
0.010
0.630
0.650
15
0.090
2.286
Notes:
E
S
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
. parting line.
are determined at the mold
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
c
A A2
A1
Base Plane
Seating Plane
L
B
e1
eA
a
B1
9.2 44-pin PLCC
HD
D
6
1
44
40
Symbol
39
7
E
17
HE
GE
29
18
28
c
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
Dimension in inch
Min. Nom. Max.
Dimension in mm
Min. Nom. Max.
0.185
4.699
0.508
0.020
0.145
0.150
0.155
3.683
3.81
3.937
0.026
0.028
0.032
0.66
0.711
0.813
0.016
0.018
0.022
0.406
0.457
0.559
0.008
0.010
0.014
0.203
0.254
0.356
0.648
0.653
0.658
16.46
16.59
16.71
0.648
0.653
0.658
16.46
16.59
16.71
0.050
BSC
1.27
BSC
0.590
0.610
0.630
14.99
15.49
16.00
0.590
0.610
0.630
14.99
15.49
16.00
0.680
0.690
0.700
17.27
17.53
17.78
0.680
0.690
0.700
17.27
17.53
17.78
0.090
0.100
0.110
2.296
2.54
2.794
0.004
0.10
L
Notes:
A2 A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
e
b
b1
Seating Plane
A1
y
GD
- 33 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
9.3 44-pin PQFP
HD
D
Symbol
34
44
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
33
1
E HE
11
12
e
b
22
Dimension in inch
Dimension in mm
Min. Nom. Max.
Min. Nom.
Max.
---
---
---
---
0.002
0.01
0.02
0.05
0.25
0.5
0.075
0.081
0.087
1.90
2.05
2.20
0.01
0.014
0.018
0.25
0.35
0.45
0.004
0.006
0.010
0.101
0.152
0.254
0.390
0.394
0.398
9.9
10.00
10.1
0.390
0.394
0.398
9.9
10.00
10.1
---
---
0.025
0.031
0.036
0.635
0.80
0.952
0.510
0.520
0.530
12.95
13.2
13.45
13.45
0.510
0.520
0.530
12.95
13.2
0.025
0.031
0.037
0.65
0.8
0.95
0.051
0.063
0.075
1.295
1.6
1.905
0.08
0.003
0
7
0
7
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
c
A2 A
Seating Plane
See Detail F
A1
y
L
L1
Detail F
- 34 -
Publication Release Date: April 22, 2008
Revision A8
W78E858
10. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A
Oct. 2001
-
B
Jul. 2002
15
Modify timer 2 interrupt vector address
C
Nov. 2002
5
EEPROM address of command code
D
May. 2004
6
Remove erase acquisition flow
6
Add a demo code
Initial Issued
A5
April 20, 2005
33
Add Important Notice
A6
May 3, 2006
7
Revise “03H to MXPSR” to ”02H to MXPSR”
A7
November 6, 2006
A8
April 22, 2008
Remove block diagram
14
Update P3 reset state
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
- 35 -
Publication Release Date: April 22, 2008
Revision A8
工商网监
湘ICP备2023018690号
