XL210-512-TQ128 Datasheet
2018/09/05
XMOS © 2018, All Rights Reserved
Document Number: X007786,
XL210-512-TQ128 Datasheet
1
Table of Contents
1
xCORE Multicore Microcontrollers . . . .
2
XL210-512-TQ128 Features . . . . . . .
3
Pin Configuration . . . . . . . . . . . . .
4
Signal Description . . . . . . . . . . . . .
5
Example Application Diagram . . . . . .
6
Product Overview . . . . . . . . . . . . .
7
PLL . . . . . . . . . . . . . . . . . . . . . .
8
Boot Procedure . . . . . . . . . . . . . . .
9
Memory . . . . . . . . . . . . . . . . . . .
10 JTAG . . . . . . . . . . . . . . . . . . . . .
11 Board Integration . . . . . . . . . . . . .
12 Electrical Characteristics . . . . . . . . .
13 Package Information . . . . . . . . . . .
14 Ordering Information . . . . . . . . . . .
Appendices . . . . . . . . . . . . . . . . . . . .
A
Configuration of the XL210-512-TQ128
B
Processor Status Configuration . . . . .
C
Tile Configuration . . . . . . . . . . . . .
D
Node Configuration . . . . . . . . . . . .
E
JTAG, xSCOPE and Debugging . . . . . .
F
Schematics Design Check List . . . . . .
G
PCB Layout Design Check List . . . . . .
H
Associated Design Documentation . . .
I
Related Documentation . . . . . . . . . .
J
Revision History . . . . . . . . . . . . . .
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2
4
5
6
10
11
14
15
18
19
20
23
27
28
29
29
31
42
50
58
60
62
63
63
64
TO OUR VALUED CUSTOMERS
It is our intention to provide you with accurate and comprehensive documentation for the hardware and
software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/.
XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with
no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes
no representation that the information, or any particular implementation thereof, is or will be free from any
claims of infringement and again, shall have no liability in relation to any such claims.
XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries,
and may not be used without written permission. Company and product names mentioned in this document
are the trademarks or registered trademarks of their respective owners.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
1
2
xCORE Multicore Microcontrollers
The xCORE-200 Series is a comprehensive range of 32-bit multicore microcontrollers that brings the low latency and timing determinism of the xCORE architecture to mainstream embedded applications. Unlike conventional microcontrollers,
xCORE multicore microcontrollers execute multiple real-time tasks simultaneously
and communicate between tasks using a high speed network. Because xCORE
multicore microcontrollers are completely deterministic, you can write software to
implement functions that traditionally require dedicated hardware.
X0Dxx
I/O pins
xTIME
scheduler
Hardware response ports
PLL
JTAG
xCORE logical core
xCORE logical core
Figure 1:
XL210-512TQ128 block
diagram
xCORE logical core
xCORE logical core
SRAM
OTP
X1Dxx
I/O pins
Hardware response ports
xCORE logical core
xCONNECT Switch
xCORE logical core
xTIME
scheduler
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
OTP
SRAM
Key features of the XL210-512-TQ128 include:
· Tiles: Devices consist of one or more xCORE tiles. Each tile contains between
five and eight 32-bit xCOREs with highly integrated I/O and on-chip memory.
· Logical cores Each logical core can execute tasks such as computational code,
DSP code, control software (including logic decisions and executing a state
machine) or software that handles I/O. Section 6.1
· xTIME scheduler The xTIME scheduler performs functions similar to an RTOS,
in hardware. It services and synchronizes events in a core, so there is no
requirement for interrupt handler routines. The xTIME scheduler triggers cores
on events generated by hardware resources such as the I/O pins, communication
channels and timers. Once triggered, a core runs independently and concurrently
to other cores, until it pauses to wait for more events. Section 6.2
· Channels and channel ends Tasks running on logical cores communicate using
channels formed between two channel ends. Data can be passed synchronously
or asynchronously between the channel ends assigned to the communicating
tasks. Section 6.5
· xCONNECT Switch and Links Between tiles, channel communications are implemented over a high performance network of xCONNECT Links and routed
through a hardware xCONNECT Switch. Section 6.6
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
3
· Ports The I/O pins are connected to the processing cores by Hardware Response
ports. The port logic can drive its pins high and low, or it can sample the value
on its pins optionally waiting for a particular condition. Section 6.3
· Clock blocks xCORE devices include a set of programmable clock blocks that
can be used to govern the rate at which ports execute. Section 6.4
· Memory Each xCORE Tile integrates a bank of SRAM for instructions and data,
and a block of one-time programmable (OTP) memory that can be configured for
system wide security features. Section 9
· PLL The PLL is used to create a high-speed processor clock given a low speed
external oscillator. Section 7
· JTAG The JTAG module can be used for loading programs, boundary scan testing,
in-circuit source-level debugging and programming the OTP memory. Section 10
1.1
Software
Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS
provides tested and proven software libraries, which allow you to quickly add
interface and processor functionality such as USB, Ethernet, PWM, graphics driver,
and audio EQ to your applications.
1.2
xTIMEcomposer Studio
The xTIMEcomposer Studio development environment provides all the tools you
need to write and debug your programs, profile your application, and write images
into flash memory or OTP memory on the device. Because xCORE devices operate deterministically, they can be simulated like hardware within xTIMEcomposer:
uniquely in the embedded world, xTIMEcomposer Studio therefore includes a static
timing analyzer, cycle-accurate simulator, and high-speed in-circuit instrumentation.
xTIMEcomposer can be driven from either a graphical development environment,
or the command line. The tools are supported on Windows, Linux and MacOS X
and available at no cost from xmos.com/downloads. Information on using the
tools is provided in the xTIMEcomposer User Guide, X3766.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
2
4
XL210-512-TQ128 Features
· Multicore Microcontroller with Advanced Multi-Core RISC Architecture
• 10 real-time logical cores on 2 xCORE tiles
• Cores share up to 1000 MIPS
— Up to 2000 MIPS in dual issue mode
• Each logical core has:
— Guaranteed throughput of between 1/5 and 1/5 of tile MIPS
— 16x32bit dedicated registers
• 167 high-density 16/32-bit instructions
— All have single clock-cycle execution (except for divide)
— 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic
functions
· Programmable I/O
• 88 general-purpose I/O pins, configurable as input or output
— Up to 32 x 1bit port, 12 x 4bit port, 8 x 8bit port, 4 x 16bit port
— 4 xCONNECT links
• Port sampling rates of up to 60 MHz with respect to an external clock
• 64 channel endss (32 per tile) for communication with other cores, on or off-chip
· Memory
• 512KB internal single-cycle SRAM (max 256KB per tile) for code and data storage
• 16KB internal OTP (max 8KB per tile) for application boot code
· Hardware resources
• 12 clock blocks (6 per tile)
• 20 timers (10 per tile)
• 8 locks (4 per tile)
· JTAG Module for On-Chip Debug
· Security Features
• Programming lock disables debug and prevents read-back of memory contents
• AES bootloader ensures secrecy of IP held on external flash memory
· Ambient Temperature Range
• Commercial qualification: 0 °C to 70 °C
• Industrial qualification: -40 °C to 85 °C
· Speed Grade
• 20: 1000 MIPS
· Power Consumption
• 570 mA (typical)
· 128-pin TQFP package 0.4 mm pitch
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
TDO
4F
97
X0D29
4F
98
X0D30
VDD
X0D31
4F
VDD
101
99
PLL_AVDD
102
100
PLL_AGND
103
X1D40
OTP_VCC
8D
105
104
8D
106
X1D41
X1D43
8D
107
X1D42
VDDIOT
8D
109
108
X1D26
VDDIOT
4E
111
110
4E
112
X1D27
4F
113
X1D28
4F
114
X1D29
4F
115
X1D30
4F
116
X1D31
4E
117
X1D32
VDD
X1D33
4E
118
X1D10
X1D11
1C
120
119
TRST_N
1D
122
121
CLK
RST_N
VDD
125
123
TMS
126
124
TDI
TCK
127
Pin Configuration
128
3
5
1
96
4E
X0D33
X0D36
1M
2
95
4F
X0D28
X0D37
1N
3
94
4E
X0D32
X 0 Lo4
7
93
4E
X0D27
X 0 Lo3
7
92
4E
VDDIOL
X 0 L i4
0
4
X0D38
1O
5
X 0 L i3
0
X0D39
1P
6
X 0 L i2
0
X0D40
8D
7
X 0 L i1
0
X 0 Lo2
7
90
1L
X0D35
X0D41
8D
8
X 0 L i0
0
X 0 Lo1
7
89
1K
X0D34
X 0 Lo0
7
88
1J
X0D25
X 0 L i0
7
87
1I
X0D24
VDD
91
9
X0D42
8D
10
X 0 Lo0
0
X0D43
8D
11
X 0 Lo1
0
X1D34
1K
12
X 0 Lo2
0
VDDIOL
86
13
X1D35
1L
14
X 0 Lo3
0
X1D36
1M
15
X 0 Lo4
0
VDD
16
VDD
17
X1D37
1N
VDDIOL
18
VDD
X 0 L i1
7
85
1B
X1D01
X 0 L i2
7
84
1A
X1D00
X 0 L i3
7
83
4A
82
X 0 L i4
7
GND
81
X 0 L i4
3
4A
78
X1D08
VDD
79
X 0 Lo4
4
X1D09
VDDIOR
80
19
X0D26
VDDIOR
VDD
4B
X1D07
X1D38
1O
20
X 0 L i3
3
X1D39
1P
21
X 0 L i2
3
X 0 Lo3
4
76
4B
X1D06
X1D16
4D
22
X 0 L i1
3
X 0 Lo2
4
75
4B
X1D05
X1D17
4D
23
X 0 L i0
3
X 0 Lo1
4
74
4B
X1D04
X 0 Lo0
4
73
4A
X1D03
VDD
77
24
VDDIOR
X1D18
4D
25
X 0 Lo0
3
X1D19
4D
26
X 0 Lo1
3
X 0 L i0
4
71
4A
X1D02
X0D01
1B
27
X 0 Lo2
3
X 0 L i1
4
70
4D
X0D19
X0D10
1C
28
X 0 Lo3
3
X 0 L i2
4
69
4D
X0D18
X 0 L i3
4
68
4D
X0D17
X 0 L i4
4
67
4D
VDDIOL
72
29
X 0 Lo4
3
VDD
X007786,
1G
1H
X0D22
X0D23
X0D16
64
1F
X0D13
63
1E
X0D12
62
60
4C
X0D21
61
59
58
4C
X0D20
VDD
4C
X0D15
57
56
4C
1J
X1D25
X0D14
1I
X1D24
55
4C
X1D21
VDD
4C
X1D20
54
4C
X1D15
53
49
4C
X1D14
52
48
VDDIOR
51
47
VDD
50
46
VDDIOL
1F
X1D13
45
1E
X1D12
44
43
41
40
4A
4B
X0D07
X0D09
4B
X0D06
42
4B
X0D05
VDD
4B
X0D04
4A
1D
X0D11
X0D08
NC
39
65
4A
32
4A
1A
X0D03
X0D00
X0D02
VDDIOR
38
66
VDD
31
37
1H
36
X1D23
35
30
34
1G
33
X1D22
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
4
6
Signal Description
This section lists the signals and I/O pins available on the XL210-512-TQ128. The
device provides a combination of 1bit, 4bit, 8bit and 16bit ports, as well as wider
ports that are fully or partially (gray) bonded out. All pins of a port provide either
output or input, but signals in different directions cannot be mapped onto the
same port.
Pins may have one or more of the following properties:
· PD/PU: The IO pin has a weak pull-down or pull-up resistor. The resistor
is enabled during and after reset. Enabling a link or port that uses the pin
disables the resistor. Thereafter, the resistor can be enabled or disabled under
software control. The resistor is designed to ensure defined logic input state for
unconnected pins. It should not be used to pull external circuitry. Note that the
resistors are highly non-linear and only a maximum pull current is specified in
Section 12.3.
· ST: The IO pin has a Schmitt Trigger on its input.
· IOL/IOT/IOR: The IO pin is powered from VDDIOL, VDDIOT, and VDDIOR respectively
Power pins (8)
Signal
Function
Type
GND
Digital ground
GND
OTP_VCC
OTP power supply
PWR
PLL_AGND
Analog ground for PLL
PWR
PLL_AVDD
Analog PLL power
PWR
VDD
Digital tile power
PWR
VDDIOL
Digital I/O power (left)
PWR
VDDIOR
Digital I/O power (right)
PWR
VDDIOT
Digital I/O power (top)
PWR
Properties
JTAG pins (6)
X007786,
Signal
Function
Type
Properties
RST_N
Global reset input
Input
IOL, PU, ST
TCK
Test clock
Input
IOL, PD, ST
TDI
Test data input
Input
IOL, PU
TDO
Test data output
Output
IOL, PD
TMS
Test mode select
Input
IOL, PU
TRST_N
Test reset input
Input
IOL, PU, ST
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
7
I/O pins (88)
Signal
Function
X0D00
X0D01
X0 L32
out
Type
Properties
1A0
I/O
IOL, PD
1B0
I/O
IOL, PD
X0D02
4A0
8A0
16A0
32A20
I/O
IOL, PD
X0D03
4A1
8A1
16A1
32A21
I/O
IOL, PD
X0D04
4B0
8A2
16A2
32A22
I/O
IOL, PD
X0D05
4B1
8A3
16A3
32A23
I/O
IOL, PD
X0D06
4B2
8A4
16A4
32A24
I/O
IOL, PD
X0D07
4B3
8A5
16A5
32A25
I/O
IOL, PD
X0D08
4A2
8A6
16A6
32A26
I/O
IOL, PD
X0D09
4A3
8A7
16A7
32A27
I/O
IOL, PD
1C0
I/O
IOL, PD
X0D11
1D0
I/O
IOL, PD
X0D12
1E0
I/O
IOR, PD
X0D13
1F0
I/O
IOR, PD
X0D10
X0 L33
out
X0D14
4C0
8B0
16A8
32A28
I/O
IOR, PD
X0D15
4C1
8B1
16A9
32A29
I/O
IOR, PD
X0D16
X0 L44
in
4D0
8B2
16A10
I/O
IOR, PD
X0D17
X0 L43
in
4D1
8B3
16A11
I/O
IOR, PD
X0D18
X0 L42
in
4D2
8B4
16A12
I/O
IOR, PD
X0D19
X0 L41
in
4D3
8B5
16A13
I/O
IOR, PD
X0D20
4C2
8B6
16A14
32A30
I/O
IOR, PD
X0D21
4C3
8B7
16A15
32A31
I/O
IOR, PD
X0D22
1G0
I/O
IOR, PD
X0D23
1H0
I/O
IOR, PD
X0D24
X0 L70
in
1I0
I/O
IOR, PD
X0D25
X0 L70
out
1J0
I/O
IOR, PD
X0D26
X0 L73
out
4E0
8C0
16B0
I/O
IOR, PD
X0D27
X0 L74
out
4E1
8C1
16B1
I/O
IOR, PD
X0D28
4F0
8C2
16B2
I/O
IOR, PD
X0D29
4F1
8C3
16B3
I/O
IOR, PD
X0D30
4F2
8C4
16B4
I/O
IOR, PD
X0D31
4F3
8C5
16B5
I/O
IOR, PD
X0D32
4E2
8C6
16B6
I/O
IOR, PD
X0D33
4E3
8C7
16B7
I/O
IOR, PD
X0D34
X0 L71
out
1K0
I/O
IOR, PD
X0D35
X0 L72
out
1L0
I/O
IOR, PD
X0D36
1M0
8D0
16B8
I/O
IOL, PD
X0D37
X0 L04
in
1N0
8D1
16B9
I/O
IOL, PD
X0D38
X0 L03
in
1O0
8D2
16B10
I/O
IOL, PD
X0D39
X0 L02
in
1P0
8D3
16B11
I/O
IOL, PD
X0D40
X0 L01
in
8D4
16B12
I/O
IOL, PD
(continued)
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
8
Signal
Function
Type
Properties
X0D41
X0 L00
in
8D5
16B13
I/O
IOL, PD
X0D42
X0 L00
out
8D6
16B14
I/O
IOL, PD
X0D43
X0 L01
out
8D7
16B15
I/O
IOL, PD
X1D00
X0 L72
in
1A0
I/O
IOR, PD
X1D01
X0 L71
in
1B0
I/O
IOR, PD
X1D02
X0 L40
in
4A0
8A0
16A0
32A20
I/O
IOR, PD
X1D03
X0 L40
out
4A1
8A1
16A1
32A21
I/O
IOR, PD
X1D04
X0 L41
out
4B0
8A2
16A2
32A22
I/O
IOR, PD
X1D05
X0 L42
out
4B1
8A3
16A3
32A23
I/O
IOR, PD
X1D06
X0 L43
out
4B2
8A4
16A4
32A24
I/O
IOR, PD
X1D07
X0 L44
out
4B3
8A5
16A5
32A25
I/O
IOR, PD
X1D08
X0 L74
in
4A2
8A6
16A6
32A26
I/O
IOR, PD
X1D09
X0 L73
in
4A3
8A7
16A7
32A27
I/O
IOR, PD
X1D10
1C0
I/O
IOT, PD
X1D11
1D0
I/O
IOT, PD
X1D12
1E0
I/O
IOL, PD
X1D13
1F0
I/O
IOL, PD
X1D14
4C0
8B0
16A8
32A28
I/O
IOR, PD
X1D15
4C1
8B1
16A9
32A29
I/O
IOR, PD
X1D16
X0 L31
in
4D0
8B2
16A10
I/O
IOL, PD
X1D17
X0 L30
in
4D1
8B3
16A11
I/O
IOL, PD
X1D18
X0 L30
out
4D2
8B4
16A12
I/O
IOL, PD
X1D19
X0 L31
out
4D3
8B5
16A13
I/O
IOL, PD
X1D20
4C2
8B6
16A14
32A30
I/O
IOR, PD
X1D21
4C3
8B7
16A15
32A31
I/O
IOR, PD
1G0
I/O
IOL, PD
X1D23
1H0
I/O
IOL, PD
X1D24
1I0
I/O
IOR, PD
X1D25
1J0
I/O
IOR, PD
X1D22
X0 L34
out
X1D26
4E0
8C0
16B0
I/O
IOT, PD
X1D27
4E1
8C1
16B1
I/O
IOT, PD
X1D28
4F0
8C2
16B2
I/O
IOT, PD
X1D29
4F1
8C3
16B3
I/O
IOT, PD
X1D30
4F2
8C4
16B4
I/O
IOT, PD
X1D31
4F3
8C5
16B5
I/O
IOT, PD
X1D32
4E2
8C6
16B6
I/O
IOT, PD
X1D33
4E3
8C7
16B7
I/O
IOT, PD
X1D34
X0 L02
out
1K0
I/O
IOL, PD
X1D35
X0 L03
out
1L0
I/O
IOL, PD
X1D36
X0 L04
out
1M0
8D0
16B8
I/O
IOL, PD
X1D37
X0 L34
in
1N0
8D1
16B9
I/O
IOL, PD
X1D38
X0 L33
in
1O0
8D2
16B10
I/O
IOL, PD
X1D39
X0 L32
in
1P0
8D3
16B11
I/O
IOL, PD
(continued)
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Signal
9
Type
Properties
X1D40
Function
8D4
16B12
I/O
IOT, PD
X1D41
8D5
16B13
I/O
IOT, PD
X1D42
8D6
16B14
I/O
IOT, PD
X1D43
8D7
16B15
I/O
IOT, PD
System pins (1)
X007786,
Signal
Function
Type
Properties
CLK
PLL reference clock
Input
IOL, PD, ST
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
5
10
Example Application Diagram
IN
IN
1V0
OUT
3V3
PLL_AGND
VDD
RESET
SUPERVISOR
PLL_AVDD
OUT
RST_N
TRST_N
OSCILLATOR
25 MHz
CLK
OTP_VCC
XnDnn
GPIO
xCORE200
VDDIOT
VDDIOL
GND
Figure 2:
Simplified
Reference
Schematic
X0D01
X0D04
X0D05
X0D06
X0D07
X0D10
VDDIOR
QSPI FLASH
· see Section 11 for details on the power supplies and PCB design
X007786,
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XL210-512-TQ128 Datasheet
6
11
Product Overview
The XL210-512-TQ128 is a powerful device that consists of two xCORE Tiles,
each comprising a flexible logical processing cores with tightly integrated I/O and
on-chip memory.
6.1
Logical cores
Each tile has up to 5 active logical cores, which issue instructions down a shared
five-stage pipeline. Instructions from the active cores are issued round-robin. Each
core is allocated a fifth of the processing cycles. Figure 3 shows the guaranteed
core performance.
Figure 3:
Logical core
performance
Speed
MIPS
Frequency
1000 MIPS
500 MHz
grade
10
MIPS per
logical core
100
There is no way that the performance of a logical core can be reduced below these
predicted levels (unless priority threads are used: in this case the guaranteed
minimum performance is computed based on the number of priority threads as
defined in the architecture manual).
The logical cores are triggered by events instead of interrupts and run to completion.
A logical core can be paused to wait for an event.
6.2
xTIME scheduler
The xTIME scheduler handles the events generated by xCORE Tile resources, such
as channel ends, timers and I/O pins. It ensures that all events are serviced and
synchronized, without the need for an RTOS. Events that occur at the I/O pins are
handled by the Hardware-Response ports and fed directly to the appropriate xCORE
Tile. An xCORE Tile can also choose to wait for a specified time to elapse, or for
data to become available on a channel.
Tasks do not need to be prioritised as each of them runs on their own logical
xCORE. It is possible to share a set of low priority tasks on a single core using
cooperative multitasking.
6.3
Hardware Response Ports
Hardware Response ports connect an xCORE tile to one or more physical pins and
as such define the interface between hardware attached to the XL210-512-TQ128,
and the software running on it. A combination of 1bit, 4bit, 8bit, 16bit and 32bit
ports are available. All pins of a port provide either output or input. Signals in
different directions cannot be mapped onto the same port.
The port logic can drive its pins high or low, or it can sample the value on its pins,
optionally waiting for a particular condition. Ports are accessed using dedicated
instructions that are executed in a single processor cycle. xCORE-200 IO pins can
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XL210-512-TQ128 Datasheet
12
reference clock
readyOut
conditional
value
clock port
clock
block
readyIn port
port counter
port
logic
stamp/time
PORT
FIFO
PINS
Figure 4:
Port block
diagram
port
value
output (drive)
SERDES
transfer
register
CORE
input (sample)
be used as open collector outputs, where signals are driven low if a zero is output,
but left high impedance if a one is output. This option is set on a per-port basis.
Data is transferred between the pins and core using a FIFO that comprises a SERDES
and transfer register, providing options for serialization and buffered data.
Each port has a 16-bit counter that can be used to control the time at which data is
transferred between the port value and transfer register. The counter values can
be obtained at any time to find out when data was obtained, or used to delay I/O
until some time in the future. The port counter value is automatically saved as a
timestamp, that can be used to provide precise control of response times.
The ports and xCONNECT links are multiplexed onto the physical pins. If an
xConnect Link is enabled, the pins of the underlying ports are disabled. If a port
is enabled, it overrules ports with higher widths that share the same pins. The pins
on the wider port that are not shared remain available for use when the narrower
port is enabled. Ports always operate at their specified width, even if they share
pins with another port.
6.4
Clock blocks
xCORE devices include a set of programmable clocks called clock blocks that can
be used to govern the rate at which ports execute. Each xCORE tile has six clock
blocks: the first clock block provides the tile reference clock and runs at a default
frequency of 100MHz; the remaining clock blocks can be set to run at different
frequencies.
A clock block can use a 1-bit port as its clock source allowing external application
clocks to be used to drive the input and output interfaces. xCORE-200 clock blocks
optionally divide the clock input from a 1-bit port.
X007786,
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XL210-512-TQ128 Datasheet
13
100MHz
reference
clock
1-bit port
...
...
divider
readyIn
clock block
Figure 5:
Clock block
diagram
port counter
In many cases I/O signals are accompanied by strobing signals. The xCORE ports
can input and interpret strobe (known as readyIn and readyOut) signals generated
by external sources, and ports can generate strobe signals to accompany output
data.
On reset, each port is connected to clock block 0, which runs from the xCORE Tile
reference clock.
6.5
Channels and Channel Ends
Logical cores communicate using point-to-point connections, formed between two
channel ends. A channel-end is a resource on an xCORE tile, that is allocated by
the program. Each channel-end has a unique system-wide identifier that comprises
a unique number and their tile identifier. Data is transmitted to a channel-end by
an output-instruction; and the other side executes an input-instruction. Data can
be passed synchronously or asynchronously between the channel ends.
6.6
xCONNECT Switch and Links
XMOS devices provide a scalable architecture, where multiple xCORE devices can
be connected together to form one system. Each xCORE device has an xCONNECT
interconnect that provides a communication infrastructure for all tasks that run on
the various xCORE tiles on the system.
The interconnect relies on a collection of switches and XMOS links. Each xCORE
device has an on-chip switch that can set up circuits or route data. The switches
are connected by xConnect Links. An XMOS link provides a physical connection
between two switches. The switch has a routing algorithm that supports many
different topologies, including lines, meshes, trees, and hypercubes.
The links operate in either 2 wires per direction or 5 wires per direction mode,
depending on the amount of bandwidth required. Circuit switched, streaming
and packet switched data can both be supported efficiently. Streams provide the
fastest possible data rates between xCORE Tiles (up to 250 MBit/s), but each stream
requires a single link to be reserved between switches on two tiles. All packet
communications can be multiplexed onto a single link.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
14
xCONNECT Link to another device switch
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
xCONNECT
switch
CORE
CORE
Figure 6:
Switch, links
and channel
ends
CORE
CORE
CORE
CORE
xCORE Tile
xCORE Tile
Information on the supported routing topologies that can be used to connect
multiple devices together can be found in the XS1-L Link Performance and Design
Guide, X2999.
7
PLL
The PLL creates a high-speed clock that is used for the switch, tile, and reference
clock. The initial PLL multiplication value is shown in Figure 7:
Figure 7:
The initial PLL
multiplier
values
Oscillator
Frequency
9-25 MHz
Tile Boot
Frequency
144-400 MHz
PLL Ratio
16
PLL settings
OD
F
R
1 63
0
Figure 7 also lists the values of OD, F and R, which are the registers that define
the ratio of the tile frequency to the oscillator frequency:
Fcor e = Fosc ×
F +1
1
1
×
×
2
R+1
OD + 1
OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and
F +1
1
260MHz ≤ Fosc × 2 × R+1 ≤ 1.3GHz. The OD, F , and R values can be modified
by writing to the digital node PLL configuration register.
If a different tile frequency is required (eg, 500 MHz), then the PLL must be
reprogrammed after boot to provide the required tile frequency. The XMOS tools
perform this operation by default. Further details on configuring the clock can be
found in the xCORE-200 Clock Frequency Control document.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
8
15
Boot Procedure
The device is kept in reset by driving RST_N low. When in reset, all GPIO pins have
a pull-down enabled. When the device is taken out of reset by releasing RST_N
the processor starts its internal reset process. After 15-150 µs (depending on the
input clock) the processor boots.
The xCORE Tile boot procedure is illustrated in Figure 8. If bit 5 of the security
register (see §9.1) is set, the device boots from OTP. To get a high value, a 3K3
pull-up resistor should be strapped onto the pin. To assure a low value, a pull-down
resistor is required if other external devices are connected to this port.
Start
Boot ROM
Primary boot
Security Register
Bit [5] set
No
Yes
Copy OTP contents
to base of SRAM
OTP
Figure 8:
Boot
procedure
Figure 9:
Boot source
pins
Boot according to
boot source pins
Execute program
X0D06
X0D05
X0D04
Tile 0 boot
Tile 1 boot
Enabled links
0
0
0
QSPI master
Channel end 0
None
0
0
1
SPI master
Channel end 0
None
0
1
0
SPI slave
Channel end 0
None
0
1
1
SPI slave
SPI slave
None
1
0
0
Channel end 0
Channel end 0
XL0 (2w)
The boot image has the following format:
· A 32-bit program size s in words.
· Program consisting of s × 4 bytes.
· A 32-bit CRC, or the value 0x0D15AB1E to indicate that no CRC check should be
performed.
The program size and CRC are stored least significant byte first. The program
is loaded into the lowest memory address of RAM, and the program is started
from that address. The CRC is calculated over the byte stream represented by the
program size and the program itself. The polynomial used is 0xEDB88320 (IEEE
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
16
802.3); the CRC register is initialized with 0xFFFFFFFF and the residue is inverted
to produce the CRC.
8.1
Boot from QSPI master
If set to boot from QSPI master, the processor enables the six pins specified in
Figure 10, and drives the SPI clock at 50 MHz (assuming a 400 MHz core clock). A
READ command is issued with a 24-bit address 0x000000. The clock polarity and
phase are 0 / 0.
Figure 10:
QSPI pins
Pin
Signal
Description
X0D01
SS
Slave Select
X0D04..X0D07
SPIO
Data
X0D10
SCLK
Clock
The xCORE Tile expects each byte to be transferred with the least-significant nibble
first. Programmers who write bytes into an QSPI interface using the most significant
nibble first may have to reverse the nibbles in each byte of the image stored in the
QSPI device.
The pins used for QSPI boot are hardcoded in the boot ROM and cannot be changed.
If required, an QSPI boot program can be burned into OTP that uses different pins.
8.2
Boot from SPI master
If set to boot from SPI master, the processor enables the four pins specified in
Figure 11, and drives the SPI clock at 2.5 MHz (assuming a 400 MHz core clock). A
READ command is issued with a 24-bit address 0x000000. The clock polarity and
phase are 0 / 0.
Figure 11:
SPI master
pins
Pin
Signal
Description
X0D00
MISO
Master In Slave Out (Data)
X0D01
SS
Slave Select
X0D10
SCLK
Clock
X0D11
MOSI
Master Out Slave In (Data)
The xCORE Tile expects each byte to be transferred with the least-significant bit
first. Programmers who write bytes into an SPI interface using the most significant
bit first may have to reverse the bits in each byte of the image stored in the SPI
device.
If a large boot image is to be read in, it is faster to first load a small boot-loader
that reads the large image using a faster SPI clock, for example 50 MHz or as fast
as the flash device supports.
The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed.
If required, an SPI boot program can be burned into OTP that uses different pins.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
8.3
17
Boot from SPI slave
If set to boot from SPI slave, the processor enables the three pins specified in
Figure 12 and expects a boot image to be clocked in. The supported clock polarity
and phase are 0/0 and 1/1.
Figure 12:
SPI slave pins
Pin
Signal
Description
X0D00
SS
Slave Select
X0D10
SCLK
Clock
X0D11
MOSI
Master Out Slave In (Data)
The xCORE Tile expects each byte to be transferred with the least-significant bit
first. The pins used for SPI boot are hardcoded in the boot ROM and cannot be
changed. If required, an SPI boot program can be burned into OTP that uses
different pins.
8.4
Boot from xConnect Link
If set to boot from an xConnect Link, the processor enables its link(s) around
2 us after the boot process starts. Enabling the Link switches off the pull-down
resistors on the link, drives all the TX wires low (the initial state for the Link), and
monitors the RX pins for boot-traffic; they must be low at this stage. If the internal
pull-down is too weak to drain any residual charge, external pull-downs of 10K
may be required on those pins.
The boot-rom on the core will then:
1. Allocate channel-end 0.
2. Input a word on channel-end 0. It will use this word as a channel to acknowledge
the boot. Provide the null-channel-end 0x0000FF02 if no acknowledgment is
required.
3. Input the boot image specified above, including the CRC.
4. Input an END control token.
5. Output an END control token to the channel-end received in step 2.
6. Free channel-end 0.
7. Jump to the loaded code.
8.5
Boot from OTP
If an xCORE tile is set to use secure boot (see Figure 8), the boot image is read
from address 0 of the OTP memory in the tile’s security module.
This feature can be used to implement a secure bootloader which loads an encrypted image from external flash, decrypts and CRC checks it with the processor,
and discontinues the boot process if the decryption or CRC check fails. XMOS
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
18
provides a default secure bootloader that can be written to the OTP along with
secret decryption keys.
Each tile has its own individual OTP memory, and hence some tiles can be booted
from OTP while others are booted from SPI or the channel interface. This enables
systems to be partially programmed, dedicating one or more tiles to perform a
particular function, leaving the other tiles user-programmable.
8.6
Security register
The security register enables security features on the xCORE tile. The features
shown in Figure 13 provide a strong level of protection and are sufficient for
providing strong IP security.
Feature
Bit
Description
Disable JTAG
0
The JTAG interface is disabled, making it impossible for
the tile state or memory content to be accessed via the
JTAG interface.
Disable Link access
1
Other tiles are forbidden access to the processor state
via the system switch. Disabling both JTAG and Link
access transforms an xCORE Tile into a “secure island”
with other tiles free for non-secure user application
code.
Secure Boot
5
The xCORE Tile is forced to boot from address 0 of the
OTP, allowing the xCORE Tile boot ROM to be bypassed
(see §8).
Redundant rows
7
Enables redundant rows in OTP.
Sector Lock 0
8
Disable programming of OTP sector 0.
Sector Lock 1
9
Disable programming of OTP sector 1.
Sector Lock 2
10
Disable programming of OTP sector 2.
Sector Lock 3
11
Disable programming of OTP sector 3.
OTP Master Lock
12
Disable OTP programming completely: disables updates
to all sectors and security register.
Disable JTAG-OTP
13
Disable all (read & write) access from the JTAG interface
to this OTP.
21..15
General purpose software accessable security register
available to end-users.
31..22
General purpose user programmable JTAG UserID code
extension.
Figure 13:
Security
register
features
9
Memory
9.1
OTP
Each xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with
a security register that configures system wide security features. The OTP holds
data in four sectors each containing 512 rows of 32 bits which can be used to
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
19
implement secure bootloaders and store encryption keys. Data for the security
register is loaded from the OTP on power up. All additional data in OTP is copied
from the OTP to SRAM and executed first on the processor.
The OTP memory is programmed using three special I/O ports: the OTP address
port is a 16-bit port with resource ID 0x100200, the OTP data is written via a 32-bit
port with resource ID 0x200100, and the OTP control is on a 16-bit port with ID
0x100300. Programming is performed through libotp and xburn.
9.2
SRAM
Each xCORE Tile integrates a single 256KB SRAM bank for both instructions and
data. All internal memory is 32 bits wide, and instructions are either 16-bit or
32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and
are executed within one tile clock cycle. There is no dedicated external memory
interface, although data memory can be expanded through appropriate use of the
ports.
10
JTAG
The JTAG module can be used for loading programs, boundary scan testing, incircuit source-level debugging and programming the OTP memory.
TDI
TDI
BS TAP
TDO
TDO
TCK
TMS
Figure 14:
JTAG chain
structure
TRST_N
The JTAG chain structure is illustrated in Figure 14. It comprises a single 1149.1
compliant TAP that can be used for boundary scan of the I/O pins. It has a 4-bit
IR and 32-bit DR. It also provides access to a chip TAP that in turn can access the
xCORE Tile for loading code and debugging.
The TRST_N pin must be asserted low during and after power up for 100 ns. If JTAG
is not required, the TRST_N pin can be tied to ground to hold the JTAG module in
reset.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
20
The JTAG device identification register can be read by using the IDCODE instruction.
Its contents are specified in Figure 15.
Figure 15:
IDCODE
return value
Bit31
Device Identification Register
Version
0
0
0
Bit0
Part Number
0
0
0
0
0
0
0
0
0
0
0
0
Manufacturer Identity
0
0
0
0
0
1
0
0
1
0
1
5
1
0
0
0
6
1
1
1
0
0
3
1
1
3
The JTAG usercode register can be read by using the USERCODE instruction. Its
contents are specified in Figure 16. The OTP User ID field is read from bits [22:31]
of the security register on xCORE Tile 0, see §9.1 (all zero on unprogrammed
devices).
Figure 16:
USERCODE
return value
11
Bit31
Usercode Register
OTP User ID
0
0
0
0
0
0
0
0
0
Bit0
Unused
0
0
0
0
0
0
0
Silicon Revision
0
1
2
0
1
0
0
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Board Integration
The device has the following power supply pins:
· VDD pins for the xCORE Tile
· VDDIO pins for the I/O lines. Separate I/O supplies are provided for the left, top,
and right side of the package; different I/O voltages may be supplied on those.
The signal description (Section 4) specifies which I/O is powered from which
power-supply
· PLL_AVDD pins for the PLL
· OTP_VCC pins for the OTP
Several pins of each type are provided to minimize the effect of inductance within
the package, all of which must be connected. The power supplies must be brought
up monotonically and input voltages must not exceed specification at any time.
VDDIO/OTP_VCC and VDD can ramp up independently. In order to reduce stresses
on the device, it is preferable to make them ramp up in a short time frame of each
other, no more than 50 ms apart. RST_N and TRST_N should be kept low until all
power supplies are stable and within tolerances of their final voltage. When RST_N
comes up, the processor will attempt to boot within a very short period of time.
If booting from external flash, ensure that there is enough time between before
RST_N coming up for the external flash to settle. Power sequencing is summarised
in Figure 17
The PLL_AVDD supply should be separated from the other noisier supplies on
the board. The PLL requires a very clean power supply, and a low pass filter (for
example, a 4.7 Ω resistor and 100 nF multi-layer ceramic capacitor) is recommended
on this pin.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bring up
in short
succession
21
System
dependent
timing
1.0
VDD
0
3.3
VDDIO,
OTP_VCC
V
Figure 17:
Sequencing
of power
supplies and
RST_N
0
3.3
RST_N
0
Time
The following ground pins are provided:
· PLL_AGND for PLL_AVDD
· GND for all other supplies
All ground pins must be connected directly to the board ground.
The VDD and VDDIO supplies should be decoupled close to the chip by several
100 nF low inductance multi-layer ceramic capacitors between the supplies and GND
(for example, 100nF 0402 for each supply pin). The ground side of the decoupling
capacitors should have as short a path back to the GND pins as possible. A bulk
decoupling capacitor of at least 10 uF should be placed on each of these supplies.
RST_N is an active-low asynchronous-assertion global reset signal. Following a
reset, the PLL re-establishes lock after which the device boots up according to the
boot mode (see §8). RST_N and must be asserted low during and after power up
for 100 ns.
11.1
Land patterns and solder stencils
The package is a 128 pin Thin Quad Flat Package (TQFP) with exposed ground
paddle/heat slug on a 0.4mm pitch.
The land patterns and solder stencils will depend on the PCB manufacturing
process. We recommend you design them with using the IPC specifications “Generic
Requirements for Surface Mount Design and Land Pattern Standards” IPC-7351B.
This standard aims to achieve desired targets of heel, toe and side fillets for
solder-joints. The mechanical drawings in Section 13 specify the dimensions and
tolerances.
11.2
Ground and Thermal Vias
Vias under the heat slug into the ground plane of the PCB are recommended for a
low inductance ground connection and good thermal performance. Typical designs
could use 16 vias in a 4 x 4 grid, equally spaced across the heat slug.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
11.3
22
Moisture Sensitivity
XMOS devices are, like all semiconductor devices, susceptible to moisture absorption. When removed from the sealed packaging, the devices slowly absorb moisture
from the surrounding environment. If the level of moisture present in the device
is too high during reflow, damage can occur due to the increased internal vapour
pressure of moisture. Example damage can include bond wire damage, die lifting,
internal or external package cracks and/or delamination.
All XMOS devices are Moisture Sensitivity Level (MSL) 3 - devices have a shelf life
of 168 hours between removal from the packaging and reflow, provided they
are stored below 30C and 60% RH. If devices have exceeded these values or an
included moisture indicator card shows excessive levels of moisture, then the parts
should be baked as appropriate before use. This is based on information from Joint
IPC/JEDEC Standard For Moisture/Reflow Sensitivity Classification For Nonhermetic
Solid State Surface-Mount Devices J-STD-020 Revision D.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
12
23
Electrical Characteristics
12.1
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition
for extended periods may affect device reliability and lifetime.
Figure 18:
Absolute
maximum
ratings
Symbol
Parameter
MIN
MAX
VDD
Tile DC supply voltage
-0.2
1.1
UNITS
V
Notes
PLL_AVDD
PLL analog supply
-0.2
1.1
V
VDDIO
I/O supply voltage
-0.3
3.75
V
OTP_VCC
OTP supply voltage
-0.3
3.75
V
Tj
Junction temperature
125
°C
Tstg
Storage temperature
-65
150
°C
V(Vin)
Voltage applied to any IO pin
-0.3
3.75
V
I(XxDxx)
GPIO current
-30
30
mA
I(VDDIOL)
Current for VDDIOL domain
490
mA
A, B, C
I(VDDIOR)
Current for VDDIOR domain
490
mA
A, B, C
I(VDDIOT)
Current for VDDIOT domain
98
mA
A, C
A Exceeding these current limits will result in premature aging and reduced lifetime.
B This current consumption must be evenly distributed over all VDDIO pins.
C All main power (VDD, VDDIO) and ground (VSS) pins must always be connected to the external
power supply, in the permitted range.
12.2
Symbol
Parameter
MIN
TYP
MAX
UNITS
VDD
Tile DC supply voltage
0.95
1.00
1.05
V
VDDIOL
I/O supply voltage
3.135
3.30
3.465
V
VDDIOR
I/O supply voltage
3.135
3.30
3.465
V
VDDIOT 3v3
I/O supply voltage
3.135
3.30
3.465
V
VDDIOT 2v5
I/O supply voltage
2.375
2.50
2.625
V
PLL_AVDD
PLL analog supply
0.95
1.00
1.05
V
OTP_VCC
OTP supply voltage
3.135
3.30
3.465
V
Cl
xCORE Tile I/O load
capacitance
Ta
Figure 19:
Operating
conditions
X007786,
Operating Conditions
Ambient operating
temperature (Commercial)
Ambient operating
temperature (Industrial)
Tj
Junction temperature
25
pF
0
70
°C
-40
85
°C
125
°C
Notes
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
12.3
Figure 20:
DC characteristics
24
DC Characteristics, VDDIO=3V3
Symbol
Parameter
MIN
MAX
UNITS
Notes
V(IH)
Input high voltage
2.00
TYP
3.60
V
A
V(IL)
Input low voltage
-0.30
0.70
V
A
V(OH)
Output high voltage
V
B, C
V(OL)
Output low voltage
V
B, C
I(PU)
Internal pull-up current (Vin=0V)
µA
D
I(PD)
Internal pull-down current
(Vin=3.3V)
100
µA
D
I(LC)
Input leakage current
10
µA
2.20
0.40
-100
-10
3.0
3.0
2.0
2.0
1.0
1.0
0.0
40
60
80
100
-100
-80
-60
-40
-20
0
0.0
I(PU) current, uA
ESD Stress Voltage
Symbol
Parameter
HBM
Human body model
CDM
Charged Device Model
12.5
Figure 23:
Reset timing
20
I(PD) current, uA
12.4
Figure 22:
ESD stress
voltage
0
IO Pin Voltage, V
Figure 21:
Typical
internal
pull-down
and pull-up
currents
IO Pin Voltage, V
A All pins except power supply pins.
B Pins X1D40, X1D41, X1D42, X1D43, X1D26, and X1D27 are nominal 8 mA drivers, the remainder of
the general-purpose I/Os are 4 mA.
C Measured with 4 mA drivers sourcing 4 mA, 8 mA drivers sourcing 8 mA.
D Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs
should not be used to pull external circuitry. In order to pull the pin to the opposite state, a 4K7
resistor is recommended to overome the internal pull current.
MAX
UNITS
-2.00
MIN
TYP
2.00
KV
-500
500
Notes
V
Reset Timing
Symbol
Parameters
MIN
T(RST)
Reset pulse width
5
T(INIT)
Initialization time
TYP
MAX
UNITS
Notes
µs
150
µs
A
A Shows the time taken to start booting after RST_N has gone high.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
12.6
Figure 24:
xCORE Tile
currents
25
Power Consumption
Symbol
Parameter
I(DDCQ)
Quiescent VDD current
PD
Tile power dissipation
IDD
I(ADDPLL)
MIN TYP MAX
UNITS
Notes
45
mA
A, B, C
325
µW/MIPS
A, D, E, F
Active VDD current
570 700
mA
A, G
PLL_AVDD current
5
mA
H
7
A
B
C
D
E
F
G
Use for budgetary purposes only.
Assumes typical tile and I/O voltages with no switching activity.
Includes PLL current.
Assumes typical tile and I/O voltages with nominal switching activity.
Assumes 1 MHz = 1 MIPS.
PD(TYP) value is the usage power consumption under typical operating conditions.
Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 500 MHz, average device resource
usage.
H PLL_AVDD = 1.0 V
The tile power consumption of the device is highly application dependent and
should be used for budgetary purposes only.
More detailed power analysis can be found in the XS1-L Power Consumption
document,
12.7
Figure 25:
Clock
Clock
Symbol
Parameter
MIN
TYP
MAX
UNITS
f
Frequency
9
25
25
MHz
Notes
SR
Slew rate
0.10
TJ(LT)
Long term jitter (pk-pk)
2
%
A
f(MAX)
Processor clock frequency
500
MHz
B
V/ns
A Percentage of CLK period.
B Assumes typical tile and I/O voltages with nominal activity.
Further details can be found in the XS1-L Clock Frequency Control document,
12.8
Figure 26:
I/O AC characteristics
xCORE Tile I/O AC Characteristics
Symbol
Parameter
MIN TYP MAX UNITS
T(XOVALID)
Input data valid window
8
T(XOINVALID)
Output data invalid window
9
T(XIFMAX)
Rate at which data can be sampled
with respect to an external clock
Notes
ns
ns
60
MHz
The input valid window parameter relates to the capability of the device to capture
data input to the chip with respect to an external clock source. It is calculated as the
sum of the input setup time and input hold time with respect to the external clock
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
26
as measured at the pins. The output invalid window specifies the time for which
an output is invalid with respect to the external clock. Note that these parameters
are specified as a window rather than absolute numbers since the device provides
functionality to delay the incoming clock with respect to the incoming data.
Information on interfacing to high-speed synchronous interfaces can be found in
the Port I/O Timing document, X5821.
12.9
Figure 27:
Link
performance
xConnect Link Performance
Symbol
Parameter
MAX
UNITS
Notes
B(2blinkP)
2b link bandwidth (packetized)
MIN
TYP
87
MBit/s
A, B
B(5blinkP)
5b link bandwidth (packetized)
217
MBit/s
A, B
B(2blinkS)
2b link bandwidth (streaming)
100
MBit/s
B
B(5blinkS)
5b link bandwidth (streaming)
250
MBit/s
B
A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header
and payload.
B 7.5 ns symbol time.
The asynchronous nature of links means that the relative phasing of CLK clocks is
not important in a multi-clock system, providing each meets the required stability
criteria.
12.10
Figure 28:
JTAG timing
JTAG Timing
Symbol
Parameter
f(TCK_D)
TCK frequency (debug)
MIN
TYP
MAX
UNITS
18
MHz
10
MHz
f(TCK_B)
TCK frequency (boundary scan)
T(SETUP)
TDO to TCK setup time
5
ns
A
T(HOLD)
TDO to TCK hold time
5
ns
A
T(DELAY)
TCK to output delay
ns
B
15
Notes
A Timing applies to TMS and TDI inputs.
B Timing applies to TDO output from negative edge of TCK.
All JTAG operations are synchronous to TCK apart from the global asynchronous
reset TRST_N.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
13
27
Package Information
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
13.1
Part Marking
FXCCRNTMM
MCYYWWXX
Figure 29:
Part marking
scheme
14
28
LLLLLL.LL
F - Product family
X - Reserved
CC - Number of logical cores
R - RAM [in log2(kbytes)]
N - Flash size [in log2(Mbytes)+1]
T - Temperature grade
MM - Speed grade
MC - Manufacturer
YYWW - Date
XX - Reserved
Wafer lot code
Ordering Information
Figure 30:
Orderable
part numbers
X007786,
Product Code
XL210-512-TQ128-C20
XL210-512-TQ128-I20
Marking
L11090C20
L11090I20
Qualification
Commercial
Industrial
Speed Grade
1000 MIPS
1000 MIPS
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
29
Appendices
A
Configuration of the XL210-512-TQ128
The device is configured through banks of registers, as shown in Figure 31.
xTIME
scheduler
Hardware response ports
PLL
JTAG
xTIME
scheduler
Hardware response ports
Figure 31:
Registers
xCORE logical core
SRAM
OTP
Tile configuration
xCORE logical core
Node configuration
xCONNECT
Switch
xCORE logical core
xCORE logical core
Tile configuration
Processor status
xCORE logical core
xCORE logical core
X1Dxx
I/O pins
Processor status
X0Dxx
I/O pins
xCORE logical core
xCORE logical core
xCORE logical core
xCORE logical core
OTP
SRAM
The following communication sequences specify how to access those registers.
Any messages transmitted contain the most significant 24 bits of the channel-end
to which a response is to be sent. This comprises the node-identifier and the
channel number within the node. if no response is required on a write operation,
supply 24-bits with the last 8-bits set, which suppresses the reply message. Any
multi-byte data is sent most significant byte first.
A.1
Accessing a processor status register
The processor status registers are accessed directly from the processor instruction
set. The instructions GETPS and SETPS read and write a word. The register number
should be translated into a processor-status resource identifier by shifting the
register number left 8 places, and ORing it with 0x0B. Alternatively, the functions
getps(reg) and setps(reg,value) can be used from XC.
A.2
Accessing an xCORE Tile configuration register
xCORE Tile configuration registers can be accessed through the interconnect using
the functions write_tile_config_reg(tileref, ...) and read_tile_config_reg(tile
> ref, ...), where tileref is the name of the xCORE Tile, e.g. tile[1]. These
functions implement the protocols described below.
Instead of using the functions above, a channel-end can be allocated to communicate with the xCORE tile configuration registers. The destination of the channel-end
should be set to 0xnnnnC20C where nnnnnn is the tile-identifier.
A write message comprises the following:
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
30
control-token
24-bit response
16-bit
32-bit
control-token
192
channel-end identifier
register number
data
1
The response to a write message comprises either control tokens 3 and 1 (for
success), or control tokens 4 and 1 (for failure).
A read message comprises the following:
control-token
24-bit response
16-bit
control-token
193
channel-end identifier
register number
1
The response to the read message comprises either control token 3, 32-bit of data,
and control-token 1 (for success), or control tokens 4 and 1 (for failure).
A.3
Accessing node configuration
Node configuration registers can be accessed through the interconnect using
the functions write_node_config_reg(device, ...) and read_node_config_reg(device,
> ...), where device is the name of the node. These functions implement the
protocols described below.
Instead of using the functions above, a channel-end can be allocated to communicate with the node configuration registers. The destination of the channel-end
should be set to 0xnnnnC30C where nnnn is the node-identifier.
A write message comprises the following:
control-token
24-bit response
16-bit
32-bit
control-token
192
channel-end identifier
register number
data
1
The response to a write message comprises either control tokens 3 and 1 (for
success), or control tokens 4 and 1 (for failure).
A read message comprises the following:
control-token
24-bit response
16-bit
control-token
193
channel-end identifier
register number
1
The response to a read message comprises either control token 3, 32-bit of data,
and control-token 1 (for success), or control tokens 4 and 1 (for failure).
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
B
31
Processor Status Configuration
The processor status control registers can be accessed directly by the processor
using processor status reads and writes (use getps(reg) and setps(reg,value) for
reads and writes).
Number
Figure 32:
Summary
X007786,
Perm
Description
0x00
RW
RAM base address
0x01
RW
Vector base address
0x02
RW
xCORE Tile control
0x03
RO
xCORE Tile boot status
0x05
RW
Security configuration
0x06
RW
Ring Oscillator Control
0x07
RO
Ring Oscillator Value
0x08
RO
Ring Oscillator Value
0x09
RO
Ring Oscillator Value
0x0A
RO
Ring Oscillator Value
0x0C
RO
RAM size
0x10
DRW
Debug SSR
0x11
DRW
Debug SPC
0x12
DRW
Debug SSP
0x13
DRW
DGETREG operand 1
0x14
DRW
DGETREG operand 2
0x15
DRW
Debug interrupt type
0x16
DRW
Debug interrupt data
0x18
DRW
Debug core control
0x20 .. 0x27
DRW
Debug scratch
0x30 .. 0x33
DRW
Instruction breakpoint address
0x40 .. 0x43
DRW
Instruction breakpoint control
0x50 .. 0x53
DRW
Data watchpoint address 1
0x60 .. 0x63
DRW
Data watchpoint address 2
0x70 .. 0x73
DRW
Data breakpoint control register
0x80 .. 0x83
DRW
Resources breakpoint mask
0x90 .. 0x93
DRW
Resources breakpoint value
0x9C .. 0x9F
DRW
Resources breakpoint control register
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
B.1
32
RAM base address: 0x00
This register contains the base address of the RAM. It is initialized to 0x00040000.
0x00:
RAM base
address
Bits
Perm
31:2
RW
1:0
RO
B.2
Init
Description
Most significant 16 bits of all addresses.
-
Reserved
Vector base address: 0x01
Base address of event vectors in each resource. On an interrupt or event, the 16
most significant bits of the destination address are provided by this register; the
least significant 16 bits come from the event vector.
0x01:
Vector base
address
Bits
Perm
31:18
RW
17:0
RO
B.3
Init
Description
The event and interrupt vectors.
-
Reserved
xCORE Tile control: 0x02
Register to control features in the xCORE tile
Bits
0x02:
xCORE Tile
control
X007786,
Perm
Init
Description
31:26
RO
-
Reserved
25:18
RW
0
RGMII TX data delay value (in PLL output cycle increments)
17:9
RW
0
RGMII TX clock divider value. TX clk rises when counter (clocked
by PLL output) reaches this value and falls when counter reaches
(value»1). Value programmed into this field should be actual
divide value required minus 1
8
RW
0
Enable RGMII interface periph ports
7:6
RO
-
5
RW
0
Reserved
Select the dynamic mode (1) for the clock divider when the clock
divider is enabled. In dynamic mode the clock divider is only
activated when all active threads are paused. In static mode the
clock divider is always enabled.
4
RW
0
Enable the clock divider. This divides the output of the PLL to
facilitate one of the low power modes.
3:0
RO
-
Reserved
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
B.4
33
xCORE Tile boot status: 0x03
This read-only register describes the boot status of the xCORE tile.
Bits
Perm
Init
RO
23:16
RO
15:9
RO
8
RO
7:6
RO
5
RO
Indicates if core1 has been powered off
4
RO
Cause the ROM to not poll the OTP for correct read levels
3
RO
Boot ROM boots from RAM
2
RO
Boot ROM boots from JTAG
1:0
RO
The boot PLL mode pin value.
0x03:
xCORE Tile
boot status
B.5
-
Description
31:24
Reserved
Processor number.
-
Reserved
Overwrite BOOT_MODE.
-
Reserved
Security configuration: 0x05
Copy of the security register as read from OTP.
Bits
0x05:
Security
configuration
X007786,
Perm
31
RW
30:15
RO
14
RW
Init
Description
Disables write permission on this register
-
Reserved
Disable access to XCore’s global debug
13
RO
12
RW
lock all OTP sectors
11:8
RW
lock bit for each OTP sector
7
RW
6
RO
5
RW
4
RW
3:1
RO
0
RW
-
Reserved
Enable OTP reduanacy
-
Reserved
Override boot mode and read boot image from OTP
Disable JTAG access to the PLL/BOOT configuration registers
-
Reserved
Disable access to XCore’s JTAG debug TAP
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
B.6
34
Ring Oscillator Control: 0x06
There are four free-running oscillators that clock four counters. The oscillators
can be started and stopped using this register. The counters should only be read
when the ring oscillator has been stopped for at least 10 core clock cycles (this can
be achieved by inserting two nop instructions between the SETPS and GETPS). The
counter values can be read using four subsequent registers. The ring oscillators
are asynchronous to the xCORE tile clock and can be used as a source of random
bits.
0x06:
Ring
Oscillator
Control
Bits
Perm
31:2
RO
-
1
RW
0
Core ring oscillator enable.
0
RW
0
Peripheral ring oscillator enable.
B.7
Init
Description
Reserved
Ring Oscillator Value: 0x07
This register contains the current count of the xCORE Tile Cell ring oscillator. This
value is not reset on a system reset.
0x07:
Ring
Oscillator
Value
Bits
Perm
Init
31:16
RO
-
15:0
RO
0
B.8
Description
Reserved
Ring oscillator Counter data.
Ring Oscillator Value: 0x08
This register contains the current count of the xCORE Tile Wire ring oscillator. This
value is not reset on a system reset.
0x08:
Ring
Oscillator
Value
Bits
Perm
Init
31:16
RO
-
15:0
RO
0
B.9
Description
Reserved
Ring oscillator Counter data.
Ring Oscillator Value: 0x09
This register contains the current count of the Peripheral Cell ring oscillator. This
value is not reset on a system reset.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x09:
Ring
Oscillator
Value
Bits
Perm
35
Init
31:16
RO
-
15:0
RO
0
B.10
Description
Reserved
Ring oscillator Counter data.
Ring Oscillator Value: 0x0A
This register contains the current count of the Peripheral Wire ring oscillator. This
value is not reset on a system reset.
0x0A:
Ring
Oscillator
Value
Bits
Perm
Init
31:16
RO
-
15:0
RO
0
B.11
Description
Reserved
Ring oscillator Counter data.
RAM size: 0x0C
The size of the RAM in bytes
0x0C:
RAM size
Bits
Perm
31:2
RO
1:0
RO
B.12
Init
Description
Most significant 16 bits of all addresses.
-
Reserved
Debug SSR: 0x10
This register contains the value of the SSR register when the debugger was called.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bits
31:11
Perm
36
Init
RO
-
Description
Reserved
10
DRW
Address space indentifier
9
DRW
Determines the issue mode (DI bit) upon Kernel Entry after
Exception or Interrupt.
8
RO
7
DRW
When 1 the thread is in fast mode and will continually issue.
6
DRW
When 1 the thread is paused waiting for events, a lock or another
resource.
0x10:
Debug SSR
Determines the issue mode (DI bit).
5
RO
4
DRW
-
Reserved
1 when in kernel mode.
3
DRW
1 when in an interrupt handler.
2
DRW
1 when in an event enabling sequence.
1
DRW
When 1 interrupts are enabled for the thread.
0
DRW
When 1 events are enabled for the thread.
B.13
Debug SPC: 0x11
This register contains the value of the SPC register when the debugger was called.
0x11:
Debug SPC
Bits
Perm
31:0
DRW
B.14
Init
Description
Value.
Debug SSP: 0x12
This register contains the value of the SSP register when the debugger was called.
0x12:
Debug SSP
Bits
Perm
31:0
DRW
B.15
Init
Description
Value.
DGETREG operand 1: 0x13
The resource ID of the logical core whose state is to be read.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x13:
DGETREG
operand 1
Bits
Perm
31:8
RO
7:0
B.16
37
Init
Description
-
Reserved
DRW
Thread number to be read
DGETREG operand 2: 0x14
Register number to be read by DGETREG
0x14:
DGETREG
operand 2
Bits
Perm
31:5
RO
4:0
B.17
Init
Description
-
Reserved
DRW
Register number to be read
Debug interrupt type: 0x15
Register that specifies what activated the debug interrupt.
Bits
Perm
Init
-
Description
31:18
RO
17:16
DRW
Number of the hardware breakpoint/watchpoint which caused
the interrupt (always 0 for =HOST= and =DCALL=). If multiple
breakpoints/watchpoints trigger at once, the lowest number is
taken.
15:8
DRW
Number of thread which caused the debug interrupt (always 0
in the case of =HOST=).
7:3
RO
-
2:0
DRW
0
0x15:
Debug
interrupt type
B.18
Reserved
Reserved
Indicates the cause of the debug interrupt
1: Host initiated a debug interrupt through JTAG
2: Program executed a DCALL instruction
3: Instruction breakpoint
4: Data watch point
5: Resource watch point
Debug interrupt data: 0x16
On a data watchpoint, this register contains the effective address of the memory
operation that triggered the debugger. On a resource watchpoint, it countains the
resource identifier.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x16:
Debug
interrupt data
Bits
Perm
31:0
DRW
B.19
38
Init
Description
Value.
Debug core control: 0x18
This register enables the debugger to temporarily disable logical cores. When
returning from the debug interrupts, the cores set in this register will not execute.
This enables single stepping to be implemented.
0x18:
Debug core
control
Bits
Perm
31:8
RO
7:0
B.20
Init
-
DRW
Description
Reserved
1-hot vector defining which threads are stopped when not in
debug mode. Every bit which is set prevents the respective
thread from running.
Debug scratch: 0x20 .. 0x27
A set of registers used by the debug ROM to communicate with an external
debugger, for example over JTAG. This is the same set of registers as the Debug
Scratch registers in the xCORE tile configuration.
0x20 .. 0x27:
Debug
scratch
Bits
Perm
31:0
DRW
B.21
Init
Description
Value.
Instruction breakpoint address: 0x30 .. 0x33
This register contains the address of the instruction breakpoint. If the PC matches
this address, then a debug interrupt will be taken. There are four instruction
breakpoints that are controlled individually.
0x30 .. 0x33:
Instruction
breakpoint
address
X007786,
Bits
Perm
31:0
DRW
Init
Description
Value.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
B.22
39
Instruction breakpoint control: 0x40 .. 0x43
This register controls which logical cores may take an instruction breakpoint, and
under which condition.
Bits
0x40 .. 0x43:
Instruction
breakpoint
control
Perm
Init
Description
31:24
RO
-
23:16
DRW
0
RO
-
1
DRW
0
When 0 break when PC == IBREAK_ADDR. When 1 = break when
PC != IBREAK_ADDR.
0
DRW
0
When 1 the instruction breakpoint is enabled.
15:2
B.23
Reserved
A bit for each thread in the machine allowing the breakpoint to
be enabled individually for each thread.
Reserved
Data watchpoint address 1: 0x50 .. 0x53
This set of registers contains the first address for the four data watchpoints.
0x50 .. 0x53:
Data
watchpoint
address 1
Bits
Perm
31:0
DRW
B.24
Init
Description
Value.
Data watchpoint address 2: 0x60 .. 0x63
This set of registers contains the second address for the four data watchpoints.
0x60 .. 0x63:
Data
watchpoint
address 2
Bits
Perm
31:0
DRW
B.25
Init
Description
Value.
Data breakpoint control register: 0x70 .. 0x73
This set of registers controls each of the four data watchpoints.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bits
0x70 .. 0x73:
Data
breakpoint
control
register
Perm
40
Init
31:24
RO
-
23:16
DRW
0
15:3
Description
Reserved
A bit for each thread in the machine allowing the breakpoint to
be enabled individually for each thread.
RO
-
2
DRW
0
When 1 the breakpoints will be be triggered on loads.
1
DRW
0
Determines the break condition: 0 = A AND B, 1 = A OR B.
0
DRW
0
When 1 the instruction breakpoint is enabled.
B.26
Reserved
Resources breakpoint mask: 0x80 .. 0x83
This set of registers contains the mask for the four resource watchpoints.
0x80 .. 0x83:
Resources
breakpoint
mask
Bits
Perm
31:0
DRW
B.27
Init
Description
Value.
Resources breakpoint value: 0x90 .. 0x93
This set of registers contains the value for the four resource watchpoints.
0x90 .. 0x93:
Resources
breakpoint
value
Bits
Perm
31:0
DRW
B.28
Init
Description
Value.
Resources breakpoint control register: 0x9C .. 0x9F
This set of registers controls each of the four resource watchpoints.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bits
0x9C .. 0x9F:
Resources
breakpoint
control
register
X007786,
Perm
41
Init
31:24
RO
-
23:16
DRW
0
15:2
Description
Reserved
A bit for each thread in the machine allowing the breakpoint to
be enabled individually for each thread.
RO
-
1
DRW
0
Reserved
When 0 break when condition A is met. When 1 = break when
condition B is met.
0
DRW
0
When 1 the instruction breakpoint is enabled.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
C
42
Tile Configuration
The xCORE Tile control registers can be accessed using configuration reads and
writes (use write_tile_config_reg(tileref, ...) and read_tile_config_reg(tileref,
> ...) for reads and writes).
Number
Perm
Description
0x00
CRO
Device identification
0x01
CRO
xCORE Tile description 1
0x02
CRO
xCORE Tile description 2
0x04
CRW
Control PSwitch permissions to debug registers
0x05
CRW
Cause debug interrupts
0x06
CRW
xCORE Tile clock divider
0x07
CRO
Security configuration
0x20 .. 0x27
CRW
Debug scratch
0x40
CRO
PC of logical core 0
0x41
CRO
PC of logical core 1
Figure 33:
Summary
C.1
0x42
CRO
PC of logical core 2
0x43
CRO
PC of logical core 3
0x44
CRO
PC of logical core 4
0x45
CRO
PC of logical core 5
0x46
CRO
PC of logical core 6
0x47
CRO
PC of logical core 7
0x60
CRO
SR of logical core 0
0x61
CRO
SR of logical core 1
0x62
CRO
SR of logical core 2
0x63
CRO
SR of logical core 3
0x64
CRO
SR of logical core 4
0x65
CRO
SR of logical core 5
0x66
CRO
SR of logical core 6
0x67
CRO
SR of logical core 7
Device identification: 0x00
This register identifies the xCORE Tile
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x00:
Device
identification
43
Bits
Perm
31:24
CRO
Processor ID of this XCore.
23:16
CRO
Number of the node in which this XCore is located.
15:8
CRO
XCore revision.
7:0
CRO
XCore version.
C.2
Init
Description
xCORE Tile description 1: 0x01
This register describes the number of logical cores, synchronisers, locks and
channel ends available on this xCORE tile.
0x01:
xCORE Tile
description 1
Bits
Perm
31:24
CRO
Number of channel ends.
23:16
CRO
Number of the locks.
15:8
CRO
Number of synchronisers.
7:0
C.3
RO
Init
-
Description
Reserved
xCORE Tile description 2: 0x02
This register describes the number of timers and clock blocks available on this
xCORE tile.
Bits
0x02:
xCORE Tile
description 2
31:16
Perm
RO
Init
-
Description
Reserved
15:8
CRO
Number of clock blocks.
7:0
CRO
Number of timers.
C.4
Control PSwitch permissions to debug registers: 0x04
This register can be used to control whether the debug registers (marked with
permission CRW) are accessible through the tile configuration registers. When this
bit is set, write -access to those registers is disabled, preventing debugging of the
xCORE tile over the interconnect.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x04:
Control
PSwitch
permissions
to debug
registers
44
Bits
Perm
Init
31
CRW
0
RO
-
CRW
0
30:1
0
C.5
Description
When 1 the PSwitch is restricted to RO access to all CRW registers
from SSwitch, XCore(PS_DBG_Scratch) and JTAG
Reserved
When 1 the PSwitch is restricted to RO access to all CRW registers
from SSwitch
Cause debug interrupts: 0x05
This register can be used to raise a debug interrupt in this xCORE tile.
Bits
0x05:
Cause debug
interrupts
Perm
31:2
C.6
Init
Description
RO
-
1
CRW
0
Reserved
1 when the processor is in debug mode.
0
CRW
0
Request a debug interrupt on the processor.
xCORE Tile clock divider: 0x06
This register contains the value used to divide the PLL clock to create the xCORE
tile clock. The divider is enabled under control of the tile control register
0x06:
xCORE Tile
clock divider
Bits
Perm
Init
31
CRW
0
30:16
15:0
C.7
RO
-
CRW
0
Description
Clock disable. Writing ’1’ will remove the clock to the tile.
Reserved
Clock divider.
Security configuration: 0x07
Copy of the security register as read from OTP.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bits
Perm
31
CRO
30:15
45
Init
Disables write permission on this register
RO
14
CRO
13
RO
Description
-
Reserved
Disable access to XCore’s global debug
-
Reserved
12
CRO
lock all OTP sectors
11:8
CRO
lock bit for each OTP sector
7
CRO
Enable OTP reduanacy
0x07:
Security
configuration
6
RO
5
CRO
Override boot mode and read boot image from OTP
4
CRO
Disable JTAG access to the PLL/BOOT configuration registers
3:1
0
C.8
-
RO
-
CRO
Reserved
Reserved
Disable access to XCore’s JTAG debug TAP
Debug scratch: 0x20 .. 0x27
A set of registers used by the debug ROM to communicate with an external
debugger, for example over the switch. This is the same set of registers as the
Debug Scratch registers in the processor status.
0x20 .. 0x27:
Debug
scratch
Bits
Perm
31:0
CRW
C.9
Init
Description
Value.
PC of logical core 0: 0x40
Value of the PC of logical core 0.
0x40:
PC of logical
core 0
Bits
Perm
31:0
CRO
C.10
Init
Description
Value.
PC of logical core 1: 0x41
Value of the PC of logical core 1.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x41:
PC of logical
core 1
Bits
Perm
31:0
CRO
C.11
46
Init
Description
Value.
PC of logical core 2: 0x42
Value of the PC of logical core 2.
0x42:
PC of logical
core 2
Bits
Perm
31:0
CRO
C.12
Init
Description
Value.
PC of logical core 3: 0x43
Value of the PC of logical core 3.
0x43:
PC of logical
core 3
Bits
Perm
31:0
CRO
C.13
Init
Description
Value.
PC of logical core 4: 0x44
Value of the PC of logical core 4.
0x44:
PC of logical
core 4
Bits
Perm
31:0
CRO
C.14
Init
Description
Value.
PC of logical core 5: 0x45
Value of the PC of logical core 5.
0x45:
PC of logical
core 5
X007786,
Bits
Perm
31:0
CRO
Init
Description
Value.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
C.15
47
PC of logical core 6: 0x46
Value of the PC of logical core 6.
0x46:
PC of logical
core 6
Bits
Perm
31:0
CRO
C.16
Init
Description
Value.
PC of logical core 7: 0x47
Value of the PC of logical core 7.
0x47:
PC of logical
core 7
Bits
Perm
31:0
CRO
C.17
Init
Description
Value.
SR of logical core 0: 0x60
Value of the SR of logical core 0
0x60:
SR of logical
core 0
Bits
Perm
31:0
CRO
C.18
Init
Description
Value.
SR of logical core 1: 0x61
Value of the SR of logical core 1
0x61:
SR of logical
core 1
Bits
Perm
31:0
CRO
C.19
Init
Description
Value.
SR of logical core 2: 0x62
Value of the SR of logical core 2
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x62:
SR of logical
core 2
Bits
Perm
31:0
CRO
C.20
48
Init
Description
Value.
SR of logical core 3: 0x63
Value of the SR of logical core 3
0x63:
SR of logical
core 3
Bits
Perm
31:0
CRO
C.21
Init
Description
Value.
SR of logical core 4: 0x64
Value of the SR of logical core 4
0x64:
SR of logical
core 4
Bits
Perm
31:0
CRO
C.22
Init
Description
Value.
SR of logical core 5: 0x65
Value of the SR of logical core 5
0x65:
SR of logical
core 5
Bits
Perm
31:0
CRO
C.23
Init
Description
Value.
SR of logical core 6: 0x66
Value of the SR of logical core 6
0x66:
SR of logical
core 6
X007786,
Bits
Perm
31:0
CRO
Init
Description
Value.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
C.24
49
SR of logical core 7: 0x67
Value of the SR of logical core 7
0x67:
SR of logical
core 7
X007786,
Bits
Perm
31:0
CRO
Init
Description
Value.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
D
50
Node Configuration
The digital node control registers can be accessed using configuration reads and
writes (use write_node_config_reg(device, ...) and read_node_config_reg(device,
> ...) for reads and writes).
Number
0x00
Figure 34:
Summary
Perm
Description
RO
Device identification
0x01
RO
System switch description
0x04
RW
Switch configuration
0x05
RW
Switch node identifier
0x06
RW
PLL settings
0x07
RW
System switch clock divider
0x08
RW
Reference clock
0x09
R
System JTAG device ID register
0x0A
R
System USERCODE register
0x0C
RW
Directions 0-7
0x0D
RW
Directions 8-15
0x10
RW
Reserved
0x11
RW
Reserved.
0x1F
RO
Debug source
0x20 .. 0x28
RW
Link status, direction, and network
0x40 .. 0x47
RO
PLink status and network
0x80 .. 0x88
RW
Link configuration and initialization
0xA0 .. 0xA7
RW
Static link configuration
D.1
Device identification: 0x00
This register contains version and revision identifiers and the mode-pins as sampled
at boot-time.
Bits
0x00:
Device
identification
X007786,
Perm
Init
-
Description
31:24
RO
23:16
RO
Reserved
Sampled values of BootCtl pins on Power On Reset.
15:8
RO
SSwitch revision.
7:0
RO
SSwitch version.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
D.2
51
System switch description: 0x01
This register specifies the number of processors and links that are connected to
this switch.
Bits
0x01:
System
switch
description
Perm
Init
RO
23:16
RO
Number of SLinks on the SSwitch.
15:8
RO
Number of processors on the SSwitch.
7:0
RO
Number of processors on the device.
D.3
-
Description
31:24
Reserved
Switch configuration: 0x04
This register enables the setting of two security modes (that disable updates to the
PLL or any other registers) and the header-mode.
Bits
Perm
31
0x04:
Switch
configuration
RW
Init
0
30:9
RO
-
8
RW
0
7:1
RO
-
0
RW
0
D.4
Description
0 = SSCTL registers have write access. 1 = SSCTL registers can
not be written to.
Reserved
0 = PLL_CTL_REG has write access. 1 = PLL_CTL_REG can not be
written to.
Reserved
0 = 2-byte headers, 1 = 1-byte headers (reset as 0).
Switch node identifier: 0x05
This register contains the node identifier.
0x05:
Switch node
identifier
Bits
Perm
Init
31:16
RO
-
15:0
RW
0
D.5
Description
Reserved
The unique ID of this node.
PLL settings: 0x06
An on-chip PLL multiplies the input clock up to a higher frequency clock, used to
clock the I/O, processor, and switch, see Oscillator. Note: a write to this register
will cause the tile to be reset.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bits
Perm
52
Init
Description
31
RW
If set to 1, the chip will not be reset
30
RW
If set to 1, the chip will not wait for the PLL to re-lock. Only use
this if a gradual change is made to the PLL
29
DW
If set to 1, set the PLL to be bypassed
28
DW
If set to 1, set the boot mode to boot from JTAG
27:26
RO
25:23
RW
22:21
RO
20:8
RW
7
RO
6:0
RW
0x06:
PLL settings
D.6
-
Reserved
Output divider value range from 0 (8’h0) to 7 (8’h7). OD value.
-
Reserved
Feedback multiplication ratio, range from 0 (8’h0) to 4095
(8’h3FF). F value.
-
Reserved
Oscilator input divider value range from 0 (8’h0) to 63 (8’h3F).
R value.
System switch clock divider: 0x07
Sets the ratio of the PLL clock and the switch clock.
0x07:
System
switch clock
divider
Bits
Perm
Init
31:16
RO
-
15:0
RW
0
D.7
Description
Reserved
SSwitch clock generation
Reference clock: 0x08
Sets the ratio of the PLL clock and the reference clock used by the node.
0x08:
Reference
clock
X007786,
Bits
Perm
Init
31:16
RO
-
15:0
RW
3
Description
Reserved
Software ref. clock divider
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
D.8
System JTAG device ID register: 0x09
Bits
0x09:
System JTAG
device ID
register
Perm
31:28
RO
27:12
RO
11:1
RO
0
RO
D.9
0x0A:
System
USERCODE
register
53
Init
Description
System USERCODE register: 0x0A
Bits
Perm
Init
Description
31:18
RO
JTAG USERCODE value programmed into OTP SR
17:0
RO
metal fixable ID code
D.10
Directions 0-7: 0x0C
This register contains eight directions, for packets with a mismatch in bits 7..0 of
the node-identifier. The direction in which a packet will be routed is goverened by
the most significant mismatching bit.
Bits
0x0C:
Directions
0-7
Perm
Init
Description
31:28
RW
0
The direction for packets whose dimension is 7.
27:24
RW
0
The direction for packets whose dimension is 6.
23:20
RW
0
The direction for packets whose dimension is 5.
19:16
RW
0
The direction for packets whose dimension is 4.
15:12
RW
0
The direction for packets whose dimension is 3.
11:8
RW
0
The direction for packets whose dimension is 2.
7:4
RW
0
The direction for packets whose dimension is 1.
3:0
RW
0
The direction for packets whose dimension is 0.
D.11
Directions 8-15: 0x0D
This register contains eight directions, for packets with a mismatch in bits 15..8 of
the node-identifier. The direction in which a packet will be routed is goverened by
the most significant mismatching bit.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bits
0x0D:
Directions
8-15
Perm
54
Init
Description
31:28
RW
0
The direction for packets whose dimension is F.
27:24
RW
0
The direction for packets whose dimension is E.
23:20
RW
0
The direction for packets whose dimension is D.
19:16
RW
0
The direction for packets whose dimension is C.
15:12
RW
0
The direction for packets whose dimension is B.
11:8
RW
0
The direction for packets whose dimension is A.
7:4
RW
0
The direction for packets whose dimension is 9.
3:0
RW
0
The direction for packets whose dimension is 8.
D.12
Reserved: 0x10
Reserved.
Bits
0x10:
Reserved
Perm
Init
Description
31:2
RO
-
Reserved
1
RW
0
Reserved.
0
RW
0
Reserved.
D.13
Reserved.: 0x11
Reserved.
0x11:
Reserved.
Bits
Perm
31:2
RO
-
Reserved
1
RW
0
Reserved.
0
RW
0
Reserved.
D.14
Init
Description
Debug source: 0x1F
Contains the source of the most recent debug event.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
0x1F:
Debug source
Bits
Perm
31:5
RO
55
Init
Description
-
Reserved
4
RW
3:2
RO
1
RW
If set, XCore1 is the source of last GlobalDebug event.
0
RW
If set, XCore0 is the source of last GlobalDebug event.
D.15
Reserved.
-
Reserved
Link status, direction, and network: 0x20 .. 0x28
These registers contain status information for low level debugging (read-only), the
network number that each link belongs to, and the direction that each link is part
of. The registers control links 0..7.
Bits
Perm
Init
RO
25:24
RO
Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 Undefine.
23:16
RO
When the link is in use, this is the destination link number to
which all packets are sent.
15:12
RO
-
11:8
RW
0
7:6
RO
-
5:4
RW
0
3
RO
-
2
RO
1 when the current packet is considered junk and will be thrown
away.
1
RO
1 when the dest side of the link is in use.
0
RO
1 when the source side of the link is in use.
0x20 .. 0x28:
Link status,
direction, and
network
D.16
-
Description
31:26
Reserved
Reserved
The direction that this link operates in.
Reserved
Determines the network to which this link belongs, reset as 0.
Reserved
PLink status and network: 0x40 .. 0x47
These registers contain status information and the network number that each
processor-link belongs to.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
Bits
Perm
56
Init
-
Description
31:26
RO
Reserved
25:24
RO
Identify the SRC_TARGET type 0 - SLink, 1 - PLink, 2 - SSCTL, 3 Undefine.
23:16
RO
When the link is in use, this is the destination link number to
which all packets are sent.
15:6
RO
-
5:4
RW
0
3
RO
-
2
RO
1 when the current packet is considered junk and will be thrown
away.
1
RO
1 when the dest side of the link is in use.
0
RO
1 when the source side of the link is in use.
0x40 .. 0x47:
PLink status
and network
D.17
Reserved
Determines the network to which this link belongs, reset as 0.
Reserved
Link configuration and initialization: 0x80 .. 0x88
These registers contain configuration and debugging information specific to external links. The link speed and width can be set, the link can be initialized, and the
link status can be monitored. The registers control links 0..7.
Bits
0x80 .. 0x88:
Link
configuration
and
initialization
X007786,
Perm
Init
Description
31
RW
Write to this bit with ’1’ will enable the XLink, writing ’0’ will
disable it. This bit controls the muxing of ports with overlapping
xlinks.
30
RW
0
29:28
RO
-
27
RO
26
RO
0
This end of the xlink has issued credit to allow the remote end
to transmit
25
RO
0
This end of the xlink has credit to allow it to transmit.
24
WO
Clear this end of the xlink’s credit and issue a HELLO token.
23
WO
Reset the receiver. The next symbol that is detected will be the
first symbol in a token.
0: operate in 2 wire mode; 1: operate in 5 wire mode
Reserved
Rx buffer overflow or illegal token encoding received.
22
RO
-
21:11
RW
0
Reserved
Specify min. number of idle system clocks between two continuous symbols witin a transmit token -1.
10:0
RW
0
Specify min. number of idle system clocks between two continuous transmit tokens -1.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
D.18
57
Static link configuration: 0xA0 .. 0xA7
These registers are used for static (ie, non-routed) links. When a link is made static,
all traffic is forwarded to the designated channel end and no routing is attempted.
The registers control links C, D, A, B, G, H, E, and F in that order.
Bits
0xA0 .. 0xA7:
Static link
configuration
X007786,
Perm
Init
31
RW
0
30:9
RO
-
8
RW
0
7:5
RO
-
4:0
RW
0
Description
Enable static forwarding.
Reserved
The destination processor on this node that packets received in
static mode are forwarded to.
Reserved
The destination channel end on this node that packets received
in static mode are forwarded to.
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
E
58
JTAG, xSCOPE and Debugging
If you intend to design a board that can be used with the XMOS toolchain and
xTAG debugger, you will need an xSYS header on your board. Figure 35 shows a
decision diagram which explains what type of xSYS connectivity you need. The
three subsections below explain the options in detail.
YES
YES
Is xSCOPE
required
YES
Figure 35:
Decision
diagram for
the xSYS
header
Use full xSYS header
See section 3
E.1
Is debugging
required?
NO
Is fast printf
required ?
NO
YES
Does the SPI
flash need to be
programmed?
NO
NO
Use JTAG xSYS header
See section 2
No xSYS header required
See section 1
No xSYS header
The use of an xSYS header is optional, and may not be required for volume
production designs. However, the XMOS toolchain expects the xSYS header; if you
do not have an xSYS header then you must provide your own method for writing to
flash/OTP and for debugging.
E.2
JTAG-only xSYS header
The xSYS header connects to an xTAG debugger, which has a 20-pin 0.1" female
IDC header. The design will hence need a male IDC header. We advise to use a
boxed header to guard against incorrect plug-ins. If you use a 90 degree angled
header, make sure that pins 2, 4, 6, ..., 20 are along the edge of the PCB.
Connect pins 4, 8, 12, 16, 20 of the xSYS header to ground, and then connect:
· TDI to pin 5 of the xSYS header
· TMS to pin 7 of the xSYS header
· TCK to pin 9 of the xSYS header
· TDO to pin 13 of the xSYS header
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XL210-512-TQ128 Datasheet
59
The RST_N net should be open-drain, active-low, and have a pull-up to VDDIO.
E.3
Full xSYS header
For a full xSYS header you will need to connect the pins as discussed in Section E.2,
and then connect a 2-wire xCONNECT Link to the xSYS header. The links can be
found in the Signal description table (Section 4): they are labelled XL0, XL1, etc in
the function column. The 2-wire link comprises two inputs and outputs, labelled
0
0
1
1
out , out , in , and in . For example, if you choose to use XL0 for xSCOPE I/O, you
need to connect up XL01out , XL00out , XL00in , XL01in as follows:
· XL01out (X0D43) to pin 6 of the xSYS header with a 33R series resistor close to
the device.
· XL00out (X0D42) to pin 10 of the xSYS header with a 33R series resistor close to
the device.
· XL00in (X0D41) to pin 14 of the xSYS header.
· XL01in (X0D40) to pin 18 of the xSYS header.
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
F
60
Schematics Design Check List
This section is a checklist for use by schematics designers using the
XL210-512-TQ128. Each of the following sections contains items to
check for each design.
F.1
Power supplies
The VDD (core) supply ramps monotonically (rises constantly) from 0V
to its final value (0.95V - 1.05V) within 10ms (Section 11).
The VDD (core) supply is capable of supplying 700 mA (Section 11 and
Figure 20).
PLL_AVDD is filtered with a low pass filter, for example an RC filter,
.
see Section 11
F.2
Power supply decoupling
The design has multiple decoupling capacitors per supply, for example
at least four0402 or 0603 size surface mount capacitors of 100nF in
value, per supply (Section 11).
A bulk decoupling capacitor of at least 10uF is placed on each supply
(Section 11).
F.3
Power on reset
The RST_N and TRST_N pins are asserted (low) until all supplies are
good. There is enough time between VDDIO power good and RST_N
to allow any boot flash to settle.
F.4
Clock
The CLK input pin is supplied with a clock with monotonic rising edges
and low jitter.
You have chosen an input clock frequency that is supported by the
device (Section 7).
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XL210-512-TQ128 Datasheet
F.5
61
Boot
The device is connected to a QSPI flash for booting, connected to
X0D01, X0D04..X0D07, and X0D10 (Section 8). If not, you must boot
the device through OTP or JTAG, or set it to boot from SPI and connect
a SPI flash.
The Flash that you have chosen is supported by xflash, or you have
created a specification file for it.
F.6
JTAG, XScope, and debugging
You have decided as to whether you need an XSYS header or not
(Section E)
If you have not included an XSYS header, you have devised a method
to program the SPI-flash or OTP (Section E).
F.7
GPIO
You have not mapped both inputs and outputs to the same multi-bit
port.
Pins X0D04, X0D05, X0D06, and X0D07 are output only and are,
during and after reset, pulled high and low appropriately (Section 8)
F.8
Multi device designs
Skip this section if your design only includes a single XMOS device.
One device is connected to a QSPI or SPI flash for booting.
Devices that boot from link have, for example, X0D06 pulled high and
have link XL0 connected to a device to boot from (Section 8).
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XL210-512-TQ128 Datasheet
G
62
PCB Layout Design Check List
This section is a checklist for use by PCB designers using the XS2-L10A512-TQ128. Each of the following sections contains items to check for
each design.
G.1
Ground Plane
Multiple vias (eg, 9) have been used to connect the center pad to the
PCB ground plane. These minimize impedance and conduct heat away
from the device. (Section 11.2).
Other than ground vias, there are no (or only a few) vias underneath
or closely around the device. This create a good, solid, ground plane.
G.2
Power supply decoupling
The decoupling capacitors are all placed close to a supply pin (Section 11).
The decoupling capacitors are spaced around the device (Section 11).
The ground side of each decoupling capacitor has a direct path back
to the center ground of the device.
G.3
PLL_AVDD
The PLL_AVDD filter (especially the capacitor) is placed close to the
PLL_AVDD pin (Section 11).
X007786,
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XL210-512-TQ128 Datasheet
H
63
Associated Design Documentation
Document Title
Information
Document
Estimating Power Consumption For
XS1-L Devices
Power consumption
Link
XMOS Programming Guide
Timers, ports, clocks, cores and
channels
Link
xTIMEcomposer User Guide
Compilers, assembler and
linker/mapper
Link
Timing analyzer, xScope, debugger
Flash and OTP programming utilities
I
Related Documentation
Document Title
Information
Document
xCORE200: the XMOS XS2
Architecture
ISA manual
Link
I/O timings for xCORE200
Port timings
Link
xCONNECT Architecture
Link, switch and system information
Link
XS1-L Link Performance and Design
Guidelines
Link timings
Link
XS1-L Clock Frequency Control
Advanced clock control
Link
XS1-L Active Power Conservation
Low-power mode during idle
Link
X007786,
XS2-L10A-512-TQ128
XL210-512-TQ128 Datasheet
J
64
Revision History
Date
Description
2015-03-20
Preliminary release
2015-04-14
Added RST to pins to be pulled hard, and removed reference to TCK from Errata
Removed TRST_N references in packages that have no TRST_N
2015-04-29
VDDIOR and VDD (pins 47/48) switched - Section 3
2015-05-06
Removed references to DEBUG_N
2015-07-09
Updated electrical characteristics - Section 12
2015-08-27
Updated part marking - Section 14
2016-04-20
Typical internal pull-up and pull down current diagrams added - Section 12
2017-02-02
Clarified available boot modes/source pins - Section 8
2017-09-19
Added Absolute Maximum Ratings - Section 12.1
Reference document links updated - Section H
2018-03-23
Incorrect IDCODE return value updated - Section 10
Updated package information - Section 13
2018-09-05
Power up and reset requirements updated - Section 11
Link to IPC-7351B document updated - Section 11.1
Copyright © 2018, All Rights Reserved.
Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and
is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in
relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation
thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any
such claims.
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XS2-L10A-512-TQ128
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