XS1-A10A-128-FB217-C8

XS1-A10A-128-FB217 Datasheet 2015/04/14 XMOS © 2015, All Rights Reserved Document Number: X2625, XS1-A10A-128-FB217 Datasheet 1 Table of Contents 1 xCORE Multicore Microcontrollers . . 2 XS1-A10A-128-FB217 Features . . . 3 Pin Configuration . . . . . . . . . . . 4 Signal Description . . . . . . . . . . . 5 Example Application Diagram . . . . 6 Product Overview . . . . . . . . . . . 7 xCORE Tile Resources . . . . . . . . . 8 Oscillator . . . . . . . . . . . . . . . . 9 Boot Procedure . . . . . . . . . . . . . 10 Memory . . . . . . . . . . . . . . . . . 11 Analog-to-Digital Converter . . . . . 12 Supervisor Logic . . . . . . . . . . . . 13 Energy management . . . . . . . . . 14 JTAG . . . . . . . . . . . . . . . . . . . 15 Board Integration . . . . . . . . . . . 16 Example XS1-A10A-128-FB217 Board 17 DC and Switching Characteristics . . 18 Package Information . . . . . . . . . 19 Ordering Information . . . . . . . . . Appendices . . . . . . . . . . . . . . . . . . A Configuring the device . . . . . . . . B Processor Status Configuration . . . C xCORE Tile Configuration . . . . . . D Digital Node Configuration . . . . . . E Analogue Node Configuration . . . . F ADC Configuration . . . . . . . . . . G Deep sleep memory Configuration . H Oscillator Configuration . . . . . . . I Real time clock Configuration . . . . J Power control block Configuration . K XMOS USB Interface . . . . . . . . . . L Device Errata . . . . . . . . . . . . . . M JTAG, xSCOPE and Debugging . . . . N Schematics Design Check List . . . . O PCB Layout Design Check List . . . . P Associated Design Documentation . Q Related Documentation . . . . . . . . R Revision History . . . . . . . . . . . . X2625, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 5 6 10 11 12 15 17 19 20 21 21 24 25 28 32 37 38 39 39 42 51 58 65 69 73 74 76 76 89 89 90 92 94 95 95 96 XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 2 TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/. XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation that the information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used without written permission. Company and product names mentioned in this document are the trademarks or registered trademarks of their respective owners. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 1 3 xCORE Multicore Microcontrollers Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAG debug Hardware response ports xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCONNECT channels, links I/O pins xCORE logical core xCORE logical core Multichannel ADC I/O pins PLL xCONNECT: channels, links The XS1-A Series is a comprehensive range of 32-bit multicore microcontrollers that brings the low latency and timing determinism of the xCORE architecture to mainstream embedded applications. Unlike conventional microcontrollers, xCORE multicore microcontrollers execute multiple real-time tasks simultaneously and communicate between tasks using a high speed network. Because xCORE multicore microcontrollers are completely deterministic, you can write software to implement functions that traditionally require dedicated hardware. DC-DC PMIC xCORE logical core Hardware response ports xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core Figure 1: XS1-A Series:6-16 core devices xCONNECT channels, links I/O pins xCORE logical core xCORE logical core xCORE logical core PLL Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAG debug Key features of the XS1-A10A-128-FB217 include: · Tiles: Devices consist of one or more xCORE tiles. Each tile contains between four and eight 32-bit xCOREs with highly integrated I/O and on-chip memory. · Logical cores Each logical core can execute tasks such as computational code, DSP code, control software (including logic decisions and executing a state machine) or software that handles I/O. Section 7.1 · xTIME scheduler The xTIME scheduler performs functions similar to an RTOS, in hardware. It services and synchronizes events in a core, so there is no requirement for interrupt handler routines. The xTIME scheduler triggers cores on events generated by hardware resources such as the I/O pins, communication channels and timers. Once triggered, a core runs independently and concurrently to other cores, until it pauses to wait for more events. Section 7.2 X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 4 · Channels and channel ends Tasks running on logical cores communicate using channels formed between two channel ends. Data can be passed synchronously or asynchronously between the channel ends assigned to the communicating tasks. Section 7.5 · xCONNECT Switch and Links Between tiles, channel communications are implemented over a high performance network of xCONNECT Links and routed through a hardware xCONNECT Switch. Section 7.6 · Ports The I/O pins are connected to the processing cores by Hardware Response ports. The port logic can drive its pins high and low, or it can sample the value on its pins optionally waiting for a particular condition. Section 7.3 · Clock blocks xCORE devices include a set of programmable clock blocks that can be used to govern the rate at which ports execute. Section 7.4 · Memory Each xCORE Tile integrates a bank of SRAM for instructions and data, and a block of one-time programmable (OTP) memory that can be configured for system wide security features. Section 10 · PLL The PLL is used to create a high-speed processor clock given a low speed external oscillator. Section 8 · JTAG The JTAG module can be used for loading programs, boundary scan testing, in-circuit source-level debugging and programming the OTP memory. Section 14 1.1 Software Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS provides tested and proven software libraries, which allow you to quickly add interface and processor functionality such as USB, Ethernet, PWM, graphics driver, and audio EQ to your applications. 1.2 xTIMEcomposer Studio The xTIMEcomposer Studio development environment provides all the tools you need to write and debug your programs, profile your application, and write images into flash memory or OTP memory on the device. Because xCORE devices operate deterministically, they can be simulated like hardware within xTIMEcomposer: uniquely in the embedded world, xTIMEcomposer Studio therefore includes a static timing analyzer, cycle-accurate simulator, and high-speed in-circuit instrumentation. xTIMEcomposer can be driven from either a graphical development environment, or the command line. The tools are supported on Windows, Linux and MacOS X and available at no cost from xmos.com/downloads. Information on using the tools is provided in the xTIMEcomposer User Guide, X3766. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 2 5 XS1-A10A-128-FB217 Features · Multicore Microcontroller with Advanced Multi-Core RISC Architecture • 10 real-time logical cores on 2 xCORE tiles • Cores share up to 1000 MIPS • Each logical core has: — Guaranteed throughput of between 1/4 and 1/5 of tile MIPS — 16x32bit dedicated registers • 159 high-density 16/32-bit instructions — All have single clock-cycle execution (except for divide) — 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions · 12b 1MSPS 8-channel SAR Analog-to-Digital Converter · 1 x LDO · 2 x DC-DC converters and Power Management Unit · Watchdog Timer · Onchip clocks/oscillators • Crystal oscillator • 20MHz/31kHz silicon oscillators · Programmable I/O • 90 general-purpose I/O pins, configurable as input or output — Up to 32 x 1bit port, 12 x 4bit port, 8 x 8bit port, 4 x 16bit port — 4 xCONNECT links • Port sampling rates of up to 60 MHz with respect to an external clock • 64 channel ends for communication with other cores, on or off-chip · Memory • 128KB internal single-cycle SRAM (max 64KB per tile) for code and data storage • 16KB internal OTP (max 8KB per tile) for application boot code • 128 bytes Deep Sleep Memory · Hardware resources • 12 clock blocks (6 per tile) • 20 timers (10 per tile) • 8 locks (4 per tile) · JTAG Module for On-Chip Debug · Security Features • Programming lock disables debug and prevents read-back of memory contents • AES bootloader ensures secrecy of IP held on external flash memory · Ambient Temperature Range • Commercial qualification: 0 °C to 70 °C • Industrial qualification: -40 °C to 85 °C · Speed Grade • 10: 1000 MIPS • 8: 800 MIPS · Power Consumption (typical) • 600 mW at 500 MHz (typical) • Sleep Mode: 500 µW · 217-pin FBGA package 0.8 mm pitch X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 3 6 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A 1A 4A 4B 4B 4A 1C 1E 4C 4D 4D 4C 1G 1I 1J 4E 4F 4F 4E X0D00 X0D02 X0D04 X0D06 X0D08 X0D10 X0D12 X0D14 X0D16 X0D18 X0D20 X0D22 X0D24 X0D25 X0D26 X0D28 X0D30 X0D32 B 1B 4A 4B 4B 4A 1D 1F 4C 4D 4D 4C 1H 32A 4F 4F 4E 1M X0D03 X0D05 X0D07 X0D09 X0D11 X0D13 X0D15 X0D17 X0D19 X0D21 X0D23 X0D70 ADC_ SAMPLE 4E X0D01 X0D27 X0D29 X0D31 X0D33 X0D36 C DEBUG_ N 1O 1N TDO X0D38 X0D37 D 8D 1P TCK RST_N X0D40 X0D39 E 8D 8D TMS TDI X0D42 X0D41 F MODE[2] MODE[3] GND GND GND GND GND GND GND GND GND X0D34 G 1A 1L AVDD ADC7 GND GND GND GND GND GND GND GND GND X1D00 X0D35 H 4A 1B ADC5 ADC6 GND GND GND GND GND GND GND GND GND X1D02 X1D01 J 4B 4A ADC3 ADC4 AVSS GND GND GND GND GND GND GND GND X1D04 X1D03 K 4B 4B ADC1 ADC2 MODE[0] MODE[1] GND GND GND GND GND GND GND X1D06 X1D05 L 4B ADC0 OSC_ EXT_N 4A NC MODE[4] GND GND GND GND GND GND GND X1D08 X1D07 M XI/ CLK 1C 4A NC NC NC GND GND GND GND GND GND GND X1D10 X1D09 N 1E 1D XO NC NC NC GND GND GND GND GND GND GND X1D12 X1D11 P 4C 1F NC VSUP GND GND GND GND GND GND GND GND GND X1D14 X1D13 R 4D 4C SW1 SW1 X1D16 X1D15 T 4D 4D SW1 VDDCORE X1D18 X1D17 U 4C 4D VDDCORE VDDCORE X1D20 X1D19 V 1L 8D 8D 1P 1N 4E 4F 4F 4E 1J 1G 4C PGND PGND VDDIO PGND VDD1V8 SW2 NC X1D35 X1D43 X1D41 X1D39 X1D37 X1D33 X1D31 X1D29 X1D27 X1D25 X1D22 X1D21 W 1K 8D 8D 1O 1M 4E 4F 4F 4E 1I 32A 1H VSUP VSUP VDDIO PGND VDD1V8 SW2 NC X1D34 X1D42 X1D40 X1D38 X1D36 X1D32 X1D30 X1D28 X1D26 X1D24 X1D70 X1D23 X2625, 1K VDDIO_ OUT 8D X0D43/ WAKE XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 4 7 Signal Description This section lists the signals and I/O pins available on the XS1-A10A-128-FB217. The device provides a combination of 1bit, 4bit, 8bit and 16bit ports, as well as wider ports that are fully or partially (gray) bonded out. All pins of a port provide either output or input, but signals in different directions cannot be mapped onto the same port. Pins may have one or more of the following properties: · PD/PU: The IO pin a weak pull-down or pull-up resistor. On GPIO pins this resistor can be enabled. · ST: The IO pin has a Schmitt Trigger on its input. Power pins (10) Signal Function Type AVSS Digital ground GND GND Digital ground GND PGND Power ground GND SW1 DCDC1 switched output voltage PWR SW2 DCDC2 switched output voltage PWR VDD1V8 1v8 voltage supply PWR VDDCORE Core voltage supply PWR VDDIO Digital I/O power PWR VDDIO_OUT Digital I/O power out PWR VSUP Power supply (3V3/5V0) PWR Signal Function Type ADC0 Analog input Input ADC1 Analog input Input ADC2 Analog input Input ADC3 Analog input Input ADC4 Analog input Input ADC5 Analog input Input ADC6 Analog input Input ADC7 Analog input Input ADC_SAMPLE Sample Analog input I/O AVDD Supply and reference voltage PWR Properties Analog pins (10) Properties (continued) X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 8 Signal Function Type Properties Signal Function Type Properties MODE[4:0] Boot mode select Input PU, ST OSC_EXT_N Use Silicon Oscillator Input ST XI/CLK Crystal Oscillator/Clock Input Input XO Crystal Oscillator Output Output Signal Function Type Properties DEBUG_N Multi-chip debug I/O PU TCK Test clock Input PU, ST TDI Test data input Input PU, ST TDO Test data output Output PD, OT TMS Test mode select Input PU, ST Clocks pins (4) JTAG pins (5) Misc pins (1) Signal Function Type Properties RST_N Global reset input Input PU, ST Signal Function I/O pins (90) X0D00 Type Properties 1A0 I/O PDS , RS 1B0 I/O PDS , RS X0D01 XLA4 out X0D02 XLA3 out 4A0 8A0 16A0 32A20 I/O PDS , RU X0D03 XLA2 out 4A1 8A1 16A1 32A21 I/O PDS , RU X0D04 XLA1 out 4B0 8A2 16A2 32A22 I/O PDS , RU X0D05 XLA0 out 4B1 8A3 16A3 32A23 I/O PDS , RU X0D06 XLA0 in 4B2 8A4 16A4 32A24 I/O PDS , RU X0D07 XLA1 in 4B3 8A5 16A5 32A25 I/O PDS , RU X0D08 XLA2 in 4A2 8A6 16A6 32A26 I/O PDS , RU X0D09 XLA3 in 4A3 8A7 16A7 32A27 I/O PDS , RU X0D10 XLA4 in 1C0 I/O PDS , RS X0D11 1D0 I/O PDS , RS X0D12 1E0 I/O PDS , RU 1F0 I/O PDS , RU X0D13 XLB4 out X0D14 XLB3 out 4C0 8B0 16A8 32A28 I/O PDS , RU X0D15 XLB2 out 4C1 8B1 16A9 32A29 I/O PDS , RU X0D16 XLB1 out 4D0 8B2 16A10 I/O PDS , RU (continued) X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 9 Signal Function Type Properties X0D17 XLB0 out 4D1 8B3 16A11 I/O PDS , RU X0D18 XLB0 in 4D2 8B4 16A12 I/O PDS , RU X0D19 XLB1 in 4D3 8B5 16A13 I/O PDS , RU X0D20 XLB2 in 4C2 8B6 16A14 32A30 I/O PDS , RU X0D21 XLB3 in 4C3 8B7 16A15 32A31 I/O PDS , RU X0D22 XLB4 in 1G0 I/O PDS , RU X0D23 1H0 I/O PDS , RU X0D24 1I0 I/O PDS X0D25 1J0 I/O PDS X0D26 4E0 8C0 16B0 I/O PDS , RU X0D27 4E1 8C1 16B1 I/O PDS , RU X0D28 4F0 8C2 16B2 I/O PDS , RU X0D29 4F1 8C3 16B3 I/O PDS , RU X0D30 4F2 8C4 16B4 I/O PDS , RU X0D31 4F3 8C5 16B5 I/O PDS , RU X0D32 4E2 8C6 16B6 I/O PDS , RU X0D33 4E3 8C7 16B7 I/O PDS , RU X0D34 1K0 I/O PDS X0D35 1L0 I/O PDS X0D36 1M0 8D0 16B8 I/O PDS X0D37 1N0 8D1 16B9 I/O PDS , RU X0D38 1O0 8D2 16B10 I/O PDS , RU X0D39 1P0 8D3 16B11 I/O PDS , RU X0D40 8D4 16B12 I/O PDS , RU X0D41 8D5 16B13 I/O PDS , RU X0D42 8D6 16B14 I/O PDS , RU X0D43/WAKE 8D7 16B15 I/O PUS , RU I/O PDS 1A0 I/O PDS , RS 1B0 I/O PDS , RS 32A19 X0D70 X1D00 X1D01 XLA4 out X1D02 XLA3 out 4A0 8A0 16A0 32A20 I/O PDS , RU X1D03 XLA2 out 4A1 8A1 16A1 32A21 I/O PDS , RU X1D04 XLA1 out 4B0 8A2 16A2 32A22 I/O PDS , RU X1D05 XLA0 out 4B1 8A3 16A3 32A23 I/O PDS , RU X1D06 XLA0 in 4B2 8A4 16A4 32A24 I/O PDS , RU X1D07 XLA1 in 4B3 8A5 16A5 32A25 I/O PDS , RU X1D08 XLA2 in 4A2 8A6 16A6 32A26 I/O PDS , RU X1D09 XLA3 in 4A3 8A7 16A7 32A27 I/O PDS , RU X1D10 XLA4 in 1C0 I/O PDS , RS X1D11 1D0 I/O PDS , RS X1D12 1E0 I/O PDS , RU 1F0 I/O PDS , RU I/O PDS , RU X1D13 XLB4 out X1D14 XLB3 out 4C0 8B0 16A8 32A28 (continued) X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Signal Function X1D15 XLB2 out 4C1 8B1 16A9 Type Properties I/O X1D16 XLB1 out 4D0 8B2 PDS , RU 16A10 I/O X1D17 XLB0 out 4D1 PDS , RU 8B3 16A11 I/O X1D18 XLB0 in PDS , RU 4D2 8B4 16A12 I/O X1D19 PDS , RU XLB1 in 4D3 8B5 16A13 I/O PDS , RU X1D20 XLB2 in 4C2 8B6 16A14 32A30 I/O PDS , RU X1D21 XLB3 in 4C3 8B7 16A15 32A31 I/O PDS , RU X1D22 XLB4 in 1G0 I/O PDS , RU X1D23 1H0 I/O PDS , RU X1D24 1I0 I/O PDS X1D25 1J0 I/O PDS 32A29 X1D26 4E0 8C0 16B0 I/O PDS , RU X1D27 4E1 8C1 16B1 I/O PDS , RU X1D28 4F0 8C2 16B2 I/O PDS , RU X1D29 4F1 8C3 16B3 I/O PDS , RU X1D30 4F2 8C4 16B4 I/O PDS , RU X1D31 4F3 8C5 16B5 I/O PDS , RU X1D32 4E2 8C6 16B6 I/O PDS , RU X1D33 4E3 8C7 16B7 I/O PDS , RU X1D34 1K0 I/O PDS X1D35 1L0 I/O PDS X1D36 1M0 8D0 16B8 I/O PDS X1D37 1N0 8D1 16B9 I/O PDS , RU X1D38 1O0 8D2 16B10 I/O PDS , RU X1D39 1P0 8D3 16B11 I/O PDS , RU X1D40 8D4 16B12 I/O PDS , RU X1D41 8D5 16B13 I/O PDS , RU X1D42 8D6 16B14 I/O PDS , RU X1D43 8D7 16B15 I/O PUS , RU I/O PDS X1D70 X2625, 10 32A19 XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 5 11 Example Application Diagram 3V3 3V3 C10 100N G1 3V3 U1A AVDD C9 GND W1 W2 P2 C1 4U7 GND C2 100N GND F6 . . . . . . . . . . . . . . K14 C3 100N GND Figure 2: Simplified Reference Schematic GND X2625, VSUP VSUP VSUP VSS . . . . . . . . . . . . . . VSS XS1-A16A-128-FB217 VDDIO VDDIO VDDCORE VDDCORE VDDCORE SW1 SW1 SW1 V3 W3 GND T2 U1 U2 R1 R2 T1 VDD1V8 VDD1V8 V5 W5 SW2 SW2 V6 W6 PGND PGND PGND PGND 100N L1 4U7 L2 4U7 V1 V2 V4 W4 GND C4 C5 22U 22U GND GND XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 6 12 Product Overview Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAG debug xCORE logical core 2 Channels xCORE logical core 1 xCORE logical core 3 xCONNECT Links I/O pins xCORE logical core 0 Hardware response ports xCORE logical core 4 Multichannel ADC Oscillator Real-time clock I/O pins PLL xCONNECT: channels, links The XS1-A10A-128-FB217 comprises a digital and an analog node, as shown in Figure 3. The digital node comprises an xCORE Tile, a Switch, and a PLL (Phaselocked-loop). The analog node comprises a multi-channel ADC (Analog to Digital Converter), deep sleep memory, an oscillator, a real-time counter, and power supply control. Supervisor Watchdog, brown out PowerOnRST DC-DC PMIC xCORE logical core 1 xCORE logical core 2 xCORE logical core 3 Figure 3: Block Diagram Channels Hardware response ports xCONNECT Links I/O pins xCORE logical core 0 xCORE logical core 4 PLL Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAG debug All communication between the digital and analog node takes place over a link that is connected to the Switch of the digital node. As such, the analog node can be controlled from any node on the system. The analog functions can be configured using a set of node configuration registers, and a set of registers for each of the peripherals. The device can be programmed using high-level languages such as C/C++ and the XMOS-originated XC language, which provides extensions to C that simplify the control over concurrency, I/O and timing, or low-level assembler. 6.1 XCore Tile The xCORE Tile is a flexible multicore microcontroller component with tightly integrated I/O and on-chip memory. The tile contains multiple logical cores that run simultaneously, each of which is guaranteed a slice of processing power and can execute computational code, control software and I/O interfaces. The logical cores use channels to exchange data within a tile or across tiles. The tiles are connected via an integrated switch network, called xCONNECT, which uses a X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 13 proprietary physical layer protocol and can also be used to add additional resources to a design. The I/O pins are driven using intelligent ports that can serialize data, interpret strobe signals and wait for scheduled times or events, making the device ideal for real-time control applications. 6.2 ADC and Power Management Each XS1-A10A-128-FB217 device includes a set of analog components, including a 12b, 8-channel ADC, power management unit, watchdog timer, real-time counter and deep sleep memory. The device reduces the number of additional external components required and allows designs to be implemented using simple 2-layer boards. 7 xCORE Tile Resources 7.1 Logical cores Each tile has 5 active logical cores, which issue instructions down a shared fourstage pipeline. Instructions from the active cores are issued round-robin. If up to four logical cores are active, each core is allocated a quarter of the processing cycles. If more than four logical cores are active, each core is allocated at least 1/n cycles (for n cores). Figure 4 shows the guaranteed core performance depending on the number of cores used. Speed Figure 4: Logical core performance MIPS Frequency grade Minimum MIPS per core (for n cores) 1 2 3 4 5 8 800 MIPS 400 MHz 100 100 100 100 80 10 1000 MIPS 500 MHz 125 125 125 125 100 There is no way that the performance of a logical core can be reduced below these predicted levels. Because cores may be delayed on I/O, however, their unused processing cycles can be taken by other cores. This means that for more than four logical cores, the performance of each core is often higher than the predicted minimum but cannot be guaranteed. The logical cores are triggered by events instead of interrupts and run to completion. A logical core can be paused to wait for an event. 7.2 xTIME scheduler The xTIME scheduler handles the events generated by xCORE Tile resources, such as channel ends, timers and I/O pins. It ensures that all events are serviced and synchronized, without the need for an RTOS. Events that occur at the I/O pins are handled by the Hardware-Response ports and fed directly to the appropriate xCORE Tile. An xCORE Tile can also choose to wait for a specified time to elapse, or for data to become available on a channel. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 14 Tasks do not need to be prioritised as each of them runs on their own logical xCORE. It is possible to share a set of low priority tasks on a single core using cooperative multitasking. 7.3 Hardware Response Ports Hardware Response ports connect an xCORE tile to one or more physical pins and as such define the interface between hardware attached to the XS1-A10A-128FB217, and the software running on it. A combination of 1bit, 4bit, 8bit, 16bit and 32bit ports are available. All pins of a port provide either output or input. Signals in different directions cannot be mapped onto the same port. reference clock readyOut conditional value clock port clock block readyIn port port counter port logic stamp/time PORT FIFO PINS Figure 5: Port block diagram port value output (drive) SERDES transfer register CORE input (sample) The port logic can drive its pins high or low, or it can sample the value on its pins, optionally waiting for a particular condition. Ports are accessed using dedicated instructions that are executed in a single processor cycle. Data is transferred between the pins and core using a FIFO that comprises a SERDES and transfer register, providing options for serialization and buffered data. Each port has a 16-bit counter that can be used to control the time at which data is transferred between the port value and transfer register. The counter values can be obtained at any time to find out when data was obtained, or used to delay I/O until some time in the future. The port counter value is automatically saved as a timestamp, that can be used to provide precise control of response times. The ports and xCONNECT links are multiplexed onto the physical pins. If an xConnect Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their specified width, even if they share pins with another port. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 7.4 15 Clock blocks xCORE devices include a set of programmable clocks called clock blocks that can be used to govern the rate at which ports execute. Each xCORE tile has six clock blocks: the first clock block provides the tile reference clock and runs at a default frequency of 100MHz; the remaining clock blocks can be set to run at different frequencies. 100MHz reference clock divider 1-bit port ... ... readyIn clock block Figure 6: Clock block diagram port counter A clock block can use a 1-bit port as its clock source allowing external application clocks to be used to drive the input and output interfaces. In many cases I/O signals are accompanied by strobing signals. The xCORE ports can input and interpret strobe (known as readyIn and readyOut) signals generated by external sources, and ports can generate strobe signals to accompany output data. On reset, each port is connected to clock block 0, which runs from the processor reference clock. 7.5 Channels and Channel Ends Logical cores communicate using point-to-point connections, formed between two channel ends. A channel-end is a resource on an xCORE tile, that is allocated by the program. Each channel-end has a unique system-wide identifier that comprises a unique number and their tile identifier. Data is transmitted to a channel-end by an output-instruction; and the other side executes an input-instruction. Data can be passed synchronously or asynchronously between the channel ends. 7.6 xCONNECT Switch and Links XMOS devices provide a scalable architecture, where multiple xCORE devices can be connected together to form one system. Each xCORE device has an xCONNECT interconnect that provides a communication infrastructure for all tasks that run on the various xCORE tiles on the system. The interconnect relies on a collection of switches and XMOS links. Each xCORE device has an on-chip switch that can set up circuits or route data. The switches are connected by xConnect Links. An XMOS link provides a physical connection X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 16 xCONNECT Link to another device switch CORE CORE CORE CORE CORE CORE CORE CORE CORE CORE xCONNECT switch CORE CORE Figure 7: Switch, links and channel ends CORE CORE xCORE Tile CORE CORE xCORE Tile between two switches. The switch has a routing algorithm that supports many different topologies, including lines, meshes, trees, and hypercubes. The links operate in either 2 wires per direction or 5 wires per direction mode, depending on the amount of bandwidth required. Circuit switched, streaming and packet switched data can both be supported efficiently. Streams provide the fastest possible data rates between tiles , but each stream requires a single link to be reserved between switches on two tiles. All packet communications can be multiplexed onto a single link. Information on the supported routing topologies that can be used to connect multiple devices together can be found in the XS1-L Link Performance and Design Guide, X2999. 8 Oscillator The oscillator block provides: · An oscillator circuit. Together with an external resonator (crystal or ceramic), the oscillator circuit can provide a clock-source for both the real-time counter and the xCORE Tile. The external resonator can be chosen by the designer to have the appropriate frequency and accuracy. If desired, an external oscillator can be used on the XI/CLK input pin, this must be a 1.8 V oscillator. · A 20 MHz silicon oscillator. This enables the device to boot and execute code without requiring an external crystal. The silicon oscillator is not as accurate as an external crystal. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 17 · A 31,250 Hz oscillator. This enables the real-time counter to operate whilst the device is in low-power mode. This oscillator is not as accurate as an external crystal. The oscillator can be controlled through package pins, a set of peripheral registers, and a digital node control register. A package pin OSC_EXT_N is used to select the oscillator to use on boot. It must be grounded to select an external resonator or connected to VDDIO to select the on-chip 20 MHz oscillator. If an external resonator is used, then it must be in the range 5-100 MHz. Two more package pins, MODE0 and MODE1 are used to inform the node of the frequency. The analog node runs at the frequency provided by the oscillator. Hence, increasing the clock frequency will speed up operation of the analog node, and will speed up communicating data with the digital node. The digital node has a PLL. The PLL creates a high-speed clock that is used for the switch, tile, and reference clock. The PLL multiplication value is selected through the two MODE pins, and can be changed by software to speed up the tile or use less power. The MODE pins are set as shown in Figure 8: Figure 8: PLL multiplier values and MODE pins Oscillator Frequency 5-13 MHz 13-20 MHz 20-48 MHz 48-100 MHz MODE 1 0 0 0 1 1 1 0 0 1 Tile Frequency 130-399.75 MHz 260-400.00 MHz 167-400.00 MHz 196-400.00 MHz PLL Ratio 30.75 20 8.33 4 PLL settings OD F R 1 122 0 2 119 0 2 49 0 2 23 0 Figure 8 also lists the values of OD, F and R, which are the registers that define the ratio of the tile frequency to the oscillator frequency: Fcor e = Fosc × F +1 1 1 × × 2 R+1 OD + 1 OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and F +1 1 260MHz ≤ Fosc × 2 × R+1 ≤ 1.3GHz. The OD, F , and R values can be modified by writing to the digital node PLL configuration register. The MODE pins must be held at a static value during and after deassertion of the system reset. If a different tile frequency is required (eg, 500 MHz), then the PLL must be reprogrammed after boot to provide the required tile frequency. The XMOS tools perform this operation by default. Further details on configuring the clock can be found in the XS1-L Clock Frequency Control document, X1433. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 9 18 Boot Procedure The device is kept in reset by driving RST_N low. When in reset, all GPIO pins are high impedance. When the device is taken out of reset by releasing RST_N the processor starts its internal reset process. After approximately 750,000 input clocks, all GPIO pins have their internal pull-resistor enabled, and the processor boots at a clock speed that depends on MODE0 and MODE1. The processor boot procedure is illustrated in Figure 9. In normal usage, MODE[4:2] controls the boot source according to the table in Figure 10. If bit 5 of the security register (see §10.1) is set, the device boots from OTP. Start Boot ROM Primary boot Security Register Bit [5] set No Yes Copy OTP contents to base of SRAM OTP Figure 9: Boot procedure Figure 10: Boot source pins Boot according to boot source pins Execute program MODE MODE MODE [4] [3] [2] Boot Source X 0 0 None: Device waits to be booted via JTAG X 0 1 Reserved 0 1 0 Tile0 boots from link B, Tile1 from channel end 0 via Tile0 0 1 1 Tile0 boots from SPI, Tile1 from channel end 0 via Tile0 1 1 0 Tile0 and Tile1 independently enable link B and internal links (E, F, G, H), and boot from channel end 0 1 1 1 Tile0 and Tile 1 boot from SPI independently The boot image has the following format: · A 32-bit program size s in words. · Program consisting of s × 4 bytes. · A 32-bit CRC, or the value 0x0D15AB1E to indicate that no CRC check should be performed. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 19 The program size and CRC are stored least significant byte first. The program is loaded into the lowest memory address of RAM, and the program is started from that address. The CRC is calculated over the byte stream represented by the program size and the program itself. The polynomial used is 0xEDB88320 (IEEE 802.3); the CRC register is initialized with 0xFFFFFFFF and the residue is inverted to produce the CRC. 9.1 Boot from SPI master If set to boot from SPI master, the processor enables the four pins specified in Figure 11, and drives the SPI clock at 2.5 MHz (assuming a 400 MHz core clock). A READ command is issued with a 24-bit address 0x000000. The clock polarity and phase are 0 / 0. Figure 11: SPI master pins Pin Signal Description X0D00 MISO Master In Slave Out (Data) X0D01 SS Slave Select X0D10 SCLK Clock X0D11 MOSI Master Out Slave In (Data) The xCORE Tile expects each byte to be transferred with the least-significant bit first. Programmers who write bytes into an SPI interface using the most significant bit first may have to reverse the bits in each byte of the image stored in the SPI device. If a large boot image is to be read in, it is faster to first load a small boot-loader that reads the large image using a faster SPI clock, for example 50 MHz or as fast as the flash device supports. The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. If required, an SPI boot program can be burned into OTP that uses different pins. 9.2 Boot from xConnect Link If set to boot from an xConnect Link, the processor enables Link B around 200 ns after the boot process starts. Enabling the Link switches off the pull-down on resistors X0D16..X0D19, drives X0D16 and X0D17 low (the initial state for the Link), and monitors pins X0D18 and X0D19 for boot-traffic. X0D18 and X0D19 must be low at this stage. If the internal pull-down is too weak to drain any residual charge, external pull-downs of 10K may be required on those pins. The boot-rom on the core will then: 1. Allocate channel-end 0. 2. Input a word on channel-end 0. It will use this word as a channel to acknowledge the boot. Provide the null-channel-end 0x0000FF02 if no acknowledgment is required. 3. Input the boot image specified above, including the CRC. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 20 4. Input an END control token. 5. Output an END control token to the channel-end received in step 2. 6. Free channel-end 0. 7. Jump to the loaded code. 9.3 Boot from OTP If an xCORE tile is set to use secure boot (see Figure 9), the boot image is read from address 0 of the OTP memory in the tile’s security module. This feature can be used to implement a secure bootloader which loads an encrypted image from external flash, decrypts and CRC checks it with the processor, and discontinues the boot process if the decryption or CRC check fails. XMOS provides a default secure bootloader that can be written to the OTP along with secret decryption keys. Each tile has its own individual OTP memory, and hence some tiles can be booted from OTP while others are booted from SPI or the channel interface. This enables systems to be partially programmed, dedicating one or more tiles to perform a particular function, leaving the other tiles user-programmable. 9.4 Security register The security register enables security features on the xCORE tile. The features shown in Figure 12 provide a strong level of protection and are sufficient for providing strong IP security. 10 Memory 10.1 OTP Each xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with a security register that configures system wide security features. The OTP holds data in four sectors each containing 512 rows of 32 bits which can be used to implement secure bootloaders and store encryption keys. Data for the security register is loaded from the OTP on power up. All additional data in OTP is copied from the OTP to SRAM and executed first on the processor. The OTP memory is programmed using three special I/O ports: the OTP address port is a 16-bit port with resource ID 0x100200, the OTP data is written via a 32-bit port with resource ID 0x200100, and the OTP control is on a 16-bit port with ID 0x100300. Programming is performed through libotp and xburn. 10.2 SRAM Each xCORE Tile integrates a single 64KB SRAM bank for both instructions and data. All internal memory is 32 bits wide, and instructions are either 16-bit or X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 21 Feature Bit Description Disable JTAG 0 The JTAG interface is disabled, making it impossible for the tile state or memory content to be accessed via the JTAG interface. Disable Link access 1 Other tiles are forbidden access to the processor state via the system switch. Disabling both JTAG and Link access transforms an xCORE Tile into a “secure island” with other tiles free for non-secure user application code. Secure Boot 5 The processor is forced to boot from address 0 of the OTP, allowing the processor boot ROM to be bypassed (see §9). Redundant rows 7 Enables redundant rows in OTP. Sector Lock 0 8 Disable programming of OTP sector 0. Sector Lock 1 9 Disable programming of OTP sector 1. Sector Lock 2 10 Disable programming of OTP sector 2. Sector Lock 3 11 Disable programming of OTP sector 3. OTP Master Lock 12 Disable OTP programming completely: disables updates to all sectors and security register. Disable JTAG-OTP 13 Disable all (read & write) access from the JTAG interface to this OTP. Disable Global Debug 14 Disables access to the DEBUG_N pin. 21..15 General purpose software accessable security register available to end-users. 31..22 General purpose user programmable JTAG UserID code extension. Figure 12: Security register features 32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one tile clock cycle. There is no dedicated external memory interface, although data memory can be expanded through appropriate use of the ports. 10.3 Deep Sleep Memory The XS1-A10A-128-FB217 device includes 128 bytes of deep sleep memory for state storage during sleep mode. Deep sleep memory is volatile and if device input power is remove, the data will be lost. 11 Analog-to-Digital Converter The device has a 12-bit 1MSample/second Successive Approximation Register (SAR) Analogue to Digital Converter (ADC). It has 8 input pins which are multiplexed into the ADC. The sampling of the ADC is controlled using the ADC_SAMPLE pin that should be wired to a GPIO pin, for example X0D24 (port 1I). The sampling is triggered either by writing to the port, or by driving the pin externally. On each X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 22 rising edge of the sample pin the ADC samples, holds and converts the data value from one of the analog input pins. Each of the 8 inputs can be enabled individually. Each of the enabled analog inputs is sampled in turn, on successive rising edges of the sample pin. The data is transmitted to the channel-end that the user configures during initialization of the ADC. Data is transmitted over the channel in individual packets, or in packets that contain multiple consecutive samples. The ADC uses an external reference voltage, nominally 3V3, which represents the full range of the ADC. The ADC configuration registers are documented in Appendix F. The minimum latency for reading a value from the ADC into the xCORE register is shown in Figure 13: Figure 13: Minimum latency to read sample from ADC to xCORE 12 Sample 32-bit 32-bit 16-bit 16-bit Tile clock frequency 500 MHz 400 MHz 500 MHz 400 MHz Start of packet 840 ns 870 ns 770 ns 800 ns Subsequent samples 710 ns 740 ns 640 ns 670 ns Supervisor Logic An independent supervisor circuit provides power-on-reset, brown-out, and watchdog capabilities. This facilitates the design of systems that fail gracefully, whilst keeping BOM costs down. The reset supervisor holds the chip in reset until all power supplies are good. This provides a power-on-reset (POR). An external reset is optional and the pin RST_N can be left not-connected. If at any time any of the power supplies drop because of too little supply or too high a demand, the power supervisor will bring the chip into reset until the power supplies have been restored. This will reboot the system as if a cold-start has happened. The 16-bit watchdog timer provides 1ms accuracy and runs independently of the real-time counter. It can be programmed with a time-out of between 1 ms and 65 seconds (Appendix E). If the watchdog is not set before it times out, the XS1-A10A128-FB217 is reset. On boot, the program can read a register to test whether the reset was due to the watchdog. The watchdog timer is only enabled and clocked whilst the processor is in the AWAKE power state. 13 Energy management XS1-A10A-128-FB217 devices can be powered by: · An external 5v core and 3.3v I/O supply. · A single 3.3v supply. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 13.1 23 DC-DC XS1-A10A-128-FB217 devices include two DC-DC buck converters which can be configured to take input voltages between 3.3-5V power supply and output circuit voltages (nominally 1.8V and 1.0V) required by the analog peripherals and digital node. 13.2 Power mode controller The device transitions through multiple states during the power-up and powerdown process. RESET Power Up Transition states Waking 1/Waking 2 Wakeup Request Input Activity AWAKE Timer Event Sleep Request Figure 14: XS1-A10A128-FB217 Power Up States and Transitions System Reset Transition states Sleeping1/Sleeping2 ASLEEP The device is quiescent in the ASLEEP state, and is running in the AWAKE state. The other states allow a controlled transition between AWAKE and ASLEEP. A transition from AWAKE state to ASLEEP state is instigated by a write to the general control register. Sleep requests must only be made in the AWAKE state. A transition from the ASLEEP state into the AWAKE state is instigated by a wakeup request triggered by an input, or a timer. The device only responds to a wakeup stimulus in the ASLEEP state. If wakeup stimulus occurs whilst transitioning from AWAKE to ASLEEP, the appropriate response occurs when the ASLEEP state is reached. Configuration is through a set of registers documented in Appendix J. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 13.3 24 Deep Sleep Modes and Real-Time Counter The normal mode in which the XS1-A10A-128-FB217 operates is the AWAKE mode. In this mode, all cores, memory, and peripherals operate as normal. To save power, the XS1-A10A-128-FB217 can be put into a deep sleep mode, called ASLEEP, where the digital node is powered down, and most peripherals are powered down. The XS1-A10A-128-FB217 will stay in the ASLEEP mode until one of two conditions: 1. An external pin is asserted or deasserted (set by the program); 2. The 64-bit real-time counter reaches a value set by the program; or When the chip is awake, the real-time counter counts the number of clock ticks on the oscillator. As such, the real-time counter will run at a fixed ratio, but synchronously with the 100 MHz timers on the xCORE Tile. When asleep, the real-time counter can be automatically switched to the 31,250 Hz silicon oscillator to save power (see Appendix H). To ensure that the real-time counter increases linearly over time, a programmable value is added to the counter on every 31,250 Hz clock-tick. This means that the clock will run at a granularity of 31,250 Hz but still maintain real-time in terms of the frequency of the main oscillator. If an accurate clock is required, even whilst asleep, then an external crystal or oscillator shall be provided that is used in both AWAKE and ASLEEP state. The designer has to make a trade-off between accuracy of clocks when asleep and awake, costs, and deep-sleep power consumption. Four example designs are shown in Figure 15. Figure 15: Example trade-offs in oscillator selection Clocks used Awake Asleep 20 Mhz SiOsc 31,250 SiOsc 24 MHz Crystal 31,250 SiOsc 5 MHz ext osc 5 MHz ext osc 24 MHz Crystal 24 MHz crystal Power Asleep lowest lowest medium highest BOM costs lowest medium highest medium Accuracy Awake Asleep lowest lowest highest lowest highest highest highest highest During deep-sleep, the program can store some state in 128 bytes of Deep Sleep Memory. 13.4 Requirements during sleep mode Whilst in sleep mode, the device must still be powered as normal over 3V3 or 5V0 on VSUP, and 3V3 on VDDIO; however it will draw less power on both VSUP and VDDIO. For best results (lowest power): · The XTAL bias and XTAL oscillators should be switched off. · The sleep register should be configured to X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 25 · Disable all power supplies except DCDC2. · Set all power supplies to PFM mode · Mask the clock · Assert reset · All GPIO and JTAG pins should be quiescent, and none should be driven against a pull-up or pull-down. · 3V3 should be supplied as the input voltage to VSUP. This will result in a power consumption of less than 100 uA on both VSUP and VDDIO. If any power supply loses power-good status during the asleep-to-awake or awaketo-asleep transitions, a system reset is issued. 14 JTAG The JTAG module can be used for loading programs, boundary scan testing, incircuit source-level debugging and programming the OTP memory. X0 X1 BS TAP TDI TDI TDO CHIP TAP TDI TDO BS TAP TDI TDO CHIP TAP TDI TDO TDO TCK TMS Figure 16: JTAG chain structure TRST_N DEBUG_N The JTAG chain structure is illustrated in Figure 16. Directly after reset, three TAP controllers are present in the JTAG chain for each xCORE Tile: the debug TAP, the boundary scan TAP and the processor TAP. The debug TAP provides access into the peripherals including the ADC. The boundary scan TAP is a standard 1149.1 compliant TAP that can be used for boundary scan of the I/O pins. The processor TAP provides access into the xCORE Tile, switch and OTP for loading code and debugging. The JTAG module can be reset by holding TMS high for five clock cycles. The DEBUG_N pin is used to synchronize the debugging of multiple processors. This pin can operate in both output and input mode. In output mode and when configured to do so, DEBUG_N is driven low by the device when the processor hits a debug break point. Prior to this point the pin will be tri-stated. In input mode and when configured to do so, driving this pin low will put the processor into debug X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 26 mode. Software can set the behavior of the processor based on this pin. This pin should have an external pull up of 4K7-47K Ω or left not connected in single core applications. The JTAG device identification register can be read by using the IDCODE instruction. Its contents are specified in Figure 17. Figure 17: IDCODE return value Bit31 Device Identification Register Version 0 0 0 Bit0 Part Number 0 0 0 0 0 0 0 0 0 0 0 0 Manufacturer Identity 0 0 0 0 0 0 0 1 1 0 1 3 1 0 0 0 6 1 1 1 0 0 3 1 1 3 The JTAG usercode register can be read by using the USERCODE instruction. Its contents are specified in Figure 18. The OTP User ID field is read from bits [22:31] of the security register on xCORE Tile 0, see §10.1 (all zero on unprogrammed devices). Figure 18: USERCODE return value 15 Bit31 Usercode Register OTP User ID 0 0 0 0 0 0 0 0 0 Bit0 Unused 0 0 0 0 0 0 0 Silicon Revision 0 1 0 2 1 1 0 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Board Integration XS1-A10A-128-FB217 devices are optimized for layout on low cost PCBs using standard design rules. Careful layout is required to maximize the device performance. XMOS therefore recommends that the guidelines in this section are followed when laying out boards using the device. The XS1-A10A-128-FB217 includes two DC-DC buck converters that take input voltages between 3.3-5V and output the 1.8V and 1.0V circuits required by the digital core and analogue peripherals. The DC-DC converters should have a 4.7uF X5R or X7R ceramic capacitor and a 100nF X5R or X7R ceramic capacitor on the VSUP input pins W1 and W2. These capacitors must be placed as close as possible to the those pins (within a maximum of 5mm), with the routing optimized to minimize the inductance and resistance of the traces. The SW output pin must have an LC filter on the output with a 4.7uH inductor and 22uF X5R capacitor. The capacitor must have maximum ESR value of 0.015R, and the inductor should have a maximum DCR value of 0.07R. A list of suggested inductors is in Figure 19. Figure 19: Example 4.7 µH inductors Wurth Murata Part number 744043004 LQH55DN4R7M03L Current 1550 mA 2700 mA Max DCR 70 mΩ 57 mΩ Package 4.8 x 4.8 mm 5750 (2220) The traces from the SW output pins to the inductor and from the output capacitor back to the VDD pins must be routed to minimize the coupling between them. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 27 The power supplies must be brought up monotonically and input voltages must not exceed specification at any time. The VDDIO supply to the XS1-A10A-128-FB217 requires a 100nF X5R or X7R ceramic decoupling capacitor placed as close as possible to the supply pins. VDDIO_OUT is the switched IO supply; it is only supplied when the chip is AWAKE. This pin can be used to provide extra decoupling, or it can be used to switch other devices off during sleep mode, for example a SPI flash. No more than 240 mA should be drawn on VDDIO at any time: this includes any supply sourced statically (e.g., driving a LED from a GPIO pin), any dynamic power consumption (e.g., toggling a GPIO pin at a high frequency) and any devices powered through VDDIO_OUT. If the ADC Is used, it requires a 100nF X5R or X7R ceramic decoupling capacitor placed as close as possible to the AVDD pin. Care should be taken to minimize noise on these inputs, and if necessary an extra 10uF decoupling capacitor and ferrite bead can be used to remove noise from this supply. The crystal oscillator requires careful routing of the XI / XO nodes as these are high impedance and very noise sensitive. Hence, the traces should be as wide and short as possible, and routed over a continuous ground plane. They should not be routed near noisy supply lines or clocks. The device has a load capacitance of 18pF for the crystal. Care must be taken, so that the inductance and resistance of the ground returns from the capacitors to the ground of the device is minimized. 15.1 Land patterns and solder stencils The land pattern recommendations in this document are based on a RoHS compliant process and derived, where possible, from the nominal Generic Requirements for Surface Mount Design and Land Pattern Standards IPC-7351B specifications. This standard aims to achieve desired targets of heel, toe and side fillets for solderjoints. Solder paste and ground via recommendations are based on our engineering and development kit board production. They have been found to work and optimized as appropriate to achieve a high yield. These factors should be taken into account during design and manufacturing of the PCB. The following land patterns and solder paste contains recommendations. Final land pattern and solder paste decisions are the responsibility of the customer. These should be tuned during manufacture to suit the manufacturing process. The package is a 217 pin Fine Ball Grid Array package on a 0.8mm pitch with 0.4mm balls. An example land pattern is shown in Figure 20. Pad widths and spacings are such that solder mask can still be applied between the pads using standard design rules. This is highly recommended to reduce solder shorts. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 28 14.40 0.80 14.40 Figure 20: Example land pattern 0.80 ø0.35 15.2 Ground and Thermal Vias Vias next to every other ground ball into the ground plane of the PCB are recommended for a low inductance ground connection and good thermal performance. Vias with with a 0.6mm diameter annular ring and a 0.3mm drill would be suitable. 15.3 Moisture Sensitivity XMOS devices are, like all semiconductor devices, susceptible to moisture absorption. When removed from the sealed packaging, the devices slowly absorb moisture from the surrounding environment. If the level of moisture present in the device is too high during reflow, damage can occur due to the increased internal vapour pressure of moisture. Example damage can include bond wire damage, die lifting, internal or external package cracks and/or delamination. All XMOS devices are Moisture Sensitivity Level (MSL) 3 - devices have a shelf life of 168 hours between removal from the packaging and reflow, provided they are stored below 30C and 60% RH. If devices have exceeded these values or an included moisture indicator card shows excessive levels of moisture, then the parts should be baked as appropriate before use. This is based on information from Joint IPC/JEDEC Standard For Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface-Mount Devices J-STD-020 Revision D. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 16 29 Example XS1-A10A-128-FB217 Board Designs This section shows example schematics and layout for a 2-layer PCB. · Figures 21 shows example schematics and layout. It uses a 24 MHz crystal for the clock, and an SPI flash for booting. XS1-A10A-128-FB217 is powered directly from 3V3. · Figures 22 shows example schematics and layout for a design that uses an oscillator rather than a crystal. If required a 3V3 oscillator can be used (for example when sharing an oscillator with other parts of the design), but a resistor bridge must be included to reduce the XI/CLK input from 3V3 to 1V8. · Figure 23 shows example schematics and layout for a design that runs off the internal 20 MHz oscillator. The XS1-A10A-128-FB217 is powered directly from 3V3. Flash, AVDD, RST, and JTAG connectivity are all optional. Flash can be removed if the processor boots from OTP. The AVDD decoupler and wiring can be removed if the ADC is not used. RST_N and all JTAG wiring can be removed if debugging is not required (see Appendix M) X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 30 3V3 U1B 3V3A U1C 3V3 U1A C1 100N A19 GND T2 U1 U2 L1 T1 R1 R2 4U7 C5 V5 W5 22U L2 GND V6 W6 4U7 VDDIO VDDIO V1 V2 V4 W4 100N C3 VDDCORE VDDCORE VDDCORE 4U7 GND SW1 SW1 SW1 VDD1V8 VDD1V8 SW2 SW2 22U K10 F6 F7 F8 F9 F10 F11 F12 F13 F14 G6 G7 G8 G9 G10 G11 G12 G13 G14 H6 H7 H8 H9 H10 H11 H12 P2 W1 W2 VDDIO_OUT C6 GND VSUP VSUP VSUP GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PGND PGND PGND PGND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H13 H14 J6 J7 J8 J9 J10 J11 J12 J13 J14 K8 K9 K11 K12 K13 K14 L8 L9 L10 L11 L12 L13 L14 M8 M9 M10 M11 M12 M13 M14 N8 N9 N10 N11 N12 N13 N14 P6 P7 P8 P9 P10 P11 P12 P13 P14 X0D00 X0D01 X0D02 X0D03 X0D04 X0D05 X0D06 X0D07 X0D08 X0D09 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 WAKE/X0D43 C2 3V3 V3 W3 U1D G1 AVDD MODE[0] MODE[1] MODE[2] MODE[3] MODE[4] OSC_EXT_EN GND L2 K1 K2 J1 J2 H1 H2 G2 ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 B14 X0D70 ADC_SAMPLE TDO TDI TMS TCK GLOBAL_DEBUG RST_N N7 N6 P1 M6 M7 L1 M2 N2 V7 W7 NC NC NC NC NC NC NC NC NC NC XO XI/CLK K6 K7 F1 F2 L7 L6 MSEL GND C1 E2 E1 D1 TDO TDI TMS TCK C2 DEBUG_N D2 RST_N N1 M1 X1 C7 C8 24M ABLS 33P XS1_AnA_128_FB217 GND 33P GND X0D70 3V3 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 A14 A15 B15 A16 B16 A17 B17 A18 B18 F18 G19 B19 C19 C18 D19 D18 E19 E18 F19 X0D0 X0D1 X0D2 X0D3 X0D4 X0D5 X0D6 X0D7 X0D8 X0D9 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 X0D43 B13 X0D70 X1D00 X1D01 X1D02 X1D03 X1D04 X1D05 X1D06 X1D07 X1D08 X1D09 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21 X1D22 X1D23 X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D36 X1D37 X1D38 X1D39 X1D40 X1D41 X1D42 X1D43 X1D70 G18 H19 H18 J19 J18 K19 K18 L19 L18 M19 M18 N19 N18 P19 P18 R19 R18 T19 T18 U19 U18 V19 V18 W19 W17 V17 W16 V16 W15 V15 W14 V14 W13 V13 W8 V8 W12 V12 W11 V11 W10 V10 W9 V9 X1D0 X1D1 X1D2 X1D3 X1D4 X1D5 X1D6 X1D7 X1D8 X1D9 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21 X1D22 X1D23 X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D36 X1D37 X1D38 X1D39 X1D40 X1D41 X1D42 X1D43 W18 X1D70 3V3 XS1_AnA_128_FB217 R1 XS1_AnA_128_FB217 C9 U2 M25P40 100N 10K X0D11 5 X0D10 6 X0D1 3 7 1 SI VCC SCK SO WP_N HOLD_N CS_N GND 8 2 GND X0D0 4 ??MBIT GND XS1_AnA_128_FB217 GND GND Program Flash J1 MSEL TDI TMS TCK DEBUG_N TDO RST_N 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 3V3 3V3A L3 4U7 C10 C11 100N 10U C12 HEADER_RA XSYS Link GND 10U Copyright © XMOS Ltd 2012 Project Name For prototype designs it is recommended that one fo the three available xlink connections is bought out to the XSYS to enable XSCOPE debugging GND GND GND Analogue Supply Filter (only required if ADC is used) SA2-REF-XTAL.PrjPCB Size A3 Date 25/06/2013 Sheet Name UnA_128 Ref Xtal Rev 1V1A Sheet 1 of 1 Figure 21: Example XTAL schematic, with top and bottom layout of a 2-layer PCB X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 31 3V3 U1B 3V3A U1C 3V3 U1A L1 T1 R1 R2 4U7 C5 VDDIO_OUT C3 VDDCORE VDDCORE VDDCORE 4U7 V5 W5 L2 GND V6 W6 4U7 VDD1V8 VDD1V8 SW2 SW2 C6 22U K10 F6 F7 F8 F9 F10 F11 F12 F13 F14 G6 G7 G8 G9 G10 G11 G12 G13 G14 H6 H7 H8 H9 H10 H11 H12 GND V1 V2 V4 W4 GND SW1 SW1 SW1 1V8 22U 100N GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PGND PGND PGND PGND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H13 H14 J6 J7 J8 J9 J10 J11 J12 J13 J14 K8 K9 K11 K12 K13 K14 L8 L9 L10 L11 L12 L13 L14 M8 M9 M10 M11 M12 M13 M14 N8 N9 N10 N11 N12 N13 N14 P6 P7 P8 P9 P10 P11 P12 P13 P14 U1D G1 AVDD MODE[0] MODE[1] MODE[2] MODE[3] MODE[4] OSC_EXT_EN GND L2 K1 K2 J1 J2 H1 H2 G2 ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 B14 X0D70 ADC_SAMPLE MSEL GND 1V8 TDO TDI TMS TCK GLOBAL_DEBUG RST_N N7 N6 P1 M6 M7 L1 M2 N2 V7 W7 K6 K7 F1 F2 L7 L6 NC NC NC NC NC NC NC NC NC NC C1 E2 E1 D1 TDO TDI TMS TCK C2 DEBUG_N D2 RST_N C7 10N GND XO XI/CLK N1 M1 4 T2 U1 U2 VSUP VSUP VSUP X1 VCC A19 GND VDDIO VDDIO P2 W1 W2 3 OUT EN 1 GND 100N X0D00 X0D01 X0D02 X0D03 X0D04 X0D05 X0D06 X0D07 X0D08 X0D09 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 WAKE/X0D43 C2 3V3 V3 W3 XS1_AnA_128_FB217 24M 2 C1 ASDMB GND X0D70 3V3 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 A14 A15 B15 A16 B16 A17 B17 A18 B18 F18 G19 B19 C19 C18 D19 D18 E19 E18 F19 X0D0 X0D1 X0D2 X0D3 X0D4 X0D5 X0D6 X0D7 X0D8 X0D9 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 X0D43 B13 X0D70 X1D00 X1D01 X1D02 X1D03 X1D04 X1D05 X1D06 X1D07 X1D08 X1D09 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21 X1D22 X1D23 X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D36 X1D37 X1D38 X1D39 X1D40 X1D41 X1D42 X1D43 X1D70 G18 H19 H18 J19 J18 K19 K18 L19 L18 M19 M18 N19 N18 P19 P18 R19 R18 T19 T18 U19 U18 V19 V18 W19 W17 V17 W16 V16 W15 V15 W14 V14 W13 V13 W8 V8 W12 V12 W11 V11 W10 V10 W9 V9 X1D0 X1D1 X1D2 X1D3 X1D4 X1D5 X1D6 X1D7 X1D8 X1D9 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21 X1D22 X1D23 X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D36 X1D37 X1D38 X1D39 X1D40 X1D41 X1D42 X1D43 W18 X1D70 3V3 XS1_AnA_128_FB217 R1 XS1_AnA_128_FB217 C9 U2 M25P40 100N 10K X0D11 5 X0D10 6 X0D1 3 7 1 SI VCC SCK SO WP_N HOLD_N CS_N GND 8 2 GND X0D0 4 ??MBIT GND XS1_AnA_128_FB217 GND GND Program Flash J1 MSEL TDI TMS TCK DEBUG_N TDO RST_N 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 3V3 3V3A L3 4U7 C10 C11 100N 10U C12 HEADER_RA XSYS Link GND 10U Copyright © XMOS Ltd 2012 Project Name For prototype designs it is recommended that one fo the three available xlink connections is bought out to the XSYS to enable XSCOPE debugging GND GND GND Analogue Supply Filter (only required if ADC is used) SA2-REF-OSC.PrjPCB Size A3 Date 25/06/2013 Sheet Name UnA_128 Ref Osc Rev 1V1A Sheet 1 of 1 Figure 22: Example Oscillator schematic, with top and bottom layout of a 2-layer PCB X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 32 3V3 U1B 3V3A U1C 3V3 U1A C1 3V3 V3 W3 100N A19 GND T2 U1 U2 L1 T1 R1 R2 4U7 C5 V5 W5 22U L2 GND V6 W6 4U7 VDDIO VDDIO C3 VDDCORE VDDCORE VDDCORE 4U7 VDD1V8 VDD1V8 SW2 SW2 22U K10 F6 F7 F8 F9 F10 F11 F12 F13 F14 G6 G7 G8 G9 G10 G11 G12 G13 G14 H6 H7 H8 H9 H10 H11 H12 V1 V2 V4 W4 GND SW1 SW1 SW1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PGND PGND PGND PGND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C2 100N VDDIO_OUT C6 GND VSUP VSUP VSUP P2 W1 W2 H13 H14 J6 J7 J8 J9 J10 J11 J12 J13 J14 K8 K9 K11 K12 K13 K14 L8 L9 L10 L11 L12 L13 L14 M8 M9 M10 M11 M12 M13 M14 N8 N9 N10 N11 N12 N13 N14 P6 P7 P8 P9 P10 P11 P12 P13 P14 U1D G1 AVDD MODE[0] MODE[1] MODE[2] MODE[3] MODE[4] OSC_EXT_EN GND ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7 X0D70 L2 K1 K2 J1 J2 H1 H2 G2 B14 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC_SAMPLE TDO TDI TMS TCK GLOBAL_DEBUG RST_N N7 N6 P1 M6 M7 L1 M2 N2 V7 W7 NC NC NC NC NC NC NC NC NC NC XS1_AnA_128_FB217 XO XI/CLK K6 K7 F1 F2 L7 L6 C1 E2 E1 D1 C2 D2 N1 M1 3V3 GND X0D00 X0D01 X0D02 X0D03 X0D04 X0D05 X0D06 X0D07 X0D08 X0D09 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 WAKE/X0D43 X0D70 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 A14 A15 B15 A16 B16 A17 B17 A18 B18 F18 G19 B19 C19 C18 D19 D18 E19 E18 F19 X0D0 X0D1 X0D2 X0D3 X0D4 X0D5 X0D6 X0D7 X0D8 X0D9 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 X0D43 B13 X0D70 X1D00 X1D01 X1D02 X1D03 X1D04 X1D05 X1D06 X1D07 X1D08 X1D09 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21 X1D22 X1D23 X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D36 X1D37 X1D38 X1D39 X1D40 X1D41 X1D42 X1D43 X1D70 XS1_AnA_128_FB217 G18 H19 H18 J19 J18 K19 K18 L19 L18 M19 M18 N19 N18 P19 P18 R19 R18 T19 T18 U19 U18 V19 V18 W19 W17 V17 W16 V16 W15 V15 W14 V14 W13 V13 W8 V8 W12 V12 W11 V11 W10 V10 W9 V9 X1D0 X1D1 X1D2 X1D3 X1D4 X1D5 X1D6 X1D7 X1D8 X1D9 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D16 X1D17 X1D18 X1D19 X1D20 X1D21 X1D22 X1D23 X1D24 X1D25 X1D26 X1D27 X1D28 X1D29 X1D30 X1D31 X1D32 X1D33 X1D34 X1D35 X1D36 X1D37 X1D38 X1D39 X1D40 X1D41 X1D42 X1D43 W18 X1D70 XS1_AnA_128_FB217 XS1_AnA_128_FB217 GND GND 3V3 3V3A L3 4U7 C10 C11 100N 10U C12 10U Copyright © XMOS Ltd 2012 Project Name GND GND GND Analogue Supply Filter (only required if ADC is used) SA2-REF-MINNJ.PrjPCB Size A3 Sheet Name UnA_128 Ref Minimal Date 25/06/2013 Rev 1V1A Sheet 1 of 1 Figure 23: Example minimal system schematic, with top and bottom layout of a 2-layer PCB X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 17 33 DC and Switching Characteristics 17.1 Operating Conditions Symbol VSUP Figure 24: Operating conditions MIN TYP MAX UNITS Power Supply (3.3V Mode) 3.00 3.30 3.60 V Power Supply (5V Mode) 4.50 5.00 5.50 V VDDIO I/O supply voltage 3.00 3.30 3.60 V AVDD Analog Supply and Reference Voltage 3.00 3.30 3.60 V Cl xCORE Tile I/O load capacitance 25 pF Ta Ambient operating temperature (Commercial) 0 70 °C Ambient operating temperature (Industrial) -40 85 °C 125 °C -65 150 °C Tj Junction temperature Tstg Storage temperature 17.2 Figure 25: DC1 characteristics Parameter Notes DC1 Characteristics Symbol Parameter MIN TYP MAX UNITS VDDCORE Tile Supply Voltage 0.90 1.00 1.10 V V(RIPPLE) Ripple Voltage (peak to peak) 10 40 V(ACC) Voltage Accuracy F(S) Switching Frequency F(SVAR) Variation in Switching Frequency Effic Efficiency 80 % PGT(HIGH) Powergood Threshold (High) 95 %/VDDCORE PGT(LOW) Powergood Threshold (Low) 80 %/VDDCORE -5 5 1 -10 Notes mV % A MHz 10 % A If supplied externally. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 17.3 Figure 26: DC2 characteristics 34 DC2 Characteristics Symbol Parameter VDD1V8 1V8 Supply Voltage MIN TYP MAX V(RIPPLE) Ripple Voltage (peak to peak) V(ACC) Voltage Accuracy F(S) Switching Frequency F(SVAR) Variation in Switching Frequency Effic Efficiency 80 % PGT(HIGH) Powergood Threshold (High) 95 %/VDD1V8 PGT(LOW) Powergood Threshold (Low) 80 %/VDD1V8 1.80 UNITS Notes V 10 40 -5 5 1 mV % A MHz -10 10 % A If supplied externally. 17.4 Figure 27: ADC characteristics X2625, ADC Characteristics Symbol Parameter N Resolution MIN TYP MAX Fs Conversion Speed Nch Number of Channels Vin Input Range 0 AVDD DNL Differential Non Linearity -1 1.5 LSB INL Integral Non Linearity -4 4 LSB E(GAIN) Gain Error -10 10 LSB E(OFFSET) Offset Error -3 3 mV T(PWRUP) Power time for ADC Clock Fclk 7 1/Fclk ENOB Effective Number of bits 12 UNITS Notes bits 1 MSPS 8 V 10 XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 17.5 Figure 28: Digital I/O characteristics 35 Digital I/O Characteristics Symbol Parameter MIN MAX UNITS Notes V(IH) Input high voltage 2.00 TYP 3.60 V A V(IL) Input low voltage -0.30 0.70 V A V(OH) Output high voltage V B, C V(OL) Output low voltage V B, C R(PU) Pull-up resistance 35K Ω D R(PD) Pull-down resistance 35K Ω D 2.00 0.60 A All pins except power supply pins. B Ports 1A, 1D, 1E, 1H, 1I, 1J, 1K and 1L are nominal 8 mA drivers, the remainder of the general-purpose I/Os are 4 mA. C Measured with 4 mA drivers sourcing 4 mA, 8 mA drivers sourcing 8 mA. D Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be used to pull external circuitry. 17.6 Figure 29: ESD stress voltage Symbol Parameter HBM Human body model CDM Charged Device Model 17.7 Figure 30: Device timing characteristics ESD Stress Voltage MIN TYP MAX UNITS 2.00 kV 500 V Notes Device Timing Characteristics Symbol Parameter T(RST) Reset pulse width MIN TYP MAX 5 UNITS Initialisation (On Silicon Oscillator) TBC ms Initialisation (Crystal Oscillator) TBC ms T(WAKE) Wake up time (Sleep to Active) TBC ms T(SLEEP) Sleep Time (Active to Sleep) TBC ms T(INIT) Notes µs A A Shows the time taken to start booting after RST_N has gone high. 17.8 Figure 31: Crystal oscillator characteristics X2625, Crystal Oscillator Characteristics Symbol Parameter F(FO) Input Frequency MIN 5 TYP MAX 30 UNITS Notes MHz XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 17.9 Figure 32: External oscillator characteristics External Oscillator Characteristics Symbol Parameter F(EXT) External Frequency V(IH) Input high voltage V(IL) Input low voltage 17.10 Figure 33: xCORE Tile currents 36 MIN TYP MAX 100 1.62 UNITS 1.98 V 0.4 V Power Consumption Symbol Parameter MIN TYP MAX UNITS P(AWAKE) Active Power for awake states (Speed Grade 10) TBC 600 TBC mW Active Power for awake states (Speed Grade 8) TBC 480 TBC mW Power when asleep TBC 500 TBC µW P(SLEEP) 17.11 Notes MHz Notes Clock Symbol Parameter MAX UNITS Notes f(MAX) Processor clock frequency (Speed Grade 10) 500 MHz A Processor clock frequency (Speed Grade 8) 400 MHz A Figure 34: Clock MIN TYP A Assumes typical tile and I/O voltages with nominal activity. 17.12 Figure 35: I/O AC characteristics Processor I/O AC Characteristics Symbol Parameter MIN TYP MAX UNITS T(XOVALID) Input data valid window 8 T(XOINVALID) Output data invalid window 9 T(XIFMAX) Rate at which data can be sampled with respect to an external clock Notes ns ns 60 MHz The input valid window parameter relates to the capability of the device to capture data input to the chip with respect to an external clock source. It is calculated as the sum of the input setup time and input hold time with respect to the external clock as measured at the pins. The output invalid window specifies the time for which an output is invalid with respect to the external clock. Note that these parameters are specified as a window rather than absolute numbers since the device provides functionality to delay the incoming clock with respect to the incoming data. Information on interfacing to high-speed synchronous interfaces can be found in the XS1 Port I/O Timing document, X5821. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 17.13 xConnect Link Performance Symbol Parameter MAX UNITS Notes B(2blinkP) 2b link bandwidth (packetized) (Speed Grade 10) 103 MBit/s A, B 2b link bandwidth (packetized) (Speed Grade 8) 82 MBit/s A, B 5b link bandwidth (packetized) (Speed Grade 10) 271 MBit/s A, B 5b link bandwidth (packetized) (Speed Grade 8) 215 MBit/s A, B 2b link bandwidth (streaming) (Speed Grade 10) 125 MBit/s B 2b link bandwidth (streaming) (Speed Grade 8) 100 MBit/s B 5b link bandwidth (streaming) (Speed Grade 10) 313 MBit/s 5b link bandwidth (streaming) (Speed Grade 8) 250 MBit/s B(5blinkP) B(2blinkS) Figure 36: Link performance 37 B(5blinkS) MIN TYP B A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header and payload. B 7.5 ns symbol time. The asynchronous nature of links means that the relative phasing of CLK clocks is not important in a multi-clock system, providing each meets the required stability criteria. 17.14 Figure 37: JTAG timing JTAG Timing Symbol Parameter f(TCK_D) TCK frequency (debug) MIN f(TCK_B) TCK frequency (boundary scan) T(SETUP) TDO to TCK setup time TBC T(HOLD) TDO to TCK hold time TBC T(DELAY) TCK to output delay TYP MAX UNITS TBC MHz TBC MHz Notes ns ns TBC A ns A Timing applies to TMS and TDI inputs. All JTAG operations are synchronous to TCK. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 18 X2625, 38 Package Information XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 18.1 39 Part Marking CC - Number of logical cores F - Product family R - RAM (in log-2) T - Temperature grade M - MIPS grade CCFRTM MCYYWWXX Figure 38: Part marking scheme 19 Wafer lot code Ordering Information Figure 39: Orderable part numbers X2625, LLLLLL.LL MC - Manufacturer YYWW - Date XX - Reserved Product Code XS1–A10A–128–FB217–C8 XS1–A10A–128–FB217–C10 XS1–A10A–128–FB217–I8 XS1–A10A–128–FB217–I10 Marking 10A7C8 10A7C10 10A7I8 10A7I10 Qualification Commercial Commercial Industrial Industrial Speed Grade 800 MIPS 1000 MIPS 800 MIPS 1000 MIPS XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 40 Appendices A Configuring the device Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAGstatus Processor debug registers xCORE logical core 2 xCORE tile registers xCORE logical core 3 xCONNECT Links xCORE logical core 1 Channels I/O pins xCORE logical core 0 Hardware response ports Digital node registers xCORE logical core 4 Analog node registers ADC registersADC Multichannel Oscillator registers Oscillator Real-time clock clock registers Real-time I/O pins PLL xCONNECT: channels, links The device is configured through ten banks of registers, as shown in Figure 40. Supervisor Supervisor block registers Watchdog, out deep sleep, brown watchdog PowerOnRST Power controlPMIC registers DC-DC xCORE logical core 2 xCORE logical core 3 xCORE tile registers xCONNECT Links xCORE logical core 1 Channels I/O pins xCORE logical core 0 Hardware response ports Digital node registers xCORE logical core 4 Figure 40: Registers PLL A.1 Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAGstatus Processor registers debug Accessing a processor status register The processor status registers are accessed directly from the processor instruction set. The instructions GETPS and SETPS read and write a word. The register number should be translated into a processor-status resource identifier by shifting the register number left 8 places, and ORing it with 0x0C. Alternatively, the functions getps(reg) and setps(reg,value) can be used from XC. A.2 Accessing an xCORE Tile configuration register xCORE Tile configuration registers can be accessed through the interconnect using the functions write_tile_config_reg(tileref, ...) and read_tile_config_reg(tile > ref, ...), where tileref is the name of the xCORE Tile, e.g. tile[1]. These functions implement the protocols described below. Instead of using the functions above, a channel-end can be allocated to communicate with the xCORE tile configuration registers. The destination of the channel-end should be set to 0xnnnnC20C where nnnnnn is the tile-identifier. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 41 A write message comprises the following: control-token 24-bit response 16-bit 32-bit control-token 192 channel-end identifier register number data 1 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 16-bit control-token 193 channel-end identifier register number 1 The response to the read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). A.3 Accessing digital and analogue node configuration registers Node configuration registers can be accessed through the interconnect using the functions write_node_config_reg(device, ...) and read_node_config_reg(device, > ...), where device is the name of the node. These functions implement the protocols described below. Instead of using the functions above, a channel-end can be allocated to communicate with the node configuration registers. The destination of the channel-end should be set to 0xnnnnC30C where nnnn is the node-identifier. A write message comprises the following: control-token 24-bit response 16-bit 32-bit control-token 192 channel-end identifier register number data 1 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 16-bit control-token 193 channel-end identifier register number 1 The response to a read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). A.4 Accessing a register of an analogue peripheral Peripheral registers can be accessed through the interconnect using the functions write_periph_32(device, peripheral, ...), read_periph_32(device, peripheral, ...) > , write_periph_8(device, peripheral, ...), and read_periph_8(device, peripheral > , ...); where device is the name of the analogue device, and peripheral is the number of the peripheral. These functions implement the protocols described below. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 42 A channel-end should be allocated to communicate with the configuration registers. The destination of the channel-end should be set to 0xnnnnpp02 where nnnn is the node-identifier and pp is the peripheral identifier. A write message comprises the following: control-token 24-bit response 8-bit 8-bit 36 channel-end identifier register number size data control-token 1 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 8-bit 8-bit control-token 37 channel-end identifier register number size 1 The response to the read message comprises either control token 3, data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet B 43 Processor Status Configuration The processor status control registers can be accessed directly by the processor using processor status reads and writes (use getps(reg) and setps(reg,value) for reads and writes). Number Figure 41: Summary X2625, Perm Description 0x00 RW RAM base address 0x01 RW Vector base address 0x02 RW xCORE Tile control 0x03 RO xCORE Tile boot status 0x05 RO Security configuration 0x06 RW Ring Oscillator Control 0x07 RO Ring Oscillator Value 0x08 RO Ring Oscillator Value 0x09 RO Ring Oscillator Value 0x0A RO Ring Oscillator Value 0x10 DRW Debug SSR 0x11 DRW Debug SPC 0x12 DRW Debug SSP 0x13 DRW DGETREG operand 1 0x14 DRW DGETREG operand 2 0x15 DRW Debug interrupt type 0x16 DRW Debug interrupt data 0x18 DRW Debug core control 0x20 .. 0x27 DRW Debug scratch 0x30 .. 0x33 DRW Instruction breakpoint address 0x40 .. 0x43 DRW Instruction breakpoint control 0x50 .. 0x53 DRW Data watchpoint address 1 0x60 .. 0x63 DRW Data watchpoint address 2 0x70 .. 0x73 DRW Data breakpoint control register 0x80 .. 0x83 DRW Resources breakpoint mask 0x90 .. 0x93 DRW Resources breakpoint value 0x9C .. 0x9F DRW Resources breakpoint control register XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet B.1 44 RAM base address: 0x00 This register contains the base address of the RAM. It is initialized to 0x00010000. 0x00: RAM base address Bits Perm 31:2 RW 1:0 RO B.2 Init Description Most significant 16 bits of all addresses. - Reserved Vector base address: 0x01 Base address of event vectors in each resource. On an interrupt or event, the 16 most significant bits of the destination address are provided by this register; the least significant 16 bits come from the event vector. 0x01: Vector base address Bits Perm 31:16 RW 15:0 RO B.3 Init Description The most significant bits for all event and interrupt vectors. - Reserved xCORE Tile control: 0x02 Register to control features in the xCORE tile 0x02: xCORE Tile control Bits Perm 31:6 RO - 5 RW 0 Set to 1 to select the dynamic mode for the clock divider when the clock divider is enabled. In dynamic mode the clock divider is only activated when all active logical cores are paused. In static mode the clock divider is always enabled. 4 RW 0 Set to 1 to enable the clock divider. This slows down the xCORE tile clock in order to use less power. 3:0 RO - B.4 Init Description Reserved Reserved xCORE Tile boot status: 0x03 This read-only register describes the boot status of the xCORE tile. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 45 Init 31:24 RO 23:16 RO 15:9 RO 8 RO Set to 1 if boot from OTP is enabled. 7:0 RO The boot mode pins MODE0, MODE1, ..., specifying the boot frequency, boot source, etc. 0x03: xCORE Tile boot status B.5 - Description Reserved xCORE tile number on the switch. - Reserved Security configuration: 0x05 Copy of the security register as read from OTP. 0x05: Security configuration Bits Perm 31:0 RO B.6 Init Description Value. Ring Oscillator Control: 0x06 There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register. The counters should only be read when the ring oscillator is stopped. The counter values can be read using four subsequent registers. The ring oscillators are asynchronous to the xCORE tile clock and can be used as a source of random bits. 0x06: Ring Oscillator Control Bits Perm 31:2 RO - 1 RW 0 Set to 1 to enable the xCORE tile ring oscillators 0 RW 0 Set to 1 to enable the peripheral ring oscillators B.7 Init Description Reserved Ring Oscillator Value: 0x07 This register contains the current count of the xCORE Tile Cell ring oscillator. This value is not reset on a system reset. 0x07: Ring Oscillator Value X2625, Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet B.8 46 Ring Oscillator Value: 0x08 This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset. 0x08: Ring Oscillator Value Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. B.9 Ring Oscillator Value: 0x09 This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset. 0x09: Ring Oscillator Value Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. B.10 Ring Oscillator Value: 0x0A This register contains the current count of the Peripheral Wire ring oscillator. This value is not reset on a system reset. 0x0A: Ring Oscillator Value Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. B.11 Debug SSR: 0x10 This register contains the value of the SSR register when the debugger was called. 0x10: Debug SSR Bits Perm 31:0 RO B.12 Init - Description Reserved Debug SPC: 0x11 This register contains the value of the SPC register when the debugger was called. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x11: Debug SPC Bits Perm 31:0 DRW B.13 47 Init Description Value. Debug SSP: 0x12 This register contains the value of the SSP register when the debugger was called. 0x12: Debug SSP Bits Perm 31:0 DRW B.14 Init Description Value. DGETREG operand 1: 0x13 The resource ID of the logical core whose state is to be read. 0x13: DGETREG operand 1 Bits 31:8 7:0 B.15 Perm RO Init - DRW Description Reserved Thread number to be read DGETREG operand 2: 0x14 Register number to be read by DGETREG 0x14: DGETREG operand 2 Bits Perm 31:5 RO 4:0 B.16 DRW Init - Description Reserved Register number to be read Debug interrupt type: 0x15 Register that specifies what activated the debug interrupt. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 48 Init - Description 31:18 RO 17:16 DRW If the debug interrupt was caused by a hardware breakpoint or hardware watchpoint, this field contains the number of the breakpoint or watchpoint. If multiple breakpoints or watchpoints trigger at once, the lowest number is taken. 15:8 DRW If the debug interrupt was caused by a logical core, this field contains the number of that core. Otherwise this field is 0. 7:3 RO - 2:0 DRW 0 0x15: Debug interrupt type B.17 Reserved Reserved Indicates the cause of the debug interrupt 1: Host initiated a debug interrupt through JTAG 2: Program executed a DCALL instruction 3: Instruction breakpoint 4: Data watch point 5: Resource watch point Debug interrupt data: 0x16 On a data watchpoint, this register contains the effective address of the memory operation that triggered the debugger. On a resource watchpoint, it countains the resource identifier. 0x16: Debug interrupt data Bits Perm 31:0 DRW B.18 Init Description Value. Debug core control: 0x18 This register enables the debugger to temporarily disable logical cores. When returning from the debug interrupts, the cores set in this register will not execute. This enables single stepping to be implemented. 0x18: Debug core control X2625, Bits Perm 31:8 RO 7:0 DRW Init - Description Reserved 1-hot vector defining which logical cores are stopped when not in debug mode. Every bit which is set prevents the respective logical core from running. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet B.19 49 Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG. This is the same set of registers as the Debug Scratch registers in the xCORE tile configuration. 0x20 .. 0x27: Debug scratch Bits Perm 31:0 DRW B.20 Init Description Value. Instruction breakpoint address: 0x30 .. 0x33 This register contains the address of the instruction breakpoint. If the PC matches this address, then a debug interrupt will be taken. There are four instruction breakpoints that are controlled individually. 0x30 .. 0x33: Instruction breakpoint address Bits Perm 31:0 DRW B.21 Init Description Value. Instruction breakpoint control: 0x40 .. 0x43 This register controls which logical cores may take an instruction breakpoint, and under which condition. Bits Perm Init 31:24 RO - 23:16 DRW 0 15:2 0x40 .. 0x43: Instruction breakpoint control B.22 Description Reserved A bit for each logical core in the tile allowing the breakpoint to be enabled individually for each logical core. RO - 1 DRW 0 Reserved Set to 1 to cause an instruction breakpoint if the PC is not equal to the breakpoint address. By default, the breakpoint is triggered when the PC is equal to the breakpoint address. 0 DRW 0 When 1 the instruction breakpoint is enabled. Data watchpoint address 1: 0x50 .. 0x53 This set of registers contains the first address for the four data watchpoints. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x50 .. 0x53: Data watchpoint address 1 Bits Perm 31:0 DRW B.23 50 Init Description Value. Data watchpoint address 2: 0x60 .. 0x63 This set of registers contains the second address for the four data watchpoints. 0x60 .. 0x63: Data watchpoint address 2 Bits Perm 31:0 DRW B.24 Init Description Value. Data breakpoint control register: 0x70 .. 0x73 This set of registers controls each of the four data watchpoints. Bits Perm Init 31:24 RO - 23:16 DRW 0 15:3 0x70 .. 0x73: Data breakpoint control register B.25 Description Reserved A bit for each logical core in the tile allowing the breakpoint to be enabled individually for each logical core. RO - 2 DRW 0 Reserved Set to 1 to enable breakpoints to be triggered on loads. Breakpoints always trigger on stores. 1 DRW 0 By default, data watchpoints trigger if memory in the range [Address1..Address2] is accessed (the range is inclusive of Address1 and Address2). If set to 1, data watchpoints trigger if memory outside the range (Address2..Address1) is accessed (the range is exclusive of Address2 and Address1). 0 DRW 0 When 1 the instruction breakpoint is enabled. Resources breakpoint mask: 0x80 .. 0x83 This set of registers contains the mask for the four resource watchpoints. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x80 .. 0x83: Resources breakpoint mask Bits Perm 31:0 DRW B.26 51 Init Description Value. Resources breakpoint value: 0x90 .. 0x93 This set of registers contains the value for the four resource watchpoints. 0x90 .. 0x93: Resources breakpoint value Bits Perm 31:0 DRW B.27 Init Description Value. Resources breakpoint control register: 0x9C .. 0x9F This set of registers controls each of the four resource watchpoints. Bits X2625, Init 31:24 RO - 23:16 DRW 0 15:2 0x9C .. 0x9F: Resources breakpoint control register Perm Description Reserved A bit for each logical core in the tile allowing the breakpoint to be enabled individually for each logical core. RO - 1 DRW 0 Reserved By default, resource watchpoints trigger when the resource id masked with the set Mask equals the Value. If set to 1, resource watchpoints trigger when the resource id masked with the set Mask is not equal to the Value. 0 DRW 0 When 1 the instruction breakpoint is enabled. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet C 52 xCORE Tile Configuration The xCORE Tile control registers can be accessed using configuration reads and writes (use write_tile_config_reg(tileref, ...) and read_tile_config_reg(tileref, > ...) for reads and writes). Number Figure 42: Summary RO Device identification 0x01 RO xCORE Tile description 1 0x02 RO xCORE Tile description 2 0x04 CRW Control PSwitch permissions to debug registers 0x05 CRW Cause debug interrupts 0x06 RW xCORE Tile clock divider 0x07 RO Security configuration 0x10 .. 0x13 RO PLink status 0x20 .. 0x27 CRW Debug scratch 0x40 RO PC of logical core 0 0x41 RO PC of logical core 1 0x42 RO PC of logical core 2 0x43 RO PC of logical core 3 0x44 RO PC of logical core 4 0x60 RO SR of logical core 0 0x61 RO SR of logical core 1 0x62 RO SR of logical core 2 0x63 RO SR of logical core 3 0x64 RO SR of logical core 4 0x80 .. 0x9F RO Chanend status Device identification: 0x00 Bits X2625, Description 0x00 C.1 0x00: Device identification Perm Perm Init Description 31:24 RO Processor ID of this xCORE tile. 23:16 RO Number of the node in which this xCORE tile is located. 15:8 RO xCORE tile revision. 7:0 RO xCORE tile version. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet C.2 53 xCORE Tile description 1: 0x01 This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile. Bits 0x01: xCORE Tile description 1 Perm Init Description 31:24 RO Number of channel ends. 23:16 RO Number of locks. 15:8 RO 7:0 RO C.3 Number of synchronisers. - Reserved xCORE Tile description 2: 0x02 This register describes the number of timers and clock blocks available on this xCORE tile. Bits 0x02: xCORE Tile description 2 Perm Init 31:16 RO 15:8 RO Number of clock blocks. 7:0 RO Number of timers. C.4 - Description Reserved Control PSwitch permissions to debug registers: 0x04 This register can be used to control whether the debug registers (marked with permission CRW) are accessible through the tile configuration registers. When this bit is set, write -access to those registers is disabled, preventing debugging of the xCORE tile over the interconnect. 0x04: Control PSwitch permissions to debug registers Bits 31:1 0 C.5 Perm RO CRW Init - Description Reserved Set to 1 to restrict PSwitch access to all CRW marked registers to become read-only rather than read-write. Cause debug interrupts: 0x05 This register can be used to raise a debug interrupt in this xCORE tile. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x05: Cause debug interrupts 54 Bits Perm 31:2 RO - 1 RO 0 Set to 1 when the processor is in debug mode. 0 CRW 0 Set to 1 to request a debug interrupt on the processor. C.6 Init Description Reserved xCORE Tile clock divider: 0x06 This register contains the value used to divide the PLL clock to create the xCORE tile clock. The divider is enabled under control of the tile control register 0x06: xCORE Tile clock divider Bits Perm 31:8 RO 7:0 RW C.7 Init - Description Reserved Value of the clock divider minus one. Security configuration: 0x07 Copy of the security register as read from OTP. 0x07: Security configuration Bits Perm 31:0 RO C.8 Init Description Value. PLink status: 0x10 .. 0x13 Status of each of the four processor links; connecting the xCORE tile to the switch. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 31:26 RO 55 Init - Description Reserved 25:24 RO 00 - ChannelEnd, 01 - ERROR, 10 - PSCTL, 11 - Idle. 23:16 RO Based on SRC_TARGET_TYPE value, it represents channelEnd ID or Idle status. 15:6 RO 5:4 RO 3 RO 2 RO 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. 0x10 .. 0x13: PLink status C.9 - Reserved Two-bit network identifier - Reserved 1 when the current packet is considered junk and will be thrown away. Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch. This is the same set of registers as the Debug Scratch registers in the processor status. 0x20 .. 0x27: Debug scratch Bits Perm 31:0 CRW C.10 Init Description Value. PC of logical core 0: 0x40 Value of the PC of logical core 0. 0x40: PC of logical core 0 X2625, Bits Perm 31:0 RO Init Description Value. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet C.11 0x41: PC of logical core 1 0x42: PC of logical core 2 Bits Perm RO Perm 31:0 RO 0x44: PC of logical core 4 Bits Perm RO Value. Init Description Value. Init Description Value. PC of logical core 4: 0x44 Bits Perm 31:0 RO C.15 Description PC of logical core 3: 0x43 31:0 C.14 Init PC of logical core 2: 0x42 Bits C.13 0x43: PC of logical core 3 PC of logical core 1: 0x41 31:0 C.12 56 Init Description Value. SR of logical core 0: 0x60 Value of the SR of logical core 0 0x60: SR of logical core 0 X2625, Bits Perm 31:0 RO Init Description Value. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet C.16 0x61: SR of logical core 1 0x62: SR of logical core 2 Bits Perm RO Perm 31:0 RO 0x64: SR of logical core 4 Bits Perm RO Value. Init Description Value. Init Description Value. SR of logical core 4: 0x64 Bits Perm 31:0 RO C.20 Description SR of logical core 3: 0x63 31:0 C.19 Init SR of logical core 2: 0x62 Bits C.18 0x63: SR of logical core 3 SR of logical core 1: 0x61 31:0 C.17 57 Init Description Value. Chanend status: 0x80 .. 0x9F These registers record the status of each channel-end on the tile. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x80 .. 0x9F: Chanend status X2625, Perm 31:26 RO 58 Init - Description Reserved 25:24 RO 00 - ChannelEnd, 01 - ERROR, 10 - PSCTL, 11 - Idle. 23:16 RO Based on SRC_TARGET_TYPE value, it represents channelEnd ID or Idle status. 15:6 RO 5:4 RO 3 RO 2 RO 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. - Reserved Two-bit network identifier - Reserved 1 when the current packet is considered junk and will be thrown away. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet D 59 Digital Node Configuration The digital node control registers can be accessed using configuration reads and writes (use write_node_config_reg(device, ...) and read_node_config_reg(device, > ...) for reads and writes). Number 0x00 Figure 43: Summary Perm Description RO Device identification 0x01 RO System switch description 0x04 RW Switch configuration 0x05 RW Switch node identifier 0x06 RW PLL settings 0x07 RW System switch clock divider 0x08 RW Reference clock 0x0C RW Directions 0-7 0x0D RW Directions 8-15 0x10 RW DEBUG_N configuration 0x1F RO Debug source 0x20 .. 0x27 RW Link status, direction, and network 0x40 .. 0x43 RW PLink status and network 0x80 .. 0x87 RW Link configuration and initialization 0xA0 .. 0xA7 RW Static link configuration D.1 Device identification: 0x00 This register contains version and revision identifiers and the mode-pins as sampled at boot-time. Bits 0x00: Device identification Perm Init 31:24 RO 23:16 RO Sampled values of pins MODE0, MODE1, ... on reset. 15:8 RO SSwitch revision. 7:0 RO SSwitch version. D.2 0x00 Description Chip identifier. System switch description: 0x01 This register specifies the number of processors and links that are connected to this switch. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x01: System switch description Perm 60 Init 31:24 RO 23:16 RO Number of links on the switch. 15:8 RO Number of cores that are connected to this switch. 7:0 RO Number of links per processor. D.3 - Description Reserved Switch configuration: 0x04 This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode. Bits 0x04: Switch configuration Perm Init 31 RO 0 30:9 RO - 8 RO 0 7:1 RO - 0 RO 0 D.4 Description Set to 1 to disable any write access to the configuration registers in this switch. Reserved Set to 1 to disable updates to the PLL configuration register. Reserved Header mode. Set to 1 to enable 1-byte headers. This must be performed on all nodes in the system. Switch node identifier: 0x05 This register contains the node identifier. Bits 0x05: Switch node identifier Perm Init 31:16 RO - 15:0 RW 0 D.5 Description Reserved The unique 16-bit ID of this node. This ID is matched mostsignificant-bit first with incoming messages for routing purposes. PLL settings: 0x06 An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the tile to be reset. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 31:26 RO 25:23 RW 22:21 RO 20:8 RW 7 RO 6:0 RW 0x06: PLL settings D.6 61 Init - Description Reserved OD: Output divider value The initial value depends on pins MODE0 and MODE1. - Reserved F: Feedback multiplication ratio The initial value depends on pins MODE0 and MODE1. - Reserved R: Oscilator input divider value The initial value depends on pins MODE0 and MODE1. System switch clock divider: 0x07 Sets the ratio of the PLL clock and the switch clock. 0x07: System switch clock divider Bits Perm Init 31:16 RO - 15:0 RW 0 D.7 Description Reserved Switch clock divider. The PLL clock will be divided by this value plus one to derive the switch clock. Reference clock: 0x08 Sets the ratio of the PLL clock and the reference clock used by the node. Bits 0x08: Reference clock Perm Init 31:16 RO - 15:0 RW 3 D.8 Description Reserved Architecture reference clock divider. The PLL clock will be divided by this value plus one to derive the 100 MHz reference clock. Directions 0-7: 0x0C This register contains eight directions, for packets with a mismatch in bits 7..0 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x0C: Directions 0-7 Perm 62 Init Description 31:28 RW 0 The direction for packets whose first mismatching bit is 7. 27:24 RW 0 The direction for packets whose first mismatching bit is 6. 23:20 RW 0 The direction for packets whose first mismatching bit is 5. 19:16 RW 0 The direction for packets whose first mismatching bit is 4. 15:12 RW 0 The direction for packets whose first mismatching bit is 3. 11:8 RW 0 The direction for packets whose first mismatching bit is 2. 7:4 RW 0 The direction for packets whose first mismatching bit is 1. 3:0 RW 0 The direction for packets whose first mismatching bit is 0. D.9 Directions 8-15: 0x0D This register contains eight directions, for packets with a mismatch in bits 15..8 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. Bits 0x0D: Directions 8-15 Perm Init Description 31:28 RW 0 The direction for packets whose first mismatching bit is 15. 27:24 RW 0 The direction for packets whose first mismatching bit is 14. 23:20 RW 0 The direction for packets whose first mismatching bit is 13. 19:16 RW 0 The direction for packets whose first mismatching bit is 12. 15:12 RW 0 The direction for packets whose first mismatching bit is 11. 11:8 RW 0 The direction for packets whose first mismatching bit is 10. 7:4 RW 0 The direction for packets whose first mismatching bit is 9. 3:0 RW 0 The direction for packets whose first mismatching bit is 8. D.10 DEBUG_N configuration: 0x10 Configures the behavior of the DEBUG_N pin. 0x10: DEBUG_N configuration X2625, Bits Perm 31:2 RO Init - Description 1 RW 0 Set to 1 to enable signals on DEBUG_N to generate DCALL on the core. 0 RW 0 When set to 1, the DEBUG_N wire will be pulled down when the node enters debug mode. Reserved XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet D.11 63 Debug source: 0x1F Contains the source of the most recent debug event. 0x1F: Debug source Bits Perm 31:5 RO 4 RW 3:1 RO 0 RW D.12 Init Description - Reserved If set, the external DEBUG_N pin is the source of the most recent debug interrupt. - Reserved If set, the xCORE Tile is the source of the most recent debug interrupt. Link status, direction, and network: 0x20 .. 0x27 These registers contain status information for low level debugging (read-only), the network number that each link belongs to, and the direction that each link is part of. The registers control links C, D, A, B, G, H, E, and F in that order. Bits 0x20 .. 0x27: Link status, direction, and network X2625, Perm Init - Description 31:26 RO 25:24 RO Reserved 23:16 RO 0 15:12 RO - 11:8 RW 0 7:6 RO - 5:4 RW 0 3 RO - 2 RO 0 Set to 1 if the current packet is junk and being thrown away. A packet is considered junk if, for example, it is not routable. 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. If this link is currently routing data into the switch, this field specifies the type of link that the data is routed to: 0: plink 1: external link 2: internal control link If the link is routing data into the switch, this field specifies the destination link number to which all tokens are sent. Reserved The direction that this this link is associated with; set for routing. Reserved Determines the network to which this link belongs, set for quality of service. Reserved XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet D.13 64 PLink status and network: 0x40 .. 0x43 These registers contain status information and the network number that each processor-link belongs to. Bits Perm 31:26 RO 25:24 RO 23:16 RO Init - Description Reserved If this link is currently routing data into the switch, this field specifies the type of link that the data is routed to: 0: plink 1: external link 2: internal control link 0 If the link is routing data into the switch, this field specifies the destination link number to which all tokens are sent. 15:6 RO - 5:4 RW 0 3 RO - 2 RO 0 Set to 1 if the current packet is junk and being thrown away. A packet is considered junk if, for example, it is not routable. 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. 0x40 .. 0x43: PLink status and network D.14 Reserved Determines the network to which this link belongs, set for quality of service. Reserved Link configuration and initialization: 0x80 .. 0x87 These registers contain configuration and debugging information specific to external links. The link speed and width can be set, the link can be initialized, and the link status can be monitored. The registers control links C, D, A, B, G, H, E, and F in that order. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x80 .. 0x87: Link configuration and initialization Perm 65 Init Description 31 RW 0 Write ’1’ to this bit to enable the link, write ’0’ to disable it. This bit controls the muxing of ports with overlapping links. 30 RW 0 Set to 0 to operate in 2 wire mode or 1 to operate in 5 wire mode 29:28 RO - 27 RO 0 Set to 1 on error: an RX buffer overflow or illegal token encoding has been received. This bit clears on reading. 26 RO 0 1 if this end of the link has issued credit to allow the remote end to transmit. 25 RO 0 1 if this end of the link has credits to allow it to transmit. 24 WO 0 Set to 1 to initialize a half-duplex link. This clears this end of the link’s credit and issues a HELLO token; the other side of the link will reply with credits. This bit is self-clearing. 23 WO 0 Set to 1 to reset the receiver. The next symbol that is detected will be assumed to be the first symbol in a token. This bit is self-clearing. 22 RO - 21:11 RW 0 The number of system clocks between two subsequent transitions within a token 10:0 RW 0 The number of system clocks between two subsequent transmit tokens. D.15 Reserved Reserved Static link configuration: 0xA0 .. 0xA7 These registers are used for static (ie, non-routed) links. When a link is made static, all traffic is forwarded to the designated channel end and no routing is attempted. The registers control links C, D, A, B, G, H, E, and F in that order. Bits 0xA0 .. 0xA7: Static link configuration X2625, Perm Init 31 RW 0 30:5 RO - 4:0 RW 0 Description Enable static forwarding. Reserved The destination channel end on this node that packets received in static mode are forwarded to. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet E 66 Analogue Node Configuration The analogue node control registers can be accessed using configuration reads and writes (use write_node_config_reg(device, ...) and read_node_config_reg(device, > ...) for reads and writes). Number Figure 44: Summary E.1 Perm Description 0x00 RO Device identification register 0x04 RW Node configuration register 0x05 RW Node identifier 0x50 RW Reset and Mode Control 0x51 RW System clock frequency 0x80 RW Link Control and Status 0xD6 RW 1 KHz Watchdog Control 0xD7 RW Watchdog Disable Device identification register: 0x00 This register contains version information, and information on power-on behavior. Bits 0x00: Device identification register Perm Init Description 31:24 RO 0x0F 23:17 RO - 16 RO pin 15:8 RO 0x02 Revision number of the analogue block 7:0 RO 0x00 Version number of the analogue block E.2 Chip identifier Reserved Oscillator used on power-up. This is set by the OSC_EXT_N pin: 0: boot from crystal; 1: boot from on-silicon 20 MHz oscillator. Node configuration register: 0x04 This register is used to set the communication model to use (1 or 3 byte headers), and to prevent any further updates. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x04: Node configuration register Perm Init 31 RW 0 30:1 RO - 0 RW 0 E.3 Description Set to 1 to disable further updates to the node configuration and link control and status registers. Reserved Header mode. 0: 3-byte headers; 1: 1-byte headers. Node identifier: 0x05 Bits 0x05: Node identifier 67 Perm Init 31:16 RO - 15:0 RW 0 E.4 Description Reserved 16-bit node identifier. This does not need to be set, and is present for compatibility with XS1-switches. Reset and Mode Control: 0x50 The XS1-S has two main reset signals: a system-reset and an xCORE Tile-reset. System-reset resets the whole system including external devices, whilst xCORE Tile-reset resets the xCORE Tile(s) only. The resets are induced either by software (by a write to the register below) or by one of the following: * External reset on RST_N (System reset) * Brown out on one of the power supplies (System reset) * Watchdog timer (System reset) * Sleep sequence (xCORE Tile reset) * Clock source change (xCORE Tile reset) The minimum system reset duration is achieved when the fastest permissible clock is used. The reset durations will be proportionately longer when a slower clock is used. Note that the minimum system reset duration allows for all power rails except the VOUT2 to turn off, and decay. The length of the system reset comes from an internal counter, counting 524,288 oscillator clock cycles which gives the maximum time allowable for the supply rails to discharge. The system reset duration is a balance between leaving a long time for the supply rails to discharge, and a short time for the system to boot. Example reset times are 44 ms with a 12 MHz oscillator or 5.5 ms with a 96 MHz oscillator. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 31:25 RO 24 RW 23:18 RO 17:16 RW 68 Init - Reserved Processor mode pins. 15:2 RO - 1 WO 0 xCORE Tile reset. Set to 1 to initiate a reset of the xCORE Tile. This bit is self clearing. A write to this configuration register with this bit asserted results in no response packet being sent to the sender regardless of whether or not a response was requested. 0 WO 0 System reset. Set to 1 to initiate a reset whose scope includes most configuration and peripheral control registers. This bit is self clearing. A write to this configuration register with this bit asserted results in no response packet being sent to the sender regardless of whether or not a response was requested. E.5 X2625, Reserved Tristate processor mode pins. - 0x50: Reset and Mode Control 0x51: System clock frequency Description Reserved System clock frequency: 0x51 Bits Perm Init 31:7 RO - 6:0 RW 25 Description Reserved Oscillator clock frequency in MHz rounded up to the nearest integer value. Only values between 5 and 100 MHz are valid writes outside this range are ignored and will be NACKed. This field must be set on start up of the device and any time that the input oscillator clock frequency is changed. It must contain the system clock frequency in MHz rounded up to the nearest integer value. The following functions depend on the correct frequency settings: * Processor reset delay * The watchdog clock * The real-time clock when running in sleep mode XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet E.6 Link Control and Status: 0x80 Bits 0x80: Link Control and Status 69 Perm Init Description 31:28 RO - 27 RO 0 Set to 1 on error: an RX buffer overflow or illegal token encoding has been received. This bit clears on reading. 26 RO 0 1 if this end of the link has issued credit to allow the remote end to transmit. 25 RO 0 1 if this end of the link has credits to allow it to transmit. 24 WO 0 Set to 1 to initialize a half-duplex link. This clears this end of the link’s credit and issues a HELLO token; the other side of the link will reply with credits. This bit is self-clearing. 23 WO 0 Set to 1 to reset the receiver. The next symbol that is detected will be assumed to be the first symbol in a token. This bit is self-clearing. 22 RO - 21:11 RW 1 The number of system clocks between two subsequent transitions within a token 10:0 RW 1 The number of system clocks between two subsequent transmit tokens. E.7 Reserved Reserved 1 KHz Watchdog Control: 0xD6 The watchdog provides a mechanism to prevent programs from hanging by resetting the xCORE Tile after a pre-set time. The watchdog should be periodically “kicked” by the application, causing the count-down to be restarted. If the watchdog expires, it may be due to a program hanging, for example because of a (transient) hardware issue. The watchdog timeout is measured in 1 ms clock ticks, meaning that a time between 1 ms and 65 seconds can be set for the timeout. The watchdog timer is only clocked during the AWAKE power state. When writing the timeout value, both the timeout and its one’s complement should be written. This reduces the chances of accidentally setting kicking the watchdog. If the written value does not comprise a 16-bit value with a 16-bit one’s complement, the request will be NACKed, otherwise an ACK will be sent. If the watchdog expires, the xCORE Tile is reset. 0xD6: 1 KHz Watchdog Control X2625, Bits Perm Init 31:16 RO 0 15:0 RW 1000 Description Current value of watchdog timer. Number of 1kHz cycles after which the watchdog should expire and initiate a system reset. XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet E.8 70 Watchdog Disable: 0xD7 To enable the watchdog, write 0 to this register. To disable the watchdog, write the value 0x0D1SAB1E to this register. 0xD7: Watchdog Disable F Bits Perm 31:0 RW Init 0x0D15AB1E Description A value of 0x0D15AB1E written to this register resets and disables the watchdog timer. ADC Configuration The device has a 12-bit Analogue to Digital Converter (ADC). It has multiple input pins, and on each positive clock edge on port 1I, it samples and converts a value on the next input pin. The data is transmitted to a channel-end that must be set on enabling the ADC input pin. The ADC is peripheral 2. The control registers are accessed using 32-bit reads and writes (use write_periph_32(device, 2, ...) and read_periph_32(device, 2, ...) for reads and writes). Number Figure 45: Summary F.1 Perm Description 0x00 RW ADC Control input pin 0 0x04 RW ADC Control input pin 1 0x08 RW ADC Control input pin 2 0x0C RW ADC Control input pin 3 0x10 RW ADC Control input pin 4 0x14 RW ADC Control input pin 5 0x18 RW ADC Control input pin 6 0x1C RW ADC Control input pin 7 0x20 RW ADC General Control ADC Control input pin 0: 0x00 Controls specific to ADC input pin 0. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x00: ADC Control input pin 0 71 Bits Perm 31:8 RW 0 7:1 RO - 0 RW 0 F.2 Init Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC Control input pin 1: 0x04 Controls specific to ADC input pin 1. 0x04: ADC Control input pin 1 Bits Perm 31:8 RW 0 7:1 RO - 0 RW 0 F.3 Init Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC Control input pin 2: 0x08 Controls specific to ADC input pin 2. 0x08: ADC Control input pin 2 Bits Perm 31:8 RW Init 0 7:1 RO - 0 RW 0 F.4 Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC Control input pin 3: 0x0C Controls specific to ADC input pin 3. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x0C: ADC Control input pin 3 72 Bits Perm 31:8 RW 0 7:1 RO - 0 RW 0 F.5 Init Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC Control input pin 4: 0x10 Controls specific to ADC input pin 4. 0x10: ADC Control input pin 4 Bits Perm 31:8 RW 0 7:1 RO - 0 RW 0 F.6 Init Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC Control input pin 5: 0x14 Controls specific to ADC input pin 5. 0x14: ADC Control input pin 5 Bits Perm 31:8 RW Init 0 7:1 RO - 0 RW 0 F.7 Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC Control input pin 6: 0x18 Controls specific to ADC input pin 6. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x18: ADC Control input pin 6 73 Bits Perm 31:8 RW 0 7:1 RO - 0 RW 0 F.8 Init Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC Control input pin 7: 0x1C Controls specific to ADC input pin 7. 0x1C: ADC Control input pin 7 Bits Perm 31:8 RW 0 7:1 RO - 0 RW 0 F.9 Init Description The node and channel-end identifier to which data for this ADC input pin should be send to. This is the top 24 bits of the channel-end identifier as allocated on an xCORE Tile. Reserved Set to 1 to enable this input pin on the ADC. ADC General Control: 0x20 General ADC control. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x20: ADC General Control G Perm 74 Init 31:25 RO - 24 RO 1 Description Reserved Indicates that an ADC sample has been dropped. This bit is cleared on a read. 23:18 RO - 17:16 RW 1 Reserved Number of bits per ADC sample. The ADC values are always left aligned: 0: 8 bits samples - the least significant four bits of each sample are discarded. 1: 16 bits samples - the sample is padded with four zero bits in bits 3..0. The most significant byte is transmitted first. 2: reserved 3: 32 bits samples - the sample is padded with 20 zero bits in bits 19..0. The most significant byte is transmitted first, hence the word can be input with a single 32-bit IN instruction. 15:8 RW 1 Number of samples to be transmitted per packet. The value 0 indicates that the packet will not be terminated until interrupted by an ADC control register access. 7:2 RO - 1 RW 0 Reserved Set to 1 to switch the ADC to sample a 0.8V signal rather than the external voltage. This can be used to calibrate the ADC. When switching to and from calibration mode, one sample value should be discarded. If a sample value x is measured in calibration mode, then a scale factor 800000/x can be used to translate subsequent measurements into microvolts (using integer arithmetic). 0 RW 0 Set to 1 to enable the ADC. Note that when enabled, the ADC control registers above are read-only. The ADC must be disabled whilst setting up the per-input-pin control. On enabling the ADC, six pulses must be generated to calibrate the ADC. These pulses will not generate packets on the selected channel-end. The seventh and further pulses will deliver samples to the selected channel-end. These six pulses have to be issued every time that this bit is changed from 0 to 1. Deep sleep memory Configuration This peripheral contains a 128 byte RAM that retains state whilst the main processor is put to sleep. The Deep sleep memory is peripheral 3. The control registers are accessed using 8-bit reads and writes (use write_periph_8(device, 3, ...) and read_periph_8 > (device, 3, ...) for reads and writes). X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Number Figure 46: Summary 75 Perm Description 0x00 .. 0x7F RW Deep sleep memory 0xFF RW Deep sleep memory valid G.1 Deep sleep memory: 0x00 .. 0x7F 128 bytes of memory that can be used to hold data when the xCORE Tile is powered down. 0x00 .. 0x7F: Deep sleep memory Bits Perm 7:0 RW G.2 Init Description User defined data Deep sleep memory valid: 0xFF One byte of memory that is reset to 0. The program can write a non zero value in this register to indicate that the data in deep sleep memory is valid. 0xFF: Deep sleep memory valid H Bits Perm 7:0 RW Init 0 Description User defined data, reset to 0. Oscillator Configuration The Oscillator is peripheral 4. The control registers are accessed using 8-bit reads and writes (use write_periph_8(device, 4, ...) and read_periph_8(device, 4, ...) for reads and writes). Number Figure 47: Summary X2625, Perm Description 0x00 RW General oscillator control 0x01 RW On-silicon-oscillator control 0x02 RW Crystal-oscillator control XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet H.1 76 General oscillator control: 0x00 Bits Perm 7:2 RO - 1 RW 0 0 RW pin 0x00: General oscillator control H.2 Init Description Reserved Set to 1 to reset the xCORE Tile when the value of the oscillator select control register (bit 0) is changed. Selects the oscillator to use: 0: Crystal oscillator 1: On-silicon oscillator On-silicon-oscillator control: 0x01 This register controls the on-chip logic that implements an on-chip oscillator. The on-chip oscillator does not require an external crystal, but does not provide an accurate timing source. The nominal frequency of the on-silicon-oscillator is given below, but the actual frequency are temperature, voltage, and chip dependent. Bits Perm Init Description 7:2 RO - 1 RW 0 Selects the clock speed of the on-chip oscillator: 0: approximately 20 Mhz (fast clock) 1: approximately 31,250 Hz (slow clock) 0 RW 1 Set to 0 to disable the on-chip oscillator. Do not do this unless the xCORE Tile is running off the crystal oscillator. 0x01: On-siliconoscillator control H.3 Reserved Crystal-oscillator control: 0x02 This register controls the on-chip logic that implements the crystal oscillator; the crystal-oscillator requires an external crystal. 0x02: Crystaloscillator control X2625, Bits Perm 7:2 RO Init - Description 1 RW 1 Set to 0 to disable the crystal bias circuit. Only switch the bias off if an external oscillator rather than a crystal is connected. 0 RW 1 Set to 0 to disable the crystal oscillator. Do not do this unless the xCORE Tile is running off the on-silicon oscillator. Reserved XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet I 77 Real time clock Configuration The Real time clock is peripheral 5. The control registers are accessed using 32-bit reads and writes (use write_periph_32(device, 5, ...) and read_periph_32(device, > 5, ...) for reads and writes). Number Figure 48: Summary I.1 Perm Description 0x00 RW Real time counter least significant 32 bits 0x04 RW Real time counter most significant 32 bits Real time counter least significant 32 bits: 0x00 This registers contains the lower 32-bits of the real-time counter. 0x00: Real time counter least significant 32 bits Bits Perm 31:0 RO I.2 Init 0 Description Least significant 32 bits of real-time counter. Real time counter most significant 32 bits: 0x04 This registers contains the upper 32-bits of the real-time counter. 0x04: Real time counter most significant 32 bits J Bits Perm 31:0 RO Init 0 Description Most significant 32 bits of real-time counter. Power control block Configuration The Power control block is peripheral 6. The control registers are accessed using 32-bit reads and writes (use write_periph_32(device, 6, ...) and read_periph_32( > device, 6, ...) for reads and writes). X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Number Figure 49: Summary J.1 Perm 78 Description 0x00 RW General control 0x04 RW Time to wake-up, least significant 32 bits 0x08 RW Time to wake-up, most significant 32 bits 0x0C RW Power supply states whilst ASLEEP 0x10 RW Power supply states whilst WAKING1 0x14 RW Power supply states whilst WAKING2 0x18 RW Power supply states whilst AWAKE 0x1C RW Power supply states whilst SLEEPING1 0x20 RW Power supply states whilst SLEEPING2 0x24 RW Power sequence status 0x2C RW DCDC control 0x30 RW Power supply status 0x34 RW VDDCORE level control 0x40 RW LDO5 level control General control: 0x00 This register controls the basic settings for power modes. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 79 Bits Perm 31:8 RO - 7 RW 0 6 WO 5 RW 0 Set to 1 to use a 64-bit timer. 4 RW 0 Set to 1 to wake-up on the timer. 3 RW 1 If waking on the WAKE pin is enabled (see above), then by default the device wakes up when the WAKE pin is pulled high. Set to 0 to wake-up when the WAKE pin is pulled low. 2 RW 0 Set to 1 to wake-up when the WAKE pin is at the right level. 1 RW 0 Set to 1 to initiate sleep sequence - self clearing. Only set this bit when in AWAKE state. 0 RW 0 Sleep clock select. Set to 1 to use the default clock rather than the internal 31.25 kHz oscillator. Note: this bit is only effective in the ASLEEP state. 0x00: General control J.2 Init Description Reserved By default, when waking up, the voltage levels stored in the LEVEL CONTROL registers are used. Set to 1 to use the power-on voltage levels. Set to 1 to re-apply the current contents of the AWAKE state. Use this when the program has changed the contents of the AWAKE state register. Self clearing. Time to wake-up, least significant 32 bits: 0x04 This register stores the time to wake-up. The value is only used if wake-up from the real-time clock is enabled, and the device is asleep. 0x04: Time to wake-up, least significant 32 bits Bits Perm 31:0 RW J.3 Init 0 Description Least significant 32 bits of time to wake-up. Time to wake-up, most significant 32 bits: 0x08 This register stores the time to wake-up. The value is only used if wake-up from the real-time clock is enabled, if 64-bit comparisons are enabled, and the device is asleep. In most cases, 32-bit comparisons suffice. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x08: Time to wake-up, most significant 32 bits Bits Perm 31:0 RW J.4 80 Init Description 0 Most significant 32 bits of time to wake-up (ignored unless 64-bit timer comparison is enabled). Power supply states whilst ASLEEP: 0x0C This register controls the state the power control block should be in when in the ASLEEP state. It also defines the minimum time that the system shall stay in this state. When the minimum time is expired, the next state may be entered if either of the wake conditions (real-time counter or WAKE pin) happens. Note that the minimum number of cycles is counted in according to the currently enabled clock, which may be the slow 31 KHz clock. Bits 0x0C: Power supply states whilst ASLEEP X2625, Perm Init 31:21 RO - 20:16 RW 16 Description Reserved Log2 number of cycles to stay in this state: 0: 1 clock cycles 1: 2 clock cycles 2: 4 clock cycles ... 31: 2147483648 clock cycles 15 RO - 14 RW 0 Reserved 13:10 RO - 9 RW 0 Sets modulation used by DCDC2: 0: PWM modulation (max 475 mA) 1: PFM modulation (max 50 mA) 8 RW 0 Sets modulation used by DCDC1: 0: PWM modulation (max 700 mA) 1: PFM modulation (max 50 mA) Set to 1 to disable clock to the xCORE Tile. Reserved 7:6 RO - 5 RW 0 Reserved Set to 1 to enable VOUT6 (IO supply). Set to 1 to enable LDO5 (core PLL supply). 4 RW 0 3:2 RO - 1 RO 0 Set to 1 to enable DCDC2 (analogue supply). 0 RW 0 Set to 1 to enable DCDC1 (core supply). Reserved XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet J.5 81 Power supply states whilst WAKING1: 0x10 This register controls what state the power control block should be in when in the WAKING1 state. It also defines the minimum time that the system shall stay in this state. When the minimum time is expired, the next state is entered if all enabled power supplies are good. Bits Perm Init 31:21 RO - 20:16 RW 16 15 RO - Description Reserved Log2 number of cycles to stay in this state: 0: 1 clock cycles 1: 2 clock cycles 2: 4 clock cycles ... 31: 2147483648 clock cycles Reserved 14 RW 0 13:10 RO - 9 RW 0 Sets modulation used by DCDC2: 0: PWM modulation (max 475 mA) 1: PFM modulation (max 50 mA) 8 RW 0 Sets modulation used by DCDC1: 0: PWM modulation (max 700 mA) 1: PFM modulation (max 50 mA) 0x10: Power supply states whilst WAKING1 J.6 Set to 1 to disable clock to the xCORE Tile. Reserved 7:6 RO - 5 RW 1 Reserved Set to 1 to enable VOUT6 (IO supply). 4 RW 0 Set to 1 to enable LDO5 (core PLL supply). 3:2 RO - 1 RO 0 Set to 1 to enable DCDC2 (analogue supply). 0 RW 0 Set to 1 to enable DCDC1 (core supply). Reserved Power supply states whilst WAKING2: 0x14 This register controls what state the power control block should be in when in the WAKING2 state. It also defines the minimum time that the system shall stay in this state. When the minimum time is expired, the next state is entered if all enabled power supplies are good. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 82 Init 31:21 RO - 20:16 RW 16 15 RO - Description Reserved Log2 number of cycles to stay in this state: 0: 1 clock cycles 1: 2 clock cycles 2: 4 clock cycles ... 31: 2147483648 clock cycles Reserved 14 RW 0 13:10 RO - 9 RW 0 Sets modulation used by DCDC2: 0: PWM modulation (max 475 mA) 1: PFM modulation (max 50 mA) 8 RW 0 Sets modulation used by DCDC1: 0: PWM modulation (max 700 mA) 1: PFM modulation (max 50 mA) 7:6 RO - 5 RW 1 Set to 1 to enable VOUT6 (IO supply). 4 RW 1 Set to 1 to enable LDO5 (core PLL supply). 3:2 RO - 1 RO 1 Set to 1 to enable DCDC2 (analogue supply). 0 RW 1 Set to 1 to enable DCDC1 (core supply). 0x14: Power supply states whilst WAKING2 J.7 Set to 1 to disable clock to the xCORE Tile. Reserved Reserved Reserved Power supply states whilst AWAKE: 0x18 This register controls what state the power control block should be in when in the AWAKE state. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 83 Init 31:15 RO - Description Reserved 14 RW 0 13:10 RO - 9 RW 0 Sets modulation used by DCDC2: 0: PWM modulation (max 475 mA) 1: PFM modulation (max 50 mA) 8 RW 0 Sets modulation used by DCDC1: 0: PWM modulation (max 700 mA) 1: PFM modulation (max 50 mA) 0x18: Power supply states whilst AWAKE J.8 Set to 1 to disable clock to the xCORE Tile. Reserved 7:6 RO - 5 RW 1 Reserved Set to 1 to enable VOUT6 (IO supply). 4 RW 1 Set to 1 to enable LDO5 (core PLL supply). 3:2 RO - 1 RO 1 Set to 1 to enable DCDC2 (analogue supply). 0 RW 1 Set to 1 to enable DCDC1 (core supply). Reserved Power supply states whilst SLEEPING1: 0x1C This register controls what state the power control block should be in when in the SLEEPING1 state. It also defines the time that the system shall stay in this state. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 84 Init 31:21 RO - 20:16 RW 16 15 RO - Description Reserved Log2 number of cycles to stay in this state: 0: 1 clock cycles 1: 2 clock cycles 2: 4 clock cycles ... 31: 2147483648 clock cycles Reserved 14 RW 0 13:10 RO - 9 RW 0 Sets modulation used by DCDC2: 0: PWM modulation (max 475 mA) 1: PFM modulation (max 50 mA) 8 RW 0 Sets modulation used by DCDC1: 0: PWM modulation (max 700 mA) 1: PFM modulation (max 50 mA) 7:6 RO - 5 RW 1 Set to 1 to enable VOUT6 (IO supply). 4 RW 0 Set to 1 to enable LDO5 (core PLL supply). 3:2 RO - 1 RO 1 Set to 1 to enable DCDC2 (analogue supply). 0 RW 0 Set to 1 to enable DCDC1 (core supply). 0x1C: Power supply states whilst SLEEPING1 J.9 Set to 1 to disable clock to the xCORE Tile. Reserved Reserved Reserved Power supply states whilst SLEEPING2: 0x20 This register controls what state the power control block should be in when in the SLEEPING2 state. It also defines the time that the system shall stay in this state. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x20: Power supply states whilst SLEEPING2 Perm 85 Init 31:21 RO - 20:16 RW 16 15 RO - Description Reserved Log2 number of cycles to stay in this state: 0: 1 clock cycles 1: 2 clock cycles 2: 4 clock cycles ... 31: 2147483648 clock cycles Reserved 14 RW 0 13:10 RO - 9 RW 0 Sets modulation used by DCDC2: 0: PWM modulation (max 475 mA) 1: PFM modulation (max 50 mA) 8 RW 0 Sets modulation used by DCDC1: 0: PWM modulation (max 700 mA) 1: PFM modulation (max 50 mA) 7:6 RO - 5 RW 0 Set to 1 to enable VOUT6 (IO supply). 4 RW 0 Set to 1 to enable LDO5 (core PLL supply). 3:2 RO - 1 RO 1 Set to 1 to enable DCDC2 (analogue supply). 0 RW 0 Set to 1 to enable DCDC1 (core supply). J.10 Set to 1 to disable clock to the xCORE Tile. Reserved Reserved Reserved Power sequence status: 0x24 This register defines the current status of the power supply controller. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x24: Power sequence status Perm 86 Init Description 31:30 RO - Reserved 29 RO 0 1 if VOUT6 was enabled in the previous state. 28 RO 0 1 if LDO5 was enabled in the previous state. 27:26 RO - 25 RO 1 1 if DCDC2 was enabled in the previous state. 24 RO 0 1 if DCDC1 was enabled in the previous state. 23:19 RO - 18:16 RO 15 RO - Reserved Reserved Current state of the power sequence state machine 0: Reset 1: Asleep 2: Waking 1 3: Waking 2 4: Awake Wait 5: Awake 6: Sleeping 1 7: Sleeping 2 Reserved 14 RO 0 13:10 RO - 9 RO 0 Sets modulation used by DCDC2: 0: PWM modulation (max 475 mA) 1: PFM modulation (max 50 mA) 8 RO 0 Sets modulation used by DCDC1: 0: PWM modulation (max 700 mA) 1: PFM modulation (max 50 mA) 7:6 RO - 5 RO 0 Set to 1 to enable VOUT6 (IO supply). 4 RO 0 Set to 1 to enable LDO5 (core PLL supply). 3:2 RO - 1 RO 0 Set to 1 to enable DCDC2 (analogue supply). 0 RO 0 Set to 1 to enable DCDC1 (core supply). J.11 Set to 1 to disable clock to the xCORE Tile. Reserved Reserved Reserved DCDC control: 0x2C This register controls the two DC-DC converters. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits Perm 87 Init 31:26 RO - 25:24 RW 2 23:17 RO - 16 RW 0 15 RO - 14:13 RW 0 12:10 RO - 9:8 RW 1 7 RO - 6:5 RW 0 4:2 RO - 1:0 RW 1 0x2C: DCDC control J.12 Description Reserved Sets the power good level for VDDCORE and VDD1V8: 0: 0.80 x VDDCORE, 0.80 x VDD1V8 1: 0.85 x VDDCORE, 0.85 x VDD1V8 2: 0.90 x VDDCORE, 0.90 x VDD1V8 3: 0.75 x VDDCORE, 0.75 x VDD1V8 Reserved Clear DCDC1 and DCDC2 error flags, not self clearing. Reserved Sets the DCDC2 current limit: 0: 1A 1: 1.5A 2: 2A 3: 0.5A Reserved Sets the clock used by DCDC2 to generate VDD1V8: 0: 0.9 MHz 1: 1.0 MHz 2: 1.1 MHz 3: 1.2 MHz Reserved Sets the DCDC1 current limit: 0: 1.2A 1: 1.8A 2: 2.5A 3: 0.8A Reserved Sets the clock used by DCDC1 to generate VDDCORE: 0: 0.9 MHz 1: 1.0 MHz 2: 1.1 MHz 3: 1.2 MHz Power supply status: 0x30 This register provides the current status of the power supplies. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet Bits 0x30: Power supply status Perm 31:25 RO 88 Init - Description Reserved 24 RO 23:20 RO 19 RO 18:17 RO 16 RO 15:10 RO 9 RO 1 if DCDC2 is in current limiting mode. 8 RO 1 if DCDC1 is in current limiting mode. 7:2 RO 1 RO 1 if DCDC2 is in soft-start mode. 0 RO 1 if DCDC1 is in soft-start mode. J.13 1 if on-silicon oscillator is stable. - Reserved 1 if VDDPLL is good. - Reserved 1 if VDDCORE is good. - - Reserved Reserved VDDCORE level control: 0x34 This register can be used to set the desired voltage on VDDCORE. If the level is to be raised or lowered, it should be raised in steps of no more than 10 mV per microsecond in order to prevent overshoot and undershoot. The default value depends on the MODE pins. Bits Perm 31:7 RO - 6:0 RW pin 0x34: VDDCORE level control J.14 Init Description Reserved The required voltage in 10 mV steps: 0: 0.60V 1: 0.61V 2: 0.62V ... 69: 1.29V 70: 1.30V LDO5 level control: 0x40 This register can be used to set the desired voltage on LDO5. If the level is to be raised, it should be raised in steps of 1 (100 mV). The default value depends on the MODE pins. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 0x40: LDO5 level control X2625, 89 Bits Perm Init 31:3 RO - 2:0 RW pin Description Reserved The required voltage in 100 mV steps: 0: 0.6V 1: 0.7V 2: 0.8V ... 6: 1.2V 7: 1.3V XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet K 90 XMOS USB Interface XMOS provides a low-level USB interface for connecting the device to a USB transceiver using the UTMI+ Low Pin Interface (ULPI). The ULPI signals must be connected to the pins named in Figure 50. Note also that some ports on the same tile are used internally and are not available for use when the USB driver is active (they are available otherwise). Pin Pin Signal Pin XnD02 XnD12 ULPI_STP XnD26 XnD03 XnD13 ULPI_NXT XnD27 XnD04 XnD14 ULPI_DATA[0] XnD28 XnD15 ULPI_DATA[1] XnD29 XnD16 ULPI_DATA[2] XnD30 XnD07 XnD17 ULPI_DATA[3] XnD31 XnD08 XnD18 ULPI_DATA[4] XnD32 XnD09 XnD19 ULPI_DATA[5] XnD33 XnD20 ULPI_DATA[6] XnD21 ULPI_DATA[7] XnD37 XnD22 ULPI_DIR XnD38 XnD23 ULPI_CLK XnD39 XnD05 XnD06 Unavailable when USB active XnD40 Figure 50: ULPI signals provided by the XMOS USB driver L Signal XnD41 Signal Unavailable when USB active Unavailable when USB active XnD42 XnD43 Device Errata This section describes minor operational differences from the data sheet and recommended workarounds. As device and documentation issues become known, this section will be updated the document revised. To guarantee a logic low is seen on the pins DEBUG_N, MODE[4:0], TMS, TCK and TDI, the driving circuit should present an impedance of less than 100 Ω to ground. Usually this is not a problem for CMOS drivers driving single inputs. If one or more of these inputs are placed in parallel, however, additional logic buffers may be required to guarantee correct operation. For static inputs tied high or low, the relevant input pin should be tied directly to GND or VDDIO. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet M 91 JTAG, xSCOPE and Debugging If you intend to design a board that can be used with the XMOS toolchain and xTAG debugger, you will need an xSYS header on your board. Figure 51 shows a decision diagram which explains what type of xSYS connectivity you need. The three subsections below explain the options in detail. YES YES Is xSCOPE required YES Figure 51: Decision diagram for the xSYS header Use full xSYS header See section 3 M.1 Is debugging required? NO Is fast printf required ? NO YES Does the SPI flash need to be programmed? NO NO Use JTAG xSYS header See section 2 No xSYS header required See section 1 No xSYS header The use of an xSYS header is optional, and may not be required for volume production designs. However, the XMOS toolchain expects the xSYS header; if you do not have an xSYS header then you must provide your own method for writing to flash/OTP and for debugging. M.2 JTAG-only xSYS header The xSYS header connects to an xTAG debugger, which has a 20-pin 0.1" female IDC header. The design will hence need a male IDC header. We advise to use a boxed header to guard against incorrect plug-ins. If you use a 90 degree angled header, make sure that pins 2, 4, 6, ..., 20 are along the edge of the PCB. Connect pins 4, 8, 12, 16, 20 of the xSYS header to ground, and then connect: · TDI to pin 5 of the xSYS header · TMS to pin 7 of the xSYS header · TCK to pin 9 of the xSYS header · DEBUG_N to pin 11 of the xSYS header X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet 92 · TDO to pin 13 of the xSYS header · RST_N to pin 15 of the xSYS header · If MODE2 is configured high, connect MODE2 to pin 3 of the xSYS header. Do not connect to VDDIO. · If MODE3 is configured high, connect MODE3 to pin 3 of the xSYS header. Do not connect to VDDIO. The RST_N net should be open-drain, active-low, and have a pull-up to VDDIO. M.3 Full xSYS header For a full xSYS header you will need to connect the pins as discussed in Section M.2, and then connect a 2-wire xCONNECT Link to the xSYS header. The links can be found in the Signal description table (Section 4): they are labelled XLA, XLB, etc in the function column. The 2-wire link comprises two inputs and outputs, labelled 0 0 1 1 out , out , in , and in . For example, if you choose to use XLB of tile 0 for xSCOPE I/O, you need to connect up XLB1out , XLB0out , XLB0in , XLB1in as follows: · XLB1out (X0D16) to pin 6 of the xSYS header with a 33R series resistor close to the device. · XLB0out (X0D17) to pin 10 of the xSYS header with a 33R series resistor close to the device. · XLB0in (X0D18) to pin 14 of the xSYS header. · XLB1in (X0D19) to pin 18 of the xSYS header. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet N 93 Schematics Design Check List This section is a checklist for use by schematics designers using the XS1-A10A-128-FB217. Each of the following sections contains items to check for each design. N.1 Clock Pins MODE0 and MODE1 are set to the correct value for the chosen frequency. The MODE settings are shown in the Oscillator section, Section 8. If you have a choice between two values, choose the value with the highest multiplier ratio since that will boot faster. OSC_EXT_N is tied to ground (for use with a crystal or oscillator) or tied to VDDIO (for use with the internal oscillator). If using the internal oscillator, set MODE0 and MODE1 to be for the 20-48 MHz range (Section 8). If you have used an oscillator, it is a 1V8 oscillator. (Section 16) N.2 USB ULPI Mode This section can be skipped if you do not have an external USB PHY. If using ULPI, the ULPI signals are connected to specific ports as shown in Section K. If using ULPI, the ports that are used internally are not connected, see Section K. (Note that this limitation only applies when the ULPI is enabled, they can still be used before or after the ULPI is being used.) N.3 Boot The device is connected to a SPI flash for booting, connected to X0D0, X0D01, X0D10, and X0D11 (Section 9). If not, you must boot the device through OTP or JTAG. The device that is connected to flash has both MODE2 and MODE3 connected to pin 3 on the xSYS Header (MSEL). If no debug adapter connection is supported (not recommended) MODE2 and MODE3 are to be left NC (Section 9). MODE4 is set in accordance with Section 9. The SPI flash that you have chosen is supported by xflash, or you have created a specification file for it. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet N.4 94 JTAG, XScope, and debugging You have decided as to whether you need an XSYS header or not (Section M) If you included an XSYS header, you connected pin 3 to any MODE2/MODE3 pin that would otherwise be NC (Section M). If you have not included an XSYS header, you have devised a method to program the SPI-flash or OTP (Section M). N.5 GPIO You have not mapped both inputs and outputs to the same multi-bit port. N.6 Multi device designs Skip this section if your design only includes a single XMOS device. One device is connected to a SPI flash for booting. Devices that boot from link have MODE2 grounded and MODE3 NC. These device must have link XLB connected to a device to boot from (see 9). If you included an XSYS header, you have included buffers for RST_N, TMS, TCK, MODE2, and MODE3 (Section L). X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet O 95 PCB Layout Design Check List This section is a checklist for use by PCB designers using the XS1A10A-128-FB217. Each of the following sections contains items to check for each design. O.1 Ground Balls and Ground Plane There is one via for every other ground ball to minimize impedance and conduct heat away from the device (Section 15.1). There are only few non-ground vias around the square of ground balls, to creating a good, solid, ground plane. O.2 Power supply decoupling VSUP has a ceramic X5R or X7R bulk decoupler as close as possible to the VSUP and PGND (VDDCORE) pins; right next to the device (Section 15). The 1V0 decoupling cap is close to the VDDCORE and PGND pins (Section 15). The 1V8 decoupling cap is close to the VDD1V8 and PGND pins (Section 15). All PGND nets are connected together prior to connection to the main ground plane (Section 15). An example PCB layout is shown in Section 16. Placing the decouplers too far away may lead to the device not coming up, or not operating properly. X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet P 96 Associated Design Documentation Document Title Information Document Number Programming XC on XMOS Devices Timers, ports, clocks, cores and channels X9577 xTIMEcomposer User Guide Compilers, assembler and linker/mapper X3766 Timing analyzer, xScope, debugger Flash and OTP programming utilities Q Related Documentation Document Title Information Document Number The XMOS XS1 Architecture ISA manual X7879 XS1 Port I/O Timing Port timings X5821 xCONNECT Architecture Link, switch and system information X4249 XS1-L Link Performance and Design Guidelines Link timings X2999 XS1-L Clock Frequency Control Advanced clock control X1433 X2625, XS1-A10A-128-FB217 XS1-A10A-128-FB217 Datasheet R 97 Revision History Date Description 2013-04-16 First release 2013-07-19 Updated Features list with available ports and links - Section 2 Simplified link bits in Signal Description - Section 4 New JTAG, xSCOPE and Debugging appendix - Section M New Schematics Design Check List - Section N New PCB Layout Design Check List - Section O 2013-12-09 Added Industrial Ambient Temperature - Section 17.1 Annotated V(ACC) parameter - Section 17.2 Updated V(IH) parameter - Section 17.9 Updated V(OH) parameter - Section 17.5 2014-02-26 Added C8 and I8 parts - Section 19 2014-03-25 Added footnotes to DC and Switching Characteristics - Section 17 2015-04-14 Updated Introduction - Section 1; Pin Configuration - Section 3; Signal Description - Section 4 Copyright © 2015, All Rights Reserved. Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. X2625, XS1-A10A-128-FB217