XS1-L16A-128-QF124-I8

XS1-L16A-128-QF124 Datasheet 2015/04/14 XMOS © 2015, All Rights Reserved Document Number: X8006, XS1-L16A-128-QF124 Datasheet 1 Table of Contents 1 xCORE Multicore Microcontrollers . 2 XS1-L16A-128-QF124 Features . . 3 Pin Configuration . . . . . . . . . . 4 Signal Description . . . . . . . . . . 5 Product Overview . . . . . . . . . . 6 PLL . . . . . . . . . . . . . . . . . . . 7 Boot Procedure . . . . . . . . . . . . 8 Memory . . . . . . . . . . . . . . . . 9 JTAG . . . . . . . . . . . . . . . . . . 10 Board Integration . . . . . . . . . . 11 DC and Switching Characteristics . 12 Package Information . . . . . . . . 13 Ordering Information . . . . . . . . Appendices . . . . . . . . . . . . . . . . . A Configuration of the XS1 . . . . . . B Processor Status Configuration . . C Tile Configuration . . . . . . . . . . D Node Configuration . . . . . . . . . E XMOS USB Interface . . . . . . . . . F Device Errata . . . . . . . . . . . . . G JTAG, xSCOPE and Debugging . . . H Schematics Design Check List . . . I PCB Layout Design Check List . . . J Associated Design Documentation K Related Documentation . . . . . . . L Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 5 6 10 13 14 16 18 19 24 28 29 30 30 32 41 49 56 56 57 59 62 63 63 64 TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/. XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation that the information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used without written permission. Company and product names mentioned in this document are the trademarks or registered trademarks of their respective owners. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 1 2 xCORE Multicore Microcontrollers The XS1-L Series is a comprehensive range of 32-bit multicore microcontrollers that brings the low latency and timing determinism of the xCORE architecture to mainstream embedded applications. Unlike conventional microcontrollers, xCORE multicore microcontrollers execute multiple real-time tasks simultaneously and communicate between tasks using a high speed network. Because xCORE multicore microcontrollers are completely deterministic, you can write software to implement functions that traditionally require dedicated hardware. PLL Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAG debug Hardware response ports xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCONNECT channels, links I/O Pins xCORE logical core xCORE logical core xCORE logical core Hardware response ports xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core Figure 1: XS1-L Series: 4-16 core devices xCONNECT channels, links I/O Pins xCORE logical core xCORE logical core xCORE logical core PLL Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAG debug Key features of the XS1-L16A-128-QF124 include: · Tiles: Devices consist of one or more xCORE tiles. Each tile contains between four and eight 32-bit xCOREs with highly integrated I/O and on-chip memory. · Logical cores Each logical core can execute tasks such as computational code, DSP code, control software (including logic decisions and executing a state machine) or software that handles I/O. Section 5.1 · xTIME scheduler The xTIME scheduler performs functions similar to an RTOS, in hardware. It services and synchronizes events in a core, so there is no requirement for interrupt handler routines. The xTIME scheduler triggers cores on events generated by hardware resources such as the I/O pins, communication channels and timers. Once triggered, a core runs independently and concurrently to other cores, until it pauses to wait for more events. Section 5.2 X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 3 · Channels and channel ends Tasks running on logical cores communicate using channels formed between two channel ends. Data can be passed synchronously or asynchronously between the channel ends assigned to the communicating tasks. Section 5.5 · xCONNECT Switch and Links Between tiles, channel communications are implemented over a high performance network of xCONNECT Links and routed through a hardware xCONNECT Switch. Section 5.6 · Ports The I/O pins are connected to the processing cores by Hardware Response ports. The port logic can drive its pins high and low, or it can sample the value on its pins optionally waiting for a particular condition. Section 5.3 · Clock blocks xCORE devices include a set of programmable clock blocks that can be used to govern the rate at which ports execute. Section 5.4 · Memory Each xCORE Tile integrates a bank of SRAM for instructions and data, and a block of one-time programmable (OTP) memory that can be configured for system wide security features. Section 8 · PLL The PLL is used to create a high-speed processor clock given a low speed external oscillator. Section 6 · JTAG The JTAG module can be used for loading programs, boundary scan testing, in-circuit source-level debugging and programming the OTP memory. Section 9 1.1 Software Devices are programmed using C, C++ or xC (C with multicore extensions). XMOS provides tested and proven software libraries, which allow you to quickly add interface and processor functionality such as USB, Ethernet, PWM, graphics driver, and audio EQ to your applications. 1.2 xTIMEcomposer Studio The xTIMEcomposer Studio development environment provides all the tools you need to write and debug your programs, profile your application, and write images into flash memory or OTP memory on the device. Because xCORE devices operate deterministically, they can be simulated like hardware within xTIMEcomposer: uniquely in the embedded world, xTIMEcomposer Studio therefore includes a static timing analyzer, cycle-accurate simulator, and high-speed in-circuit instrumentation. xTIMEcomposer can be driven from either a graphical development environment, or the command line. The tools are supported on Windows, Linux and MacOS X and available at no cost from xmos.com/downloads. Information on using the tools is provided in the xTIMEcomposer User Guide, X3766. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 2 4 XS1-L16A-128-QF124 Features · Multicore Microcontroller with Advanced Multi-Core RISC Architecture • 16 real-time logical cores on 2 xCORE tiles • Cores share up to 1000 MIPS • Each logical core has: — Guaranteed throughput of between 1/4 and 1/8 of tile MIPS — 16x32bit dedicated registers • 159 high-density 16/32-bit instructions — All have single clock-cycle execution (except for divide) — 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions · Programmable I/O • 84 general-purpose I/O pins, configurable as input or output — Up to 32 x 1bit port, 12 x 4bit port, 7 x 8bit port, 3 x 16bit port — 4 xCONNECT links • Port sampling rates of up to 60 MHz with respect to an external clock • 64 channel ends for communication with other cores, on or off-chip · Memory • 128KB internal single-cycle SRAM (max 64KB per tile) for code and data storage • 16KB internal OTP (max 8KB per tile) for application boot code · Hardware resources • 12 clock blocks (6 per tile) • 20 timers (10 per tile) • 8 locks (4 per tile) · JTAG Module for On-Chip Debug · Security Features • Programming lock disables debug and prevents read-back of memory contents • AES bootloader ensures secrecy of IP held on external flash memory · Ambient Temperature Range • Commercial qualification: 0 °C to 70 °C • Industrial qualification: -40 °C to 85 °C · Speed Grade • 10: 1000 MIPS • 8: 800 MIPS · Power Consumption • Active Mode — 400 mA at 500 MHz (typical) — 320 mA at 400 MHz (typical) • Standby Mode — 28 mA · 124-pin dual-row QFN package 0.5 mm pitch X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 3 5 Pin Configuration A1 GND A68 VDD A67 X0D25 A66 X0D21 A65 X0D20 A64 X0D19 A63 X0D18 A62 X0D23 A61 X0D17 A60 X0D16 A59 X0D15 A58 X0D14 A57 X0D13 A56 X0D22 A55 X0D12 A54 X0D24 B56 VDD B55 X0D43 B54 X0D42 B53 X0D41 B52 X0D40 B51 X0D39 B50 X0D38 B49 X0D37 B48 X0D36 B47 X0D33 B46 X0D32 B45 X0D31 B44 X0D30 B43 VDD A53 VDD A52 GND A2 VDDIO A51 VDDIO A3 X0D35 B1 VDDIO B42 VDDIO A50 X1D11 A4 X0D34 B2 PCU_ WAKE B41 X0D29 A49 X1D10 A5 X0D02 B3 PCU_ GATE B40 X0D28 A48 X1D09 A6 X0D03 B4 PCU_ VDDIO B39 X0D27 A47 X1D08 A7 X0D04 B5 PCU_ VDD B38 X0D26 A46 X1D07 A8 X0D05 B6 PCU_ CLK B37 DEBUG_ N A45 X1D06 A9 X0D06 B7 CLK B36 MODE[3] A44 X1D05 A10 X0D07 B8 RST_N B35 MODE[2] A43 X1D04 A11 X0D08 B9 TDO B34 MODE[1] A42 X1D03 A12 X0D09 B10 TCK B33 MODE[0] A41 X1D02 A13 X0D10 B11 TMS B32 OTP_ VCC A40 X1D01 A14 X0D11 B12 TDI B31 X1D39 A39 X1D00 A15 X0D00 B13 TRST_ N B30 X1D38 A38 PLL_ AVDD A16 X0D01 B14 VDDIO B29 VDDIO A37 PLL_ AGND GND A17 VDDIO A18 GND X8006, A36 VDDIO A19 VDD B15 VDD B16 X1D26 B17 X1D27 B18 X1D28 B19 X1D29 B20 X1D30 B21 X1D31 B22 X1D32 B23 X1D33 B24 X1D34 B25 X1D35 B26 X1D36 B27 X1D37 B28 VDD A20 X1D24 A21 X1D12 A22 X1D22 A23 X1D13 A24 X1D14 A25 X1D15 A26 X1D16 A27 X1D17 A28 X1D23 A29 X1D18 A30 X1D19 A31 X1D20 A32 X1D21 A33 X1D25 A34 VDD A35 MODE[4] XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 4 6 Signal Description This section lists the signals and I/O pins available on the XS1-L16A-128-QF124. The device provides a combination of 1bit, 4bit, 8bit and 16bit ports, as well as wider ports that are fully or partially (gray) bonded out. All pins of a port provide either output or input, but signals in different directions cannot be mapped onto the same port. Pins may have one or more of the following properties: · PD/PU: The IO pin a weak pull-down or pull-up resistor. On GPIO pins this resistor can be enabled. · ST: The IO pin has a Schmitt Trigger on its input. Power pins (6) Signal Function Type GND Digital ground GND Properties OTP_VCC OTP power supply PWR PLL_AGND Analog ground for PLL GND PLL_AVDD Analog PLL power PWR VDD Digital tile power PWR VDDIO Digital I/O power PWR Signal Function Type Properties CLK PLL reference clock Input PD, ST MODE[4:0] Boot mode select Input PU, ST Clocks pins (2) JTAG pins (7) Signal Function Type Properties DEBUG_N Multi-chip debug I/O PU RST_N Global reset input Input PU, ST TCK Test clock Input PU, ST TDI Test data input Input PU, ST TDO Test data output Output PD, OT TMS Test mode select Input PU, ST TRST_N Test reset input Input PU, ST I/O pins (84) Signal X0D00 Function 1A0 Type Properties I/O PDS , RS (continued) X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 7 Signal Function Type Properties X0D01 XLA4 out I/O PDS , RS X0D02 XLA3 out 4A0 8A0 16A0 32A20 I/O PDS , RU X0D03 XLA2 out 4A1 8A1 16A1 32A21 I/O PDS , RU X0D04 XLA1 out 4B0 8A2 16A2 32A22 I/O PDS , RU X0D05 XLA0 out 4B1 8A3 16A3 32A23 I/O PDS , RU X0D06 XLA0 in 4B2 8A4 16A4 32A24 I/O PDS , RU X0D07 XLA1 in 4B3 8A5 16A5 32A25 I/O PDS , RU X0D08 XLA2 in 4A2 8A6 16A6 32A26 I/O PDS , RU X0D09 XLA3 in 4A3 8A7 16A7 32A27 I/O PDS , RU X0D10 XLA4 in 1C0 I/O PDS , RS X0D11 1D0 I/O PDS , RS X0D12 1E0 I/O PDS , RU 1F0 I/O PDS , RU 1B0 X0D13 XLB4 out X0D14 XLB3 out 4C0 8B0 16A8 32A28 I/O PDS , RU X0D15 XLB2 out 4C1 8B1 16A9 32A29 I/O PDS , RU X0D16 XLB1 out 4D0 8B2 16A10 I/O PDS , RU X0D17 XLB0 out 4D1 8B3 16A11 I/O PDS , RU X0D18 XLB0 in 4D2 8B4 16A12 I/O PDS , RU X0D19 XLB1 in 4D3 8B5 16A13 I/O PDS , RU X0D20 XLB2 in 4C2 8B6 16A14 32A30 I/O PDS , RU X0D21 XLB3 in 4C3 8B7 16A15 32A31 I/O PDS , RU X0D22 XLB4 in 1G0 I/O PDS , RU X0D23 1H0 I/O PDS , RU X0D24 1I0 I/O PDS X0D25 1J0 I/O PDS X0D26 4E0 8C0 16B0 I/O PDS , RU X0D27 4E1 8C1 16B1 I/O PDS , RU X0D28 4F0 8C2 16B2 I/O PDS , RU X0D29 4F1 8C3 16B3 I/O PDS , RU X0D30 4F2 8C4 16B4 I/O PDS , RU X0D31 4F3 8C5 16B5 I/O PDS , RU X0D32 4E2 8C6 16B6 I/O PDS , RU X0D33 4E3 8C7 16B7 I/O PDS , RU X0D34 1K0 I/O PDS X0D35 1L0 I/O PDS X0D36 1M0 8D0 16B8 I/O PDS X0D37 1N0 8D1 16B9 I/O PDS , RU X0D38 1O0 8D2 16B10 I/O PDS , RU X0D39 1P0 8D3 16B11 I/O PDS , RU X0D40 8D4 16B12 I/O PDS , RU X0D41 8D5 16B13 I/O PDS , RU X0D42 8D6 16B14 I/O PDS , RU X0D43 8D7 16B15 I/O PUS , RU (continued) X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Signal Function X1D00 X8006, 8 Type Properties 1A0 I/O PDS , RS 1B0 I/O PDS , RS X1D01 XLA4 out X1D02 XLA3 out 4A0 8A0 16A0 32A20 I/O PDS , RU X1D03 XLA2 out 4A1 8A1 16A1 32A21 I/O PDS , RU X1D04 XLA1 out 4B0 8A2 16A2 32A22 I/O PDS , RU X1D05 XLA0 out 4B1 8A3 16A3 32A23 I/O PDS , RU X1D06 XLA0 in 4B2 8A4 16A4 32A24 I/O PDS , RU X1D07 XLA1 in 4B3 8A5 16A5 32A25 I/O PDS , RU X1D08 XLA2 in 4A2 8A6 16A6 32A26 I/O PDS , RU X1D09 XLA3 in 4A3 8A7 16A7 32A27 I/O PDS , RU X1D10 XLA4 in 1C0 I/O PDS , RS X1D11 1D0 I/O PDS , RS X1D12 1E0 I/O PDS , RU 1F0 I/O PDS , RU X1D13 XLB4 out X1D14 XLB3 out 4C0 8B0 16A8 32A28 I/O PDS , RU X1D15 XLB2 out 4C1 8B1 16A9 32A29 I/O PDS , RU X1D16 XLB1 out 4D0 8B2 16A10 I/O PDS , RU X1D17 XLB0 out 4D1 8B3 16A11 I/O PDS , RU X1D18 XLB0 in 4D2 8B4 16A12 I/O PDS , RU X1D19 XLB1 in 4D3 8B5 16A13 I/O PDS , RU X1D20 XLB2 in 4C2 8B6 16A14 32A30 I/O PDS , RU X1D21 XLB3 in 4C3 8B7 16A15 32A31 I/O PDS , RU X1D22 XLB4 in 1G0 I/O PDS , RU X1D23 1H0 I/O PDS , RU X1D24 1I0 I/O PDS X1D25 1J0 I/O PDS X1D26 4E0 8C0 16B0 I/O PDS , RU X1D27 4E1 8C1 16B1 I/O PDS , RU X1D28 4F0 8C2 16B2 I/O PDS , RU X1D29 4F1 8C3 16B3 I/O PDS , RU X1D30 4F2 8C4 16B4 I/O PDS , RU X1D31 4F3 8C5 16B5 I/O PDS , RU X1D32 4E2 8C6 16B6 I/O PDS , RU X1D33 4E3 8C7 16B7 I/O PDS , RU X1D34 1K0 I/O PDS X1D35 1L0 I/O PDS X1D36 1M0 8D0 16B8 I/O PDS X1D37 1N0 8D1 16B9 I/O PDS , RU X1D38 1O0 8D2 16B10 I/O PDS , RU X1D39 1P0 8D3 16B11 I/O PDS , RU XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 9 pins (5) X8006, Signal Function PCU_CLK Clock input PCU_GATE Power control gate control PCU_VDD PCU tile power PCU_VDDIO PCU I/O supply PCU_WAKE Wakeup reset Type Properties XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 5 10 Product Overview The XS1-L16A-128-QF124 is a powerful device that consists of two xCORE Tiles, each comprising a flexible logical processing cores with tightly integrated I/O and on-chip memory. 5.1 Logical cores Each tile has 8 active logical cores, which issue instructions down a shared fourstage pipeline. Instructions from the active cores are issued round-robin. If up to four logical cores are active, each core is allocated a quarter of the processing cycles. If more than four logical cores are active, each core is allocated at least 1/n cycles (for n cores). Figure 2 shows the guaranteed core performance depending on the number of cores used. Speed Figure 2: Logical core performance MIPS Frequency grade Minimum MIPS per core (for n cores) 1 2 3 4 5 6 7 8 8 800 MIPS 400 MHz 100 100 100 100 80 67 57 50 10 1000 MIPS 500 MHz 125 125 125 125 100 83 71 63 There is no way that the performance of a logical core can be reduced below these predicted levels. Because cores may be delayed on I/O, however, their unused processing cycles can be taken by other cores. This means that for more than four logical cores, the performance of each core is often higher than the predicted minimum but cannot be guaranteed. The logical cores are triggered by events instead of interrupts and run to completion. A logical core can be paused to wait for an event. 5.2 xTIME scheduler The xTIME scheduler handles the events generated by xCORE Tile resources, such as channel ends, timers and I/O pins. It ensures that all events are serviced and synchronized, without the need for an RTOS. Events that occur at the I/O pins are handled by the Hardware-Response ports and fed directly to the appropriate xCORE Tile. An xCORE Tile can also choose to wait for a specified time to elapse, or for data to become available on a channel. Tasks do not need to be prioritised as each of them runs on their own logical xCORE. It is possible to share a set of low priority tasks on a single core using cooperative multitasking. 5.3 Hardware Response Ports Hardware Response ports connect an xCORE tile to one or more physical pins and as such define the interface between hardware attached to the XS1-L16A-128QF124, and the software running on it. A combination of 1bit, 4bit, 8bit, 16bit and 32bit ports are available. All pins of a port provide either output or input. Signals in different directions cannot be mapped onto the same port. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 11 reference clock readyOut conditional value clock port clock block readyIn port port counter port logic stamp/time PORT FIFO PINS Figure 3: Port block diagram port value output (drive) SERDES transfer register CORE input (sample) The port logic can drive its pins high or low, or it can sample the value on its pins, optionally waiting for a particular condition. Ports are accessed using dedicated instructions that are executed in a single processor cycle. Data is transferred between the pins and core using a FIFO that comprises a SERDES and transfer register, providing options for serialization and buffered data. Each port has a 16-bit counter that can be used to control the time at which data is transferred between the port value and transfer register. The counter values can be obtained at any time to find out when data was obtained, or used to delay I/O until some time in the future. The port counter value is automatically saved as a timestamp, that can be used to provide precise control of response times. The ports and xCONNECT links are multiplexed onto the physical pins. If an xConnect Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their specified width, even if they share pins with another port. 5.4 Clock blocks xCORE devices include a set of programmable clocks called clock blocks that can be used to govern the rate at which ports execute. Each xCORE tile has six clock blocks: the first clock block provides the tile reference clock and runs at a default frequency of 100MHz; the remaining clock blocks can be set to run at different frequencies. A clock block can use a 1-bit port as its clock source allowing external application clocks to be used to drive the input and output interfaces. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 100MHz reference clock 12 divider 1-bit port ... ... readyIn clock block Figure 4: Clock block diagram port counter In many cases I/O signals are accompanied by strobing signals. The xCORE ports can input and interpret strobe (known as readyIn and readyOut) signals generated by external sources, and ports can generate strobe signals to accompany output data. On reset, each port is connected to clock block 0, which runs from the xCORE Tile reference clock. 5.5 Channels and Channel Ends Logical cores communicate using point-to-point connections, formed between two channel ends. A channel-end is a resource on an xCORE tile, that is allocated by the program. Each channel-end has a unique system-wide identifier that comprises a unique number and their tile identifier. Data is transmitted to a channel-end by an output-instruction; and the other side executes an input-instruction. Data can be passed synchronously or asynchronously between the channel ends. 5.6 xCONNECT Switch and Links XMOS devices provide a scalable architecture, where multiple xCORE devices can be connected together to form one system. Each xCORE device has an xCONNECT interconnect that provides a communication infrastructure for all tasks that run on the various xCORE tiles on the system. The interconnect relies on a collection of switches and XMOS links. Each xCORE device has an on-chip switch that can set up circuits or route data. The switches are connected by xConnect Links. An XMOS link provides a physical connection between two switches. The switch has a routing algorithm that supports many different topologies, including lines, meshes, trees, and hypercubes. The links operate in either 2 wires per direction or 5 wires per direction mode, depending on the amount of bandwidth required. Circuit switched, streaming and packet switched data can both be supported efficiently. Streams provide the fastest possible data rates between xCORE Tiles (up to 250 MBit/s), but each stream requires a single link to be reserved between switches on two tiles. All packet communications can be multiplexed onto a single link. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 13 xCONNECT Link to another device switch CORE CORE CORE CORE CORE CORE CORE CORE CORE xCONNECT switch CORE CORE CORE Figure 5: Switch, links and channel ends CORE CORE CORE CORE xCORE Tile xCORE Tile Information on the supported routing topologies that can be used to connect multiple devices together can be found in the XS1-L Link Performance and Design Guide, X2999. 6 PLL The PLL creates a high-speed clock that is used for the switch, tile, and reference clock. The PLL multiplication value is selected through the two MODE pins, and can be changed by software to speed up the tile or use less power. The MODE pins are set as shown in Figure 6: Figure 6: PLL multiplier values and MODE pins Oscillator Frequency 5-13 MHz 13-20 MHz 20-48 MHz 48-100 MHz MODE 1 0 0 0 1 1 1 0 0 1 Tile Frequency 130-399.75 MHz 260-400.00 MHz 167-400.00 MHz 196-400.00 MHz PLL Ratio 30.75 20 8.33 4 PLL settings OD F R 1 122 0 2 119 0 2 49 0 2 23 0 Figure 6 also lists the values of OD, F and R, which are the registers that define the ratio of the tile frequency to the oscillator frequency: Fcor e = Fosc × X8006, F +1 1 1 × × 2 R+1 OD + 1 XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 14 OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and F +1 1 260MHz ≤ Fosc × 2 × R+1 ≤ 1.3GHz. The OD, F , and R values can be modified by writing to the digital node PLL configuration register. The MODE pins must be held at a static value during and after deassertion of the system reset. If a different tile frequency is required (eg, 500 MHz), then the PLL must be reprogrammed after boot to provide the required tile frequency. The XMOS tools perform this operation by default. Further details on configuring the clock can be found in the XS1-L Clock Frequency Control document, X1433. 7 Boot Procedure The device is kept in reset by driving RST_N low. When in reset, all GPIO pins are high impedance. When the device is taken out of reset by releasing RST_N the processor starts its internal reset process. After 15-150 µs (depending on the input clock), all GPIO pins have their internal pull-resistor enabled, and the processor boots at a clock speed that depends on MODE0 and MODE1. The xCORE Tile boot procedure is illustrated in Figure 7. In normal usage, MODE[4:2] controls the boot source according to the table in Figure 8. If bit 5 of the security register (see §8.1) is set, the device boots from OTP. Start Boot ROM Primary boot Security Register Bit [5] set No Yes OTP Figure 7: Boot procedure Copy OTP contents to base of SRAM Boot according to boot source pins Execute program The boot image has the following format: · A 32-bit program size s in words. · Program consisting of s × 4 bytes. · A 32-bit CRC, or the value 0x0D15AB1E to indicate that no CRC check should be performed. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 15 MODE MODE MODE [4] [3] [2] X 0 0 None: Device waits to be booted via JTAG X 0 1 Reserved 0 1 0 Tile0 boots from link B, Tile1 from channel end 0 via Tile0 0 1 1 Tile0 boots from SPI, Tile1 from channel end 0 via Tile0 1 1 0 Tile0 and Tile1 independently enable link B and internal links (E, F, G, H), and boot from channel end 0 1 1 1 Tile0 and Tile 1 boot from SPI independently Figure 8: Boot source pins Boot Source The program size and CRC are stored least significant byte first. The program is loaded into the lowest memory address of RAM, and the program is started from that address. The CRC is calculated over the byte stream represented by the program size and the program itself. The polynomial used is 0xEDB88320 (IEEE 802.3); the CRC register is initialized with 0xFFFFFFFF and the residue is inverted to produce the CRC. 7.1 Boot from SPI master If set to boot from SPI master, the processor enables the four pins specified in Figure 9, and drives the SPI clock at 2.5 MHz (assuming a 400 MHz core clock). A READ command is issued with a 24-bit address 0x000000. The clock polarity and phase are 0 / 0. Figure 9: SPI master pins Pin Signal Description X0D00 MISO Master In Slave Out (Data) X0D01 SS Slave Select X0D10 SCLK Clock X0D11 MOSI Master Out Slave In (Data) The xCORE Tile expects each byte to be transferred with the least-significant bit first. Programmers who write bytes into an SPI interface using the most significant bit first may have to reverse the bits in each byte of the image stored in the SPI device. If a large boot image is to be read in, it is faster to first load a small boot-loader that reads the large image using a faster SPI clock, for example 50 MHz or as fast as the flash device supports. The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. If required, an SPI boot program can be burned into OTP that uses different pins. 7.2 Boot from xConnect Link If set to boot from an xConnect Link, the processor enables Link B around 200 ns after the boot process starts. Enabling the Link switches off the pull-down on X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 16 resistors X0D16..X0D19, drives X0D16 and X0D17 low (the initial state for the Link), and monitors pins X0D18 and X0D19 for boot-traffic. X0D18 and X0D19 must be low at this stage. If the internal pull-down is too weak to drain any residual charge, external pull-downs of 10K may be required on those pins. The boot-rom on the core will then: 1. Allocate channel-end 0. 2. Input a word on channel-end 0. It will use this word as a channel to acknowledge the boot. Provide the null-channel-end 0x0000FF02 if no acknowledgment is required. 3. Input the boot image specified above, including the CRC. 4. Input an END control token. 5. Output an END control token to the channel-end received in step 2. 6. Free channel-end 0. 7. Jump to the loaded code. 7.3 Boot from OTP If an xCORE tile is set to use secure boot (see Figure 7), the boot image is read from address 0 of the OTP memory in the tile’s security module. This feature can be used to implement a secure bootloader which loads an encrypted image from external flash, decrypts and CRC checks it with the processor, and discontinues the boot process if the decryption or CRC check fails. XMOS provides a default secure bootloader that can be written to the OTP along with secret decryption keys. Each tile has its own individual OTP memory, and hence some tiles can be booted from OTP while others are booted from SPI or the channel interface. This enables systems to be partially programmed, dedicating one or more tiles to perform a particular function, leaving the other tiles user-programmable. 7.4 Security register The security register enables security features on the xCORE tile. The features shown in Figure 10 provide a strong level of protection and are sufficient for providing strong IP security. 8 Memory 8.1 OTP Each xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with a security register that configures system wide security features. The OTP holds X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 17 Feature Bit Description Disable JTAG 0 The JTAG interface is disabled, making it impossible for the tile state or memory content to be accessed via the JTAG interface. Disable Link access 1 Other tiles are forbidden access to the processor state via the system switch. Disabling both JTAG and Link access transforms an xCORE Tile into a “secure island” with other tiles free for non-secure user application code. Secure Boot 5 The xCORE Tile is forced to boot from address 0 of the OTP, allowing the xCORE Tile boot ROM to be bypassed (see §7). Redundant rows 7 Enables redundant rows in OTP. Sector Lock 0 8 Disable programming of OTP sector 0. Sector Lock 1 9 Disable programming of OTP sector 1. Sector Lock 2 10 Disable programming of OTP sector 2. Sector Lock 3 11 Disable programming of OTP sector 3. OTP Master Lock 12 Disable OTP programming completely: disables updates to all sectors and security register. Disable JTAG-OTP 13 Disable all (read & write) access from the JTAG interface to this OTP. Disable Global Debug 14 Disables access to the DEBUG_N pin. 21..15 General purpose software accessable security register available to end-users. 31..22 General purpose user programmable JTAG UserID code extension. Figure 10: Security register features data in four sectors each containing 512 rows of 32 bits which can be used to implement secure bootloaders and store encryption keys. Data for the security register is loaded from the OTP on power up. All additional data in OTP is copied from the OTP to SRAM and executed first on the processor. The OTP memory is programmed using three special I/O ports: the OTP address port is a 16-bit port with resource ID 0x100200, the OTP data is written via a 32-bit port with resource ID 0x200100, and the OTP control is on a 16-bit port with ID 0x100300. Programming is performed through libotp and xburn. 8.2 SRAM Each xCORE Tile integrates a single 64KB SRAM bank for both instructions and data. All internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one tile clock cycle. There is no dedicated external memory interface, although data memory can be expanded through appropriate use of the ports. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 9 18 JTAG The JTAG module can be used for loading programs, boundary scan testing, incircuit source-level debugging and programming the OTP memory. X0 X1 BS TAP TDI TDI CHIP TAP TDO TDI BS TAP TDO TDI CHIP TAP TDO TDI TDO TDO TCK TMS Figure 11: JTAG chain structure TRST_N DEBUG_N The JTAG chain structure is illustrated in Figure 11. Directly after reset, two TAP controllers are present in the JTAG chain for each xCORE Tile: the boundary scan TAP and the chip TAP. The boundary scan TAP is a standard 1149.1 compliant TAP that can be used for boundary scan of the I/O pins. The chip TAP provides access into the xCORE Tile, switch and OTP for loading code and debugging. The TRST_N pin must be asserted low during and after power up for 100 ns. If JTAG is not required, the TRST_N pin can be tied to ground to hold the JTAG module in reset. The DEBUG_N pin is used to synchronize the debugging of multiple xCORE Tiles. This pin can operate in both output and input mode. In output mode and when configured to do so, DEBUG_N is driven low by the device when the processor hits a debug break point. Prior to this point the pin will be tri-stated. In input mode and when configured to do so, driving this pin low will put the xCORE Tile into debug mode. Software can set the behavior of the xCORE Tile based on this pin. This pin should have an external pull up of 4K7-47K Ω or left not connected in single core applications. The JTAG device identification register can be read by using the IDCODE instruction. Its contents are specified in Figure 12. Figure 12: IDCODE return value X8006, Bit31 Device Identification Register Version 0 0 0 0 Bit0 Part Number 0 0 0 0 0 0 0 0 0 0 0 0 Manufacturer Identity 0 0 0 0 0 0 1 2 0 0 1 1 6 0 0 0 1 3 1 1 0 0 1 1 3 XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 19 The JTAG usercode register can be read by using the USERCODE instruction. Its contents are specified in Figure 13. The OTP User ID field is read from bits [22:31] of the security register on xCORE Tile 0, see §8.1 (all zero on unprogrammed devices). Figure 13: USERCODE return value Bit31 Usercode Register OTP User ID 0 0 0 0 0 9.1 0 0 0 0 Bit0 Unused 0 0 0 0 0 0 0 Silicon Revision 0 1 0 2 1 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCU PCU_WAKE should be left unconnected, PCU_GATE should be left unconnected and PCU_CLK must be tied to CLK. 10 Board Integration The device has the following power supply pins: · VDD pins for the xCORE Tile · VDDIO pins for the I/O lines · PLL_AVDD pins for the PLL · PCU_VDD and PCU_VDDIO pins for the PCU · OTP_VCC pins for the OTP Several pins of each type are provided to minimize the effect of inductance within the package, all of which must be connected. The power supplies must be brought up monotonically and input voltages must not exceed specification at any time. The VDD supply must ramp from 0 V to its final value within 10 ms to ensure correct startup. The VDDIO and OTP_VCC supply must ramp to its final value before VDD reaches 0.4 V. The PLL_AVDD supply should be separated from the other noisier supplies on the board. The PLL requires a very clean power supply, and a low pass filter (for example, a 2.2 Ω resistor and 100 nF multi-layer ceramic capacitor) is recommended on this pin. The PCU_VDD supply must be connected to the VDD supply. The PCU_VDDIO supply must be connected to the VDDIO supply. The OTP_VCC supply should be connected to the VDDIO supply. The following ground pins are provided: X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 20 · PLL_AGND for PLL_AVDD · GND for all other supplies All ground pins must be connected directly to the board ground. The VDD and VDDIO supplies should be decoupled close to the chip by several 100 nF low inductance multi-layer ceramic capacitors between the supplies and GND (for example, 4x100nF 0402 low inductance MLCCs per supply rail). The ground side of the decoupling capacitors should have as short a path back to the GND pins as possible. A bulk decoupling capacitor of at least 10 uF should be placed on each of these supplies. RST_N is an active-low asynchronous-assertion global reset signal. Following a reset, the PLL re-establishes lock after which the device boots up according to the boot mode (see §7). RST_N and must be asserted low during and after power up for 100 ns. 10.1 Land patterns and solder stencils The land pattern recommendations in this document are based on a RoHS compliant process and derived, where possible, from the nominal Generic Requirements for Surface Mount Design and Land Pattern Standards IPC-7351B specifications. This standard aims to achieve desired targets of heel, toe and side fillets for solderjoints. Solder paste and ground via recommendations are based on our engineering and development kit board production. They have been found to work and optimized as appropriate to achieve a high yield. The size, type and number of vias used in the center pad affects how much solder wicks down the vias during reflow. This in turn, along with solder paster coverage, affects the final assembled package height. These factors should be taken into account during design and manufacturing of the PCB. The following land patterns and solder paste contains recommendations. Final land pattern and solder paste decisions are the responsibility of the customer. These should be tuned during manufacture to suit the manufacturing process. The package is a 124 pin dual row Quad Flat No lead package with exposed heat slug on a 0.5mm pitch. An example land pattern is shown in Figure 14. Pad widths and spacings are such that solder mask can still be applied between the pads using standard design rules. This is highly recommended to reduce solder shorts between pads. See the recommended PCB solder mask diagram in Figure 15. 10.2 Solder Stencil The solder joints in the QFN package are formed exclusively from the solder paste deposited from the solder stencil. At the small aperture sizes required, the design of the stencil becomes important to ensure a reliable final solder joint volume and reliable solder joints. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 21 9.50 0.75 1.00 2.80 4.00 2.80 Figure 14: Example land pattern 7.50 1.00 0.30x0.30 0.50 0.5mm 0.4mm PAD PAD PAD SOLDERMASK 0.3mm Figure 15: Detail of outer pads X8006, PAD 0.3mm PAD 0.75mm PAD 0.1mm XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 22 The solder stencil recommendations here are based on those suggested in the IPC specification IPC-7525A "Stencil Design Guidelines". As the aperture size in the stencil becomes very small, the amount of solder which remains on the PCB pad after printing is reduced. This occurs due to friction between the walls of the stencil and the solder paste dragging the paste from the pad when the stencil is removed. This effect is minimized as the thickness of the stencil is reduced. For the 124 pin QFN package, our recommendations are to use a 4mil thick laser cut stencil. The solder stencil apertures for the pads should be 0.3mm square with 0.06mm radiused corners. This is the same size as the pads themselves apart from radiused corners to aid in paste transfer. This can be seen in the Figure 16. Soldermask Copper Pad 0.3mm Solderpaste Figure 16: Solder stencil for outer pads 0.3mm These dimensions should be the final aperture sizes used on the stencil, this should be agreed with the stencil makers or assembly house. It is common for assembly houses to subject the paste mask data to a global undersize before cutting the stencil. If this undersize is applied to these small apertures the paste transfer is likely to be poor and open solder joints may result. For the center pad of this package, four squares of solder paste is recommended, 1mm on a side as shown in Figure 17. This gives a paste to pad area ratio of 51%. 10.3 Ground and Thermal Vias Vias under the heat slug into the ground plane of the PCB are recommended for a low inductance ground connection and good thermal performance. A 3 x 3 grid of vias, with a 0.6mm diameter annular ring and a 0.3mm drill, equally spaced across the heat slug, would be suitable. 10.4 Moisture Sensitivity XMOS devices are, like all semiconductor devices, susceptible to moisture absorption. When removed from the sealed packaging, the devices slowly absorb moisture from the surrounding environment. If the level of moisture present in the device is too high during reflow, damage can occur due to the increased internal vapour pressure of moisture. Example damage can include bond wire damage, die lifting, internal or external package cracks and/or delamination. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 23 2.8mm 1.0mm 2.8mm 0.3mm Figure 17: Solder stencil for centre pad Soldermask Copper Pad Solderpaste 1.0mm 0.3mm All XMOS devices are Moisture Sensitivity Level (MSL) 3 - devices have a shelf life of 168 hours between removal from the packaging and reflow, provided they are stored below 30C and 60% RH. If devices have exceeded these values or an included moisture indicator card shows excessive levels of moisture, then the parts should be baked as appropriate before use. This is based on information from Joint IPC/JEDEC Standard For Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface-Mount Devices J-STD-020 Revision D. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 11 24 DC and Switching Characteristics 11.1 Operating Conditions Symbol Parameter MIN TYP MAX UNITS VDD Tile DC supply voltage 0.95 1.00 1.05 V VDDIO I/O supply voltage 3.00 3.30 3.60 V PLL_AVDD PLL analog supply 0.95 1.00 1.05 V PCU_VDD PCU tile DC supply voltage 0.95 1.00 1.05 V PCU_VDDIO PCU I/O DC supply voltage 3.00 3.30 3.60 V OTP_VCC OTP supply voltage 3.00 3.30 3.60 V Cl xCORE Tile I/O load capacitance Ambient operating temperature (Commercial) Ta Figure 18: Operating conditions Ambient operating temperature (Industrial) Tj Junction temperature Tstg Storage temperature 11.2 Figure 19: DC characteristics 25 pF 0 70 °C -40 85 °C 125 °C -65 150 °C Notes DC Characteristics Symbol Parameter MIN MAX UNITS Notes V(IH) Input high voltage 2.00 TYP 3.60 V A V(IL) Input low voltage -0.30 0.70 V A V(OH) Output high voltage V B, C V(OL) Output low voltage V B, C R(PU) Pull-up resistance 35K Ω D R(PD) Pull-down resistance 35K Ω D 2.00 0.60 A All pins except power supply pins. B Ports 1A, 1D, 1E, 1H, 1I, 1J, 1K and 1L are nominal 8 mA drivers, the remainder of the general-purpose I/Os are 4 mA. C Measured with 4 mA drivers sourcing 4 mA, 8 mA drivers sourcing 8 mA. D Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be used to pull external circuitry. 11.3 Figure 20: ESD stress voltage X8006, ESD Stress Voltage Symbol Parameter HBM Human body model MM Machine model MAX UNITS -2.00 MIN TYP 2.00 KV -200 200 Notes V XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 11.4 Figure 21: Reset timing 25 Reset Timing Symbol Parameters MIN T(RST) Reset pulse width 5 T(INIT) Initialization time TYP MAX UNITS Notes us 150 µs A A Shows the time taken to start booting after RST_N has gone high. 11.5 Figure 22: xCORE Tile currents Power Consumption Symbol Parameter I(DDCQ) Quiescent VDD current PD Tile power dissipation IDD I(ADDPLL) UNITS Notes 28 mA A, B, C 450 µW/MIPS A, D, E, F Active VDD current (Speed Grade 8) 320 600 mA A, G Active VDD current (Speed Grade 10) 400 750 mA A, H mA I PLL_AVDD current MIN TYP MAX 14 A B C D E F G Use for budgetary purposes only. Assumes typical tile and I/O voltages with no switching activity. Includes PLL current. Assumes typical tile and I/O voltages with nominal switching activity. Assumes 1 MHz = 1 MIPS. PD(TYP) value is the usage power consumption under typical operating conditions. Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 400 MHz, average device resource usage. H Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 500 MHz, average device resource usage. I PLL_AVDD = 1.0 V The tile power consumption of the device is highly application dependent and should be used for budgetary purposes only. More detailed power analysis can be found in the XS1-L Power Consumption document, X2999. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 11.6 26 Clock Symbol Parameter MIN TYP MAX UNITS f Frequency 4.22 20 100 MHz SR Slew rate 0.10 TJ(LT) Long term jitter (pk-pk) 2 % A f(MAX) Processor clock frequency (Speed Grade 8) 400 MHz B Processor clock frequency (Speed Grade 10) 500 MHz B Figure 23: Clock Notes V/ns A Percentage of CLK period. B Assumes typical tile and I/O voltages with nominal activity. Further details can be found in the XS1-L Clock Frequency Control document, X1433. 11.7 Figure 24: I/O AC characteristics xCORE Tile I/O AC Characteristics Symbol Parameter MIN TYP MAX UNITS T(XOVALID) Input data valid window 8 T(XOINVALID) Output data invalid window 9 T(XIFMAX) Rate at which data can be sampled with respect to an external clock Notes ns ns 60 MHz The input valid window parameter relates to the capability of the device to capture data input to the chip with respect to an external clock source. It is calculated as the sum of the input setup time and input hold time with respect to the external clock as measured at the pins. The output invalid window specifies the time for which an output is invalid with respect to the external clock. Note that these parameters are specified as a window rather than absolute numbers since the device provides functionality to delay the incoming clock with respect to the incoming data. Information on interfacing to high-speed synchronous interfaces can be found in the XS1 Port I/O Timing document, X5821. 11.8 Figure 25: Link performance xConnect Link Performance Symbol Parameter MAX UNITS Notes B(2blinkP) 2b link bandwidth (packetized) MIN TYP 87 MBit/s A, B B(5blinkP) 5b link bandwidth (packetized) 217 MBit/s A, B B(2blinkS) 2b link bandwidth (streaming) 100 MBit/s B B(5blinkS) 5b link bandwidth (streaming) 250 MBit/s B A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header and payload. B 7.5 ns symbol time. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 27 The asynchronous nature of links means that the relative phasing of CLK clocks is not important in a multi-clock system, providing each meets the required stability criteria. 11.9 Figure 26: JTAG timing JTAG Timing Symbol Parameter f(TCK_D) TCK frequency (debug) MIN TYP MAX UNITS 18 MHz 10 MHz f(TCK_B) TCK frequency (boundary scan) T(SETUP) TDO to TCK setup time 5 ns A T(HOLD) TDO to TCK hold time 5 ns A T(DELAY) TCK to output delay ns B 15 Notes A Timing applies to TMS and TDI inputs. B Timing applies to TDO output from negative edge of TCK. All JTAG operations are synchronous to TCK apart from the global asynchronous reset TRST_N. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 12 X8006, 28 Package Information XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 12.1 29 Part Marking CC - Number of logical cores F - Product family R - RAM (in log-2) T - Temperature grade M - MIPS grade CCFRTM MCYYWWXX Figure 27: Part marking scheme 13 Wafer lot code Ordering Information Figure 28: Orderable part numbers X8006, LLLLLL.LL MC - Manufacturer YYWW - Date XX - Reserved Product Code XS1–L16A–128–QF124–C8 XS1–L16A–128–QF124–C10 XS1–L16A–128–QF124–I8 XS1–L16A–128–QF124–I10 Marking 16L7C8 16L7C10 16L7I8 16L7I10 Qualification Commercial Commercial Industrial Industrial Speed Grade 800 MIPS 1000 MIPS 800 MIPS 1000 MIPS XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 30 Appendices A Configuration of the XS1 The device is configured through three banks of registers, as shown in Figure 29. PLL Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAGstatus Processor registers debug xCORE logical core 2 xCORE logical core 3 xCORE logical core 4 xCONNECT links xCORE logical core 1 Channels Hardware response ports xCORE tile registers Node registers Channels I/O pins xCORE logical core 0 Node registers xCORE logical core 5 xCORE logical core 6 xCORE logical core 7 xCORE logical core 1 xCORE logical core 2 xCORE logical core 3 xCORE logical core 4 xCORE logical core 5 xCORE tile registers xCONNECT links I/O pins xCORE logical core 0 Hardware response ports xCORE logical core 6 xCORE logical core 7 Figure 29: Registers PLL Security OTP ROM xTIME: schedulers timers, clocks SRAM 64KB JTAGstatus Processor registers debug The following communication sequences specify how to access those registers. Any messages transmitted contain the most significant 24 bits of the channel-end to which a response is to be sent. This comprises the node-identifier and the channel number within the node. if no response is required on a write operation, supply 24-bits with the last 8-bits set, which suppresses the reply message. Any multi-byte data is sent most significant byte first. A.1 Accessing a processor status register The processor status registers are accessed directly from the processor instruction set. The instructions GETPS and SETPS read and write a word. The register number should be translated into a processor-status resource identifier by shifting the register number left 8 places, and ORing it with 0x0C. Alternatively, the functions getps(reg) and setps(reg,value) can be used from XC. A.2 Accessing an xCORE Tile configuration register xCORE Tile configuration registers can be accessed through the interconnect using the functions write_tile_config_reg(tileref, ...) and read_tile_config_reg(tile X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 31 > ref, ...), where tileref is the name of the xCORE Tile, e.g. tile[1]. These functions implement the protocols described below. Instead of using the functions above, a channel-end can be allocated to communicate with the xCORE tile configuration registers. The destination of the channel-end should be set to 0xnnnnC20C where nnnnnn is the tile-identifier. A write message comprises the following: control-token 24-bit response 16-bit 32-bit control-token 192 channel-end identifier register number data 1 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 16-bit control-token 193 channel-end identifier register number 1 The response to the read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). A.3 Accessing node configuration Node configuration registers can be accessed through the interconnect using the functions write_node_config_reg(device, ...) and read_node_config_reg(device, > ...), where device is the name of the node. These functions implement the protocols described below. Instead of using the functions above, a channel-end can be allocated to communicate with the node configuration registers. The destination of the channel-end should be set to 0xnnnnC30C where nnnn is the node-identifier. A write message comprises the following: control-token 24-bit response 16-bit 32-bit control-token 192 channel-end identifier register number data 1 The response to a write message comprises either control tokens 3 and 1 (for success), or control tokens 4 and 1 (for failure). A read message comprises the following: control-token 24-bit response 16-bit control-token 193 channel-end identifier register number 1 The response to a read message comprises either control token 3, 32-bit of data, and control-token 1 (for success), or control tokens 4 and 1 (for failure). X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet B 32 Processor Status Configuration The processor status control registers can be accessed directly by the processor using processor status reads and writes (use getps(reg) and setps(reg,value) for reads and writes). Number Figure 30: Summary X8006, Perm Description 0x00 RW RAM base address 0x01 RW Vector base address 0x02 RW xCORE Tile control 0x03 RO xCORE Tile boot status 0x05 RO Security configuration 0x06 RW Ring Oscillator Control 0x07 RO Ring Oscillator Value 0x08 RO Ring Oscillator Value 0x09 RO Ring Oscillator Value 0x0A RO Ring Oscillator Value 0x10 DRW Debug SSR 0x11 DRW Debug SPC 0x12 DRW Debug SSP 0x13 DRW DGETREG operand 1 0x14 DRW DGETREG operand 2 0x15 DRW Debug interrupt type 0x16 DRW Debug interrupt data 0x18 DRW Debug core control 0x20 .. 0x27 DRW Debug scratch 0x30 .. 0x33 DRW Instruction breakpoint address 0x40 .. 0x43 DRW Instruction breakpoint control 0x50 .. 0x53 DRW Data watchpoint address 1 0x60 .. 0x63 DRW Data watchpoint address 2 0x70 .. 0x73 DRW Data breakpoint control register 0x80 .. 0x83 DRW Resources breakpoint mask 0x90 .. 0x93 DRW Resources breakpoint value 0x9C .. 0x9F DRW Resources breakpoint control register XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet B.1 33 RAM base address: 0x00 This register contains the base address of the RAM. It is initialized to 0x00010000. 0x00: RAM base address Bits Perm 31:2 RW 1:0 RO B.2 Init Description Most significant 16 bits of all addresses. - Reserved Vector base address: 0x01 Base address of event vectors in each resource. On an interrupt or event, the 16 most significant bits of the destination address are provided by this register; the least significant 16 bits come from the event vector. 0x01: Vector base address Bits Perm 31:16 RW 15:0 RO B.3 Init Description The most significant bits for all event and interrupt vectors. - Reserved xCORE Tile control: 0x02 Register to control features in the xCORE tile 0x02: xCORE Tile control Bits Perm 31:6 RO - 5 RW 0 Set to 1 to select the dynamic mode for the clock divider when the clock divider is enabled. In dynamic mode the clock divider is only activated when all active logical cores are paused. In static mode the clock divider is always enabled. 4 RW 0 Set to 1 to enable the clock divider. This slows down the xCORE tile clock in order to use less power. 3:0 RO - B.4 Init Description Reserved Reserved xCORE Tile boot status: 0x03 This read-only register describes the boot status of the xCORE tile. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits Perm 34 Init 31:24 RO 23:16 RO 15:9 RO 8 RO Set to 1 if boot from OTP is enabled. 7:0 RO The boot mode pins MODE0, MODE1, ..., specifying the boot frequency, boot source, etc. 0x03: xCORE Tile boot status B.5 - Description Reserved xCORE tile number on the switch. - Reserved Security configuration: 0x05 Copy of the security register as read from OTP. 0x05: Security configuration Bits Perm 31:0 RO B.6 Init Description Value. Ring Oscillator Control: 0x06 There are four free-running oscillators that clock four counters. The oscillators can be started and stopped using this register. The counters should only be read when the ring oscillator is stopped. The counter values can be read using four subsequent registers. The ring oscillators are asynchronous to the xCORE tile clock and can be used as a source of random bits. 0x06: Ring Oscillator Control Bits Perm 31:2 RO - 1 RW 0 Set to 1 to enable the xCORE tile ring oscillators 0 RW 0 Set to 1 to enable the peripheral ring oscillators B.7 Init Description Reserved Ring Oscillator Value: 0x07 This register contains the current count of the xCORE Tile Cell ring oscillator. This value is not reset on a system reset. 0x07: Ring Oscillator Value X8006, Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet B.8 35 Ring Oscillator Value: 0x08 This register contains the current count of the xCORE Tile Wire ring oscillator. This value is not reset on a system reset. 0x08: Ring Oscillator Value Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. B.9 Ring Oscillator Value: 0x09 This register contains the current count of the Peripheral Cell ring oscillator. This value is not reset on a system reset. 0x09: Ring Oscillator Value Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. B.10 Ring Oscillator Value: 0x0A This register contains the current count of the Peripheral Wire ring oscillator. This value is not reset on a system reset. 0x0A: Ring Oscillator Value Bits Perm Init Description 31:16 RO - Reserved 15:0 RO - Ring oscillator counter data. B.11 Debug SSR: 0x10 This register contains the value of the SSR register when the debugger was called. 0x10: Debug SSR Bits Perm 31:0 RO B.12 Init - Description Reserved Debug SPC: 0x11 This register contains the value of the SPC register when the debugger was called. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 0x11: Debug SPC Bits Perm 31:0 DRW B.13 36 Init Description Value. Debug SSP: 0x12 This register contains the value of the SSP register when the debugger was called. 0x12: Debug SSP Bits Perm 31:0 DRW B.14 Init Description Value. DGETREG operand 1: 0x13 The resource ID of the logical core whose state is to be read. 0x13: DGETREG operand 1 Bits 31:8 7:0 B.15 Perm RO Init - DRW Description Reserved Thread number to be read DGETREG operand 2: 0x14 Register number to be read by DGETREG 0x14: DGETREG operand 2 Bits Perm 31:5 RO 4:0 B.16 DRW Init - Description Reserved Register number to be read Debug interrupt type: 0x15 Register that specifies what activated the debug interrupt. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits Perm 37 Init - Description 31:18 RO 17:16 DRW If the debug interrupt was caused by a hardware breakpoint or hardware watchpoint, this field contains the number of the breakpoint or watchpoint. If multiple breakpoints or watchpoints trigger at once, the lowest number is taken. 15:8 DRW If the debug interrupt was caused by a logical core, this field contains the number of that core. Otherwise this field is 0. 7:3 RO - 2:0 DRW 0 0x15: Debug interrupt type B.17 Reserved Reserved Indicates the cause of the debug interrupt 1: Host initiated a debug interrupt through JTAG 2: Program executed a DCALL instruction 3: Instruction breakpoint 4: Data watch point 5: Resource watch point Debug interrupt data: 0x16 On a data watchpoint, this register contains the effective address of the memory operation that triggered the debugger. On a resource watchpoint, it countains the resource identifier. 0x16: Debug interrupt data Bits Perm 31:0 DRW B.18 Init Description Value. Debug core control: 0x18 This register enables the debugger to temporarily disable logical cores. When returning from the debug interrupts, the cores set in this register will not execute. This enables single stepping to be implemented. 0x18: Debug core control X8006, Bits Perm 31:8 RO 7:0 DRW Init - Description Reserved 1-hot vector defining which logical cores are stopped when not in debug mode. Every bit which is set prevents the respective logical core from running. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet B.19 38 Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over JTAG. This is the same set of registers as the Debug Scratch registers in the xCORE tile configuration. 0x20 .. 0x27: Debug scratch Bits Perm 31:0 DRW B.20 Init Description Value. Instruction breakpoint address: 0x30 .. 0x33 This register contains the address of the instruction breakpoint. If the PC matches this address, then a debug interrupt will be taken. There are four instruction breakpoints that are controlled individually. 0x30 .. 0x33: Instruction breakpoint address Bits Perm 31:0 DRW B.21 Init Description Value. Instruction breakpoint control: 0x40 .. 0x43 This register controls which logical cores may take an instruction breakpoint, and under which condition. Bits Perm Init 31:24 RO - 23:16 DRW 0 15:2 0x40 .. 0x43: Instruction breakpoint control B.22 Description Reserved A bit for each logical core in the tile allowing the breakpoint to be enabled individually for each logical core. RO - 1 DRW 0 Reserved Set to 1 to cause an instruction breakpoint if the PC is not equal to the breakpoint address. By default, the breakpoint is triggered when the PC is equal to the breakpoint address. 0 DRW 0 When 1 the instruction breakpoint is enabled. Data watchpoint address 1: 0x50 .. 0x53 This set of registers contains the first address for the four data watchpoints. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 0x50 .. 0x53: Data watchpoint address 1 Bits Perm 31:0 DRW B.23 39 Init Description Value. Data watchpoint address 2: 0x60 .. 0x63 This set of registers contains the second address for the four data watchpoints. 0x60 .. 0x63: Data watchpoint address 2 Bits Perm 31:0 DRW B.24 Init Description Value. Data breakpoint control register: 0x70 .. 0x73 This set of registers controls each of the four data watchpoints. Bits Perm Init 31:24 RO - 23:16 DRW 0 15:3 0x70 .. 0x73: Data breakpoint control register B.25 Description Reserved A bit for each logical core in the tile allowing the breakpoint to be enabled individually for each logical core. RO - 2 DRW 0 Reserved Set to 1 to enable breakpoints to be triggered on loads. Breakpoints always trigger on stores. 1 DRW 0 By default, data watchpoints trigger if memory in the range [Address1..Address2] is accessed (the range is inclusive of Address1 and Address2). If set to 1, data watchpoints trigger if memory outside the range (Address2..Address1) is accessed (the range is exclusive of Address2 and Address1). 0 DRW 0 When 1 the instruction breakpoint is enabled. Resources breakpoint mask: 0x80 .. 0x83 This set of registers contains the mask for the four resource watchpoints. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 0x80 .. 0x83: Resources breakpoint mask Bits Perm 31:0 DRW B.26 40 Init Description Value. Resources breakpoint value: 0x90 .. 0x93 This set of registers contains the value for the four resource watchpoints. 0x90 .. 0x93: Resources breakpoint value Bits Perm 31:0 DRW B.27 Init Description Value. Resources breakpoint control register: 0x9C .. 0x9F This set of registers controls each of the four resource watchpoints. Bits X8006, Init 31:24 RO - 23:16 DRW 0 15:2 0x9C .. 0x9F: Resources breakpoint control register Perm Description Reserved A bit for each logical core in the tile allowing the breakpoint to be enabled individually for each logical core. RO - 1 DRW 0 Reserved By default, resource watchpoints trigger when the resource id masked with the set Mask equals the Value. If set to 1, resource watchpoints trigger when the resource id masked with the set Mask is not equal to the Value. 0 DRW 0 When 1 the instruction breakpoint is enabled. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet C 41 Tile Configuration The xCORE Tile control registers can be accessed using configuration reads and writes (use write_tile_config_reg(tileref, ...) and read_tile_config_reg(tileref, > ...) for reads and writes). Number Figure 31: Summary X8006, Perm Description 0x00 RO Device identification 0x01 RO xCORE Tile description 1 0x02 RO xCORE Tile description 2 0x04 CRW Control PSwitch permissions to debug registers 0x05 CRW Cause debug interrupts 0x06 RW xCORE Tile clock divider 0x07 RO Security configuration 0x10 .. 0x13 RO PLink status 0x20 .. 0x27 CRW Debug scratch 0x40 RO PC of logical core 0 0x41 RO PC of logical core 1 0x42 RO PC of logical core 2 0x43 RO PC of logical core 3 0x44 RO PC of logical core 4 0x45 RO PC of logical core 5 0x46 RO PC of logical core 6 0x47 RO PC of logical core 7 0x60 RO SR of logical core 0 0x61 RO SR of logical core 1 0x62 RO SR of logical core 2 0x63 RO SR of logical core 3 0x64 RO SR of logical core 4 0x65 RO SR of logical core 5 0x66 RO SR of logical core 6 0x67 RO SR of logical core 7 0x80 .. 0x9F RO Chanend status XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet C.1 Device identification: 0x00 Bits 0x00: Device identification 42 Perm Init Description 31:24 RO Processor ID of this xCORE tile. 23:16 RO Number of the node in which this xCORE tile is located. 15:8 RO xCORE tile revision. 7:0 RO xCORE tile version. C.2 xCORE Tile description 1: 0x01 This register describes the number of logical cores, synchronisers, locks and channel ends available on this xCORE tile. Bits 0x01: xCORE Tile description 1 Perm Init Description 31:24 RO Number of channel ends. 23:16 RO Number of locks. 15:8 RO Number of synchronisers. 7:0 RO C.3 - Reserved xCORE Tile description 2: 0x02 This register describes the number of timers and clock blocks available on this xCORE tile. Bits 0x02: xCORE Tile description 2 Perm Init 31:16 RO 15:8 RO Number of clock blocks. 7:0 RO Number of timers. C.4 - Description Reserved Control PSwitch permissions to debug registers: 0x04 This register can be used to control whether the debug registers (marked with permission CRW) are accessible through the tile configuration registers. When this bit is set, write -access to those registers is disabled, preventing debugging of the xCORE tile over the interconnect. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 0x04: Control PSwitch permissions to debug registers Bits 31:1 0 C.5 Perm RO 43 Init - CRW Description Reserved Set to 1 to restrict PSwitch access to all CRW marked registers to become read-only rather than read-write. Cause debug interrupts: 0x05 This register can be used to raise a debug interrupt in this xCORE tile. 0x05: Cause debug interrupts Bits Perm 31:2 RO - 1 RO 0 Set to 1 when the processor is in debug mode. 0 CRW 0 Set to 1 to request a debug interrupt on the processor. C.6 Init Description Reserved xCORE Tile clock divider: 0x06 This register contains the value used to divide the PLL clock to create the xCORE tile clock. The divider is enabled under control of the tile control register 0x06: xCORE Tile clock divider Bits Perm 31:8 RO 7:0 RW C.7 Init - Description Reserved Value of the clock divider minus one. Security configuration: 0x07 Copy of the security register as read from OTP. 0x07: Security configuration Bits Perm 31:0 RO C.8 Init Description Value. PLink status: 0x10 .. 0x13 Status of each of the four processor links; connecting the xCORE tile to the switch. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits Perm 31:26 RO 44 Init - Description Reserved 25:24 RO 00 - ChannelEnd, 01 - ERROR, 10 - PSCTL, 11 - Idle. 23:16 RO Based on SRC_TARGET_TYPE value, it represents channelEnd ID or Idle status. 15:6 RO 5:4 RO 3 RO 2 RO 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. 0x10 .. 0x13: PLink status C.9 - Reserved Two-bit network identifier - Reserved 1 when the current packet is considered junk and will be thrown away. Debug scratch: 0x20 .. 0x27 A set of registers used by the debug ROM to communicate with an external debugger, for example over the switch. This is the same set of registers as the Debug Scratch registers in the processor status. 0x20 .. 0x27: Debug scratch Bits Perm 31:0 CRW C.10 Init Description Value. PC of logical core 0: 0x40 Value of the PC of logical core 0. 0x40: PC of logical core 0 X8006, Bits Perm 31:0 RO Init Description Value. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet C.11 0x41: PC of logical core 1 0x42: PC of logical core 2 Bits Perm RO Perm 31:0 RO 0x44: PC of logical core 4 Bits Perm RO 0x45: PC of logical core 5 X8006, Value. Init Description Value. Init Description Value. PC of logical core 4: 0x44 Bits Perm 31:0 RO C.15 Description PC of logical core 3: 0x43 31:0 C.14 Init PC of logical core 2: 0x42 Bits C.13 0x43: PC of logical core 3 PC of logical core 1: 0x41 31:0 C.12 45 Init Description Value. PC of logical core 5: 0x45 Bits Perm 31:0 RO Init Description Value. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet C.16 0x46: PC of logical core 6 0x47: PC of logical core 7 PC of logical core 6: 0x46 Bits Perm 31:0 RO C.17 Init Description Value. PC of logical core 7: 0x47 Bits Perm 31:0 RO C.18 46 Init Description Value. SR of logical core 0: 0x60 Value of the SR of logical core 0 0x60: SR of logical core 0 Bits Perm 31:0 RO C.19 0x61: SR of logical core 1 0x62: SR of logical core 2 X8006, Description Value. SR of logical core 1: 0x61 Bits Perm 31:0 RO C.20 Init Init Description Value. SR of logical core 2: 0x62 Bits Perm 31:0 RO Init Description Value. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet C.21 0x63: SR of logical core 3 0x64: SR of logical core 4 Bits Perm RO Perm 31:0 RO 0x66: SR of logical core 6 Bits Perm RO 0x67: SR of logical core 7 Perm 31:0 RO Init Description Value. Init Description Value. Init Description Value. SR of logical core 7: 0x67 Bits Perm 31:0 RO C.26 Value. SR of logical core 6: 0x66 Bits C.25 Description SR of logical core 5: 0x65 31:0 C.24 Init SR of logical core 4: 0x64 Bits C.23 0x65: SR of logical core 5 SR of logical core 3: 0x63 31:0 C.22 47 Init Description Value. Chanend status: 0x80 .. 0x9F These registers record the status of each channel-end on the tile. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits 0x80 .. 0x9F: Chanend status X8006, Perm 31:26 RO 48 Init - Description Reserved 25:24 RO 00 - ChannelEnd, 01 - ERROR, 10 - PSCTL, 11 - Idle. 23:16 RO Based on SRC_TARGET_TYPE value, it represents channelEnd ID or Idle status. 15:6 RO 5:4 RO 3 RO 2 RO 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. - Reserved Two-bit network identifier - Reserved 1 when the current packet is considered junk and will be thrown away. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet D 49 Node Configuration The digital node control registers can be accessed using configuration reads and writes (use write_node_config_reg(device, ...) and read_node_config_reg(device, > ...) for reads and writes). Number 0x00 Figure 32: Summary Perm Description RO Device identification 0x01 RO System switch description 0x04 RW Switch configuration 0x05 RW Switch node identifier 0x06 RW PLL settings 0x07 RW System switch clock divider 0x08 RW Reference clock 0x0C RW Directions 0-7 0x0D RW Directions 8-15 0x10 RW DEBUG_N configuration 0x1F RO Debug source 0x20 .. 0x27 RW Link status, direction, and network 0x40 .. 0x43 RW PLink status and network 0x80 .. 0x87 RW Link configuration and initialization 0xA0 .. 0xA7 RW Static link configuration D.1 Device identification: 0x00 This register contains version and revision identifiers and the mode-pins as sampled at boot-time. Bits 0x00: Device identification Perm Init 31:24 RO 23:16 RO Sampled values of pins MODE0, MODE1, ... on reset. 15:8 RO SSwitch revision. 7:0 RO SSwitch version. D.2 0x00 Description Chip identifier. System switch description: 0x01 This register specifies the number of processors and links that are connected to this switch. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits 0x01: System switch description Perm 50 Init 31:24 RO 23:16 RO Number of links on the switch. 15:8 RO Number of cores that are connected to this switch. 7:0 RO Number of links per processor. D.3 - Description Reserved Switch configuration: 0x04 This register enables the setting of two security modes (that disable updates to the PLL or any other registers) and the header-mode. Bits 0x04: Switch configuration Perm Init 31 RO 0 30:9 RO - 8 RO 0 7:1 RO - 0 RO 0 D.4 Description Set to 1 to disable any write access to the configuration registers in this switch. Reserved Set to 1 to disable updates to the PLL configuration register. Reserved Header mode. Set to 1 to enable 1-byte headers. This must be performed on all nodes in the system. Switch node identifier: 0x05 This register contains the node identifier. Bits 0x05: Switch node identifier Perm Init 31:16 RO - 15:0 RW 0 D.5 Description Reserved The unique 16-bit ID of this node. This ID is matched mostsignificant-bit first with incoming messages for routing purposes. PLL settings: 0x06 An on-chip PLL multiplies the input clock up to a higher frequency clock, used to clock the I/O, processor, and switch, see Oscillator. Note: a write to this register will cause the tile to be reset. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits Perm 31:26 RO 25:23 RW 22:21 RO 20:8 RW 7 RO 6:0 RW 0x06: PLL settings D.6 51 Init - Description Reserved OD: Output divider value The initial value depends on pins MODE0 and MODE1. - Reserved F: Feedback multiplication ratio The initial value depends on pins MODE0 and MODE1. - Reserved R: Oscilator input divider value The initial value depends on pins MODE0 and MODE1. System switch clock divider: 0x07 Sets the ratio of the PLL clock and the switch clock. 0x07: System switch clock divider Bits Perm Init 31:16 RO - 15:0 RW 0 D.7 Description Reserved Switch clock divider. The PLL clock will be divided by this value plus one to derive the switch clock. Reference clock: 0x08 Sets the ratio of the PLL clock and the reference clock used by the node. Bits 0x08: Reference clock Perm Init 31:16 RO - 15:0 RW 3 D.8 Description Reserved Architecture reference clock divider. The PLL clock will be divided by this value plus one to derive the 100 MHz reference clock. Directions 0-7: 0x0C This register contains eight directions, for packets with a mismatch in bits 7..0 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits 0x0C: Directions 0-7 Perm 52 Init Description 31:28 RW 0 The direction for packets whose first mismatching bit is 7. 27:24 RW 0 The direction for packets whose first mismatching bit is 6. 23:20 RW 0 The direction for packets whose first mismatching bit is 5. 19:16 RW 0 The direction for packets whose first mismatching bit is 4. 15:12 RW 0 The direction for packets whose first mismatching bit is 3. 11:8 RW 0 The direction for packets whose first mismatching bit is 2. 7:4 RW 0 The direction for packets whose first mismatching bit is 1. 3:0 RW 0 The direction for packets whose first mismatching bit is 0. D.9 Directions 8-15: 0x0D This register contains eight directions, for packets with a mismatch in bits 15..8 of the node-identifier. The direction in which a packet will be routed is goverened by the most significant mismatching bit. Bits 0x0D: Directions 8-15 Perm Init Description 31:28 RW 0 The direction for packets whose first mismatching bit is 15. 27:24 RW 0 The direction for packets whose first mismatching bit is 14. 23:20 RW 0 The direction for packets whose first mismatching bit is 13. 19:16 RW 0 The direction for packets whose first mismatching bit is 12. 15:12 RW 0 The direction for packets whose first mismatching bit is 11. 11:8 RW 0 The direction for packets whose first mismatching bit is 10. 7:4 RW 0 The direction for packets whose first mismatching bit is 9. 3:0 RW 0 The direction for packets whose first mismatching bit is 8. D.10 DEBUG_N configuration: 0x10 Configures the behavior of the DEBUG_N pin. 0x10: DEBUG_N configuration X8006, Bits Perm 31:2 RO Init - Description 1 RW 0 Set to 1 to enable signals on DEBUG_N to generate DCALL on the core. 0 RW 0 When set to 1, the DEBUG_N wire will be pulled down when the node enters debug mode. Reserved XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet D.11 53 Debug source: 0x1F Contains the source of the most recent debug event. 0x1F: Debug source Bits Perm 31:5 RO 4 RW 3:1 RO 0 RW D.12 Init Description - Reserved If set, the external DEBUG_N pin is the source of the most recent debug interrupt. - Reserved If set, the xCORE Tile is the source of the most recent debug interrupt. Link status, direction, and network: 0x20 .. 0x27 These registers contain status information for low level debugging (read-only), the network number that each link belongs to, and the direction that each link is part of. The registers control links C, D, A, B, G, H, E, and F in that order. Bits 0x20 .. 0x27: Link status, direction, and network X8006, Perm Init - Description 31:26 RO 25:24 RO Reserved 23:16 RO 0 15:12 RO - 11:8 RW 0 7:6 RO - 5:4 RW 0 3 RO - 2 RO 0 Set to 1 if the current packet is junk and being thrown away. A packet is considered junk if, for example, it is not routable. 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. If this link is currently routing data into the switch, this field specifies the type of link that the data is routed to: 0: plink 1: external link 2: internal control link If the link is routing data into the switch, this field specifies the destination link number to which all tokens are sent. Reserved The direction that this this link is associated with; set for routing. Reserved Determines the network to which this link belongs, set for quality of service. Reserved XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet D.13 54 PLink status and network: 0x40 .. 0x43 These registers contain status information and the network number that each processor-link belongs to. Bits Perm 31:26 RO 25:24 RO 23:16 RO Init - Description Reserved If this link is currently routing data into the switch, this field specifies the type of link that the data is routed to: 0: plink 1: external link 2: internal control link 0 If the link is routing data into the switch, this field specifies the destination link number to which all tokens are sent. 15:6 RO - 5:4 RW 0 3 RO - 2 RO 0 Set to 1 if the current packet is junk and being thrown away. A packet is considered junk if, for example, it is not routable. 1 RO 0 Set to 1 if the switch is routing data into the link, and if a route exists from another link. 0 RO 0 Set to 1 if the link is routing data into the switch, and if a route is created to another link on the switch. 0x40 .. 0x43: PLink status and network D.14 Reserved Determines the network to which this link belongs, set for quality of service. Reserved Link configuration and initialization: 0x80 .. 0x87 These registers contain configuration and debugging information specific to external links. The link speed and width can be set, the link can be initialized, and the link status can be monitored. The registers control links C, D, A, B, G, H, E, and F in that order. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet Bits 0x80 .. 0x87: Link configuration and initialization Perm 55 Init Description 31 RW 0 Write ’1’ to this bit to enable the link, write ’0’ to disable it. This bit controls the muxing of ports with overlapping links. 30 RW 0 Set to 0 to operate in 2 wire mode or 1 to operate in 5 wire mode 29:28 RO - 27 RO 0 Set to 1 on error: an RX buffer overflow or illegal token encoding has been received. This bit clears on reading. 26 RO 0 1 if this end of the link has issued credit to allow the remote end to transmit. 25 RO 0 1 if this end of the link has credits to allow it to transmit. 24 WO 0 Set to 1 to initialize a half-duplex link. This clears this end of the link’s credit and issues a HELLO token; the other side of the link will reply with credits. This bit is self-clearing. 23 WO 0 Set to 1 to reset the receiver. The next symbol that is detected will be assumed to be the first symbol in a token. This bit is self-clearing. 22 RO - 21:11 RW 0 The number of system clocks between two subsequent transitions within a token 10:0 RW 0 The number of system clocks between two subsequent transmit tokens. D.15 Reserved Reserved Static link configuration: 0xA0 .. 0xA7 These registers are used for static (ie, non-routed) links. When a link is made static, all traffic is forwarded to the designated channel end and no routing is attempted. The registers control links C, D, A, B, G, H, E, and F in that order. Bits 0xA0 .. 0xA7: Static link configuration X8006, Perm Init 31 RW 0 30:5 RO - 4:0 RW 0 Description Enable static forwarding. Reserved The destination channel end on this node that packets received in static mode are forwarded to. XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet E 56 XMOS USB Interface XMOS provides a low-level USB interface for connecting the device to a USB transceiver using the UTMI+ Low Pin Interface (ULPI). The ULPI signals must be connected to the pins named in Figure 33. Note also that some ports on the same tile are used internally and are not available for use when the USB driver is active (they are available otherwise). Pin Pin Signal Pin XnD02 XnD12 ULPI_STP XnD26 XnD03 XnD13 ULPI_NXT XnD27 XnD04 XnD14 ULPI_DATA[0] XnD28 XnD15 ULPI_DATA[1] XnD29 XnD16 ULPI_DATA[2] XnD30 XnD07 XnD17 ULPI_DATA[3] XnD31 XnD08 XnD18 ULPI_DATA[4] XnD32 XnD09 XnD19 ULPI_DATA[5] XnD33 XnD20 ULPI_DATA[6] XnD21 ULPI_DATA[7] XnD37 XnD22 ULPI_DIR XnD38 XnD23 ULPI_CLK XnD39 XnD05 XnD06 Unavailable when USB active XnD40 Figure 33: ULPI signals provided by the XMOS USB driver F Signal XnD41 Signal Unavailable when USB active Unavailable when USB active XnD42 XnD43 Device Errata This section describes minor operational differences from the data sheet and recommended workarounds. As device and documentation issues become known, this section will be updated the document revised. To guarantee a logic low is seen on the pins RST_N, DEBUG_N, MODE[4:0], TRST_N, TMS, TCK and TDI, the driving circuit should present an impedance of less than 100 Ω to ground. Usually this is not a problem for CMOS drivers driving single inputs. If one or more of these inputs are placed in parallel, however, additional logic buffers may be required to guarantee correct operation. For static inputs tied high or low, the relevant input pin should be tied directly to GND or VDDIO. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet G 57 JTAG, xSCOPE and Debugging If you intend to design a board that can be used with the XMOS toolchain and xTAG debugger, you will need an xSYS header on your board. Figure 34 shows a decision diagram which explains what type of xSYS connectivity you need. The three subsections below explain the options in detail. YES YES Is xSCOPE required YES Figure 34: Decision diagram for the xSYS header Use full xSYS header See section 3 G.1 Is debugging required? NO Is fast printf required ? NO YES Does the SPI flash need to be programmed? NO NO Use JTAG xSYS header See section 2 No xSYS header required See section 1 No xSYS header The use of an xSYS header is optional, and may not be required for volume production designs. However, the XMOS toolchain expects the xSYS header; if you do not have an xSYS header then you must provide your own method for writing to flash/OTP and for debugging. G.2 JTAG-only xSYS header The xSYS header connects to an xTAG debugger, which has a 20-pin 0.1" female IDC header. The design will hence need a male IDC header. We advise to use a boxed header to guard against incorrect plug-ins. If you use a 90 degree angled header, make sure that pins 2, 4, 6, ..., 20 are along the edge of the PCB. Connect pins 4, 8, 12, 16, 20 of the xSYS header to ground, and then connect: · TDI to pin 5 of the xSYS header · TMS to pin 7 of the xSYS header · TCK to pin 9 of the xSYS header · DEBUG_N to pin 11 of the xSYS header X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 58 · TDO to pin 13 of the xSYS header · RST_N and TRST_N to pin 15 of the xSYS header · If MODE2 is configured high, connect MODE2 to pin 3 of the xSYS header. Do not connect to VDDIO. · If MODE3 is configured high, connect MODE3 to pin 3 of the xSYS header. Do not connect to VDDIO. The RST_N net should be open-drain, active-low, and have a pull-up to VDDIO. G.3 Full xSYS header For a full xSYS header you will need to connect the pins as discussed in Section G.2, and then connect a 2-wire xCONNECT Link to the xSYS header. The links can be found in the Signal description table (Section 4): they are labelled XLA, XLB, etc in the function column. The 2-wire link comprises two inputs and outputs, labelled 0 0 1 1 out , out , in , and in . For example, if you choose to use XLB of tile 0 for xSCOPE I/O, you need to connect up XLB1out , XLB0out , XLB0in , XLB1in as follows: · XLB1out (X0D16) to pin 6 of the xSYS header with a 33R series resistor close to the device. · XLB0out (X0D17) to pin 10 of the xSYS header with a 33R series resistor close to the device. · XLB0in (X0D18) to pin 14 of the xSYS header. · XLB1in (X0D19) to pin 18 of the xSYS header. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet H 59 Schematics Design Check List This section is a checklist for use by schematics designers using the XS1-L16A-128-QF124. Each of the following sections contains items to check for each design. H.1 Power supplies VDDIO and OTP_VCC supply is within specification before the VDD (core) supply is turned on. Specifically, the VDDIO and OTP_VCC supply is within specification before VDD (core) reaches 0.4V (Section 10). The VDD (core) supply ramps monotonically (rises constantly) from 0V to its final value (0.95V - 1.05V) within 10ms (Section 10). The VDD (core) supply is capable of supplying 600mA (Section 10). PLL_AVDD is filtered with a low pass filter, for example an RC filter, . see Section 10 The PCU_VDD pin is connected to the VDD supply and PCU_VDDIO is connected to the VDDIO supply (Section 10). H.2 Power supply decoupling The design has multiple decoupling capacitors per supply, for example at least four0402 or 0603 size surface mount capacitors of 100nF in value, per supply (Section 10). A bulk decoupling capacitor of at least 10uF is placed on each supply (Section 10). H.3 Power on reset The RST_N and TRST_N pins are asserted (low) during or after power up. The device is not used until these resets have taken place. As the errata in the datasheets show, the internal pull-ups on these two pins can occasionally provide stronger than normal pull-up currents. For this reason, an RC type reset circuit is discouraged as behavior would be unpredictable. A voltage supervisor type reset device is recommended to guarantee a good reset. This also has the benefit of resetting the system should the relevant supply go out of specification. X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet H.4 60 Clock The CLK input pin is supplied with a clock with monotonic rising edges and low jitter. The PCU_CLK pin is supplied with a clock, for example it is tied to the main CLK (Section 9.1). The PCU_WAKE and PCU_GATE pins should be left unconnected (Section 9.1). Pins MODE0 and MODE1 are set to the correct value for the chosen oscillator frequency. The MODE settings are shown in the Oscillator section, Section 6. If you have a choice between two values, choose the value with the highest multiplier ratio since that will boot faster. H.5 USB ULPI Mode This section can be skipped if you do not have an external USB PHY. If using ULPI, the ULPI signals are connected to specific ports as shown in Section E. If using ULPI, the ports that are used internally are not connected, see Section E. (Note that this limitation only applies when the ULPI is enabled, they can still be used before or after the ULPI is being used.) H.6 Boot The device is connected to a SPI flash for booting, connected to X0D0, X0D01, X0D10, and X0D11 (Section 7). If not, you must boot the device through OTP or JTAG. The device that is connected to flash has both MODE2 and MODE3 connected to pin 3 on the xSYS Header (MSEL). If no debug adapter connection is supported (not recommended) MODE2 and MODE3 are to be left NC (Section 7). MODE4 is set in accordance with Section 7. The SPI flash that you have chosen is supported by xflash, or you have created a specification file for it. H.7 JTAG, XScope, and debugging You have decided as to whether you need an XSYS header or not (Section G) X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet 61 If you included an XSYS header, you connected pin 3 to any MODE2/MODE3 pin that would otherwise be NC (Section G). If you have not included an XSYS header, you have devised a method to program the SPI-flash or OTP (Section G). H.8 GPIO You have not mapped both inputs and outputs to the same multi-bit port. H.9 Multi device designs Skip this section if your design only includes a single XMOS device. One device is connected to a SPI flash for booting. Devices that boot from link have MODE2 grounded and MODE3 NC. These device must have link XLB connected to a device to boot from (see 7). If you included an XSYS header, you have included buffers for RST_N, TRST_N, TMS, TCK, MODE2, and MODE3 (Section F). X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet I 62 PCB Layout Design Check List This section is a checklist for use by PCB designers using the XS1-L16A128-QF124. Each of the following sections contains items to check for each design. I.1 Land pattern and solder stencil You have used a land pattern suitable for the small QFN pads. (Section 10.1) You have used a solder stencil with the correct aperture and thinness. (Section 10.1) I.2 Ground Plane Multiple vias (eg, 9) have been used to connect the center pad to the PCB ground plane. These minimize impedance and conduct heat away from the device. (Section 10.3). Other than ground vias, there are no (or only a few) vias underneath or closely around the device. This create a good, solid, ground plane. I.3 Power supply decoupling The decoupling capacitors are all placed close to a supply pin (Section 10). The decoupling capacitors are spaced around the device (Section 10). The ground side of each decoupling capacitor has a direct path back to the center ground of the device. I.4 PLL_AVDD The PLL_AVDD filter (especially the capacitor) is placed close to the PLL_AVDD pin (Section 10). X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet J 63 Associated Design Documentation Document Title Information Document Number Estimating Power Consumption For XS1-L Devices Power consumption X4271 Programming XC on XMOS Devices Timers, ports, clocks, cores and channels X9577 xTIMEcomposer User Guide Compilers, assembler and linker/mapper X3766 Timing analyzer, xScope, debugger Flash and OTP programming utilities K Related Documentation Document Title Information Document Number The XMOS XS1 Architecture ISA manual X7879 XS1 Port I/O Timing Port timings X5821 xCONNECT Architecture Link, switch and system information X4249 XS1-L Link Performance and Design Guidelines Link timings X2999 XS1-L Clock Frequency Control Advanced clock control X1433 XS1-L Active Power Conservation Low-power mode during idle X7411 X8006, XS1-L16A-128-QF124 XS1-L16A-128-QF124 Datasheet L 64 Revision History Date Description 2013-01-30 New datasheet - revised part numbering 2013-02-26 New multicore microcontroller introduction Moved configuration sections to appendices 2013-07-19 Updated Features list with available ports and links - Section 2 Simplified link bits in Signal Description - Section 4 New JTAG, xSCOPE and Debugging appendix - Section G New Schematics Design Check List - Section H New PCB Layout Design Check List - Section I 2013-09-16 Removed references to PCU. Pins set to GND - Section 3 2013-12-09 Added Industrial Ambient Temperature - Section 11.1 2013-12-17 Added references to PCU - Section 3 and 9.1 2014-03-25 Updated BOTTOM VIEW in mechanical drawing - Section 12 2014-06-25 Added PCU_GATE, PCU_CLK, PCU_VDD, PCU_VDDIO to Schematics Checklist Section H 2015-04-14 Updated Introduction - Section 1; Pin Configuration - Section 3; Signal Description - Section 4 Copyright © 2015, All Rights Reserved. Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. X8006, XS1-L16A-128-QF124