XS1-G02B-FB144-I4

XS1-G02B-FB144 Datasheet Document Number: 1100C Not for New Designs Publication Date: 2011/05/16 Copyright © 2010 XMOS Limited, All Rights Reserved. XS1-G02B-FB144 Datasheet 1 Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 Features . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . Signal Description . . . . . . . . . . Block Diagram . . . . . . . . . . . . Product Overview . . . . . . . . . . DC and Switching Characteristics . Package Information . . . . . . . . Ordering Information . . . . . . . . Development Tools . . . . . . . . . Addendum: XMOS USB Interface . . Associated Design Documentation Related Documentation . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 7 8 15 19 20 20 20 21 22 23 TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. 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Document Number: 1100C XS1-G02B-FB144 Datasheet 1 2 Features · Dual-Core Device with Advanced Multi-Threaded RISC Architecture • Up to 800 MIPS shared between up to 16 real-time threads • Each thread has: — Guaranteed throughput of between 1/4 and 1/8 of core MIPS — 16x32bit dedicated registers • 159 high-density 16/32-bit instructions — All have single clock-cycle execution (except for divide) — High-performance DSP (32x32→64-bit MAC) and cryptographic instructions · Programmable I/O • 88 general-purpose I/O pins, configurable as input, output or bi-directional ports • Port sampling rates of up to 60 MHz with respect to an external clock • 64 channel ends for communication with other threads, on or off-chip · Non-Volatile Memory • 128KB internal single-cycle SRAM (max 64KB per core) for code and data storage • 32KB internal OTP (max 8KB per core) for application boot code · JTAG Module for On-Chip Debug · Security Features • Programming lock disables debug and prevents read-back of memory contents • AES bootloader ensures secrecy of IP held on external flash memory · Ambient Temperature Range • Commercial qualification: 0 °C to 70 °C • Industrial qualification: -40 °C to 85 °C · Speed Grade • 400 MHz part: 400 MIPS · 144-pin FBGA package 0.8 mm pitch Document Number: 1100C XS1-G02B-FB144 Datasheet 2 3 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 A IO VDD X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 X0D43 VSS B X0D33 VSS X0D18 X0D19 X0D20 IO VDD VSS X0D21 X0D22 X0D23 IO VDD X2D24 C X0D32 X0D17 VDD X0D06 X0D07 X0D08 X0D09 X0D10 X0D11 VDD X2D12 X2D25 D X0D31 X0D16 X0D05 SS_PLL_ BYPASS SS_ RESET VDD SS_XC_ CFG[0] X2D00 X2D13 X2D26 E X0D30 X0D15 X0D04 SS_CLK VSS VSS VSS VSS DEBUG_ N X2D01 X2D14 X2D27 F X0D29 IO VDD X0D03 SS_PLL_ AGND VSS VSS VSS VSS VDD X2D02 VSS X2D28 G X0D28 VSS X0D02 VDD VSS VSS VSS VSS SS_ TEST_ ENA X2D03 IO VDD X2D29 H X0D27 X0D14 X0D01 SS_PLL_ AVDD VSS VSS VSS VSS SS_TCK X2D04 X2D15 X2D30 J X0D26 X0D13 X0D00 SS_PLL_ LOCK SS_TMS SS_TDO VDD SS_TDI SS_TRST X2D05 X2D16 X2D31 K X0D25 X0D12 VDD X2D11 X2D10 X2D09 X2D08 X2D07 X2D06 VDD X2D17 X2D32 L X0D24 IO VDD X2D23 X2D22 X2D21 VSS IO VDD X2D20 X2D19 X2D18 VSS X2D33 M VSS X2D43 X2D42 X2D41 X2D40 X2D39 X2D38 X2D37 X2D36 X2D35 X2D34 IO VDD SS_OTP_ SS_XC0_ BS[0] VPP Document Number: 1100C XS1-G02B-FB144 Datasheet 3 4 Signal Description Module Signal Function Type Active Properties PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger, OT=Output Tristate, S=Switchable RS =Required for SPI boot (§5.8), RU =Required for USB-enabled devices (§10) Power PLL JTAG VSS Digital ground GND — VDD Digital core power PWR — IO VDD Digital I/O power PWR — SS_PLL_AGND Analog ground for PLL GND — SS_PLL_AVDD Analog PLL power PWR — SS_OTP_VPP OTP programming voltage PWR — SS_RESET Global reset input Input — PU, ST SS_CLK PLL reference clock Input — PD, ST SS_PLL_BYPASS PLL bypass Input — PD SS_XC0_BS[0:0] Boot status (core 0) I/O — PU SS_TDI Test data input Input — PU, ST SS_TDO Test data output Output — PD SS_TMS Test mode select Input — PU, ST SS_TRST Test reset input Input — PU, ST SS_TCK Test clock Input — PU DEBUG_N Multi-chip debug I/O Low PU P1A0 I/O — RS P1B0 I/O — RS X0D00 XCore 0 I/O X0D01 X0LA4i 5b X0D02 X0LA3i 5b P4A0 P8A0 P16A0 P32A20 I/O — RU X0D03 X0LA2i 5b P4A1 P8A1 P16A1 P32A21 I/O — RU X0D04 X0LA1i 2b/5b P4B0 P8A2 P16A2 P32A22 I/O — RU X0D05 X0LA0i 2b/5b P4B1 P8A3 P16A3 P32A23 I/O — RU X0D06 X0LA0o 2b/5b P4B2 P8A4 P16A4 P32A24 I/O — RU X0D07 X0LA1o 2b/5b P4B3 P8A5 P16A5 P32A25 I/O — RU X0D08 X0LA2o 5b P4A2 P8A6 P16A6 P32A26 I/O — RU X0D09 X0LA3o 5b P4A3 P8A7 P16A7 P32A27 I/O — RU X0D10 X0LA4o 5b P1C0 I/O — RS X0D11 P1D0 I/O — RS X0D12 P1E0 I/O — RU P1F0 I/O — RU X0D13 X0LB4i 5b X0D14 X0LB3i 5b P4C0 P8B0 P16A8 P32A28 I/O — RU X0D15 X0LB2i 5b P4C1 P8B1 P16A9 P32A29 I/O — RU X0D16 X0LB1i 2b/5b P4D0 P8B2 P16A10 I/O — RU X0D17 X0LB0i 2b/5b P4D1 P8B3 P16A11 I/O — RU X0D18 X0LB0o 2b/5b P4D2 P8B4 P16A12 I/O — RU X0D19 X0LB1o 2b/5b P4D3 P8B5 P16A13 I/O — RU X0D20 X0LB2o 5b P4C2 P8B6 P16A14 P32A30 I/O — RU X0D21 X0LB3o 5b P4C3 P8B7 P16A15 P32A31 I/O — RU (continued) Document Number: 1100C XS1-G02B-FB144 Datasheet Module XCore 0 I/O 5 Name Function X0D22 X0LB4o 5b Type Active Properties P1G0 I/O — RU X0D23 P1H0 I/O — RU X0D24 P1I0 I/O — X0D25 P1J0 I/O — X0D26 P4E0 P8C0 P16B0 I/O — RU X0D27 P4E1 P8C1 P16B1 I/O — RU X0D28 P4F0 P8C2 P16B2 I/O — RU X0D29 P4F1 P8C3 P16B3 I/O — RU X0D30 P4F2 P8C4 P16B4 I/O — RU X0D31 P4F3 P8C5 P16B5 I/O — RU X0D32 P4E2 P8C6 P16B6 I/O — RU X0D33 P4E3 P8C7 P16B7 I/O — RU I/O — X0D34 P1K0 X0D35 P1L0 I/O — X0D36 P1M0 P8D0 P16B8 I/O — X0D37 P1N0 P8D1 P16B9 I/O — RU X0D38 P1O0 P8D2 P16B10 I/O — RU X0D39 P1P0 P8D3 P16B11 I/O — RU X0D40 P8D4 P16B12 I/O — RU X0D41 P8D5 P16B13 I/O — RU X0D42 P8D6 P16B14 I/O — RU X0D43 P8D7 P16B15 I/O — RU I/O — P1A0 X2D00 X2D01 X2LA4i 5b X2D02 X2D11 X2LA3i 5b X2LA2i 5b X2LA1i 2b/5b X2LA0i 2b/5b X2LA0o 2b/5b X2LA1o 2b/5b X2LA2o 5b X2LA3o 5b X2LA4o P1C0 5b P1D0 X2D12 P1E0 P1F0 X2D03 X2D04 X2D05 X2D06 X2D07 X2D08 X2D09 XCore 2 I/O X2D10 P1B0 I/O — P4A0 P8A0 P16A0 P32A20 I/O — RU P4A1 P8A1 P16A1 P32A21 I/O — RU P4B0 P8A2 P16A2 P32A22 I/O — RU P4B1 P8A3 P16A3 P32A23 I/O — RU P4B2 P8A4 P16A4 P32A24 I/O — RU P4B3 P8A5 P16A5 P32A25 I/O — RU P4A2 P8A6 P16A6 P32A26 I/O — RU P4A3 P8A7 P16A7 P32A27 I/O — RU I/O — I/O — I/O — RU I/O — RU X2D13 X2LB4i 5b X2D14 X2LB3i 5b P4C0 P8B0 P16A8 P32A28 I/O — RU X2D15 X2LB2i 5b P4C1 P8B1 P16A9 P32A29 I/O — RU X2D16 X2LB1i 2b/5b P4D0 P8B2 P16A10 I/O — RU X2D17 X2LB0i 2b/5b P4D1 P8B3 P16A11 I/O — RU X2D18 X2LB0o 2b/5b P4D2 P8B4 P16A12 I/O — RU X2D19 X2LB1o 2b/5b P4D3 P8B5 P16A13 I/O — RU X2D20 X2LB2o 5b P4C2 P8B6 P16A14 P32A30 I/O — RU (continued) Document Number: 1100C XS1-G02B-FB144 Datasheet Module XCore 2 I/O Reserved 6 Name Function X2D21 X2LB3o 5b Type Active Properties I/O — X2D22 X2LB4o 5b RU P1G0 I/O — RU X2D23 P1H0 I/O — RU X2D24 P1I0 I/O — X2D25 P1J0 P4C3 P8B7 P16A15 P32A31 I/O — X2D26 P4E0 P8C0 P16B0 I/O — RU X2D27 P4E1 P8C1 P16B1 I/O — RU X2D28 P4F0 P8C2 P16B2 I/O — RU X2D29 P4F1 P8C3 P16B3 I/O — RU X2D30 P4F2 P8C4 P16B4 I/O — RU X2D31 P4F3 P8C5 P16B5 I/O — RU X2D32 P4E2 P8C6 P16B6 I/O — RU X2D33 P4E3 P8C7 P16B7 I/O — RU I/O — X2D34 P1K0 X2D35 P1L0 I/O — X2D36 P1M0 P8D0 P16B8 I/O — X2D37 P1N0 P8D1 P16B9 I/O — RU X2D38 P1O0 P8D2 P16B10 I/O — RU X2D39 P1P0 P8D3 P16B11 I/O — RU X2D40 P8D4 P16B12 I/O — RU X2D41 P8D5 P16B13 I/O — RU X2D42 P8D6 P16B14 I/O — RU X2D43 P8D7 P16B15 I/O — RU SS_PLL_LOCK Reserved (do not connect) Output — PD SS_TEST_ENA Reserved (tie to VSS) Input — PD SS_XC_CFG[0:0] Reserved (tie to IO VDD) Input — PD Document Number: 1100C XS1-G02B-FB144 Datasheet Block Diagram Thread 1 Thread 1 Boot ROM Port 16B 10 Timers Thread 5 Thread 5 10 Timers 4 Locks Thread 6 Thread 6 4 Locks 7 Synchronizers Thread 7 Thread 7 7 Synchronizers Port 4B Port 4C Port 4D ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ 1G 1H ¶ 1I ¶ 1J ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ 1K ¶ 1L ¶ 1M ¶ 1N ¶ 1O ¶ 1P ¶ · X2D00 · X2D01 · X2D02 · X2D03 · X2D08 · X2D09 · X2D04 · X2D05 · X2D06 · X2D07 · X2D10 · X2D11 · X2D12 · X2D13 · X2D14 · X2D15 · X2D20 · X2D21 · X2D16 · X2D17 · X2D18 · X2D19 · X2D22 · X2D23 · X2D24 · X2D25 · X2D26 · X2D27 · X2D32 · X2D33 · X2D28 · X2D29 · X2D30 · X2D31 · X2D34 · X2D35 · X2D36 · X2D37 · X2D38 · X2D39 ·X2D40 ·X2D41 ·X2D42 ·X2D43 X2 X0 PLL_BYPASS PLL_LOCK PLL_AVDD PLL_AGND CLK XC0_BS0 RST_N Port 4E 6 Clock Blocks Port 16A Thread 4 Port 8B Security Register Port 4F Port 4E Port 8C · · · · Thread 3 Port 8C Thread 4 8KB OTP Port 16B 6 Clock Blocks 1G · 1H · 1I · 1J · · · · · · · · 1K · · 1L · 1M · 1N · 1O · 1P Thread 2 1C 1D ¶ 1E ¶ 1F Port 8D Thread 3 Switch Security Register 32 Channel Ends Thread 2 Switch 8KB OTP ¶ X0LA Boot ROM 1A 1B X0LB 64KB SRAM Port 4A Thread 0 Port 8A Thread 0 Switch Port 16A Port 8B Port 4D 64KB SRAM 32 Channel Ends Port 4B 1C 1D 1E 1F Port 4C · · Port 8A Port 4A 1B Port 4F · · · · · · · · · · · 1A Port 8D · · · · · · · · · · X0LA X0D00 ¶ X0D01 ¶ X0D02 ¶ X0D03 ¶ X0D08 ¶ X0D09 ¶ X0D04 ¶ X0D05 ¶ X0D06 ¶ X0D07 ¶ X0D10 ¶ X0D11 ¶ X0D12 ¶ X0D13 ¶ X0D14 ¶ X0D15 ¶ X0D20 ¶ X0D21 ¶ X0D16 ¶ X0D17 ¶ X0D18 ¶ X0D19 ¶ X0D22 ¶ X0D23 ¶ X0D24 ¶ X0D25 ¶ X0D26 ¶ X0D27 ¶ X0D32 ¶ X0D33 ¶ X0D28 ¶ X0D29 ¶ X0D30 ¶ X0D31 ¶ X0D34 ¶ X0D35 ¶ X0D36 ¶ X0D37 ¶ X0D38 ¶ X0D39 ¶ X0D40 ¶ X0D41 ¶ X0D42 ¶ X0D43 ¶ X0LB 4 7 PLL JTAG TDI TDO TCK TMS TRST_N DEBUG_N OTP_VPP VDD VDDIO GND Document Number: 1100C XS1-G02B-FB144 Datasheet 5 8 Product Overview The XMOS XS1-G02B-FB144 is a powerful device that provides a simple design process and highly-flexible solution to many applications. The device consists of two XCores, each comprising an event-driven processor with tightly integrated I/O and on-chip memory. The processors run mutiple tasks simultaneously using hardware threads, each of which is guaranteed a slice of processing power and can execute computational code, control software and I/O interfaces. Threads use channels to exchange data within a core or across cores. The cores are connected via an integrated switch network, which uses a proprietary physical layer protocol, and which can also be used to add additional resources to a design. The I/O pins are driven using intelligent ports that can serialize data, interpret strobe signals and wait for scheduled times or events, making the device ideal for real-time control applications. The device can be configured using a set of software components that are rapidly customized and composed. XMOS provides source code libraries for many standard components. The device can be programmed using high-level languages such as C/C++ and the XMOS-originated XC language. XC provides extensions to C that simplify the control over concurrency, I/O and time. The XMOS toolchain includes compilers, a simulator, debugger and static timing analyzer. The combination of real-time software, a compiler and timing analyzer enables the programmer to close timings on components of the design without a detailed understanding of the hardware characteristics. 5.1 Threads, Synchronizers and Locks Each XCore has up to eight active threads, which issue instructions down a shared four-stage pipeline. Instructions from the active threads are issued round-robin. If up to four threads are active, each thread is allocated a quarter of the processing cycles. If more than four threads are active, each thread is allocated at least 1/n cycles (for n threads). Figure 1 shows the guaranteed thread performance depending on the number of threads used. Figure 1: Thread performance Speed Grade 400 MHz Minimum MIPS per thread (for n threads) 1 2 3 4 5 6 7 8 100 100 100 100 80 67 57 50 There is no way that the performance of a thread can be reduced below these predicted levels. Because threads may be delayed on I/O, however, their unused processor cycles can be taken by other threads. This means that for more than four threads, the performance of each thread is often higher than the predicted minimum. Document Number: 1100C XS1-G02B-FB144 Datasheet 5.2 9 Channel Ends, Links and Switch Threads communicate using point-to-point connections formed between two channel ends. Between cores, channel communications are implemented over XMOS Links and routed through switches. The links operate in either 2bit/direction or 5bit/direction mode, depending on the amount of bandwidth required. Circuit switched, streaming and packet switched data can both be supported efficiently. Streams provide the fastest possible data rates between XCores (up to 250 MBit/s), but each stream requires a single link to be reserved between switches on two cores. All packet communications can be multiplexed onto a single link. A total of eight 5bit links are available between both cores. Information on the supported routing topologies that can be used to connect multiple devices together can be found in the XS1-G Link Performance and Design Guides, document number X2215. 5.3 Ports and Clock Blocks Ports provide an interface between the threads and I/O pins. The operation of each port is synchronized to a clock block. A clock block can be connected to an external clock input, or it can be run from the divided reference clock. A clock block can also output its signal to a pin. On reset, each port is connected to clock block 0, which runs from the reference clock. The ports and links are multiplexed, allowing the pins to be configured for use by ports of different widths or links. If an XMOS Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their specified width, even if they share pins with another port. 5.4 Timers Timers are 32-bit counters that are relative to the reference clock. A timer is defined to tick every 10 ns. This value is derived from the reference clock, which is configured to tick at 100 MHz by default. 5.5 SRAM Each XCore integrates a single 64 KB SRAM bank for both instructions and data. All internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one core clock cycle. There is no dedicated external memory interface, although data memory can be expanded through appropriate use of the ports. Document Number: 1100C XS1-G02B-FB144 Datasheet 5.6 10 OTP Each XCore integrates 8 KB one-time programmable (OTP) memory along with a security register that configures system wide security features. The OTP holds data in 2k rows x 32-bit configuration which can be used to implement secure bootloaders and store encryption keys. Data for the security register is loaded from the OTP on power up. 5.6.1 Security Register The security register enables the following security features: • Secure Boot: The XCore is forced to boot from address 0 of the OTP, allowing the XCore boot ROM to be bypassed (see §5.8). This feature can be used to implement a secure bootloader which loads an encrypted image from external flash, decrypts and CRC checks it with the processor, and discontinues the boot process if the decryption or CRC check fails. XMOS provides a default secure bootloader that can be written to the OTP along with secret decryption keys. • Disable JTAG: The JTAG interface is disabled, making it impossible for the processor state or memory content to be accessed via the JTAG interface. • Disable Link access: Other processors are forbidden access to the processor state via the system switch. Disabling both JTAG and Link access transforms a core into a “secure island” with other cores free for non-secure user application code. • Disable Global Debug access: Disables access to the SS_DEBUG pin. • OTP Master and Sector Lock: Further access to the OTP is prevented by setting the master lock. Locks can also be applied to each of the four OTP sectors individually. These security features provide a strong level of protection and are sufficient for providing strong IP security. 5.7 PLL The PLL is used to generate all on-chip clocks. SS_CLK is the reference clock input. It should be supplied with a clock with monotonic rising edges and should be stable before SS_RESET is taken high. Many standard clock frequencies can be used with appropriate settings configured into the PLL. At boot time, before the PLL can be reconfigured, the PLL multiplier is set using the pins specified in the table in Figure 2. The PLL increases the clock frequency to the core frequency used to run the processor data path and the switch. Document Number: 1100C XS1-G02B-FB144 Datasheet Figure 2: PLL boot modes 11 SS_PLL_BYPASS PLL Multiplier SS_CLK Input (MHz) Boot Frequency (MHz) 0 20 12.5–20 250–400 1 0.5