SIT2024BELS3-XXN-16.000000E 数据手册
SiT2024B
Automotive AEC-Q100 SOT23 Oscillator
Features
Applications
AEC-Q100 with extended temperature range (-55°C to 125°C)
Frequencies between 1 MHz and 110 MHz accurate to
6 decimal places
Supply voltage of 1.8V or 2.25V to 3.63V
Excellent total frequency stability as low as ±20 ppm
Industry best G-sensitivity of 0.1 PPB/G
Low power consumption of 3.8 mA typical at 1.8V
LVCMOS/LVTTL compatible output
5-pin SOT23-5 package: 2.9 x 2.8 mm x mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
Automotive, extreme temperature and other high-rel
electronics
Infotainment systems, collision detection devices, and
in-vehicle networking
Powertrain control
Electrical Characteristics
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Range
Output Frequency Range
f
1
–
110
MHz
Refer to Tables 14 to 16 for a list of supported frequencies
Frequency Stability and Aging
Frequency Stability
F_stab
-20
–
+20
ppm
-25
–
+25
ppm
-30
–
+30
ppm
-50
–
+50
ppm
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Operating Temperature Range
Operating Temperature
Range (ambient)
T_use
-40
–
+85
°C
-40
–
+105
°C
AEC-Q100 Grade 2
-40
–
+125
°C
AEC-Q100 Grade 1
–
+125
°C
Extended cold, AEC-Q100 Grade1
-55
AEC-Q100 Grade 3
Supply Voltage and Current Consumption
Supply Voltage
Current Consumption
Vdd
Idd
1.62
1.8
1.98
V
2.25
–
3.63
V
All voltages between 2.25V and 3.63V including 2.5V, 2.8V,
3.0V and 3.3V are supported.
–
4.0
4.8
mA
No load condition, f = 20 MHz, Vdd = 2.25V to 3.63V
–
3.8
4.5
mA
No load condition, f = 20 MHz, Vdd = 1.8V
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
DC
45
–
55
%
Tr, Tf
–
1.5
3
ns
All Vdds
Vdd = 2.25V - 3.63V, 20% - 80%
–
1.3
2.5
ns
Vdd = 1.8V, 20% - 80%
Output High Voltage
VOH
90%
–
–
Vdd
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Output Low Voltage
VOL
–
–
10%
Vdd
Input High Voltage
VIH
70%
–
–
Vdd
Input Low Voltage
VIL
–
–
30%
Vdd
Pin 1, OE
Input Pull-up Impedance
Z_in
–
100
–
kΩ
Pin 1, OE logic high or logic low
T_start
–
–
5.5
ms
Measured from the time Vdd reaches its rated minimum value
Enable/Disable Time
T_oe
–
–
130
ns
f = 110 MHz. For other frequencies, T_oe = 100 ns + 3 * cycles
Standby Current
I_std
–
2.6
–
µA
Vdd = 2.8V to 3.3V, ST = Low, Output is weakly pulled down
–
1.4
–
µA
Vdd = 2.5V, ST = Low, Output is weakly pulled down
–
0.6
–
µA
Vdd = 1.8V, ST = Low, Output is weakly pulled down
Input Characteristics
Pin 1, OE
Startup and Resume Timing
Startup Time
Rev 1.8
May 22, 2019
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SiT2024B Automotive AEC-Q100 SOT23 Oscillator
Table 1. Electrical Characteristics (continued)
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
RMS Period Jitter
T_jitt
RMS Phase Jitter (random)
T_phj
–
1.6
2.5
ps
f = 75 MHz, 2.25V to 3.63V
–
1.9
3.0
ps
f = 75 MHz, 1.8V
–
0.5
–
ps
f = 75 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
–
1.3
–
ps
f = 75 MHz, Integration bandwidth = 12 kHz to 20 MHz
Table 2. Pin Description
Symbol
1
GND
2
NC
Top View
Functionality
Power
No Connect
Output Enable
3
OE/NC
No Connect
Electrical ground
GND
1
NC
2
OE/NC
3
YXXXX
Pin
No connect
H[1]: specified frequency output
L: output is high impedance. Only output driver is disabled.
Any voltage between 0 and Vdd or Open[1]: Specified
frequency output. Pin 3 has no function.
5
OUT
4
VDD
[2]
4
VDD
Power
Power supply voltage
5
OUT
Output
Oscillator output
Figure 1. Pin Assignments
Notes:
1. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If pin 3 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance
of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Min.
Max.
Unit
Storage Temperature
Parameter
-65
150
°C
Vdd
-0.5
4
V
Electrostatic Discharge
–
2000
V
Soldering Temperature (follow standard Pb free soldering guidelines)
–
260
°C
Junction Temperature[3]
–
150
°C
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration[4]
Package
SOT23-5
θJA, 4 Layer Board
θJC, Bottom
(°C/W)
(°C/W)
421
175
Note:
4. Refer to JESD51 for θJA and θJC definitions, and reference layout used to determine the θJA and θJC values in the above table.
Table 5. Maximum Operating Junction Temperature[5]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
85°C
95°C
105°C
115°C
125°C
135°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Condition/Test Method
Mechanical Shock
MIL-STD-883F, Method 2002
Mechanical Vibration
MIL-STD-883F, Method 2007
Temperature Cycle
JESD22, Method A104
Solderability
MIL-STD-883F, Method 2003
Moisture Sensitivity Level
MSL1 @ 260°C
Rev 1.8
Page 2 of 15
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SiT2024B Automotive AEC-Q100 SOT23 Oscillator
Test Circuit and Waveform
Vout
Test
Point
Vdd
tr
15 pF
(including probe
and fixture
capacitance)
80% Vdd
4
5
1
2
tf
0.1µF
3
50%
Power
Supply
20% Vdd
High Pulse
(TH)
Period
Vdd
1k
Low Pulse
(TL)
OE/ST Function
Figure 3. Waveform[6]
[6]
Figure 2. Test Circuit
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
T_oe
T_start
Pin 4 Voltage
OE Voltage
No Glitch
during start up
CLK Output
CLK Output
HZ
HZ
T_start: Time to start from power-off
T_oe: Time to re-enable the clock output
Figure 4. Startup Timing (OE Mode)[7]
Figure 5. OE Enable Timing (OE Mode Only)
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
T_oe: Time to put the output in High Z mode
Figure 6. OE Disable Timing (OE Mode Only)
Note:
7. SiT2024 has “no runt” pulses and “no glitch” output during startup or resume.
Rev 1.8
Page 3 of 15
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SiT2024B Automotive AEC-Q100 SOT23 Oscillator
Performance Plots[8]
1.8 V
2.5 V
2.8 V
3V
3.3 V
6.0
DUT1
DUT2
DUT3
DUT4
DUT5
DUT6
DUT7
DUT8
DUT9
DUT10
DUT11
DUT12
DUT13
DUT14
DUT15
DUT16
DUT17
DUT18
DUT19
DUT20
25
5.5
20
Frequency (ppm)
Idd (mA)
5.0
4.5
4.0
3.5
15
10
5
0
-5
-10
-15
-20
3.0
0
20
40
60
80
100
-25
-55
Frequency (MHz)
2.8 V
5
25
45
65
85
105
125
3.0 V
Figure 8. Frequency vs Temperature
3.3 V
1.8 V
4.0
55
3.5
54
2.5 V
2.8 V
3.0 V
3.3 V
53
3.0
Duty cycle (%)
RMS period jitter (ps)
2.5 V
-15
Temperature (°C)
Figure 7. Idd vs Frequency
1.8 V
-35
2.5
2.0
1.5
1.0
52
51
50
49
48
47
0.5
46
0.0
0
20
40
60
80
45
100
0
20
40
Frequency (MHz)
Figure 9. RMS Period Jitter vs Frequency
2.5 V
2.8 V
3.0 V
1.8 V
3.3 V
2.5
2.5
2.0
2.0
1.5
1.0
100
2.5 V
2.8 V
3.0 V
3.3 V
1.5
1.0
0.5
0.5
0.0
0.0
-40
-20
0
20
40
60
80
100
-40
120
Figure 11. 20%-80% Rise Time vs Temperature
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Rev 1.8
80
Figure 10. Duty Cycle vs Frequency
Fall time (ns)
Rise time (ns)
1.8 V
60
Frequency (MHz)
Figure 12. 20%-80% Fall Time vs Temperature
Page 4 of 15
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SiT2024B Automotive AEC-Q100 SOT23 Oscillator
Performance Plots[8]
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
1.8 V
2.5 V
3.0 V
2.8 V
3.3 V
1.0
2.0
1.9
0.9
1.8
0.8
1.6
IPJ (ps)
IPJ (ps)
1.7
1.5
1.4
1.3
0.7
0.6
0.5
1.2
0.4
1.1
1.0
10
20
30
40
50
60
70
80
90
100
110
0.3
10
Frequency (MHz)
Figure 13. RMS Integrated Phase Jitter Random
(12 kHz to 20 MHz) vs Frequency[9]
20
30
40
50
60
70
80
90
100
110
Frequency (MHz)
Figure 14. RMS Integrated Phase Jitter Random
(900 kHz to 20 MHz) vs Frequency[9]
Notes:
8. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
9. Phase noise plots are measured with Agilent E5052B signal source analyzer. Integration range is up to 5 MHz for carrier frequencies below 40 MHz.
Rev 1.8
Page 5 of 15
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SiT2024B Automotive AEC-Q100 SOT23 Oscillator
Programmable Drive Strength
The SiT2024 includes a programmable drive strength
feature to provide a simple, flexible tool to optimize the
clock rise/fall time for specific applications. Benefits from
the programmable drive strength feature are:
Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time.
Improves the downstream clock receiver’s (RX) jitter by
decreasing (speeding up) the clock rise/fall time.
Ability to drive large capacitive loads while maintaining
full swing with sharp edge rates.
For more detailed information about rise/fall time control
and drive strength selection, see the SiTime Application
Notes section.
The SiT2024 can support up to 60 pF in maximum
capacitive loads with drive strength settings. Refer to the
Rise/Tall Time Tables (Table 7 to 11) to determine the proper
drive strength for the desired combination of output load vs.
rise/fall time.
SiT2024 Drive Strength Selection
Tables 7 through 11 define the rise/fall time for a given
capacitive load and supply voltage.
1. Select the table that matches the SiT2024 nominal
supply voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).
2.
Select the capacitive load column that matches the
application requirement (5 pF to 60 pF)
3.
Under the capacitive load column, select the desired
rise/fall times.
4.
The left-most column represents the part number
code for the corresponding drive strength.
5.
Add the drive strength code to the part number for
ordering purposes.
EMI Reduction by Slowing Rise/Fall Time
Figure 15 shows the harmonic power reduction as the
rise/fall times are increased (slowed down). The rise/fall
times are expressed as a ratio of the clock period. For the
ratio of 0.05, the signal is very close to a square wave. For
the ratio of 0.45, the rise/fall times are very close to neartriangular waveform. These results, for example, show that
the 11th clock harmonic can be reduced by 35 dB if the
rise/fall edge is increased from 5% of the period to 45% of
the period.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 7
through 11, the maximum frequency the oscillator can
operate with guaranteed full swing of the output voltage over
temperature can be calculated as:
Max Frequency =
1
5 x Trf_20/80
where Trf_20/80 is the typical value for 20%-80% rise/fall
time.
Example 1
Calculate fMAX for the following condition:
Figure 15. Harmonic EMI reduction as a Function
of Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to
speed up the rise/fall time of the input clock. Some
chipsets may also require faster rise/fall time in order to
reduce their sensitivity to this type of jitter. Refer to the
Rise/Fall Time Tables (Table 7 to Table 11) to determine
the proper drive strength.
Vdd = 3.3V (Table 11)
Capacitive Load: 30 pF
Desired Tr/f time = 1.31 ns
(rise/fall time part number code = F)
Part number for the above example:
SiT2024BAES2-18E-66.666660
Drive strength code is inserted here. Default setting is “-”
High Output Load Capability
The rise/fall time of the input clock varies as a function of
the actual capacitive load the clock drives. At any given
drive strength, the rise/fall time becomes slower as the
output load increases. As an example, for a 3.3V SiT2024
device with default drive strength setting, the typical
rise/fall time is 1 ns for 15 pF output load. The typical
rise/fall time slows down to 2.6 ns when the output load
increases to 45 pF. One can choose to speed up the
rise/fall time to 1.83 ns by then increasing the drive
strength setting on the SiT2024.
Rev 1.8
Page 6 of 15
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SiT2024B Automotive AEC-Q100 SOT23 Oscillator
Rise/Fall Time (20% to 80%) vs CLOAD Tables
Table 7. Vdd = 1.8V Rise/Fall Times for Specific CLOAD
Table 8. Vdd = 2.5V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
L
A
R
B
T
E
U
F or "‐": default
5 pF
6.16
3.19
2.11
1.65
0.93
0.78
0.70
0.65
15 pF
11.61
6.35
4.31
3.23
1.91
1.66
1.48
1.30
30 pF
22.00
11.00
7.65
5.79
3.32
2.94
2.64
2.40
Rise/Fall Time Typ (ns)
45 pF
31.27
16.01
10.77
8.18
4.66
4.09
3.68
3.35
60 pF
39.91
21.52
14.47
11.08
6.48
5.74
5.09
4.56
Table 9. Vdd = 2.8V Rise/Fall Times for Specific CLOAD
Drive Strength \ CLOAD
L
A
R
B
T
E or "‐": default
U
F
5 pF
4.13
2.11
1.45
1.09
0.62
15 pF
8.25
4.27
2.81
2.20
1.28
30 pF
12.82
7.64
5.16
3.88
2.27
45 pF
21.45
11.20
7.65
5.86
3.51
60 pF
27.79
14.49
9.88
7.57
4.45
0.54
0.43
0.34
1.00
0.96
0.88
2.01
1.81
1.64
3.10
2.79
2.54
4.01
3.65
3.32
Table 10. Vdd = 3.0V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
L
A
R
B
T
5 pF
3.77
1.94
1.29
0.97
0.55
15 pF
7.54
3.90
2.57
2.00
1.12
30 pF
12.28
7.03
4.72
3.54
2.08
45 pF
19.57
10.24
7.01
5.43
3.22
60 pF
25.27
13.34
9.06
6.93
4.08
E or "‐": default
U
F
0.44
0.34
0.29
1.00
0.88
0.81
1.83
1.64
1.48
2.82
2.52
2.29
3.67
3.30
2.99
Drive Strength \ CLOAD
L
A
R
B
T or "‐": default
E
U
F
5 pF
3.60
1.84
1.22
0.89
0.51
0.38
0.30
0.27
15 pF
7.21
3.71
2.46
1.92
1.00
0.92
0.83
0.76
30 pF
11.97
6.72
4.54
3.39
1.97
1.72
1.55
1.39
45 pF
18.74
9.86
6.76
5.20
3.07
2.71
2.40
2.16
60 pF
24.30
12.68
8.62
6.64
3.90
3.51
3.13
2.85
Table 11. Vdd = 3.3V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
L
A
R
B
5 pF
3.39
1.74
1.16
0.81
15 pF
6.88
3.50
2.33
1.82
30 pF
11.63
6.38
4.29
3.22
45 pF
17.56
8.98
6.04
4.52
60 pF
23.59
12.19
8.34
6.33
T or "‐": default
E
U
F
0.46
0.33
0.28
0.25
1.00
0.87
0.79
0.72
1.86
1.64
1.46
1.31
2.60
2.30
2.05
1.83
3.84
3.35
2.93
2.61
Rev 1.8
Page 7 of 15
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SiT2024B Automotive AEC-Q100 SOT23 Oscillator
In addition, the SiT2024 supports “no runt” pulses and
“no glitch” output during startup or when the output driver
is re-enabled from the OE disable mode as shown in the
waveform captures in Figure 16 and Figure 17.
Pin 3 Configuration Options (OE or NC)
Pin 3 of the SiT2024 can be factory-programmed to
support three modes: Output Enable (OE) or
No Connect (NC).
Output Enable (OE) Mode
In the OE mode, applying logic low to the OE pin only
disables the output driver and puts it in Hi-Z mode. The
core of the device continues to operate normally. Power
consumption is reduced due to the inactivity of the
output. When the OE pin is pulled High, the output is
typically enabled in