W83793G / W83793AG
Nuvoton H/W Monitor
DATE: DECEMBER 12, 2008
REVISION: 1.4
W83793G / W83793AG
Table of Content1.
2.
3.
4.
5.
6.
7.
8.
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES ................................................................................................................................. 2
2.1
Monitoring Items ............................................................................................................. 2
2.2
Address Resolution Protocol and Alert Standard Format............................................... 2
2.3
Actions Enabling ............................................................................................................. 2
2.4
General ........................................................................................................................... 2
2.5
Package .......................................................................................................................... 3
KEY SPECIFICATIONS .............................................................................................................. 4
BLOCK DIAGRAM ...................................................................................................................... 5
PIN CONFIGURATION ............................................................................................................... 7
PIN DESCRIPTION..................................................................................................................... 9
6.1
Pin Type Description....................................................................................................... 9
6.2
Pin Description List ......................................................................................................... 9
FUNCTIONAL DESCRIPTION ................................................................................................. 15
CONFIGURATION REGISTERS .............................................................................................. 16
8.1
ID, Bank Select Registers ............................................................................................. 16
8.1.1
8.1.2
8.2
Watch Dog Timer Registers.......................................................................................... 21
8.2.1
8.2.2
8.3
Temperature Sensors Control Register Map ........................................................... 55
Temperature Sensors Control Register Details ....................................................... 56
Voltage Channel Registers ........................................................................................... 59
8.9.1
8.9.2
8.10
Multi-Function Pin Control Register Map ................................................................. 50
Multi-Function Pin Control Register Details ............................................................. 51
Temperature Sensors Control Register ........................................................................ 54
8.8.1
8.8.2
8.9
OVT/BEEP Control Registers Map .......................................................................... 45
OVT/BEEP Control Registers Details ...................................................................... 46
Multi-Function Pin Control Register .............................................................................. 49
8.7.1
8.7.2
8.8
INT/SMI Control/Status Register Map ..................................................................... 37
INT/SMI Control/Status Register Details ................................................................. 38
OVT/BEEP Control Register ......................................................................................... 43
8.6.1
8.6.2
8.7
VID Control/Status Registers Map .......................................................................... 30
VID Register Details ................................................................................................ 31
INT/SMI# Control/Status Registers .............................................................................. 36
8.5.1
8.5.2
8.6
Register Maps ......................................................................................................... 26
Register Details ....................................................................................................... 27
VID Control/Status Registers ........................................................................................ 29
8.4.1
8.4.2
8.5
Watch Dog Timer Registers Map ............................................................................ 22
Watch Dog Timer Register Details .......................................................................... 23
Configuration and Address Select Registers ................................................................ 25
8.3.1
8.3.2
8.4
ID, Bank Select Registers Map ............................................................................... 17
ID, Bank Select Register Details ............................................................................. 18
Voltage Channel Registers Map .............................................................................. 60
Voltage Channel Register Details ........................................................................... 62
Temperature Channel Registers .................................................................................. 64
8.10.1
8.10.2
Temperature Channel Register Map ....................................................................... 65
Temperature Channel Register Details ................................................................... 67
- I –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.11
Fan Control Registers ................................................................................................... 68
8.11.1
8.11.2
8.12
PECI Control Registers................................................................................................. 96
8.12.1
8.12.2
8.13
14.
ASF Register Map ................................................................................................. 105
ASF Register Details ............................................................................................. 111
SPECIFICATIONS .................................................................................................................. 127
9.1
Absolute Maximum Ratings ........................................................................................ 127
9.2
DC Characteristics ...................................................................................................... 127
9.3
AC Characteristics ...................................................................................................... 130
9.3.1
9.3.2
9.3.3
10.
11.
12.
13.
PECI Register Map.................................................................................................. 97
PECI Register Details.............................................................................................. 99
ASF Control Registers ................................................................................................ 104
8.13.1
8.13.2
9.
Fan Register Map .................................................................................................... 69
Fan Register Details ................................................................................................ 73
Access Interface .................................................................................................... 131
Dynamic Vcore Limit Setting ................................................................................. 132
Power on Reset ..................................................................................................... 133
ORDERING INFORMATION .................................................................................................. 134
TOP MARKING SPECIFICATION .......................................................................................... 135
PACKAGE DRAWING AND DIMENSIONS ............................................................................ 137
APPENDIX .............................................................................................................................. 138
13.1 Register Summary ...................................................................................................... 138
REVISION HISTORY .............................................................................................................. 148
- II –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
1. GENERAL DESCRIPTION
The W83793G is an evolving version of the W83792D. Besides the conventional functions of the
W83792D, the W83793G uniquely provides several innovative features. It is ASF 2.0 specification
compliant, SMBus 2.0 ARP command compatible and has 8 sets of SMART FANTM. The W83793G can
monitor several critical hardware parameters of the system, including power supply voltages, fan
speeds, and temperatures, which are very important for a high-end computer system, such as a server,
or a workstation to work stably and efficiently.
A 10-bit analog-to-digital converter (ADC) is built inside the W83793G. The W83793G can
simultaneously monitor 10 analog voltage inputs (including power 5VDD/5VSB/VBAT/Vtt monitoring),
12 fan tachometer inputs, 6 remote temperatures, 4 of which support Current Mode (dual current
source) temperature measurement method, and the Watch Dog Timer function. The remote
temperature can be sensed by thermistors, or directly from Intel® / AMDTM CPU with thermal diode
output. The W83793G provides 8 PWM (pulse width modulation) / DC fan output modes for smart fan
control – “Thermal CruiseTM” mode and “SMART FANTM II” mode. In “Thermal CruiseTM” mode,
temperatures of CPU and the system can be maintained within specific programmable ranges under
the hardware control. The W83793G, as SMART FANTM II, provides 8 temperature sets, each of which
can control the fan’s duty cycle. With this design, the fan can work at the lowest possible speed to avoid
acoustic noise. As for the warning mechanism, the W83793G provides SMI#, OVT#, IRQ, and BEEP
signals for system protection events. The W83793G also has 2 specific pins to provide selectable
address settings for the applications of multiple devices (up to 4 devices) wired through the I2C
interface.
The W83793G can serve as an ASF sensor to respond to ASF master’s request for the implementation
of network management in OS-absent status. With the W83793G’s compliance with ASF2.0 sensor
specification, the network server is able to monitor the system status of each client in OS-absent state
by PET (Platform Event Trap) frame values returned from the W83793G, such as temperatures,
voltages, fan speed and case open. Moreover, the W83793G supports SMBus 2.0 ARP command to
solve the address conflict problems by dynamically assigning a new address for ASF Function after
UDID is sent.
Through the application software or BIOS, users can read all the monitored parameters of the system
from time to time. A pop-up warning can also be activated when the monitored item is out of the
proper/preset range. The application software could be Nuvoton's Hardware DoctorTM or other
management application software. Besides, users can set the bounds (alarm thresholds) of these
monitored parameters and activate corresponding maskable interrupts.
There is a feature reduced version of the W83793G available, W83793AG, which supports almost the
same functions as those of W83793G, but removes 3 sets of thermal diode inputs (TD2 ~ TD4, Pin 31
~ Pin 36), VcoreB input, and VIDB. The package of the W83793AG is the same as that of W83793G,
which is 56-pin SSOP.
- 1 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
2. FEATURES
2.1
Monitoring Items
VOLTAGE
Monitoring 10 voltages (4 power pins – 5VSB, 5VDD, VBAT, Vtt, and 6 external pins – VcoreA,
VcoreB, VSEN1~4). (W83793AG does not support Vcore B.)
TEMPERATURE
4 thermal diode (D+, D-) inputs, supporting Current Mode (dual current source) temperature
measurement method. (W83793AG supports 1 thermal diode input only; TD2 ~ TD4 are removed
in the W83793AG.)
2 thermistor inputs
Support Intel® PECI
FAN
8 DC/PWM fan outputs for fan speed control
8 fan speed inputs for monitoring (up to 12 by register setups)
SMART FANTM -- controls the most fitting speed automatically by temperature.
CASEOPEN
CASEOPEN# detection input.
2.2
Address Resolution Protocol and Alert Standard Format
Support System Management Bus (SMBus) version 2.0 specification
Comply with hardware sensor slave ARP (Address Resolution Protocol)
Response ASF 2.0 command --- GetEventData, GetEventStatus, DeviceTypePoll
Comply with ASF 2.0 sensors (Monitoring fan speed, voltage, temperature, thermal trip and case
open event/status)
Support Remote Control subset: Remote Power on/ Power off/ Reset.
2.3
Actions Enabling
Issue SMI#, OVT# signals to activate system protection
Issue BEEP signal to activate system speaker or buzzer
2.4
General
I 2 C serial bus interface
PP
PP
Watch Dog Timer function with pin WDTRST# and SYSRST_IN.
- 2 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
2 pins (A0, A1) to provide selectable address settings for the application of multiple devices (up to 4
devices) wired together through the I 2 C interface
PP
PP
5V operation
2.5
Package
56 Pin SSOP 300mil. (For both W83793G and W83793AG)
- 3 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
3. KEY SPECIFICATIONS
Voltage monitoring accuracy
z
Temperature Sensor Accuracy
±1%
Remote Diode Sensor Accuracy
± 1°C
Resolution
0.5 ℃
Supply Voltage (Pin 7, 5VSB)
5±0.25V
z
Operating Supply Current
25 mA typ.
Current without 48MHz input at Pin 1
8 mA typ.
ADC Resolution
10 Bits
z
- 4 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
4. BLOCK DIAGRAM
W83793G
PWRBTN#
IRQ/SMI#
Beep/Alert
Generator
ADDR [0:1]
Control Circuit
& Value Ram
ASF Command
Decoder
SMBus
Interface
OVT#/BEEP
D+[1:4]
D-[1:4]
Amplify
Circuit
SCL
SMBus & ARP
Control
Current
Dispatcher
Channel
Mux
10-bits
Delta_sigma
ADC
THR [1:2]
SDA
Vtt
Intel PECI Interface
Fan Control
VCORE [1:2]
VSEN [1:4]
VREF
Band Gap
Reference
Watch Dog
Timer
VID Control
Caseopen
Detection
PECI
FANIN [1:12]
FANCTRL [1:8]
Caseopen
W83793G
VIDA 7:0 VIDB 7:0
SYSRSTIN#
WDTRST#
VIDBSEL
W83793AG
- 5 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PWRBTN#
IRQ/SMI#
Beep/Alert
Generator
ADDR [0:1]
Control Circuit
& Value Ram
ASF Command
Decoder
SMBus
Interface
OVT#/BEEP
D+1
D-1
Amplify
Circuit
SCL
SMBus & ARP
Control
Current
Dispatcher
Channel
Mux
10-bits
Delta_sigma
ADC
THR [1:2]
SDA
Vtt
Intel PECI Interface
Fan Control
VCORE
VSEN [1:4]
VREF
Band Gap
Reference
Watch Dog
Timer
VID Control
Caseopen
Detection
PECI
FANIN [1:12]
FANCTRL [1:8]
Caseopen
W83793AG
SYSRSTIN#
WDTRST#
VIDA 7:0
- 6 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
5. PIN CONFIGURATION
W83793G (56 SSOP)
CLK
OVT#/BEEP
IRQ/SMI#
SCL
SDA
PWRBTN#
5VSB
CASEOPEN#
VBAT
VIDA4/FANIN8
VIDA5/FANCTL8
VIDA6
VIDA7
WDTRST#
SYSRSTIN#
GND
PECI
VTT
VSEN1
VSEN2
VSEN4
VSEN3
VCOREA
VCOREB
5VDD
VREF
THR1
THR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VIDB7/FANCTL8
VIDB6/FANIN8
VIDB5/FANCTL7
VIDB4/FANIN7
VIDB3/FANCTL6
VIDB2/FANIN6
VIDB1/FANCTL5
VIDB0/FANCTL4
FANIN5
FANIN4
FANCTL3/VIDBSEL
FANIN3
FANCTL2/ADDR1
FANIN2
FANCTL1/ADDR0
FANIN1
VIDA3/FANIN12
VIDA2/FANIN11
VIDA1/FANIN10
VIDA0/FANIN9
4_D4_D+
3_D3_D+
2_D2_D+
1_D1_D+
- 7 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
W83793AG (56 SSOP)
CLK
OVT#/BEEP
IRQ/SMI#
SCL
SDA
PWRBTN#
5VSB
CASEOPEN#
VBAT
VIDA4/FANIN8
VIDA5/FANCTL8
VIDA6
VIDA7
WDTRST#
SYSRSTIN#
GND
PECI
VTT
VSEN1
VSEN2
VSEN4
VSEN3
VCOREA
NC
5VDD
VREF
THR1
THR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FANCTL8
FANIN8
FANCTL7
FANIN7
FANCTL6
FANIN6
FANCTL5
FANCTL4
FANIN5
FANIN4
FANCTL3
FANIN3
FANCTL2/ADDR1
FANIN2
FANCTL1/ADDR0
FANIN1
VIDA3/FANIN12
VIDA2/FANIN11
VIDA1/FANIN10
VIDA0/FANIN9
NC
NC
NC
NC
NC
NC
1_D1_D+
- 8 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
6. PIN DESCRIPTION
6.1
Pin Type Description
SYMBOL
DESCRIPTION
t
TTL level
v1
Vil/Vih=0.4/0.6 level
v2
Vil/Vih=0.8/1.4 level
v3
Vtt level
s
Schmitt trigger
12
12mA sink/source capability
OUT
Output pin
OD
Open-drain output pin
AOUT
Output pin (Analog)
IN
Input pin (digital)
AIN
Input pin(Analog)
6.2
Pin Description List
PIN NAME
CLK
PIN NO.
1
POWER
PLANE
5VSB
TYPE
IN ts
OVT#
BEEP
DESCRIPTION
48MHz System clock while 5VDD is
powered up. PECI and the fan will use this
clock to drive logics.
Over temperature alert. Low active.
2
5VSB
IRQ
3
OD 12
OUT 12
Interrupt request output when abnormal
events occur.
OD 12
System
drain).
5VSB
SMI#
BEEP output when any abnormal event
occurs. If there is no abnormal event, this
pin asserts low.
Management
Interrupt
SCL
4
5VSB
IN ts
Serial Bus Clock.
SDA
5
5VSB
IN/OD 12ts
Serial Bus bi-directional data.
(open
- 9 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PIN NAME
PWRBTN#
5VSB
PIN NO.
6
7
POWER
PLANE
5VSB
-
DESCRIPTION
OD 12
Power Button output signal to enable/
disable the power supply. This pin is
related to ASF commands.
POWER
This pin is the power source for the
W83793G. Bypass with the parallel
combination of 10μF (electrolytic or
tantalum) and 0.1μF (ceramic) bypass
capacitors.
IN ts
CASE OPEN detection. An active low
input from an external device when case
is opened. This signal will be latched even
when the case is closed.
CASEOPEN#
8
VBAT
9
POWER
VBAT supplies power for CASEOPEN#. It
is also a voltage monitor channel.
10
IN v1s or
IN v2s
Voltage Supply readouts bit 4 from CPU
A. (Default)
FANIN8
IN ts
0V to +5V amplitude fan tachometer input
VIDA5
IN v1s or
IN v2s
Voltage Supply readouts bit 5 from CPU
A. (Default)
OUT /
OD 12a
FAN control output. The 8th fan control
signal can be programmed to output
through pin 56 or this pin. When this pin is
programmed to be fan control signal, it
only supports the PWM mode.
IN ts
0V to +5V amplitude fan tachometer input
VIDA4
FANCTL8
11
VBAT
TYPE
5VSB
5VSB
FANIN12
VIDA6
12
5VSB
IN v1s or
IN v2s
Voltage Supply readouts bit 6 from CPU
A.
VIDA7
13
5VSB
IN v1s or
IN v2s
Voltage Supply readouts bit 7 from CPU
A. (Default)
WDTRST#
14
5VSB
OD 12
Low active system reset. If triggered, this
pin will send out 100ms low pulse for
system reset.
SYSRSTIN#
15
5VSB
IN ts
System reset input, used to control WDT.
GND
16
POWER
System Ground.
PECI
17
IN/O V3
Intel® CPU PECI interface
VTT
18
POWER
Intel® CPU Vtt power
5VSB
- 10 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PIN NAME
PIN NO.
POWER
PLANE
TYPE
DESCRIPTION
VSEN1
19
AIN
Voltage sensor input. The detection range
is 0~4.096V
VSEN2
20
AIN
Voltage sensor input. The detection range
is 0~4.096V
VSEN4
21
AIN
Voltage sensor input. The detection range
is 0~2.048V.
VSEN3
22
AIN
Voltage sensor input. The detection range
is 0~4.096V.
VCOREA
23
AIN
CPU A core voltage input. The detection
range is 0~2.048V
VCOREB*
24
AIN
CPU B Core Voltage Input. The detection
range is 0~2.048V.
POWER
+5V VDD power. Bypass with the parallel
combination of 10μF (electrolytic or
tantalum) and 0.1μF (ceramic) bypass
capacitors.
-
5VDD
25
-
VREF
26
AOUT
Reference voltage output.
THR1
27
AIN
Thermistor 1 terminal input.
THR2
28
AIN
Thermistor 2 terminal input.
1_D+
29
AIN
Thermal diode 1 D+.
1_D-
30
AIN
Thermal diode 1 D-.
2_D+*
31
AIN
Thermal diode 2 D+.
2_D-*
32
AIN
Thermal diode 2 D-.
3_D+*
33
AIN
Thermal diode 3 D+.
3_D-*
34
AIN
Thermal diode 3 D-.
4_D+*
35
AIN
Thermal diode 4 D+.
4_D-*
36
AIN
Thermal diode 4 D-.
VIDA0
37
IN v1s or
IN v2s
Voltage Supply readouts bit 0 from CPU
A. (Default)
5VSB
- 11 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PIN NAME
PIN NO.
POWER
PLANE
TYPE
DESCRIPTION
FANIN9
IN ts
0V to +5V amplitude fan tachometer input
VIDA1
IN v1s or
IN v2s
Voltage Supply readouts bit 1 from CPU
A. (Default)
FANIN10
IN ts
0V to +5V amplitude fan tachometer input
VIDA2
IN v1s
Voltage Supply readouts bit 2 from CPU
A. (Default)
FANIN11
IN ts
0V to +5V amplitude fan tachometer input
VIDA3
IN v1s
Voltage Supply readouts bit 3 from CPU
A. (Default)
IN ts
0V to +5V amplitude fan tachometer input
IN ts
0V to +5V amplitude fan tachometer input
OUT
OD 12
AOUT
Fan speed control PWM/DC output. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
38
39
40
5VSB
5VSB
5VSB
FANIN12
FANIN1
41
5VSB
FANCTL1
42
5VSB
ADDR0
FANIN2
43
5VSB
FANCTL2
44
FANCTL3
45
46
IN ts
I2C device address bit 0 trapping during
5VSB power on.
IN ts
0V to +5V amplitude fan tachometer input
OUT / OD 12
/ AOUT
Fan speed control PWM/DC output. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
IN ts
I2C device address bit 1 trapping during
5VSB power on.
IN ts
0V to +5V amplitude fan tachometer input
OUT / OD 12
/ AOUT
Fan speed control PWM/DC output. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
5VSB
ADDR1
FANIN3
/
/
5VSB
5VSB
- 12 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PIN NAME
PIN NO.
POWER
PLANE
VIDBSEL**
TYPE
DESCRIPTION
IN ts
The pin straps the fan mode and VID
mode during 5VSB power on. When
strapped to high, it will select VID mode.
When strapped to low, it will select Fan
mode for pin49~56.
FANIN4
47
5VSB
IN ts
0V to +5V amplitude fan tachometer input
FANIN5
48
5VSB
IN ts
0V to +5V amplitude fan tachometer input
OUT / OD 12
/ AOUT
Fan speed control PWM/DC output. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
IN v1s or
IN v2s
Voltage Supply readouts bit 0 from CPU
B.
OUT / OD 12
/ AOUT
Fan speed control PWM/DC output. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
VIDB1*
IN v1s or
IN v2s
Voltage Supply readouts bit 1 from CPU
B.
FANIN9
INts
0V to +5V amplitude fan tachometer input
FANIN6
INts
0V to +5V amplitude fan tachometer input
IN v1s or
IN v2s
Voltage Supply readouts bit 2 from CPU
B.
OUT / OD 12
/ AOUT
Fan speed control PWM/DC output. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
FANIN10
INts
0V to +5V amplitude fan tachometer input
VIDB3*
IN v1s
IN v2s
FANCTL4
49
5VSB
VIDB0*
FANCTL5
50
51
5VSB
5VSB
VIDB2*
FANCTL6
52
FANIN7
53
5VSB
5VSB
or
INts
Voltage Supply readouts bit 3 from CPU
B.
0V to +5V amplitude fan tachometer input
- 13 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PIN NAME
PIN NO.
POWER
PLANE
TYPE
IN v1s
IN v2s
VIDB4*
DESCRIPTION
or
Voltage Supply readouts bit 4 from CPU
B.
OUT / OD 12
/ AOUT
Fan speed control PWM/DC output. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
FANIN11
INts
0V to +5V amplitude fan tachometer input
VIDB5*
IN v1s
IN v2s
FANIN8
IN ts
0V to +5V amplitude fan tachometer input
IN v1s or
IN v2s
Voltage Supply readouts bit 6 from CPU
B.
OUT / OD 12
/ AOUT
Fan speed control PWM/DC output. The
8th fan control signal can be programmed
to output through pin 11 or this pin. When
the power of 5VDD is 0V, this pin will drive
logic 0. The power of this pin is supplied
by 5VSB.
As DC output, 64 steps output voltage
scaled from 0 to 5VSB.
IN v1s or
IN v2s
Voltage Supply readouts bit 7 from CPU
B.
FANCTL7
54
55
5VSB
5VSB
VIDB6*
FANCTL8
56
VIDB7*
5VSB
or
Voltage Supply readouts bit 5 from CPU
B.
Pins with * are for the W83793G only, not for the W83793AG.
Pins with ** are for the W83793G only. Please always strap low to select FANIN or FANCTL for the
W83793AG.
- 14 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
7. FUNCTIONAL DESCRIPTION
This section is blank now. Refer to Chap 8 for function description.
- 15 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8. CONFIGURATION REGISTERS
8.1
ID, Bank Select Registers
Inside the W83793G resides three banks of registers. Customers must set the banks correctly to
access correct registers. All the registers described here can be accessed in all banks.
- 16 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.1.1 ID, Bank Select Registers Map
Address 00 HEX , 0D HEX , 0E HEX , 0F HEX in all three register banks are reserved as ID and Bank Select
registers.
Mnemonic
Register Name
Type
BankSel.
Bank Select
RW
VendorID.
Nuvoton Vendor ID
RO
ChipID.
Nuvoton Chip ID
RO
DeviceID.
Nuvoton Device Version ID
RO
- 17 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.1.2
ID, Bank Select Register Details
8.1.2.1. Bank Select Register (Bank Select)
Three banks of registers are inside the W83793G. The register bank could be selected by
programming the Bank Select register. All 00 HEX Addresses in these three banks are defined as Bank
Select register.
Location:
Type:
Reset:
Bank 0, 1, 2 Address 00 HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
BANKSELECT
BIT
7
NAME
RESET
6
5
4
3
2
1
0
HBACS
Reserve
BANK Select
1
0 HEX
0 HEX
BIT
DESCRIPTION
7
HBACS (High Byte Access)
0: Return the low byte while reading Nuvoton Vendor ID.
1: Return the high byte while reading Nuvoton Vendor ID.
6-3
Reserved.
2-0
BANK Select.
000BIN: Bank 0 is selected.
001BIN: Bank 1 is selected.
010BIN: Bank 2 is selected.
8.1.2.2. Nuvoton Vendor ID Register (Vender ID)
The Nuvoton Vendor ID contains two-byte data. By programming register HBACS, the customer can
choose to access either the high or the low byte of Nuvoton Vendor ID.
Location: Bank 0, 1, 2 Address 0D HEX
Type:
Read Only
Reset:
No Reset
VENDORID (NUVOTON VENDOR ID)
BIT
NAME
7
6
5
4
3
2
1
0
VendorID
- 18 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
FIXED
5C HEX / A3 HEX
BIT
7-0
DESCRIPTION
VendorID.
Return 5C HEX if HBACS = 1; return A3 HEX if HBACS = 0.
8.1.2.3.
Nuvoton Chip ID Register (ChipID)
Location: Bank 0, 1, 2 Address 0E HEX
Type:
Read Only
Reset:
No Reset
CHIPID (NUVOTON CHIP ID)
BIT
7
6
5
NAME
RESET
BIT
7-0
4
3
2
1
0
ChipID
7B HEX
DESCRIPTION
ChipID.
Chip ID of W83793G is 7BH EX
- 19 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.1.2.4.
Nuvoton Version ID Register (Device ID)
Location: Bank 0, 1, 2 Address 0F HEX
Type:
Read Only
Reset:
No Reset
VERSION ID
BIT
7
NAME
FIXED
BIT
7-0
6
5
4
3
2
1
0
DeviceID
11 HEX /12 HEX
DESCRIPTION
Version ID.
Device ID of the W83793G. 11 HEX for B Version, and 12 HEX for C Version.
- 20 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.2
Watch Dog Timer Registers
The W83793G is integrated with a Watch Dog Timer, which enables users to reset the system by Pin
14 while the system is in an abnormal state. Once Watch Dog Timer is enabled, the W83793G starts to
count down, and the host should set the timer for further count down or clear/disable the timer to
prevent the W83793G from issuing reset signals.
- 21 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.2.1 Watch Dog Timer Registers Map
Watch Dog Timer consists of four registers. WDTLock and ENABLE_WDT are used to activate
Soft-WDT and Hard-WDT, respectively. WDT_STS and DownCounter can inform the host whether the
system time is up or not.
Mnemonic
Register Name
Type
WDTLock.
Lock Watch Dog
WO
EnableWDT.
Watch Dog Enable
RO
WDT_STS.
Watch Dog Status
R/W
DownCounter.
Watch Dog Timer
R/W
Two kinds of watchdog timer functions
are supported by the W83793G. One is
so-called Soft Watch Dog Timer, and
the other is Hard Watch Dog Timer.
Hard Watch Dog timer, if enabled, will start a 4-minute WDT after the system reset is completed. (A
low-to-high transition on SYSRSTIN# pin). BIOS needs to write a 00 HEX into Watch Dog Timer Register
(04 HEX ) to disable the timer within 4 minutes. Otherwise, Pin 14 WDTRST# will assert to reset the
system.
Soft Watch Dog Timer will start counting down whenever Timeout Time is set and Soft Watch Dog
Timer is enabled. WDTRST# will be issued when the time runs out.
Soft Watch Dog Timer will be disabled automatically after receiving a SYSRSTIN_N low signal.
Bank0, CR40 [2]/ENWDT must be set to 1 if wish to program the four Watch Dog Timer Registers.
- 22 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.2.2
Watch Dog Timer Register Details
8.2.2.1. Lock Watch Dog Register (WDT Lock)
Writing this register enables the Soft or Hard Watch Dog Timer. This register type is write only and
ENABLE_WDT confirms whether the write is successful.
Location:
Type:
Reset:
Bank 0 Address 01 HEX
Write Only
VSB5V (Pin 7) Rising,
SYSRSTIN_N (Pin 15) Falling in Soft WDT mode.
WDTLOCK (WATCH DOG TIMER LOCK)
Bit
7
6
5
4
Name
3
2
1
0
UNLOCK CODE
Bit
Description
7-0
Unlock Code.
Write 55 HEX , Enables Soft Watch Dog Timer.
Write AA HEX , Disables Soft Watch Dog Timer.
Write 33 HEX , Enables Hard Watch Dog Timer.
Write CC HEX , Disables Hard Watch Dog Timer.
8.2.2.2.
Watch Dog Enable Register (Enable WDT)
Location:
Type:
Reset:
Bank 0 Address 02 HEX
Read Only
VSB5V (Pin 7) Rising.
ENABLE WDT (WATCH DOG TIMER ENABLE STATUS)
Bit
7
6
5
Name
Reset
4
3
2
Reserve
0
0
0
Bit
Description
7-2
Reserved
1
HARD.
1: Hard Watch Dog is enabled.
0: Hard Watch Dog is disabled.
0
SOFT.
1: Soft Watch Dog is enabled.
0: Soft Watch Dog is disabled.
0
1
HARD
0
0
0
0
SOFT
0
- 23 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.2.2.3.
Watch Dog Status Register
Location: Bank 0 Address 03 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising.
WDT_STS (WATCH DOG STATUS)
Bit
7
6
Name
5
4
3
Reserve
Reset
0
0
2
WDT STAGE
0
0
0
1
0
HARD_TO
SOFT_TO
0
0
0
Bit
Description
7-4
Reserved
3-2
WDT Stage.
These 2 bits record last WDT stage for BIOS readout. The information is used to help
BIOS to identify WDT timeout issuance.
1
HARD_TO.
1: A hard timeout occurs. This bit will be cleared after reading.
0
SOFT_TO.
1: A soft timeout occurs. This bit will be cleared after reading.
8.2.2.4.
Watch Dog Timer Register (Down Counter)
Location:
Type:
Reset:
Bank 0 Address 04 HEX
Read / Write
VSB5V (Pin 7) Rising.
DOWN COUNTER (WATCH DOG TIMER)
Bit
7
Name
6
5
4
3
2
1
0
Timeout Time
Reset
00 HEX
Bit
Description
7-0
Timeout Time.
To write 00 HEX can disable the timer while in Hard Watch Dog Timer mode.
To set Timeout Time for SOFT Watch Dog Timer, the unit is minute.
Timeout Time is unit in minutes. 0 represents time is up or the timer is cleared. 1 represents there is still
1 second to 1 minute time for this timer. Similarly, 2 means there is still 1 minute 1 second to 2 minutes
left.
- 24 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.3
Configuration and Address Select Registers
- 25 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.3.1
Register Maps
Mnemonic
I2CADDR
TEMPD1/2ADDR
Register Name
Type
I2C Address
R/W
LM75 Temperature Sensor
I2C Address
R/W
8.3.1.1. I2C Address Registers
Map
There are four Addresses (58 HEX , 5A HEX , 5C HEX , 5E HEX ) that can be assigned for the I2C interface. Four
I2C Addresses for each LM75-like Temperature Sensor (90 HEX , 92 HEX , 94 HEX , 96 HEX for TD1 and 98 HEX ,
9A HEX , 9C HEX , 9E HEX for TD2) are also provided. These four addresses can be set by strapping pin 42
& 44 input value at 100ms after power ready.
The registers for Temperature sensor D1 & D2 can also be accessed by respective addresses that are
set as I2C address of the W83793G. The default of this LM75-like function is enabled and can be
disabled by setting bit 3 and bit 7 of TEMPD1/2ADDR to 1.
8.3.1.2.
Configuration Register Maps
Mnemonic
CONFIG
Register Name
Type
Configuration Register
R/W
Configuration Register controls the
system reset source, stop, power down
and warning output mode.
- 26 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.3.2
Register Details
I2C Address Register (I2CADDR)
8.3.2.1.
Location:
Type:
Reset:
Bank 0 Address 0B HEX
Read Only
100ms after VSB5V (Pin 7) Rising.
I2CADDR
Bit
7
6
5
4
Name
3
2
1
0
SMBUSADDR
Bit
Description
7-0
SMBUSADDR.
The value of SMBUSADDR is the strapping pin voltage on PADDR0 (pin42) and
PADDR1 (pin44) at 100ms after VSB power ready.
ADDR1
ADDR0
I2C Address
0
0
58 HEX
0
1
5A HEX
1
0
5C HEX
1
1
5E HEX
LM75-like Temperature Sensor I2C Address Register
8.3.2.2.
Location: Bank 0 Address 0C HEX
Type:
Read / Write
Reset:
100ms after VSB5V (Pin 7) Rising.
TEMPD1/2ADDR
Bit
7
Name
DIS_TD2
I2CADDR75B
DIS_TD1
I2CADDR75A
0
Trapped Value
0
Trapped Value
Reset
6
5
4
3
2
1
0
Bit
Description
7
DIS_TD2.
If set to 1, temperature sensor 2 cannot be accessed by temperature sensor 2 I2C
address.
6-4
I2CADDR75B.
The value of I2CADDR75B is obtained by strapping PADDR0 (pin42) and PADDR1
(pin44) at 100ms after valid VSB power is issued.
- 27 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
ADDR1
ADDR0
I2CADDR75B
Temperature sensor 2 I2C Address
0
0
100
98 HEX
0
1
101
9A HEX
1
0
110
9C HEX
1
1
111
9E HEX
3
DIS_TD1.
If set to 1, it cannot access the registers for temperature sensor 1 by temperature
sensor 1 I2C address.
2-0
I2CADDR75A.
The value of I2CADDR75B is obtained by strapping PADDR0 (pin42) and PADDR1
(pin44) at 100ms after valid VSB power is issued.
ADDR1
ADDR0
I2CADDR75A
Temperature sensor 1 I2C Address
0
0
000
90 HEX
0
1
001
92 HEX
1
0
010
94 HEX
1
1
011
96 HEX
8.3.2.3.
Configuration Register
Location: Bank 0 Address 40 HEX
Type:
Read / Write
Reset:
bit 0~3 & 7:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
Bit 4 & 5:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set.
CONFIG
Bit
7
6
5
4
3
2
1
0
Name
INIT
Reserve
SYSRST_MD
RST_VDD_MD
EN_BAT_MNT
EN_WDT
INT_Clear
START
Reset
0
0
0
0
0
0
0
0
Bit
Description
7
INIT.
Setting to one restores power-on default values to all registers, except the Serial Bus
Address register. This bit clears itself since the power-on default is zero.
6
Reserved
- 28 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
5
SYSRST_MD.
Write 1, the whole chip will be reset when the SYSRSTIN# input signal is issued.
Write 0, no operation when the SYSRSTIN# input signal is issued.
4
RST_VDD_MD.
Write 1, the whole chip will be reset when 5VDD is up. Write 0, no operation when
5VDD is up.
3
EN_BAT_MNT.
Write 1; battery voltage monitor is enabled. Write 0; battery voltage monitor is
disabled. If enable this bit, the monitor value is valid after one monitor cycle.
2
EN_WDT.
Setting this bit to 1 will enable the Watch Dog Timer function, which resets the
system (pin 47) while the time is out.
1
INT_Clear.
A one disables the SMI# and IRQ# outputs without affecting the contents of Interrupt
Status Registers. The device will stop monitoring at last channel. It will resume upon
clearing of this bit.
0
START.
1: Enables startup of monitoring operations;
0: Puts the analog part in the Power-down mode.
8.4
VID Control/Status Registers
The W83793G provides dual Vcore monitoring channels. Vcore Channels are automatically monitored
once 5VSB is applied onto the W83793G, but the W83793G will issue alert information only when the
corresponding high/low limits of Vcore channels are being violated. ASF is also based on these limit
registers to judge the current channel status and report to the host.
Two methods are used to assign the Vcore Limits, manually or automatically by VID inputs. The
following register sets allow users to choose their preferred method.
Please be noted that VIDB are for the W83793G only; the W83793AG does not support VIDB.
- 29 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.4.1
VID Control/Status Registers Map
Mnemonic
Register Name
Type
VIDIN_A
VIDA Input Value
RO
VIDIN_B
VIDB Input Value
RO
VIDA_Latch
VIDA Latch Value
RO
VIDB_Latch
VIDB Latch Value
RO
VID_Control
VID Control
R/W
VCORE_LIMHI
Vcore High Tolerance
R/W
VCORE_LIMLO
Vcore Low Tolerance
R/W
The W83793G supplies two sets of VID input pins for VOCREA and VCOREB channels. If dynamic VID
function is enabled, the high/low limit of VCOREA and VCOREB channel will auto-update when the VID
input value changes.
Some VIDA and all VIDB input pins are multi-function pin. Programming Multi-function Pin Control
Registers at Bank0, CR58h properly is required to make these pins function.
- 30 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.4.2
VID Register Details
8.4.2.1.
VIDA Input Value Register (VIDIN_A)
Location: Bank 0 Address 05 HEX
Type:
Read Only
VIDIN_A
Bit
7
6
5
4
3
2
1
0
Name
VIDAIN7
VIDAIN6
VIDAIN5
VIDAIN4
VIDAIN3
VIDAIN2
VIDAIN1
VIDAIN0
Bit
Description
7
VIDAIN7.
Real time pin 13 input value. This is available for VRM11 only.
6
VIDAIN6.
Real time pin 12 input value. This is available for VRM10 and VRM11 only.
5
VIDAIN5.
Real time pin 11 input value. This is available for VRM10, VRM11 and AMD
OpteronTM 6-bit VID only.
4
VIDAIN4.
Real time pin 10 input value.
3
VIDAIN3.
Real time pin 40 input value.
2
VIDAIN2.
Real time pin 39 input value.
1
VIDAIN1.
Real time pin 38 input value.
0
VIDAIN0.
Real time pin 37 input value.
8.4.2.2.
VIDB Input Value Register (VIDIN_B)
Location: Bank 0 Address 06 HEX
Type:
Read Only
VIDIN_B
Bit
7
6
5
4
3
2
1
0
Name
VIDBIN7
VIDBIN6
VIDBIN5
VIDBIN4
VIDBIN3
VIDBIN2
VIDBIN1
VIDBIN0
Bit
Description
- 31 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7
VIDBIN7.
Real time pin 56 input value. This is available for VRM11 only.
6
VIDBIN6.
Real time pin 55 input value. This is available for VRM10 and VRM11 only.
5
VIDBIN5.
Real time pin 54 input value. This is available for VRM10, VRM11 and AMD
OpteronTM 6-bit VID only.
4
VIDBIN4.
Real time pin 53 input value.
3
VIDBIN3.
Real time pin 52 input value.
2
VIDBIN2.
Real time pin 51 input value.
1
VIDBIN1.
Real time pin 50 input value.
0
VIDBIN0.
Real time pin 49 input value.
8.4.2.3. VIDA Latch Value Register (VIDA_Latch)
Previous VIDIN_A and VIDIN_B allow users to read the current value on VID pins, but VIDA_Latch and
VIDB_Latch allow users to keep the VID value at any time by assigning the Latch_VIDA/Latch_VIDB
bits to 1.
Location: Bank 0 Address 07 HEX
Type:
Read Only
VIDA_LATCH
Bit
Name
7
VIDA7
6
VIDA6
5
VIDA5
4
3
VIDA4
2
VIDA3
VIDA2
1
VIDA1
0
VIDA0
Bit
Description
7
VIDA7.
Reading this bit returns VIDA7 register value if Latch_VIDA is set to 1. Otherwise,
the pin value of VIDAIN7 is returned.
6
VIDA6.
Reading this bit returns VIDA6 register value if Latch_VIDA is set to 1. Otherwise,
the pin value of VIDAIN6 is returned.
5
VIDA5.
Reading this bit returns VIDA5 register value if Latch_VIDA is set to 1. Otherwise,
the pin value of VIDAIN5 is returned.
4
VIDA4.
- 32 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
Reading this bit eturns VIDA4 register value if Latch_VIDA is set to 1. Otherwise, the
pin value of VIDAIN4 is returned.
3
VIDA3.
Reading this bit returns VIDA3 register value if Latch_VIDA is set to 1. Otherwise,
the pin value of VIDAIN3 is returned.
2
VIDA2.
Reading this bit returns VIDA2 register value if Latch_VIDA is set to 1. Otherwise,
the pin value of VIDAIN2 is returned.
1
VIDA1.
Reading this bit returns VIDA1 register value if Latch_VIDA is set to 1. Otherwise,
the pin value of VIDAIN1 is returned.
0
VIDA0.
Reading this bit returns VIDA0 register value if Latch_VIDA is set to 1. Otherwise,
the pin value of VIDAIN0 is returned.
8.4.2.4.
VIDB Latch Value Register (VIDB_Latch)
Location: Bank 0 Address 08 HEX
Type:
Read Only
VIDB_LATCH
Bit
Name
7
VIDB7
6
VIDB6
5
VIDB5
4
3
VIDB4
2
VIDB3
VIDB2
1
VIDB1
0
VIDB0
Bit
Description
7
VIDB7.
Reading this bit returns VIDB7 register value if Latch_VIDB is set to 1. Otherwise,
the pin value of VIDBIN7 is returned.
6
VIDB6.
Reading this bit returns VIDB6 register value if Latch_VIDB is set to 1. Otherwise,
the pin value of VIDBIN6 is returned.
5
VIDB5.
Reading this bit returns VIDB5 register value if Latch_VIDB is set to 1. Otherwise,
the pin value of VIDBIN5 is returned.
4
VIDB4.
Reading this bit returns VIDB4 register value if Latch_VIDB is set to 1. Otherwise,
the pin value of VIDBIN4 is returned.
3
VIDB3.
Reading this bit returns VIDB3 register value if Latch_VIDB is set to 1. Otherwise,
the pin value of VIDBIN3 is returned.
2
VIDB2.
Reading this bit returns VIDB2 register value if Latch_VIDB is set to 1. Otherwise,
- 33 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
the pin value of VIDBIN2 is returned.
1
VIDB1.
Reading this bit returns VIDB1 register value if Latch_VIDB is set to 1. Otherwise,
the pin value of VIDBIN1 is returned.
0
VIDB0.
Reading this bit returns VIDB0 register value if Latch_VIDB is set to 1. Otherwise,
the pin value of VIDBIN0 is returned.
8.4.2.5.
VID Control Register (VID_Control)
Location:
Type:
Reset:
Bank 0 Address 59 HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
VID_CONTROL
Bit
Name
Reset
7
6
5
4
3
2
1
Level_Select
EN_DVID
Latch_VIDB
Latch_VIDA
VID_SEL
00 BIN
0
0
0
001 BIN
0
Bit
Description
7-6
Level_Select.
Set VID input pin V IH /V IL level
00 BIN : 0.6V/0.4 for VRM10, 11
01 BIN : 1.6V/0.8V for AMD VID
10 BIN : 2.0V/0.8V
11 BIN :.Reserved.
5
EN_DVID.
Writing 1 enables the dynamic VID function. If VID is changed, the high/low limit of
corresponding Vcore sensing voltage will be auto-updated.
If manually programming High/Low limit of Vcore sensing voltage is required, this bit
has to be cleared as 0.
4
Latch_VIDB.
If write 1, CR08 latches the current pin value of VIDB.
3
Latch_VIDA.
If write 1, CR07 latches the current pin value of VIDA.
2-0
VID_SEL.
Selectable VID tables:
000 BIN : Reserved
- 34 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
001 BIN : VRM10 (default)
010 BIN : VRM11
011 BIN : AMD OpteronTM 5 bit VID Codes
100 BIN : AMD OpteronTM 6 bit VID Codes
8.4.2.6.
Vcore High Tolerance Register (VCORE_LIMHI)
Location:
Type:
Reset:
Bank 0 Address 09 HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
VCORE_LIMHI
Bit
7
6
5
Name
4
3
2
1
0
Vcore High Tolerance
Reset
64 HEX
Bit
Description
7-0
Vcore High Tolerance.
If the dynamic VID function (set Bank0 CR59 bit5 to 1) is enabled, writing Tolerance
register will force VCORE Limit to update with new voltage limits for VCORE.
The unit is 2mV
8.4.2.7.
Vcore Low Tolerance Register (VCORE_LIMLO)
Location:
Type:
Reset:
Bank 0 Address 0A HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
VCORE_LIMLO
Bit
Name
Reset
7
6
5
4
3
2
1
0
Vcore Low Tolerance
64 HEX
- 35 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7-0
Vcore Low Tolerance.
If the dynamic VID function (set Bank0 CR59 bit5 to 1) is enabled, writing Tolerance
register will force VCORE Limit Generator to generate new voltage limits for VCORE.
The unit is 2mV
8.5
INT/SMI# Control/Status Registers
Several mechanisms are provided to alarm the system when monitored channels are abnormal. In this
paragraph, three kinds of control/status registers are introduced. “Real time status” shows the current
status of each channel; “Channel Mask” defines which channel needs to issue warning when abnormal
operation occurs, and when the warning should be ignored due to floating or in other circumstances.
The final one is “Interrupt Status,” which gives the host information of which channel is issuing alert,
and the host can base on this channel and do proper process to ensure a reliable system.
- 36 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.5.1
INT/SMI Control/Status Register Map
Mnemonic
Register Name
INT_STS1
Interrupt Status 1
INT_STS5
Interrupt Status 5
MASK1
SMI/IRQ Mask 1
MASK5
SMI/IRQ Mask 5
REAL_STS1
Real Time status 1
REAL_STS5
Real Time status 5
SMIINT_Ctrl
SMI/IRQ Control
Type
RO
R/W
RO
R/W
Pin 3 of the W83793G is a multi-function pin. It can be the IRQ output or the SMI# output signal. The
function is selected by programming Bank0 CR50 SMI/IRQ Control register.
The interrupt mode for voltage and FANIN is only two-time interrupt mode.
For temperature, there are three modes to serve: Comparator mode, One-Time Interrupt mode,
and Two-Time Interrupt mode.
- 37 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.5.2
INT/SMI Control/Status Register Details
8.5.2.1. Interrupt Status Register (INT_STS)
A one represents corresponding channel have been exceed its limit. Read Interrupt Status will clear the
interrupt flag.
VIDCHG will assert if VID has a change during last 1ms.
TART will assert while target temperature cannot be achieved after 3 minutes full speed of
corresponding FAN.
Location:
- 38 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
INT_STS1 - Bank 0 Address 41 HEX
INT_STS2 - Bank 0 Address 42 HEX
INT_STS3 - Bank 0 Address 43 HEX
Type:
Reset:
INT_STS4 - Bank 0 Address 44 HEX
INT_STS5 - Bank 0 Address 45 HEX
Read Only
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
INT_STS1
Bit
7
Name
VSEN4
VSEN3
VSEN2
VSEN1
Reserve
0
0
0
0
0
Reset
6
5
4
3
2
1
0
VTT
VCOREB
VCOREA
0
0
0
INT_STS2
Bit
7
Name
Reset
6
5
4
3
2
1
0
TD4
TD3
TD2
TD1
VIDCHG
VBAT
5VSB
5VDD
0
0
0
0
0
0
0
0
INT_STS3
Bit
7
6
5
4
3
2
Name
FANIN6
FANIN5
FANIN4
FANIN3
FANIN2
FANIN1
TR2
TR1
0
0
0
0
0
0
0
0
Reset
1
0
INT_STS4
Bit
7
6
5
4
3
2
1
0
Name
Reserve
Chassis
FANIN12
FANIN11
FANIN10
FANIN9
FANIN8
FANIN7
0
0
0
0
0
0
0
0
Reset
INT_STS5
Bit
7
6
Name
Reset
5
Reserve
0
0
4
3
2
1
0
TART6
TART5
TART4
TART3
TART2
TART1
0
0
0
0
0
0
- 39 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.5.2.2. SMI/IRM Mask Register (MASK)
Setting to one will disable the corresponding interrupt sources. Clearing to 0 will enable that
source.
interrupt
SMI Mask4 bit 7 is CLR_CHS (Clear Chassis), writing this bit to one will clear the internal caseopen latch.
After the latch is cleared, CLR_CHS will self-reset to 0.
Location:
MASK1 - Bank 0 Address 46 HEX
MASK4 - Bank 0 Address 49 HEX
MASK2 - Bank 0 Address 47 HEX
MASK5 - Bank 0 Address 4A HEX
MASK3 - Bank 0 Address 48 HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
Type:
Reset:
MASK1
Bit
7
6
5
4
3
Name
VSEN4
VSEN3
VSEN2
VSEN1
Reserve
0
0
0
0
0
Reset
2
1
0
VTT
VCOREB
VCOREA
0
0
0
MASK2
Bit
7
Name
Reset
6
5
4
3
2
1
0
TD4
TD3
TD2
TD1
VIDCHG
VBAT
5VSB
5VDD
0
0
0
0
0
0
0
0
MASK3
Bit
7
6
5
4
3
2
Name
FANIN6
FANIN5
FANIN4
FANIN3
FANIN2
FANIN1
TR2
TR1
0
0
0
0
0
0
0
0
Reset
1
0
MASK4
Bit
7
6
5
4
3
2
1
0
Name
CLR_CHS
Chassis
FANIN12
FANIN11
FANIN10
FANIN9
FANIN8
FANIN7
0
0
0
0
0
0
0
0
Reset
- 40 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
MASK5
Bit
7
6
Name
5
Reserve
Reset
0
4
3
2
1
0
TART6
TART5
TART4
TART3
TART2
TART1
0
0
0
0
0
0
0
8.5.2.3. Real Time status Register (REAL_STS)
Real-time status registers show whether the values of related channels exceed the limit or not at the
polling moment. The returning of 1 indicates the limit of related channel defined in limit registers has been
exceeded.
Location:
REAL_STS1 - Bank 0 Address 4B HEX
REAL_STS4 - Bank 0 Address 4E HEX
REAL_STS2 - Bank 0 Address 4C HEX
REAL_STS5 - Bank 0 Address 4F HEX
REAL_STS3 - Bank 0 Address 4D HEX
Type:
Read Only
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
REAL_STS1
Bit
7
Name
VSEN4
VSEN3
VSEN2
VSEN1
Reserve
0
0
0
0
0
Reset
6
5
4
3
2
1
0
VTT
VCOREB
VCOREA
0
0
0
REAL_STS2
Bit
7
Name
Reset
6
5
4
3
2
1
0
TD4
TD3
TD2
TD1
VIDCHG
VBAT
5VSB
5VDD
0
0
0
0
0
0
0
0
REAL_STS3
Bit
7
6
5
4
3
2
Name
FANIN6
FANIN5
FANIN4
FANIN3
FANIN2
FANIN1
TR2
TR1
0
0
0
0
0
0
0
0
Reset
1
0
REAL_STS4
- 41 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
7
6
5
4
3
2
1
0
Name
Reserve
Chassis
FANIN12
FANIN11
FANIN10
FANIN9
FANIN8
FANIN7
0
0
0
0
0
0
0
0
Reset
REAL_STS5
Bit
7
6
Name
5
Reserve
Reset
0
8.5.2.4.
4
3
2
1
0
TART6
TART5
TART4
TART3
TART2
TART1
0
0
0
0
0
0
0
SMI/IRQ Control Register (SMIINT_Ctrl)
Location:
Type:
Reset:
Bank 0 Address 50 HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
SMIINT_CTRL
Bit
7
6
Name
Reset
Reserve
0
0
5
4
3
IRQ_MD
IRQSEL
0
1
2
1
TEMP_SMI_MD
0
0
0
EN_IRQSMI
POL
0
0
Bit
Description
7-6
Reserved.
5
IRQ_MD.
If set to 0, the bit outputs IRQ output level signal. If set to 1, the bit outputs 200 us
pulse signal. The default value is 0.
4
IRQ_SEL.
Set Pin 3 to the IRQ mode. While this bit is set to 1 and EN_IRQSMI is set to 1, Pin 3
is enabled with IRQ interrupt output.
3-2
TEMP_SMI_MD.
Temperature SMI# Mode Select.
00 BIN : Comparator Interrupt Mode:(Default)
Temperature TD1/TD2/TD3/TD4/TR1/TR2 exceeding T O (Critical temperature)
limit causes an interrupt and this interrupt will be cleared by reading all the Interrupt
Status.
01 BIN : Two Time Interrupt Mode:
- 42 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
Temperature sensors TD1/TD2/TD3/TD4/TR1/TR2 are used in the interrupt mode
with hysteresis. Temperature exceeding T O (Critical Temperature) causes an interrupt.
Temperatures that fall below T HYST (Critical Temperature Hysteresis) will also cause an
interrupt if the previous interrupt has been reset by reading all the interrupt Status
Register. Once the temperature exceeds T O (Critical Temperature), an interrupt will be
issued and the bit will be reset before the temperature falls to T HYST (Critical
Temperature Hysteresis).
10 BIN : One Time Interrupt Mode:
Temperature sensors TD1/TD2/TD3/TD4/TR1/TR2 are used in the interrupt mode
with hysteresis. Temperature exceeding T O (Critical Temperature) causes an interrupt
and then temperature going below T HYST (Critical Temperature Hysteresis) will not
cause an interrupt. Once an interrupt event has occurred by exceeding T O (Critical
Temperature), then going below T HYST (Critical Temperature Hysteresis), and interrupt
will not occur again until the temperature exceeding T O (Critical Temperature).
11 BIN : Two Time Non-related Interrupt Mode:
Temperature sensors TD1/TD2/TD3/TD4/TR1/TR2 are used in the interrupt mode
with hysteresis. Temperature exceeding T O , causes an interrupt and then temperature
going below T HYST will also cause an interrupt. Once an interrupt event has occurred by
exceeding T O , then reset, if the temperature remains above the T HYST .
If this mode is selected, for all monitor channels (it is not necessary to read the
status for generating the next IRQ/SMI# pulse.
Tcritical
Tcrit-hysteresis
Twarning
Twarning-hysteresis
SMI#
**
**
**
**
Two-Time Intrrupt Mode
** : Interrupt Status is read
Note: It can be programmed to be as not necessary to
read the status for generating the next SMI# pulse by
setting TEMP_SMI_MD = 2'b11.
1
EN_IRQSMI.
A one enables the IRQ/SMI# Interrupt output.
0
POL. (polarity)
When set to 1, IRQ/SMI# active high. Set to 0, IRQ/SMI# active low.
8.6
OVT/BEEP Control Register
Another solution to deal with abnormal situation is through OVT (Over Temperature) or Beep.
- 43 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
OVT, as the name suggests, represents abnormal temperatures. In some applications, it can work with
Fan control to throttle the Fan Speed.
Beep can directly use sound of two tones to inform the user of abnormal system operation. Unlike OVT,
Beep can be issued due to abnormal operations of any channel.
- 44 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.6.1
OVT/BEEP Control Registers Map
Mnemonic
Register Name
Type
OVT_Ctrl
OVT Control
R/W
OVT_BeepEn
OVT/Beep Global Enable
R/W
BEEP_Ctrl1
BEEP Control 1
BEEP_Ctrl5
BEEP Control 5
R/W
Pin 2 of the W83793G is also a multi-function pin. It can be OVT# output signal or BEEP output signal
and be selected by programming Bank0 CR52 OVT/BEEP Control register.
- 45 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.6.2
OVT/BEEP Control Registers Details
8.6.2.1.
OVT Control Register (OVT_Ctrl)
Location:
Type:
Reset:
Bank 0 Address 51 HEX
Read / Write
VSB5V (Pin 7) Rising.
OVT_CTRL
Bit
7
6
5
4
3
2
1
0
Name
OVT_M
D
EN_OV
TR2
EN_OV
TR1
EN_OV
TD4
EN_OV
TD3
EN_OV
TD2
EN_OV
TD1
OVTPO
L
0
0
0
0
0
0
0
0
Reset
Bit
Description
7
OVT_MD.
There are two OVT# signal output types.
0 BIN : Comparator Mode: (Default)
Temperature exceeding Tcritical (Critical Temperature) activates the OVT# output
until the temperature is lower than T HYST (Critical Temperature Hysteresis).
1 BIN : Interrupt Mode:
Temperatures exceeding Tcritical (Critical Temperature) will activate the OVT#
output until temperature sensor TD1/TD2/TD3/TD4/TR1/TR2 registers are read.
If the current temperature rises from T HYST (Critical Temperature Hysteresis) and
exceeds Tcritical (Critical Temperature), the OVT# pin will be de-asserted. If the
temperature falls below T HYST , the OVT# pin will also generates an interrupt until it is
reset by reading temperature sensor TD1/TD2/TD3/TD4/TR1/TR2 (interrupt status).
Once the interrupt is generated, the OVT# pin does not issue additional interrupts even
it the temperature remains above Tcritical.
6
EN_OVTR2.
Enable the over-temperature (OVT) of temperature sensor TR2 if set to 1. The
default value is 0; the OVTR2 output is disabled through pin OVT#. Pin OVT# is wire
OR with OVTD1, OVTD2, OVTD3, OVTD4 and OVTR1.
5
EN_OVTR1.
Enable temperature sensor TR1 over-temperature (OVT) output if set to 1. The
default value is 0; the OVTR1 output is disabled through pin OVT#. Pin OVT# is wire
OR with OVTD1, OVTD2, OVTD3, OVTD4 and OVTR2.
4
EN_OVTD4.
Enable temperature sensor TD4 over-temperature (OVT) output if set to 1. The
default value is 0; the OVTD4 output is disabled through pin OVT#. Pin OVT# is wire
OR with OVTD1, OVTD2, OVTD3, OVTR1 and OVTR2
3
EN_OVTD3.
Enable temperature sensor TD3 over-temperature (OVT) output if set to 1. The
default value is 0; the OVTD3 output is disabled through pin OVT#. Pin OVT# is wire
- 46 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
OR with OVTD1, OVTD2, OVTD4, OVTR1 and OVTR2
2
EN_OVTD2.
Enable temperature sensor TD2 over-temperature (OVT) output if set to 1. The
default value is 0; the OVTD2 output is disabled through pin OVT#. Pin OVT# is wire
OR with OVTD1, OVTD3, OVTD4, OVTR1 and OVTR2
1
EN_OVTD1.
Enable temperature sensor TD1 over-temperature (OVT) output if set to 1. The
default value is 0; the OVTD1 output is disabled through pin OVT#. Pin OVT# is wire
OR with OVTD2, OVTD3, OVTD4, OVTR1 and OVTR2
0
OVTPOL.
Write 1, pin OVT# is active high. Write 0, pin OVT# is active low.
8.6.2.2.
OVT/Beep Global Enable Register (OVT_BeepEn)
Location:
Type:
Reset:
Bank 0 Address 52 HEX
Read / Write
VSB5V(Pin 7) Rising.
OVT_BEEPEN
Bit
7
6
5
Name
Reset
4
3
Reserved
0
0
0
0
0
2
1
0
BEEPS
EL
EN_BE
EP
EN_OV
T
0
0
0
Bit
Description
7-3
Reserved.
2
BEEPSEL.
1: Direct Beep signal to Pin 2.
0: Direct OVT signal to Pin 2.
1
EN_BEEP. (Beep Output Global Enable)
1: Beep is enabled. Users can select event trigger source from BEEP_Ctrl.
0: Beep is disabled.
0
ENOVT. (OVT Output Global Enable)
1: OVT is enabled. Users can select OVT trigger source from OVT_Ctrl.
0: OVT is disabled.
8.6.2.3. BEEP Control Register (BEEP_Ctrl)
Setting to one will enable the corresponding BEEP output. Clearing to 0 will disable that BEEP output.
- 47 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Location:
BEEP_Ctrl1 - Bank 0 Address 53 HEX
BEEP_Ctrl4 - Bank 0 Address 56 HEX
BEEP_Ctrl2 - Bank 0 Address 54 HEX
BEEP_Ctrl5 - Bank 0 Address 57 HEX
BEEP_Ctrl3 - Bank 0 Address 55 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
BEEP_CTRL1
Bit
Name
7
6
5
4
3
2
1
0
VSEN4
VSEN3
VSEN2
VSEN1
Reserve
VTT
VCOREB
VCOREA
0
0
0
0
0
0
0
0
Reset
BEEP_CTRL2
Bit
7
Name
Reset
6
5
4
3
2
1
0
TD4
TD3
TD2
TD1
RESERVE
VBAT
5VSB
5VDD
0
0
0
0
0
0
0
0
BEEP_CTRL3
Bit
7
6
5
4
3
2
Name
FANIN6
FANIN5
FANIN4
FANIN3
FANIN2
FANIN1
TR2
TR1
0
0
0
0
0
0
0
0
Reset
1
0
BEEP_CTRL4
Bit
7
6
5
4
3
2
1
0
Name
Reserve
Chassis
FANIN12
FANIN11
FANIN10
FANIN9
FANIN8
FANIN7
0
0
0
0
0
0
0
0
Reset
BEEP_CTRL5
Bit
Name
7
6
Reserve
5
TART6
4
3
TART5
TART4
2
TART3
1
TART2
0
TART1
- 48 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset
8.7
0
0
0
0
0
0
0
0
Multi-Function Pin Control Register
Many functions exhibited in the W83793G are not default functions, and might share pin out with other
functions. Here lists three registers that define the function enable registers.
- 49 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.7.1
Multi-Function Pin Control Register Map
Mnemonic
Register Name
Type
MFC
Multi-Function Pin Control
R/W
FANIN_Ctrl
FANIN Control
R/W
FAN_SEL
FANIN Input Pin Redirection
R/W
In the W83793G, Pin 10~13, Pin 37~40, and Pin 49~56 are multi-function pins. All non-default
functions are enabled by setting Bank0 CR58, CR5C and CR5D.
- 50 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.7.2
Multi-Function Pin Control Register Details
8.7.2.1.
Multi-Function Pin Control Register (MFC)
Location:
Type:
Reset:
Bank 0 Address 58 HEX
Read / Write
bit 0~6:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
Bit7: Trapping at 100ms after VSB5V (Pin 7) Rising.
MFC
Bit
7
6
Name
VIDBSEL
SIB_SEL
Trap
0
Reset
5
4
3
2
SID_SEL
0
SIC_SEL
0
0
0
1
0
SIA_SEL
FAN8SEL
0
0
Bit
Description
7
VIDBSEL.
Pin 49~56 function select. Power-on Strapping input value of Pin 46.
1 BIN : Pin 49~56 are VIDB.
0 BIN : Pin 49~54 are fan speed control output or fan tachometer input; the functions
of Pin 55~56 are controlled by bit SIB_SEL.
6
SIB_SEL.
While VIDBSEL is 0, SIB_SEL sets the functions of Pin 55~56:
0 BIN: Pin 55~56 are FANIN8/FANCTRL8.
1 BIN : Reserved.
This bit must be set to 0.
5-4
SID_SEL.
Set the functions of Pin39~40:
0X BIN : Pin 39~40 are VIDA2/VIDA3.
10 BIN : Pin 39~40 are FANIN1/FANIN12.
11 BIN : Reserved.
These two bits should not be set to 11 BIN .
3-2
SIC_SEL.
Set the functions of Pin37~38:
0x BIN : Pin 37~38 are VIDA0/VIDA1.
10 BIN : Pin 37~38 are FAIN9/FANI10.
11 BIN : Reserved.
These two bits should not be set to 11 BIN .
- 51 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
1
SIA_SEL.
Set the functions of Pin12~13:
0 BIN : Pin 12~13 are VIDA6/VIDA7.
1 BIN : Reserved.
This bit must be set to 0.
0
FAN8SEL.
Set the functions of Pin10~11:
0 BIN : Pin 10~11 are VIDA4/VIDA5.
1 BIN : Pin 12~13 are FANIN8/FANCTRL8.
8.7.2.2. FANIN Control Register (FANIN_Ctrl)
The register enables the setup of the multi-function fan inputs. With any reset, the register is
cleared. (00 HEX )
Location:
Type:
Reset:
Bank 0 Address 5C HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANIN_CTRL
Bit
7
6
5
4
3
2
1
0
Name
Reserve
EN_FAN
IN12
EN_FAN
IN11
EN_FAN
IN10
EN_FAN
IN9
EN_FAN
IN8
EN_FAN
IN7
EN_FAN
IN6
0
0
0
0
0
0
0
0
Reset
Bit
Description
7
Reserved.
6
EN_FANIN12.(Fan In 12 Enable Bit)
1: If SID_SEL = 10 BIN , enable FANIN12 monitor.
0: Disable. The default is VID function.
5
EN_FANIN11.(Fan In 11 Enable Bit)
If SID_SEL = 10, setting to 1 will enable FANIN11 monitor.
If cleared, Pin39 can be selected as Processor A VID Bit 2(EN_D-VID).
4
EN_FANIN10.(Fan In 10 Enable Bit)
If SIC_SEL = 10, setting to 1 will enable FANIN10 monitor.
If cleared, Pin 38 can be selected as Processor A VID Bit 1.
3
EN_FANIN9.(Fan In 9 Enable Bit)
- 52 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
If SIC_SEL = 10, setting to 1 will enable FANIN9 monitor.
If cleared, Pin 37 can be selected as Processor A VID Bit 0(EN_D-VID).
2
EN_FANIN8.(Fan In 8 Enable Bit)
Setting to 1 enables FANIN8 monitor.
If wish to connect FANIN8 to Pin55 is desired, VIDBSEL, SIDB_SEL and FAN8SEL must
be set to 0.
If wish to connect FANIN8 to Pin 10, setting FAN8SEL = 1 is a must.
Setting to 0 enables Pin 10 with Processor A VID Bit 4(EN_D-VID)
1
EN_FANIN7.(Fan In 7 Enable Bit)
If VIDBSEL = 0, setting to 1 will enable FANIN7 monitor.
Setting to 0 enables Pin 53 with Processor B VID Bit 4(VIDBSEL = 1)
0
EN_FANIN6.(Fan In 6 Enable Bit)
If VIDBSEL = 0, setting to 1 will enable FANIN6 monitor.
Setting to 0 enables Pin 51 with Processor B VID Bit2(VIDBSEL = 1)
8.7.2.3.
FANIN Input Pin Redirection Register (FANIN_Sel)
Location:
Type:
Reset:
Bank 0 Address 5D HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANIN_SEL
Bit
7
6
Name
Reset
5
4
Reserved
0
0
0
0
3
2
1
0
FANIN12Sel
FANIN11Sel
FANIN10Sel
FANIN9Sel
0
0
0
0
Bit
Description
7-4
Reserve.
3
FANIN12Sel.
If FANIN12Sel is set to 0, connect FANIIN12 to Pin 40; otherwise, connect FANIN12 to Pin
11.
When FANIIN12 is connected to Pin 11, Bank0 CR58 bit0 FAN8SEL must be set to 1.
2
FANIN11Sel.
If FANIN11Sel is set to 0, connect FANIIN11 to Pin 39; otherwise, connect FANIN11 to Pin
54.
- 53 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
When FANIIN11 is connected to Pin 54, Bank0 CR58 bit7 VIDBSEL must be set to 0.
1
FANIN10Sel.
If FANIN10Sel is set to 0, connect FANIIN10 to Pin 38; otherwise, connect FANIN10 to Pin
52.
When FANIIN10 is connected to Pin 52, VIDBSEL must set be to 0.
0
FANIN9Sel.
If FANIN9Sel is set to 0, connect FANIIN9 to Pin 37; otherwise, connect FANIN9 to Pin 50.
When FANIIN9 is connected to Pin 50, VIDBSEL must be set to 0.
8.8
Temperature Sensors Control Register
The W83793G provides two sets of LM75-like sensors, which function as two independent sensors
through different I2C address accesses (90 HEX ~ 9E HEX ). These two sensors can also be accessed and
controlled from the W83793G addresses (58 HEX ~ 5E HEX ). Here lists the control registers for the
LM75-like sensors.
- 54 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.8.1
Temperature Sensors Control Register Map
Mnemonic
Register Name
Type
TD1_Config.
Temperature Sensor
Configuration (LM75A)
TD1
TD2_Config.
Temperature Sensor
Configuration (LM75B)
TD2
TD_MD
Temperature Sensor mode
Select 1
R/W
TR_MD
Temperature Sensor mode
Select 2
R/W
Temperature Channel Offset
R/W
R/W
R/W
TempOffset
Please be noted that the W83793G supports 4 thermal diode inputs and 2 thermistor inputs, while
the W83793AG supports only 1 thermal diode input and 2 thermistor inputs.
- 55 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.8.2
Temperature Sensors Control Register Details
8.8.2.1.
TD1 Configuration (LM75A) Register (TD1_Config)
Location: Bank 0 Address 5A HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TD1_CONFIG
Bit
7
6
Name
5
Reserve
Reset
0
4
3
2
FaultQ1
0
1
0
Reserve
00
0
STOP1
0
0
0
Bit
Description
7-6
Reserved.
5-4
FaultQ1.
Number of faults to detect before setting OVT# output to avoid false strapping due
to noise.
3-1
Reserved.
0
STOP1.
If temperature sensor TD1 is set as an internal temperature sensor (CR5D), setting
to 1 will stop the temperature sensor.
8.8.2.2.
TD2 Configuration (LM75B) Register (TD2_Config)
Location:
Type:
Reset:
Bank 0 Address 5B HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TD2_CONFIG
Bit
7
6
Name
Reset
5
Reserve
0
4
3
2
FaultQ2
0
1
0
Reserve
00
0
0
STOP2
0
0
- 56 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7-6
Reserved.
5-4
FaultQ2.
Number of faults to detect before setting OVT# output to avoid false strapping due
to noise.
3-1
Reserved.
0
STOP2.
If temperature sensor TD2 is set as internal temperature sensor (CR5D), setting to
1 will stop the temperature sensor monitoring.
8.8.2.3. TD Mode Select Register (TD_MD)
Before enabling monitoring, it needs to set correct values to the pins (Bank0.CR58) and sensor select
registers (Bank0.CR5E).
Location:
Type:
Reset:
TD_MD - Bank 0 Address 5E HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TD_MD
Bit
Name
7
6
5
4
3
2
1
0
TD4_MD
TD3_MD
TD2_MD
TD1_MD
01
01
01
01
Reset
Bit
Description
7-6
TD4_MD.
Temperature D4 mode
00 BIN : Temperature D4 stops monitoring.
01 BIN : Temperature D4 starts monitoring using the internal temperature sensor
(default).
10 BIN : Reserved.
11 BIN : Temperature D4 starts monitoring using the temperature sensor in Intel
CPU and obtains the results by PECI.
5-4
TD3_MD.
Temperature D3 mode
00 BIN : Temperature D3 stops monitoring.
01 BIN : Temperature D3 starts monitoring using the internal temperature sensor
(default).
- 57 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
10 BIN : Reserved.
11 BIN : Temperature D3 starts monitoring using the temperature sensor in Intel
CPU and obtains the results by PECI.
3-2
TD2_MD.
Temperature D2 mode
00 BIN : Temperature D2 stops monitor
01 BIN : Temperature D2 starts monitoring using the internal temperature sensor
(default).
10 BIN : Reserved.
11 BIN : Temperature D2 starts monitoring using the temperature sensor in Intel
CPU and obtains the results by PECI.
1-0
TD1_MD.
Temperature D1 mode
00 BIN : Temperature D1 stops monitoring.
01 BIN : Temperature D1 starts monitoring using the internal temperature sensor
(default).
10 BIN : Reserved.
11 BIN : Temperature D1 starts monitoring using the temperature sensor in Intel
CPU and obtains the results by PECI.
8.8.2.4.
TR Mode Select Register (TR_MD)
Location:
Type:
Reset:
TR_MD - Bank 0 Address 5F HEX
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TR_MD
Bit
7
6
5
4
Name
Reset
3
2
Reserve
0
0
0
0
0
Bit
Description
7-2
Reserve.
1
TR2_MD.
Setting to 1 will enable Temperature sensor TR2 monitor.
0
TR1_MD.
Setting to 1 will enable Temperature sensor TR1 monitor.
0
1
0
TR2_MD
TR1_MD
1
1
- 58 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.8.2.5. Temperature Channel Offset Register (TempOffset)
Each temperature channel has a corresponding offset register. In some situations, the customer may
want to shift the offset. The default is 00 HEX .
Location:
TD4Offset - Bank 0 Address AB HEX
TD1Offset - Bank 0 Address A8 HEX
TD2Offset - Bank 0 Address A9 HEX
TR1Offset - Bank 0 Address AC HEX
TD3Offset - Bank 0 Address AA HEX
TR2Offset - Bank 0 Address AD HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising.
TD/TROFFSET
Bit
Name
Reset
7
6
5
4
3
Sign
0
2
1
0
Offset value
0
0
Bit
Description
7-0
TD1~TR2 Offset Value.
8.9
Voltage Channel Registers
0
0
0
1
1
The monitored values and their corresponding limitation settings are listed. The W83793G provides
more detailed resolution for VCoreA, VCoreB, and Vtt channels. Besides the 8-bit readout, there are still
lower bits to be read.
Please be noted that VCOREB is for the W83793G only; the W83793AG does not support VCOREB.
- 59 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.9.1
Voltage Channel Registers Map
8.9.1.1.
Voltage Channel Monitor Value Register Map
Mnemonic
Register Name
Type
VcoreA.
VCOREA Readout
RO
VcoreB.
VCOREB Readout
RO
Vtt.
Vtt Readout
RO
VINLowB.
VIN Low bit Readout
RO
VSEN1.
VSEN1 Readout
RO
VSEN2.
VSEN2 Readout
RO
VSEN3.
VSEN3 Readout
RO
VSEN4.
VSEN4 Readout
RO
5VDD.
5VDD Readout
RO
5VSB.
5VSB Readout
RO
VBAT.
VBAT Readout
RO
8.9.1.2.
Voltage Channel Limit Value Registers Map
Mnemonic
VcoreA HL/LL.
Register Name
VCOREA High/Low Limit
Type
R/W
- 60 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
VcoreB HL/LL.
VCOREB High/Low Limit
R/W
Vtt HL/LL.
Vtt High/Low Limit
R/W
VINHLLowB.
VIN High Limit Low bit
R/W
VINLLLowB.
VIN Low Limit Low bit
R/W
VSEN1 HL/LL.
VSEN1 High/Low Limit
R/W
VSEN2 HL/LL.
VSEN2 High/Low Limit
R/W
VSEN3 HL/LL.
VSEN3 High/Low Limit
R/W
VSEN4 HL/LL.
VSEN4 High/Low Limit
R/W
5VDD HL/LL.
5VDD High/Low Limit
R/W
5VSB HL/LL.
5VSB High/Low Limit
R/W
VBAT HL/LL.
VBAT High/Low Limit
R/W
- 61 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.9.2
Voltage Channel Register Details
8.9.2.1. Voltage Channel Monitored Value
Location:
VCOREA Readout - Bank 0 Address 10 HEX
VCOREB Readout - Bank 0 Address 11 HEX
Vtt Readout - Bank 0 Address 12 HEX
VIN Low bit - Bank 0 Address 1B Hex
VSEN1 Readout - Bank 0 Address 14 HEX
VSEN2 Readout - Bank 0 Address 15 HEX
Type:
Read Only
Reset:
No Reset
VSEN3 Readout - Bank 0 Address 16 HEX
VSEN4 Readout - Bank 0 Address 17 HEX
5VDD Readout - Bank 0 Address 18 HEX
5VSB Readout - Bank 0 Address 19 HEX
VBAT Readout - Bank 0 Address 1A HEX
VOLTAGE READOUT
Bit
7
6
5
4
Name
3
2
1
0
1
0
Voltage Voltage
VIN LOW BIT READOUT
Bit
Name
7
6
Reserve
5
4
3
VttL
2
VCOREBL
VcoreAL
Channel VcoreA/B, and Vtt combines the 8-bit readout and the low nibble to express each channel’s
monitored results; therefore, it is 10-bit format data. For example, the monitored value of VCOREA can be
obtained from the combination of VCOREA Readout and bit 1~0 of VIN Low bit Readout. In order to read
the correct result, it needs to read the high byte first and then to read its corresponding low byte. The real
voltage calculation of these three channels should follow the formula
Vcore A Voltage = (CR [10]*4 + CR [1B] &0x03) * 0.002;
Vcore B Voltage = (CR [11]*4 + (CR [1B] &0x0C)/4) * 0.002;
Vtt
Voltage = (CR [12]*4 + (CR [1B] &0x30)/16) * 0.002;
The rest voltage channels only support 8-bit output format. The real voltage calculation of these three
channels should follow the formula
VSEN1
Voltage = CR [14] * (2 * 0.008);
VSEN2
Voltage = CR [15] * (2 * 0.008);
VSEN3
Voltage = CR [16] * (2 * 0.008);
VSEN4
Voltage = CR [17] * 0.008;
5VDD
Voltage = CR [18] * (2 * 1.5 * 0.008)+0.15;
5VSB
Voltage = CR [19] * (2 * 1.5 * 0.008)+0.15;
VBAT
Voltage = CR [1A] * (2 * 0.008);
8.9.2.2.
Voltage Channel Limitation Registers
Location:
- 62 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
VCOREA High Limit Bank 0 Address 60 HEX
VCOREA Low Limit Bank 0 Address 61 HEX
VCOREB High Limit Bank 0 Address 62 HEX
VCOREB Low Limit Bank 0 Address 63 HEX
Vtt High Limit
Bank 0 Address 64 HEX
Vtt Low Limit
Bank 0 Address 65 HEX
High Limit Low bit Bank 0 Address 68 HEX
Low Limit Low bit Bank 0 Address 69 HEX
VSEN1 High Limit Bank 0 Address 6A HEX
VSEN1 Low Limit Bank 0 Address 6B HEX
VSEN2 High Limit Bank 0 Address 6C HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set.
VSEN2 Low Limi Bank 0 Address 6D HEX
VSEN3 High Limit Bank 0 Address 6E HEX
VSEN3 Low Limit Bank 0 Address 6F HEX
VSEN4 High Limit Bank 0 Address 70 HEX
VSEN4 Low Limit Bank 0 Address 71 HEX
5VDD High Limit Bank 0 Address 72 HEX
5VDD Low Limit Bank 0 Address 73 HEX
5VSB High Limit Bank 0 Address 74 HEX
5VSB Low Limit Bank 0 Address 75 HEX
VBAT High Limit Bank 0 Address 76 HEX
VBAT Low Limit Bank 0 Address 77 HEX
VOLTAGE HIGH LIMIT
Bit
7
6
5
4
Name
3
2
1
0
2
1
0
1
0
Voltage High Limit
Reset
FF HEX
VOLTAGE LOW LIMIT
Bit
7
6
5
4
Name
3
Voltage Low Limit
Reset
00 HEX
VIN HIGH LIMIT LOW BIT
Bit
7
Name
Reset
6
5
4
3
2
Reserve
VTTHLL
VCOREBHLL
VcoreAHLL
00
11
11
11
VIN LOW LIMIT LOW BIT
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserve
VTTLLL
VCOREBLLL
VcoreALLL
00
00
00
00
The code calculation of high/low limit should follow the formula
- 63 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
VCoreA, VCoreB, Vtt Limit Setup
CR60~66 =
[Desired Voltage]/0.008;
CR68/69 =
([Desired Voltage]/0.002) – CR60~67 * 4;
VSEN1, VSEN2, VSEN3 Limit Setup
CR6A~6F =
[Desired Voltage] / 0.016;
VSEN4 Limit Setup
CR70~71 =
[Desired Voltage] / 0.08;
5VDD, 5VSB Limit Setup
CR72~75 =
[Desired Voltage] - 0.15 / 0.024;
VBAT Limit Setup
CR76~77 =
[Desired Voltage] / 0.016;
8.10 Temperature Channel Registers
- 64 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.10.1 Temperature Channel Register Map
8.10.1.1. Temperature Channel Monitored Value Register Map
Mnemonic
Register Name
Type
TD1.
Temperature Sensor TD1 Readout
RO
TD2.
Temperature Sensor TD2 Readout
RO
TD3.
Temperature Sensor TD3 Readout
RO
TD4.
Temperature Sensor TD4 Readout
RO
TDLowB.
Temperature Sensor TD Low Bit Readout
RO
TR1.
Temperature Sensor TR1 Readout
RO
TR2.
Temperature Sensor TR2 Readout
RO
8.10.1.2. Temperature Channel Limitation Value Register Map
Mnemonic
Register Name
Type
TD1 CT/CTH.
TD1 Critical Temperature / Critical Temperature
Hysteresis
R/W
TD1 WT/WTH.
TD1 Warning Temperature / Warning Temperature
Hysteresis
R/W
TD2 CT/CTH.
TD2 Critical Temperature / Critical Temperature
Hysteresis
R/W
TD2 WT/WTH.
TD2 Warning Temperature / Warning Temperature
Hysteresis
R/W
TD3 CT/CTH.
TD3 Critical Temperature / Critical Temperature
Hysteresis
R/W
- 65 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Mnemonic
Register Name
Type
TD3 WT/WTH.
TD3 Warning Temperature / Warning Temperature
Hysteresis
R/W
TD4 CT/CTH.
TD4 Critical Temperature / Critical Temperature
Hysteresis
R/W
TD4 WT/WTH.
TD4 Warning Temperature / Warning Temperature
Hysteresis
R/W
TR1 CT/CTH.
TR1 Critical Temperature / Critical Temperature
Hysteresis
R/W
TR1 WT/WTH.
TR1 Warning Temperature / Warning Temperature
Hysteresis
R/W
TR2 CT/CTH.
TR2 Critical Temperature / Critical Temperature
Hysteresis
R/W
TR2 WT/WTH.
TR2 Warning Temperature / Warning Temperature
Hysteresis
R/W
- 66 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.10.2 Temperature Channel Register Details
8.10.2.1. Temperature Channel Monitored Registers
Location:
TD1 Readout - Bank 0 Address 1C HEX
TD2 Readout - Bank 0 Address 1D HEX
TD3 Readout - Bank 0 Address 1E HEX
TD4 Readout - Bank 0 Address 1F HEX
Low bit Readout
- Bank 0 Address
22 HEX
Type:
Read Only
TR1 Readout
20 HEX
TR2 Readout
21 HEX
-
Bank
0
Address
-
Bank
0
Address
TEMP READOUT
Bit
7
6
5
4
Name
3
2
1
0
2
1
0
Temperature
TD LOW BIT READOUT
Bit
Name
7
6
TD4L
5
4
3
TD3L
TD2L
TD1L
The format of Temperature channel readout is 2’complement. TD channel expresses the
temperature using 10-bit data, including 1-bit sign bit, 7-bit integer, and 2 bits decimal. TR
channel expresses the temperature using 8-bit data, including 1-bit sign bit, and 7-bit integer.
For TD channel temperature = TDx + TDxL* 0.25
TR channel temperature = TRx
8.10.2.2. Temperature Channel Limitation Registers
Location:
TD1 Critical
- Bank 0 Address 78 HEX
TD1 Critical Hystersis - Bank 0 Address 79 HEX
TD1 Warning
- Bank 0 Address 7A HEX
TD1 Warning Hystersis - Bank 0 Address 7B HEX
TD2 Critical
- Bank 0 Address 7C HEX
TD2 Critical Hystersis - Bank 0 Address 7D HEX
TD2 Warning
- Bank 0 Address 7E HEX
TD2 Warning Hystersis - Bank 0 Address 7F HEX
TD3 Critical
- Bank 0 Address 80 HEX
TD3 Critical Hystersis - Bank 0 Address 81 HEX
TD3 Warning
- Bank 0 Address 82 HEX
TD3 Warning Hystersis - Bank 0 Address 83 HEX
TD4 Critical
- Bank 0 Address
84 HEX
TD4 Critical Hystersis - Bank 0 Address
85 HEX
TD4 Warning
- Bank 0 Address 86 HEX
TD4 Warning Hystersis - Bank 0 Address
87 HEX
TR1 Critical
- Bank 0 Address 88 HEX
TR1 Critical Hystersis - Bank 0 Address
89 HEX
TR1 Warning
- Bank 0 Address 8A HEX
TR1 Warning Hystersis-Bank 0 Address 8B HEX
TR2 Critical
- Bank 0 Address 8C HEX
- 67 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
TR2 Warning Hystersis- Bank 0 Address 8F HEX
TR2 Critical Hystersis - Bank 0 Address 8D HEX
TR2 Warning
- Bank 0 Address 8E HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising.
SENSOR CRITICAL TEMPERATURE
Bit
7
6
5
Name
4
3
2
1
0
Temp Critical Temperature
Reset
64 HEX (100 C)
SENSOR CRITICAL TEMPERATURE HYSTERSIS
Bit
7
6
Name
5
4
3
2
1
0
1
0
Sensor Critical Temperature Hysteresis
Reset
5F HEX (95 C)
SENSOR CRITICAL TEMPERATURE
Bit
7
6
5
Name
4
3
2
Sensor Warning Temperature
Reset
55 HEX (85 C)
SENSOR WARNING TEMPERATURE HYSTERSIS
Bit
Name
7
6
5
4
3
2
1
0
Sensor Warning Temperature Hysteresis
Reset
50 HEX (80 C)
The format of Temperature channel limit is 2’complement; bit 7 is sign bit, and the range is –128~127.
8.11 Fan Control Registers
All Fan Control/Status registers are located in Bank 0 and Bank 2. Bank 0 resides common-used
control/status registers, and in Bank 2 are the Smart Fan Control setups.
- 68 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.11.1 Fan Register Map
8.11.1.1. Common Register Control/Status registers Block
All common Fan Control/Status registers are located in Bank 0.
Mnemonic
Register Name
Type
Fan1CountH/L.
|
Fan12CountH/L.
Fan tachometer readout high/low Byte
RO
Fan1LimitH/L.
|
Fan12LimitH/L.
Fan Count Limit high/low Byte
RW
FanCtrl1.
FanCtrl2.
Fan Output style Control
RW
DefaultSpeed.
Default Fan Speed at power-on
RW
Fan1Duty.
|
Fan8Duty.
Current Fan output Duty Cycle
RW
PWM1Prescalar.
|
PWM8Prescalar.
Fan PWM output frequency pre-scalar
RW
Here listed registers which can read the tachometer values, and their limit registers. All of these registers
are separated into 2 bytes. Reading tachometer count high byte will lock the corresponding low byte to
ensure data consistency in next reading on the low byte.
Because FANIN 6~12 (Pins 37, 38, 39, 40, 51, 53, and 55) are multifunction pins, FanInControl
provides the selection between FanIn functions and other functions.
Fan Output style (DC/PWM), Duty cycle, and frequency controls are also provided.
8.11.1.2. Smart Fan Setup/Status registers
Registers of SmartFan setup resides in Bank 0 and Bank 2. Most used step timing control and critical
temperature setup are located in Bank 0. All the others are located in Bank 2.
Mnemonic
Register Name
Type
UpTime.
SmartFan Fan Step Up Time
RW
DownTime.
SmartFan Fan Step Down Time
RW
- 69 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Mnemonic
Register Name
Type
CriticalTemp.
All Fan full speed temperature
RW
Temperature to Fan mapping relationships in
SmartFan mode
RW
SmartFan Control Mode Select
RW
Hysteresis tolerance of each temperature source
RW
Fan Output Nonstop Duty cycle
RW
Fan Output Start Duty Cycle
RW
Fan Stop Time from nonstop level to turn off.
RW
TD1FanSelect.
TR2FanSelect.
FanCtrlMode.
TolTD12.
TolTR12.
Fan1Nonstop.
Fan8Nonstop.
Fan1Start.
Fan8Start.
Fan1StopTime.
Fan8StopTime.
Smart Fan Mode is activated on the corresponding fans once users define the relationship between the
fan and the temperature input in TempFanSelect. Under SmartFan Mode, user can select Thermal
Cruise mode or SMART FANTM II mode by assigning FanCtrlMode.
TempFanSelect enables users to arbitrarily define the Temperature-to-Fan relationship. For example,
one can define Thermistor input 1 as chassis temperature sensor, and Temperature 1(Diode Input 1) as
CPU sensor. Users can manipulate Fan1 (CPU Fan) and Fan2 (System Fan) as the following. Assigning
TD1FanSelect 03 HEX and TR1FanSelect 02 HEX , the W83793G will connect the system fan with the CPU
sensor and the Chassis sensor, but the CPU fan will only be affected by the CPU sensor. More
descriptions can be found at the register definition section for this issue.
In SmartFan Mode, a specific temperature will be defined in CriticalTemp. If any temperature input
detected is higher than this, all fans will operate at full speed simultaneously. The definitions of the
control parameters in normal use are shown in the following graph.
- 70 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.11.1.3. Thermal Cruise Mode Registers (Bank 2)
Mnemonic
Register Name
Type
Target Temperature of Temperature inputs
RW
TD1Target.
TR2Target.
Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the
target temperature. If the temperature source detects temperatures higher or lower than the target
temperatures with TolTemp tolerance, Smart Fan Control will take actions to speed up or slow down the
fan to keep the temperature within the tolerance range.
The concept is quite simple. When the temperature is higher than TargetTemp+TolTemp, the fan will be
speeded up. When the temperature is lower than TargetTemp-TolTemp, the fan will be slowed down.
Otherwise, the fan keeps its current speed.
8.11.1.4. Smart Fan II Control registers (Bank 2)
Mnemonic
Register Name
Type
- 71 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Mnemonic
Register Name
Type
Smart Fan II Fan Transition temperature levels
RW
Smart Fan II Fan Output Levels
RW
TD1Level01.
TR2Level67.
TD1FanLevel0.
TR2FanLevel6.
TempLevel67
TempLevel56
TempLevel45
TempLevel34
TempLevel23
TempLevel12
TempLevel01
SMART FANTMII algorithm provides users a mechanism to set up the fan speed via Temperature level
relationship. Each temperature source has a corresponding table, and totally six tables are used to
control Temperature 1(D1) to Temperature 6 (R2).
A table consists of 7 temperature levels and 7 fan levels as the following.
When the fan speed jumps from one level to another, there is a hysterisis mechanism to prevent the fan
from throttling. When the temperature rises from one level to another, the fan speed rises to a higher
level. However, the temperature has to be lower than the specified temperature minus the tolerance to
make the fan speed drop to the lower level.
- 72 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.11.2 Fan Register Details
8.11.2.1. Fan Tachometer Readout high/low Byte Register (FanCountH/L)
The FanCountH/L maintains current count value of corresponding fan inputs. When 5VSB is on, it is
cleared (00 HEX ). The effective width of FanCountH/L is 12-bit. The FanCountH high nibble is not used.
Location:
Fan1CountH - Bank 0 Address 23 HEX
Fan1CountL – Bank 0 Address 24 HEX
Fan2CountH – Bank 0 Address 25 HEX
Fan2CountL – Bank 0 Address 26 HEX
Fan3CountH – Bank 0 Address 27 HEX
Fan3CountL – Bank 0 Address 28 HEX
Fan4CountH – Bank 0 Address 29 HEX
Fan4CountL – Bank 0 Address 2A HEX
Fan5CountH – Bank 0 Address 2B HEX
Fan5CountL – Bank 0 Address 2C HEX
Fan6CountH – Bank 0 Address 2D HEX
Fan6CountL – Bank 0 Address 2E HEX
Type:
Reset:
Fan7CountH – Bank 0 Address 2F HEX
Fan7CountL – Bank 0 Address 30 HEX
Fan8CountH – Bank 0 Address 31 HEX
Fan8CountL – Bank 0 Address 32 HEX
Fan9CountH – Bank 0 Address 33 HEX
Fan9CountL – Bank 0 Address 34 HEX
Fan10CountH – Bank 0 Address 35 HEX
Fan10CountL – Bank 0 Address 36 HEX
Fan11CountH – Bank 0 Address 37 HEX
Fan11CountL – Bank 0 Address 38 HEX
Fan12CountH – Bank 0 Address 39 HEX
Fan12CountL – Bank 0 Address 3A HEX
Read Only
VSB5V (Pin 7) Rising
FAN1COUNTH~FAN12COUNTH
Bit
7
6
5
4
Name
3
2
1
0
FanCountH
Reset
00 HEX
Bit
Description
7-0
FanCountH (Fan tachometer readout high byte). The count value high byte of FanIn
signal period with 45KHz clock.
FAN1COUNTL~FAN12COUNTL
Bit
7
Name
6
5
4
3
2
1
0
FanCountL
Reset
00 HEX
Bit
Description
7-0
FanCountL(Fan tachometer readout low byte). The count value low byte of FanIn
signal period with 45KHz clock.
- 73 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
FAN COUNT CALCULATION
Fan1CountL together with Fan1CountH form the 12-bit count value. If Fan1CountH and Fan1CountL are
read successively, the W83793G will make these two count values consistent (i.e. the same counting). If
the user reads them in reverse order or there is other read/write in between, it is possible that the
high/low byte may come from different counting and lead to abnormal reading. Same rules can be
applied to other FanCounts.
Real RPM (Rotate per Minute) calculations should follow the formula
FanSpeed ( RPM ) =
1.35 × 10 6
(12 − bitCountValue) × ( FanPoles )
4
In this formula, 12-bitCountValue represents the values stored in FanCountH/L, and FanPoles stands for
the number of NS pole pairs inside the fan. Normally an N-S-N-S Fan (FanPoles = 4) generates 2 pulses
after completing one rotation.
The frequency range for the fan tachometer is below 4.5 KHz (if FanPoles=4, it means 135KRPM). It is
almost impossible, but a fan working faster than this will cause the malfunction of the W83793G.
8.11.2.2. Fan Count Limit High/Low Byte (FanLimitH/L)
The FanLimitH/L sets up the limit range for the fan in count values. If the counter counts value larger
than what the registers indicate, the W83793G will show alert in the real-time status and may take further
actions based on user setups. While reset it is set (FF HEX ).
Location:
Fan1LimitH - Bank 0 Address 90 HEX
Fan7LimitH – Bank 0 Address 9C HEX
Fan1LimitL – Bank 0 Address 91 HEX
Fan7LimitL – Bank 0 Address 9D HEX
Fan2LimitH – Bank 0 Address 92 HEX
Fan8LimitH – Bank 0 Address 9E HEX
Fan2LimitL – Bank 0 Address 93 HEX
Fan8LimitL – Bank 0 Address 9F HEX
Fan3LimitH – Bank 0 Address 94 HEX
Fan9LimitH – Bank 0 Address A0 HEX
Fan3LimitL – Bank 0 Address 95 HEX
Fan9LimitL – Bank 0 Address A1 HEX
Fan4LimitH – Bank 0 Address 96 HEX
Fan10LimitH – Bank 0 Address A2 HEX
Fan4LimitL – Bank 0 Address 97 HEX
Fan10LimitL – Bank 0 Address A3 HEX
Fan5LimitH – Bank 0 Address 98 HEX
Fan11LimitH – Bank 0 Address A4 HEX
Fan5LimitL – Bank 0 Address 99 HEX
Fan11LimitL – Bank 0 Address A5 HEX
Fan6LimitH – Bank 0 Address 9A HEX
Fan12LimitH – Bank 0 Address A6 HEX
Fan6LimitL – Bank 0 Address 9B HEX
Fan12LimitL – Bank 0 Address A7 HEX
Type:
Read / Write
Reset: VSB5V (Pin 7) Rising.
FAN1LIMITH ~ FAN12LIMITH
Bit
Name
Reset
7
6
5
4
3
2
1
0
FanLimitH
FF HEX
- 74 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7-0
FanLimitH (Fan tachometer limit high byte). The limitation of the count value high byte
of FanIn.
FAN1LIMITL~FAN12LIMITL
Bit
7
6
5
4
3
Name
2
1
0
FanLimitL
Reset
FF HEX
Bit
Description
7-0
FanLimitL (Fan tachometer readout limit low byte). The limitation of the count value
low byte of FanIn.
8.11.2.3. Fan Output Style Control (FanCtrl)
FanCtrl1/2 decide the fan output style. Several output styles are available in the W83793G, including the
OD mode (Open-Drain), the OB mode (Output-Buffer), and the DC mode (DAC output). The OD mode is
the default of all fan outputs.
Location:
FanCtrl1 - Bank 0 Address B0 HEX
FanCtrl2 – Bank 0 Address B1 HEX
Type:
Reset:
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANCTRL1
Bit
Name
Reset
7
6
5
4
3
2
1
0
F8OB
F7OB
F6OB
F5OB
F4OB
F3OB
F2OB
F1OB
0
0
0
0
0
0
0
0
Bit
Description
7
F8OB (Fan output 8 Output Buffer Mode Control).
0: Depends on F8DC (CRB1.Bit7). If F8DC=1, Pin 11 outputs with the DC mode.
Otherwise, the output is configured to the OD mode.
1: Depends on F8DC (CRB1.Bit7). If F8DC=1, Pin 11 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
6
F7OB (Fan output 7 Output Buffer Mode Control).
0: Depends on F7DC (CRB1.Bit6). If F7DC=1, Pin 54 outputs with the DC mode.
- 75 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
Otherwise, the output is configured to the OD mode.
1: Depends on F7DC (CRB1.Bit6). If F7DC=1, Pin 54 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
5
F6OB (Fan output 6 Output Buffer Mode Control).
0: Depends on F6DC (CRB1.Bit5). If F6DC=1, Pin 52 outputs with the DC mode.
Otherwise, the output is configured to the OD mode.
1: Depends on F6DC (CRB1.Bit5). If F6DC=1, Pin 52 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
4
F5OB (Fan output 5 Output Buffer Mode Control).
0: Depends on F5DC (CRB1.Bit4).If F5DC=1, Pin 50 outputs with the DC mode.
Otherwise, the output is configured to the OD mode.
1: Depends on F5DC (CRB1.Bit4). If F5DC=1, Pin 50 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
3
F4OB (Fan output 4 Output Buffer Mode Control).
0: Depends on F4DC (CRB1.Bit3). If F4DC=1, Pin 49 outputs with the DC mode.
Otherwise, the output is configured to the OD mode.
1: Depends on F4DC (CRB1.Bit3). If F4DC=1, Pin 49 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
2
F3OB (Fan output 3 Output Buffer Mode Control).
0: Depends on F3DC (CRB1.Bit2). If F3DC=1, Pin 46 outputs with the DC mode.
Otherwise, the output is configured to the OD mode.
1: Depends on F3DC (CRB1.Bit2). If F3DC=1, Pin 46 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
1
F2OB (Fan output 2 Output Buffer Mode Control).
0: Depends on F2DC (CRB1.Bit1). If F2DC=1, Pin 44 outputs with the DC mode.
Otherwise, the output is configured to the OD mode.
1: Depends on F2DC (CRB1.Bit1). If F2DC=1, Pin 44 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
0
F1OB (Fan output 1 Output Buffer Mode Control).
0: Depends on F1DC (CRB1.Bit0). If F1DC=1, Pin 42 outputs with the DC mode.
Otherwise, the output is configured to the OD mode.
1: Depends on F1DC (CRB1.Bit0). If F1DC=1, Pin 42 outputs with the DC mode.
Otherwise, the output is configured to the OB mode
FANCTRL2
Bit
Name
Reset
7
6
5
4
3
2
1
0
F8DC
F7DC
F6DC
F5DC
F4DC
F3DC
F2DC
F1DC
0
0
0
0
0
0
0
0
Bit
Description
7
F8DC (Fan output 8 Direct Current Mode Control).
- 76 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
0: OD or OB mode on Pin 11. Depend on F8OB (CRB0.Bit7)
1: Pin 11 is set to the DC mode.
6
F7DC (Fan output 7 Direct Current Mode Control).
0: OD or OB mode on Pin 54. Depend on F7OB (CRB0.Bit6)
1: Pin 54 is set to the DC mode.
5
F6DC (Fan output 6 Direct Current Mode Control).
0: OD or OB mode on Pin 52. Depend on F6OB (CRB0.Bit5)
1: Pin 52 is set to the DC mode.
4
F5DC (Fan output 5 Direct Current Mode Control).
0: OD or OB mode on Pin 50. Depend on F5OB (CRB0.Bit4)
1: Pin 50 is set to the DC mode.
3
F4DC (Fan output 4 Direct Current Mode Control).
0: OD or OB mode on Pin 49. Depend on F4OB (CRB0.Bit3)
1: Pin 49 is set to the DC mode.
2
F3DC (Fan output 3 Direct Current Mode Control).
0: OD or OB mode on Pin 46. Depend on F3OB (CRB0.Bit2)
1: Pin 46 is set to the DC mode.
1
F2DC (Fan output 2 Direct Current Mode Control).
0: OD or OB mode on Pin 44. Depend on F2OB (CRB0.Bit1)
1: Pin 44 is set to the DC mode.
0
F1DC (Fan output 1 Direct Current Mode Control).
0: OD or OB mode on Pin 42. Depend on F1OB (CRB0.Bit0)
1: Pin 42 is set to the DC mode.
8.11.2.4. Default Fan Speed at Power-on (DefaultSpeed)
DefaultSpeed sets the initial speed of every fan. When the system is turned on, a default will be given to
all fan outputs according to the register content. This register is specially designed to be reset by VSB
only, so at the second system power on, the system will use the last setup speed to turn on all of the
fans.
Location:
Type:
Reset:
DefaultSpeed - Bank 0 Address B2 HEX
Read / Write
VSB5V (Pin 7) Rising.
DefaultSpeed
Bit
Name
Reset
Bit
7
6
5
Reserved
0
4
3
2
1
0
DefaultSpeed
0
30 HEX
Description
- 77 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7-6
Reserved.
5-0
DefaultSpeed (Default Fan Speed at Power-on). Specifies the fan duty at next power
on.
8.11.2.5. Current Fan Output Duty Cycle (FanDuty)
FanDuty reflects the current output duty cycle. In the manual mode, the user can set preferred duty cycles.
However, in the Smart Fan mode, it is read-only.
Location:
Fan1Duty - Bank 0 Address B3 HEX
Fan2Duty - Bank 0 Address B4 HEX
Fan3Duty - Bank 0 Address B5 HEX
Fan4Duty - Bank 0 Address B6 HEX
Type:
Reset:
Fan5Duty - Bank 0 Address B7 HEX
Fan6Duty - Bank 0 Address B8 HEX
Fan7Duty - Bank 0 Address B9 HEX
Fan8Duty - Bank 0 Address BA HEX
Read / Write (Only in Manual Mode, make sure 5VDD and Pin 1 CLK are ready)
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FAN1DUTY ~ FAN8DUTY
Bit
Name
Reset
7
6
5
4
Reserved
0
0
3
2
1
0
FanDuty
Depend on DefaultSpeed.
Bit
Description
7-6
Reserved.
5-0
FanDuty(Current Fan output Duty Cycle). Specifies the current duty cycle of the fan. If
5VDD is low, this register is set to zero by the hardware.
FanDuty also has a special characteristic- sequential power-on. This function is used to avoid over loads
of the system current when the system is powered-on and all fans start to spin. The W83793G takes 0.1
second (12.5ms intervals for 8 fans) to turn on all of the fans one by one.
8.11.2.6. Fan PWM Output Frequency Prescalar (PWMPrescalar)
PWMPrescalar controls the output frequency in the PWM mode. A wide range of clocks can be selected to
satisfy customer needs. The default output frequency is 25 KHz.
Location:
PWM1Prescalar - Bank 0 Address BB HEX
PWM3Prescalar - Bank 0 Address BD HEX
PWM5Prescalar - Bank 0 Address BF HEX
PWM2Prescalar - Bank 0 Address BC HEX
PWM4Prescalar - Bank 0 Address BE HEX
PWM6Prescalar - Bank 0 Address C0 HEX
- 78 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PWM7Prescalar - Bank 0 Address C1 HEX
PWM8Prescalar - Bank 0 Address C2 HEX
Type:
Read / Write (Only in Manual Mode)
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
PWM1PRESCALAR ~ PWM8PRESCALAR
Bit
7
Name
CKSEL
Divisor
1
09 HEX
Reset
6
5
4
3
Bit
Description
7
CKSEL (clock source select).
0: 512Hz.
1: 250KHz.
6-0
Divisor (Clock Divisor). Clock frequency Divisor.
2
1
0
The clock source selected by CKSEL will be divided by the divisor and used as a fan PWM output
frequency. There are 2 divisors depending on CKSEL.
If CKSEL equals 1, then the output clock is simply equal to 250/ (Divisor+1) KHz.
If CKSEL equals 0, the output clock is 512Hz/MappedDivisor. MappedDivisor depends on Divisor[3:0] and
is described in the table below.
Divisor[3:0]
Mapped Divisor
Output Frequency
Divisor[3:0]
Mapped Divisor
Output Frequency
0000
1
512Hz
1000
12
43Hz
0001
2
256Hz
1001
16
32Hz
0010
3
171Hz
1010
32
16Hz
0011
4
128Hz
1011
64
8Hz
0100
5
102Hz
1100
128
4Hz
0101
6
85Hz
1101
256
2Hz
0110
7
73Hz
1110
512
1Hz
0111
8
64Hz
1111
1024
0.5Hz
8.11.2.7. SmartFan Output Step Up Time (UpTime)
UpTime adjusts the time interval of the fan speed up by a unit. The default setting is 0.6sec.
Location: UpTime - Bank 0 Address C3 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
- 79 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
UPTIME
Bit
7
6
5
4
Name
3
2
1
0
UpTime
Reset
06 HEX
Bit
Description
7-0
UpTime(SmartFan Step Up Time). Unit in 0.1sec. Programmed as the interval of
continuous Fan ramping up.
SmartFan is designed for the smooth operation of the fan. The fan duty is seldom suddenly increased
or decreased. Instead, most often the duty is increased or decreased by 1 LSB. The Up Time / Down
Time register defines the time interval between successive duty increases or decreases. If this value
is set too small, the fan will not have enough time to speed up after tuning the duty and sometimes
may result in unstable fan speed. On the other hand, if Up Time / Down Time is set too large, the fan
may not work fast enough to dissipate the heat. This register should never be set to 0. Otherwise, the
fan duty will be abnormal.
Only in the following cases will the fan duty soar or plummet.
ÆVDD Power – on/off
ÆCritical Temperature reached
ÆFan Turn off state to Start
ÆFan at NonStop Level to turn off state
8.11.2.8. SmartFan Output Step Down Time (DownTime)
Down Time reduces the time interval of the fastest fan speed by a unit. The default setting is 0.6sec.
Location: DownTime - Bank 0 Address C4 HE X
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
DOWNTIME
Bit
7
Name
5
4
3
2
1
0
DownTime
Reset
Bit
6
06 HEX
Description
- 80 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
7-0
DownTime (SmartFan Step Down Time). Unit in 0.1sec. Programmed as the interval
of continuous Fan ramping Down.
This register should never be set to 0. Otherwise, the fan duty will be abnormal.
8.11.2.9. All Fan Full Speed Temperature (CriticalTemp)
CriticalTemp defines a system critical temperature. Temperatures exceeding this threshold may lead
to system damage or crash. When the W83793G detects any temperature input exceeding
CriticalTemp, it will speed up all of the fans to lower the temperature.
Location:
CritcalTemp - Bank 0 Address C5 HEX
Type:
Reset:
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
UPTIME
Bit
7
Name
Reserved
CriticalTemp
0
50 HEX
Reset
6
5
4
3
Bit
Description
7
Reserved.
6-0
CriticalTemp(All Fan Full Speed Temperature).
2
1
0
8.11.2.10. Temperature to Fan mapping relationships Register (TempFanSelect)
TempFanSelect deals with the relationship between the fan and the temperature source. While reset
it is cleared (00 HEX ).
Location:
TD1FanSelect - Bank 2 Address 01 HEX
TD4FanSelect - Bank 2 Address 04 HEX
TD2FanSelect - Bank 2 Address 02 HEX
TR1FanSelect - Bank 2 Address 05 HEX
TD3FanSelect - Bank 2 Address 03 HEX
TR2FanSelect - Bank 2 Address 06 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TD1FANSELECT ~ TR2FANSELECT
- 81 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Name
Reset
7
6
5
4
3
2
1
0
Fan8
Fan7
Fan6
Fan5
Fan4
Fan3
Fan2
Fan1
0
0
0
0
0
0
0
0
Bit
Description
7
Fan8 (Enable Fan8 Smart Fan).
0: Fan8 has no relation with this temperature source.
1: Applies SmartFan control on Fan8 and this temperature.
6
Fan7 (Enable Fan7 Smart Fan).
0: Fan7 has no relation with this temperature source.
1: Applies SmartFan control on Fan7 and this temperature.
5
Fan6 (Enable Fan6 Smart Fan).
0: Fan6 has no relation with this temperature source.
1: Applies SmartFan control on Fan6 and this temperature.
4
Fan5 (Enable Fan5 Smart Fan).
0: Fan5 has no relation with this temperature source.
1: Applies SmartFan control on Fan5 and this temperature.
3
Fan4 (Enable Fan4 Smart Fan).
0: Fan4 has no relation with this temperature source.
1: Applies SmartFan control on Fan4 and this temperature.
2
Fan3 (Enable Fan3 Smart Fan).
0: Fan3 has no relation with this temperature source.
1: Applies SmartFan control on Fan3 and this temperature.
1
Fan2 (Enable Fan2 Smart Fan).
0: Fan2 has no relation with this temperature source.
1: Applies SmartFan control on Fan2 and this temperature.
0
Fan1 (Enable Fan1 Smart Fan).
0: Fan1 has no relation with this temperature source.
1: Applies SmartFan control on Fan1 and this temperature.
The following example explains the concept of TempFanSelect Mapping. In this case,
TD1FanSelect is set to 86 HEX ; TD2FanSelect is set to 52 HEX ; TD3FanSelect is set 20 HEX , and the
other 3 are left unset.
- 82 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Splitting and rotating the six registers bit by bit as the figure above helps to understand the
relationship better. For the rows of Fan1 and Fan4, all of the temperatures are de-asserted, which
means Fan1/Fan4 and the temperature are irrelevant. Thus they are in the manual mode under this
setting. For Fan2, it is clear that it is relative to temperature 1 and 2, so it will activate SmartFan
control with temperature 1/2 as its input.
- 83 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
The right graph gives a picture of how the mapping
relationship
is made by this setting.
Fan1
In this example, Fan2 retrieves information from
Temperature 1 and Temperature 2, and decides the next duty
Fan2
Temperature 2
cycle applied to Fan2. To speed up or to slow down the fan is
based on the analysis of the W83793G. Basically, the
Fan3
W83793G sorts and analyzes the information from each
Temperature 3
temperature sensor and SmartFan Controls. The analysis may
be like, “TD1 needs to speed up the fan”; “TD2 does not need
Fan4
so fast fan speed”; “TD1 does not need fast fans any more”,
and “TD2 hopes to keep the current fan speed”. Then, the
Temperature 4
Fan5
algorithm will make a decision to control the fan by the
following simple rule.
Temperature 5
Fan6
If
TD1
says, “I need a faster
Temperature 6
Fan7
fan”, and TD2 says,
“No fast fan needed”.
The W83793G will
Fan8
take request of TD1
and start to speed up the fan. In
short, the W83793G
Any Temp request
Yes
Speed Up
always takes the most critical
request and applies
faster Fan??
it to the related fan.
Temperature 1
No
Any Temp request f
hold current speed??
No
Yes
Hold current
Speed
Slow Down
8.11.2.11. SmartFan Control Mode Select Register (FanCtrlMode)
Once the SmartFan function is enabled, the W83793G supports two SmartFan modes, Thermal
Cruise mode and SMART FANTMII mode (Please refer to TempFanSelect to enable SmartFan
Function). While reset it is cleared (00 HEX ), and is in the SMART FANTMII mode.
Location: FanCtrlMode - Bank 2 Address 07 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
- 84 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANCTRLMODE
Bit
Name
Reset
7
6
Reserved
0
0
5
4
3
2
1
0
TR2_MD
TR1_MD
TD4_MD
TD3_MD
TD2_MD
TD1_MD
0
0
0
0
0
0
Bit
Description
7-6
Reserved.
5
TR2_MD (Thermistor 2 SmartFan Control Mode)
0: SMART FANTMII Mode.
1: Thermal Cruise Mode.
4
TR1_MD (Thermistor 1 SmartFan Control Mode)
0: SMART FANTMII Mode.
1: Thermal Cruise Mode.
3
TD4_MD (Thermal Diode 4 SmartFan Control Mode)
0: SMART FANTMII Mode.
1: Thermal Cruise Mode.
2
TD3_MD (Thermal Diode 3 SmartFan Control Mode)
0: SMART FANTMII Mode.
1: Thermal Cruise Mode.
1
TD2_MD (Thermal Diode 2 SmartFan Control Mode)
0: SMART FANTMII Mode.
1: Thermal Cruise Mode.
0
TD1_MD (Thermal Diode 1 SmartFan Control Mode)
0: SMART FANTMII Mode.
1: Thermal Cruise Mode.
8.11.2.12. Hysteresis Tolerance of Temperature Register (TolTemp)
In SMART FANTM mode, to prevent unstable temperatures from throttling the fan speed, the
W83793G employs a hysteresis temperature to separate the speed-up/slow-down temperature
points. While reset it is set to 2℃ (22 HEX ).
Location:
TolTD12 - Bank 2 Address 08 HEX
TolTD34 - Bank 2 Address 09 HEX
TolTR12 - Bank 2 Address 0A HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
- 85 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
TOLTD12
Bit
7
6
Name
Reset
5
4
3
2
1
TolTD2
TolTD1
2 HEX
2 HEX
Bit
Description
7-4
TolTD2 (TD 2 Tolerance Range). Unit in ℃.
3-0
TolTD1 (TD 1 Tolerance Range). Unit in ℃.
0
TOLTD34
Bit
7
6
Name
Reset
5
4
3
2
1
TolTD4
TolTD3
2 HEX
2 HEX
Bit
Description
7-4
TolTD4 (TD 4 Tolerance Range). Unit in ℃.
3-0
TolTD3 (TD 3 Tolerance Range). Unit in ℃.
0
TOLTR12
Bit
7
Name
Reset
6
5
4
3
2
1
TolTR2
TolTR1
2 HEX
2 HEX
Bit
Description
7-4
TolTR2 (TR2 Tolerance Range). Unit in ℃.
3-0
TolTR1 (TR1 Tolerance Range). Unit in ℃.
0
8.11.2.13. Fan Output Nonstop Duty Cycle Register (FanNonStop)
It takes some time to bring a fan from still to working state. Therefore, FanNonStop is designed with
a minimum duty cycle to keep the fan working when the system does not require the fan to help
reduce heat but still want to keep the fast response time to speed up the fan. (Please refer to Graph)
Location:
Fan1NonStop - Bank 2 Address 18 HEX
Fan2NonStop - Bank 2 Address 19 HEX
Fan3NonStop - Bank 2 Address 1A HEX
Fan4NonStop - Bank 2 Address 1B HEX
- 86 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Fan5NonStop - Bank 2 Address 1C HEX
Fan7NonStop - Bank 2 Address 1E HEX
Fan6NonStop - Bank 2 Address 1D HEX
Fan8NonStop - Bank 2 Address 1F HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANNONSTOP
Bit
7
Name
6
5
4
3
2
Reserved
FanNonStop
0
4 HEX
Reset
Bit
Description
7-6
Reserved.
5-0
FanNonStop(Fan Output NonStop Duty Cycle).
1
0
8.11.2.14. Fan Output Start Duty Cycle Register (FanStart)
From still to rotate, the fan usually needs a higher duty cycle to generate enough torque to conquer the
restriction force. Thus the W83793G includes a FanStart to turn on the fan with the specified duty.
(Please refer to Graph)
Location:
Fan1Start - Bank 2 Address 20 HEX
Fan5Start - Bank 2 Address 24 HEX
Fan2Start - Bank 2 Address 21 HEX
Fan6Start - Bank 2 Address 25 HEX
Fan3Start - Bank 2 Address 22 HEX
Fan7Start - Bank 2 Address 26 HEX
Fan4Start - Bank 2 Address 23 HEX
Fan8Start - Bank 2 Address 27 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANSTART
Bit
Name
7
6
4
3
2
Reserved
FanStart
0
8 HEX
Reset
Bit
5
1
0
Description
- 87 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7-6
Reserved.
5-0
FanStart(Fan Output Start Duty Cycle).
8.11.2.15. Fan Output Stop Time Register (FanStopTime)
A time interval is specified to tell the W83793G when to turn off the fan if SmartFan continuously
requests to slow down the fan which has already reached the NonStop Level. The default is 10 sec.
(Please refer to Graph)
Location:
Fan1StopTime - Bank 2 Address 28 HEX
Fan5StopTime - Bank 2 Address 2C HEX
Fan2StopTime - Bank 2 Address 29 HEX
Fan6StopTime - Bank 2 Address 2D HEX
Fan3StopTime - Bank 2 Address 2A HEX
Fan7StopTime - Bank 2 Address 2E HEX
Fan4StopTime - Bank 2 Address 2B HEX
Fan8StopTime - Bank 2 Address 2F HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
FANSTOPTIME
Bit
7
6
5
Name
4
3
2
1
0
FanStopTime
Reset
64 HEX
Bit
Description
7-0
FanStopTime (Fan Stop time from Nonstop level to the off state).
Unit in 0.1sec. Ranges from 0.1sec to 25.5sec.
If set to 0, the fan will never stop.
8.11.2.16. Target Temperature of Temperature Inputs Register (TempTarget)
In Thermal Cruise mode, each temperature source has to have a target temperature. The
W83793G will try to tune the fan speed to keep the temperature of the target device around the
target temperature. The default target temperature for diode sensors is 40℃, and 32℃ for thermistor
sensors.
Location:
TD1Target - Bank 2 Address 10 HEX
TD2Target - Bank 2 Address 11 HEX
TD3Target - Bank 2 Address 12 HEX
Type:
Read / Write
TD4Target - Bank 2 Address 13 HEX
TR1Target - Bank 2 Address 14 HEX
TR2Target - Bank 2 Address 15 HEX
- 88 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TD1TARGET ~ TD4TARGET
Bit
7
Name
Reserved
TempTarget
0
28 HEX
Reset
6
5
4
3
2
1
Bit
Description
7
Reserved.
6-0
TempTarget. (the target temperature of the Diode Temperature sensor).
Unit in ℃
0
TR1TARGET ~ TR2TARGET
Bit
7
Name
Reserved
TempTarget
0
20 HEX
Reset
6
5
4
3
2
1
Bit
Description
7
Reserved.
6-0
TempTarget. (the target temperature of the Thermistor Temperature sensor).
Unit in ℃
0
See also: TolTemp, FanCtrlMode, Thermal Cruise mode.
- 89 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.11.2.17. SMART FANTMII Fan Transition Temperature Level Registers (TempLevel)
SMART FANTMII is an algorithm providing a table mapping mechanism to translate the temperature
information into output fan duties. The mapping table requires 2 domains for the translation. In the
table, a certain temperature corresponds to a certain duty. TempLevel (Temperature) and
TempFanLevel (Duty Cycle) are used to define the table. There are totally six tables reside in the
W83793G, one table per temperature channel and 7 entries per table. Therefore, TempLevel will
have 42 registers, and another 42 registers for TempFanLevel in this and next section.
Location:
TD2Level01 - Bank 2 Address 40 HEX
TD1Level01 - Bank 2 Address 30 HEX
TD1Level12 - Bank 2 Address 31 HEX
TD2Level12 - Bank 2 Address 41 HEX
TD1Level23 - Bank 2 Address 32 HEX
TD2Level23 - Bank 2 Address 42 HEX
TD1Level34 - Bank 2 Address 33 HEX
TD2Level34 - Bank 2 Address 43 HEX
TD1Level45 - Bank 2 Address 34 HEX
TD2Level45 - Bank 2 Address 44 HEX
TD1Level56 - Bank 2 Address 35 HEX
TD2Level56 - Bank 2 Address 45 HEX
TD1Level67 - Bank 2 Address 36 HEX
TD2Level67 - Bank 2 Address 46 HEX
Type:
Reset:
TD3Level01 - Bank 2 Address 50 HEX
TD3Level12 - Bank 2 Address 51 HEX
TD3Level23 - Bank 2 Address 52 HEX
TD3Level34 - Bank 2 Address 53 HEX
TD3Level45 - Bank 2 Address 54 HEX
TD3Level56 - Bank 2 Address 55 HEX
TD3Level67 - Bank 2 Address 56 HEX
TD4Level01 - Bank 2 Address 60 HEX
TD4Level12 - Bank 2 Address 61 HEX
TD4Level23 - Bank 2 Address 62 HEX
TD4Level34 - Bank 2 Address 63 HEX
TD4Level45 - Bank 2 Address 64 HEX
TD4Level56 - Bank 2 Address 65 HEX
TD4Level67 - Bank 2 Address 66 HEX
TR1Level01 - Bank 2 Address 70 HEX
TR1Level12 - Bank 2 Address 71 HEX
TR1Level23 - Bank 2 Address 72 HEX
TR1Level34 - Bank 2 Address 73 HEX
TR1Level45 - Bank 2 Address 74 HEX
TR1Level56 - Bank 2 Address 75 HEX
TR1Level67 - Bank 2 Address 76 HEX
Read / Write
TR2Level01 - Bank 2 Address 80 HEX
TR2Level12 - Bank 2 Address 81 HEX
TR2Level23 - Bank 2 Address 82 HEX
TR2Level34 - Bank 2 Address 83 HEX
TR2Level45 - Bank 2 Address 84 HEX
TR2Level56 - Bank 2 Address 85 HEX
TR2Level67 - Bank 2 Address 86 HEX
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TD1LEVEL01 ~ TR2LEVEL01
Bit
7
Name
Reserved
TempLevel01
0
1E HEX
Reset
6
5
4
3
2
1
0
- 90 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7
Reserved.
6-0
TempLevel01. (Temperature Level between TempFanLevel0 and TempFanLevel1).
Unit in ℃
TD1LEVEL12 ~ TR2LEVEL12
Bit
7
Name
Reserved
TempLevel12
0
23 HEX
Reset
6
5
4
3
2
1
0
Bit
Description
7
Reserved.
6-0
TempLevel12. (Temperature Level between TempFanLevel1 and TempFanLevel2).
Unit in ℃
TD1LEVEL23 ~ TR2LEVEL23
Bit
7
Name
Reserved
TempLevel23
0
28 HEX
Reset
6
5
4
3
2
1
0
Bit
Description
7
Reserved.
6-0
TempLevel23. (Temperature Level between TempFanLevel2 and TempFanLevel3).
Unit in ℃
TD1LEVEL34 ~ TR2LEVEL34
Bit
7
Name
Reserved
TempLevel34
0
2D HEX
Reset
Bit
6
5
4
3
2
1
0
Description
- 91 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7
Reserved.
6-0
TempLevel34. (Temperature Level between TempFanLevel3 and TempFanLevel4).
Unit in ℃
TD1LEVEL45 ~ TR2LEVEL45
Bit
7
Name
Reserved
TempLevel45
0
32 HEX
Reset
6
5
4
3
2
1
0
Bit
Description
7
Reserved.
6-0
TempLevel45. (Temperature Level between TempFanLevel4 and TempFanLevel5).
Unit in ℃
TD1LEVEL56 ~ TR2LEVEL56
Bit
7
Name
Reserved
TempLevel56
0
37 HEX
Reset
6
5
4
3
2
1
0
Bit
Description
7
Reserved.
6-0
TempLevel56. (Temperature Level between TempFanLevel5 and TempFanLevel6).
Unit in ℃
TD1LEVEL67 ~ TR2LEVEL67
Bit
7
Name
Reserved
TempLevel67
0
3C HEX
Reset
Bit
6
5
4
3
2
1
0
Description
- 92 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7
Reserved.
6-0
TempLevel67. (Temperature Level between TempFanLevel6 and TempFanLevel7).
Unit in ℃
See also: TolTemp, FanCtrlMode, Smart Fan II mode.
8.11.2.18. Smart Fan II Fan Output Levels Registers (TempFanLevel)
The previous section describes one temperature axis of SMART FANTMII Table. Here introduced Fan
Duty axis for the table, TempFanLevel registers.
Location:
TD1FanLevel0 - Bank 2 Address 38 HEX
TD2FanLevel0 - Bank 2 Address 48 HEX
TD1FanLevel1 - Bank 2 Address 39 HEX
TD2FanLevel1 - Bank 2 Address 49 HEX
TD1FanLevel2 - Bank 2 Address 3A HEX
TD2FanLevel2 - Bank 2 Address 4A HEX
TD1FanLevel3 - Bank 2 Address 3B HEX
TD2FanLevel3 - Bank 2 Address 4B HEX
TD1FanLevel4 - Bank 2 Address 3C HEX
TD2FanLevel4 - Bank 2 Address 4C HEX
TD1FanLevel5 - Bank 2 Address 3D HEX
TD2FanLevel5 - Bank 2 Address 4D HEX
TD1FanLevel6 - Bank 2 Address 3E HEX
TD2FanLevel6 - Bank 2 Address 4E HEX
TD3FanLevel0 - Bank 2 Address 58 HEX
TD3FanLevel1 - Bank 2 Address 59 HEX
TD3FanLevel2 - Bank 2 Address 5A HEX
TD3FanLevel3 - Bank 2 Address 5B HEX
TD3FanLevel4 - Bank 2 Address 5C HEX
TD3FanLevel5 - Bank 2 Address 5D HEX
TD3FanLevel6 - Bank 2 Address 5E HEX
TD4FanLevel0 - Bank 2 Address 68 HEX
TD4FanLevel1 - Bank 2 Address 69 HEX
TD4FanLevel2 - Bank 2 Address 6A HEX
TD4FanLevel3 - Bank 2 Address 6B HEX
TD4FanLevel4 - Bank 2 Address 6C HEX
TD4FanLevel5 - Bank 2 Address 6D HEX
TD4FanLevel6 - Bank 2 Address 6E HEX
TR1FanLevel0 - Bank 2 Address 78 HEX
TR1FanLevel1 - Bank 2 Address 79 HEX
TR1FanLevel2 - Bank 2 Address 7A HEX
TR1FanLevel3 - Bank 2 Address 7B HEX
TR1FanLevel4 - Bank 2 Address 7C HEX
TR1FanLevel5 - Bank 2 Address 7D HEX
TR1FanLevel6 - Bank 2 Address 7E HEX
TR2FanLevel0 - Bank 2 Address 88 HEX
TR2FanLevel1 - Bank 2 Address 89 HEX
TR2FanLevel2 - Bank 2 Address 8A HEX
TR2FanLevel3 - Bank 2 Address 8B HEX
TR2FanLevel4 - Bank 2 Address 8C HEX
TR2FanLevel5 - Bank 2 Address 8D HEX
TR2FanLevel6 - Bank 2 Address 8E HEX
Type:
Reset:
Read / Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set,
SYSRSTIN_N (Pin 15) Falling @ SYSRST_MD (CR40.Bit5) set.
TD1FANLEVEL0 ~ TR2FANLEVEL0
- 93 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
7
Name
6
5
4
3
2
Reserved
TempFanLevel0
0
08 HEX
Reset
Bit
Description
7-6
Reserved.
5-0
TempFanLevel0. (Fan Output Level 0).
1
0
1
0
1
0
1
0
TD1FANLEVEL1 ~ TR2FANLEVEL1
Bit
7
Name
6
5
4
3
2
Reserved
TempFanLevel1
0
0C HEX
Reset
Bit
Description
7-6
Reserved.
5-0
TempFanLevel1. (Fan Output Level 1).
TD1FANLEVEL2 ~ TR2FANLEVEL2
Bit
7
Name
6
5
4
3
2
Reserved
TempFanLevel2
0
10 HEX
Reset
Bit
Description
7-6
Reserved.
5-0
TempFanLevel2. (Fan Output Level 2).
TD1FANLEVEL3 ~ TR2FANLEVEL3
Bit
Name
Reset
7
6
5
4
3
2
Reserved
TempFanLevel3
0
18 HEX
- 94 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7-6
Reserved.
5-0
TempFanLevel3. (Fan Output Level 3).
TD1FANLEVEL4 ~ TR2FANLEVEL4
Bit
7
Name
6
5
4
3
2
Reserved
TempFanLevel4
0
20 HEX
Reset
Bit
Description
7-6
Reserved.
5-0
TempFanLevel4. (Fan Output Level 4).
1
0
1
0
1
0
TD1FANLEVEL5 ~ TR2FANLEVEL5
Bit
7
Name
6
5
4
3
2
Reserved
TempFanLevel5
0
30 HEX
Reset
Bit
Description
7-6
Reserved.
5-0
TempFanLevel5. (Fan Output Level 5).
TD1FANLEVEL6 ~ TR2FANLEVEL6
Bit
Name
7
6
5
4
3
2
Reserved
TempFanLevel6
0
38 HEX
Reset
Bit
Description
7-6
Reserved.
5-0
TempFanLevel6. (Fan Output Level 6).
- 95 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
See also: TolTemp, FanCtrlMode, Smart Fan II mode.
8.12 PECI Control Registers
Intel® new generation CPUs such as Presler begin to support new single wire digital temperature
monitoring interface which is called Platform Environment Control Interface or PECI. The W83793G
supports the PECI* version 1.0 for these new generation CPUs. All PECI control registers are
located in Bank 0. Pin 1, PCLK, is the timing base of PECI control circuit. If PECI function is needed,
Pin 1 is required to feed a 48MHz clock.
The W83793G PECI configuration, including the PECI address and number of domains, must match
the CPU type. BIOS have to detect which kind of CPU it is and program the correct configuration in
the W83793G.
- 96 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.12.1 PECI Register Map
Mnemonic
Register Name
Type
AgtConfig
Agent Configuration Register
RW
Agt1Tcase
|
Agt4Tcase
Tcase Register
RW
ReportStyle
PECI Report Temperature Style Register
RW
PECI Warning Flag Register
RO
Agent Relative Temperature Registers
RO
PECIWarning
Agt1RelTempH/L
|
Agt4RelTempH/L
Three control registers and 2 status registers are listed here. The detailed operation of the PECI host
is shown in the figure below.
- 97 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Every
time the W83793G PECI host detects that the user enables an agent by setting AgtEn, it start to
Ping. If the client exists, it continues to issue GetTemp0 or GetTemp1 (when DM1Exist is asserted).
If there is no client, it sets a PECIAbsent flag to inform the host. A fault queue is made to ensure that
the host can obtain correct temperatures. However, consecutive 3 FCS errors indicate that the data
is invalid. The PECI warning flag will be set.
- 98 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.12.2 PECI Register Details
8.12.2.1. Agent Configuration Register (AgtConfig)
This register commands the PECI host to process related agents and domains. Only the agent or
domain specified in this register will process PECI transactions. It is reset to 00 HEX .
Location: AgtConfig - Bank 0 Address D0 HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set.
AGTCONFIG
Bit
7
Name
Agt4EN
Agt3EN
Agt2EN
0
0
0
Reset
6
5
4
3
2
1
0
Agt1EN
Agt4D1
Agt3D1
Agt2D1
Agt1D1
0
0
0
0
0
Bit
Description
7
Agt4EN (Agent 4 Enable Bit).
0 BIN : Agent 4 is disabled.
1 BIN : Agent 4 is enabled.
6
Agt3EN (Agent 3 Enable Bit).
0 BIN : Agent 3 is disabled.
1 BIN : Agent 3 is enabled.
5
Agt2EN (Agent 2 Enable Bit).
0 BIN : Agent 2 is disabled.
1 BIN : Agent 2 is enabled.
4
Agt1EN (Agent 1 Enable Bit).
0 BIN : Agent 1 is disabled.
1 BIN : Agent 1 is enabled.
3
Agt4D1 (Agent 4 Domain 1 Enable Bit).
0 BIN : Agent 4 does not have domain 1.
1 BIN : Agent 4 has domain 1.
2
Agt3D1 (Agent 3 Domain 1 Enable Bit).
0 BIN : Agent 3 does not have domain 1.
1 BIN : Agent 3 has domain 1.
1
Agt2D1 (Agent 2 Domain 1 Enable Bit).
0 BIN : Agent 2 does not have domain 1.
1 BIN : Agent 2 has domain 1.
0
Agt1D1 (Agent 1 Domain 1 Enable Bit).
0 BIN : Agent 1 does not have domain 1.
1 BIN : Agent 1 has domain 1.
- 99 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.12.2.2. Agent TCase Register (AgtTcase)
Intel® CPU introduces a Tcase concept on the temperature management. In Presler generation CPUs,
Tcase can be read from the CPU register by BIOS and refills the value to the W83793G registers. The
default setting is 70℃, which is 10℃ higher than TempLevel67. In later generation CPUs, the CPU
might only respond with the Tcase value as an offset temperature to PROCHOT# assertion. It is reset
to 46 HEX .
Location:
Agt1TCase - Bank 0 Address D1 HEX
Agt3TCase - Bank 0 Address D3 HEX
Agt2TCase - Bank 0 Address D2 HEX
Agt4TCase - Bank 0 Address D4 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set.
AGT1TCASE~AGT4TCASE
Bit
7
Name
Reserved
Reset
6
5
4
3
2
1
0
TCase Temperature
0
1
0
0
0
1
1
0
Bit
Description
7
Reserved.
6-0
TCase( TCase Temperature Setting).
TCase must always be a positive value; a negative value will introduce abnormal
temperature response.
8.12.2.3. PECI Report Temperature Style Register (ReportStyle)
ReportStyle controls which value to be loaded into Absolute Temp or Relative Temp.
If RtHigh = 1, the PECI host will automatically compare the highest temperature domain and load it into
Abs/Rel-Temp. If RtHigh = 0, RtDm will return Domain 0 temperature to the W83793G if the register is
set to 0, and return Domain 1 temperature to the W83793G if the register is set to 1. It is reset to
00 HEX .
Location: ReportStyle - Bank 0 Address D5 HEX
Type:
Read / Write
Reset:
VSB5V (Pin 7) Rising,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set.
REPORTSTYLE
Bit
Name
7
6
Reserved
5
4
3
RtHigh
2
RTD4
1
RTD3
0
RTD2
RTD1
- 100 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset
0
0
0
0
0
0
0
0
Bit
Description
7-5
Reserved.
4
RtHigh (Return High Temperature).
0 BIN : Return the domain temperature by RTD selection (RTD1~RTD4).
1 BIN : Return the highest temperature in the same agent.
3
RtD4 (Agent 4 Return Domain 1 Enable Bit). Only takes effect when RtHigh deasserts.
0 BIN : Agent 4 always returns the temperature from domain 0.
1 BIN : Agent 4 always returns the temperature from domain 1.
2
RtD3 (Agent 3 Return Domain 1 Enable Bit). Only takes effect when RtHigh deasserts.
0 BIN : Agent 3 always returns the temperature from domain 0.
1 BIN : Agent 3 always returns the temperature from domain 1.
1
RtD2 (Agent 2 Return Domain 1 Enable Bit). Only takes effect when RtHigh deasserts.
0 BIN : Agent 2 always returns the temperature from domain 0.
1 BIN : Agent 2 always returns the temperature from domain 1.
0
RtD1 (Agent 1 Return Domain 1 Enable Bit). Only takes effect when RtHigh deasserts.
0 BIN : Agent 1 always returns the temperature from domain 0.
1 BIN : Agent 1 always returns the temperature from domain 1.
8.12.2.4. PECI Warning Flag Register (PECIWarning)
Few warnings may be generated when the PECI protocol is applied. First, the PECI host may not be
able to detect a PECI Client (or the client does not respond to the host Ping() command). In this case,
PECI issues a flag called “Absent” to inform users that it cannot detect the client. Another case is that
the PECI Client returns invalid FCS in successive 3 time polling; the host will issue an Alert flag. It is
reset to 00 HEX .
Location: PECIWarning - Bank 0 Address D6 HEX
Type:
Read Only
Reset:
VSB5V (Pin 7) Rising,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set.
PECIWARNING
Bit
7
6
5
4
Name
Absent4
Absent3
Absent2
Absent1
Alert4
Alert3
Alert2
Alert1
0
0
0
0
0
0
0
0
Reset
Bit
Description
7
Absent4 (PECI Agent 4 Absent Bit).
0 BIN : Agent 4 is detected.
3
2
1
0
- 101 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
1 BIN : Agent 4 cannot be detected.
6
Absent3 (PECI Agent 3 Absent Bit).
0 BIN : Agent 3 is detected.
1 BIN : Agent 3 cannot be detected.
5
Absent2 (PECI Agent 2 Absent Bit).
0 BIN : Agent 2 is detected.
1 BIN : Agent 2 cannot be detected.
4
Absent1 (PECI Agent 1 Absent Bit).
0 BIN : Agent 1 is detected.
1 BIN : Agent 1 cannot be detected.
3
Alert4 (PECI Agent 4 Alert Bit).
0 BIN : Agent 4 has good FCS.
1 BIN : Agent 4 has bad FCS in last 3 transactions.
2
Alert3 (PECI Agent 3 Alert Bit).
0 BIN : Agent 3 has good FCS.
1 BIN : Agent 3 has bad FCS in last 3 transactions.
1
Alert2 (PECI Agent 2 Alert Bit).
0 BIN : Agent 2 has good FCS.
1 BIN : Agent 2 has bad FCS in last 3 transactions.
0
Alert1 (PECI Agent 1 Alert Bit).
0 BIN : Agent 1 has good FCS.
1 BIN : Agent 1 has bad FCS in last 3 transactions.
While PECI is activated, Alert flag will be asserted when the corresponding agent returns invalid FCS
for successive 3 times. In this case, the W83793G will think this agent has problems in the interface,
and for safety reason the W83793G will turn on the related fan to full speed in SmartFan mode. The
fan and PECI agent relationship is defined in TempFanSelect registers.
8.12.2.5. Agent Relative Temperature Register (AgtRelTemp)
These registers return the raw data retrieved from PECI. The data may be the error code (range:
8000H~81FFH) or relative temperatures to process the defined Tcase. The error code will only be
update in AgtRelTemp, Absolute Temperature will not be updated when the error code is received. If
the ReturnHigh mechanism is activated, the normal temperature will always be returned first. In case
both 2 domains return errors, the return priority will be Overflow Error > Underflow Error > Missing
Diode > General Error. The reset value is 8001 HEX, in that PECI is defaulted to be off. In PECI,
8001 HEX means the diode is missing.
Location:
Agt1RelTempH - Bank 0 Address D8 HEX
Agt1RelTempL - Bank 0 Address D9 HEX
Agt2RelTempH - Bank 0 Address DA HEX
Agt2RelTempL - Bank 0 Address DB HEX
Type:
Read Only
Agt3RelTempH - Bank 0 Address DC HEX
Agt3RelTempL - Bank 0 Address DD HEX
Agt4RelTempH - Bank 0 Address DE HEX
Agt4RelTempL - Bank 0 Address DF HEX
- 102 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset:
VSB5V (Pin 7) Rising,
VDD5V (Pin 25) Rising @ RST_VDD_MD (CR40.Bit4) set.
AGT1RELTEMPH/L~AGT4RELTEMPH/L
Bit
7
Name
6
5
4
Sign
Reset
1
Name
Reset
3
2
1
0
Temperature[8:2]
0
0
0
0
0
0
0
Temperature[1:0]
TEMP_2
TEMP_4
TEMP_8
TEMP_16
TEMP_32
TEMP_64
0
0
0
0
0
0
1
0
Bit
Description
15
Sign Bit. In PECI Protocol, this bit should always be 1 to represent a negative
temperature.
14-6
Temperature
The integer part of the relative temperature.
5
TEMP_2. 0.5℃ unit.
4
TEMP_4. 0.25℃ unit.
3
TEMP_8. 0.125℃ unit.
2
TEMP_16. 0.0625℃ unit.
1
TEMP_32. 0.03125℃ unit.
0
TEMP_64. 0.015625℃ unit.
On some occasions, PECI will return the abnormal states of the PECI bus in addition to the
temperature. All the information will be recorded in AgtRelTemp. In some cases, the W83793G will
also do further processing for the alert mechanism. The following describes these codes and their
effects to the W83793G.
Error
Code
Description
W83793G host operation
8000 HEX
General Sensor Error
No further processing.
8001 HEX
Sensing Device Missing
8002 HEX
Operational,
but
the
temperature is lower than
the sensor operation range.
Compulsorily write 0℃ back to the temperature
readouts.(Bank 0 Index 1C HEX ~ 1F HEX )
8003 HEX
Operational,
but
the
temperature is higher than
the sensor operation range.
compulsorily write 127℃ back to the temperature
readouts.(Bank 0 Index 1C HEX ~ 1F HEX )
8004 HEX
Reserved.
No further operation.
81FF HEX
Besides error conditions or invalid FCS, the normal temperature will be written back to Temperature
Readouts with the sum of AgtRelTemp value and Tcase value.
- 103 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.13 ASF Control Registers
ASF or Alert Standard Format provides remote system abilities to monitor, discover and manage the
local platform. All ASF control registers are located in Bank 1*.
*About the Bank Selection, please refer to the Bank Select register located at address 00 Hex.
- 104 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.13.1 ASF Register Map
8.13.1.1. SMBus ARP UDID Control Registers
Mnemonic
Register Name
Type
UDIDDevCap.
UDID Device Capability Register
RO
UDIDVersion.
UDID Version Number Register
RO
UDIDVendorH.
UDIDVendorL.
UDID Vendor ID High/Low Byte Register
RO
UDIDDevH.
UDIDDevL.
UDID Device ID High/Low Byte Register
RW
UDIDIFH.
UDIDIFL.
UDID Interface High/Low Byte Register
RW
UDIDSubVenH.
UDIDSubVenL.
UDID Subsystem
Registers
Vendor
ID
High/Low
Byte
UDIDSubDevH.
UDIDSubDevL.
UDID Subsystem
Registers
Device
ID
High/Low
Byte
RW
RW
UDIDSpeID1.
UDID Vendor Specific ID Byte 1~4
RW
Random Number Generator Byte 1~4
RO
ASF Assigned Address Register
RO
UDIDSpeID4.
RNG1.
RNG4.
ASFAddr.
Before activating ASF, the user must go through the ARP (Address Resolution Protocol) to
dynamically obtain a valid address to manipulate ASF commands. In ARP, it is very important that
UDID (Unique Device Identifier) is defined to distinguish different devices. Registers in this section are
used to set up UDID.
For detailed operation of ARP and UDID, please refer to SMBus Specification version 2.0
(http://www.smbus.org/specs/smbus20.pdf ) section 5.6 in page 34.
8.13.1.2. ASF Sensor Entity Definition Registers
In ASF Sensor, each sensor channel has 2 parameters, entity Instance and entity ID, to tell the ASF
host its related location information on the platform. If the user uses the temperature sensor in
locations different from the default, the W83793G provides all channel parameters that can be
programmed to fit customers’ application.
Mnemonic
Register Name
Type
VCA_ENTY.
VCoreA Entity ID Register
RW
- 105 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
VCB_ENTY.
VCoreB Entity ID Register
RW
Vtt_ENTY.
Vtt Entity ID Register
RW
VDD_ENTY.
VDD Entity ID Register
RW
VSB_ENTY.
VSB Entity ID Register
RW
VBAT_ENTY.
VBAT Entity ID Register
RW
VSEN1_ENTY.
VSEN4_ENTY.
FAN1_ENTY.
FAN12_ENTY.
VSEN1~VSEN4
Register
FAN1~FAN12
Register
Entity
Entity
ID
ID
RW
RW
TD1_ENTY.
TD1~TR2 Entity ID Register
RW
Chassis Entity Register
RW
TR2_ENTY.
CHS_ENTY.
For details of entity ID, please refer to Platform Event Trap Format Specification Version 1.0 Table 6 in
page 13.
Mnemonic
Register Name
Type
ENTINS1.
VCoreA/VCoreB Entity Instance Register
RW
ENTINS2.
VDD/Vtt Entity Instance Register
RW
ENTINS3.
VBAT/VSB Entity Instance Register
RW
ENTINS4.
VIN1/VIN2 Entity Instance Register
RW
ENTINS5.
VIN3/VIN4 Entity Instance Register
RW
ENTINS6.
FAN1/FAN2 Entity Instance Register
RW
ENTINS7.
FAN3/FAN4 Entity Instance Register
RW
- 106 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
ENTINS8.
FAN5/FAN6 Entity Instance Register
RW
ENTINS9.
FAN7/FAN8 Entity Instance Register
RW
ENTINS10.
FAN9/FAN10 Entity Instance Register
RW
ENTINS11.
FAN11/FAN12 Entity Instance Register
RW
ENTINS12.
TD1/TD2 Entity Instance Register
RW
ENTINS13.
TD3/TD4 Entity Instance Register
RW
ENTINS14.
TR1/TR2 Entity Instance Register
RW
ENTINS15.
Chassis Entity Instance Register
RW
Entity Instance is a sequential number which helps identify the sensor’s location. The customer can
set preferable sequence orders.
The summary of Entity and Entity Instance is in the following table.
Sensor in
W83793G
Event
Status
Index
Event Sensor Type
Event
Number
VCOREA
00h
02h
01h
Entity ID
(Programmable)
Entity Instance
(Programmable)
01h
03h
(Processor)
VCOREB
01h
02h
02h
02h
Vtt
02h
02h
03h
TD1
03h
01h (Temperature) 04h
TD2
04h
01h
05h
TD3
05h
01h
06h
03h
TD4
06h
01h
07h
04h
TR1
07h
01h
08h
05h
TR2
08h
01h
09h
06h
5VDD
09h
02h
0Ah
01h
VSB
0Ah
02h
0Bh
02h
VBAT
0Bh
02h
0Ch
03h
VSEN1
0Ch
02h (Voltage)
0Dh
04h
03h
07h
(System Board)
01h
02h
- 107 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Sensor in
W83793G
Event
Status
Index
Event Sensor Type
Event
Number
VSEN2
0Dh
02h
0Eh
05h
VSEN3
0Eh
02h
0Fh
06h
VSEN4
0Fh
02h
10h
07h
FAN1
10h
04h (Fan)
11h
01h
FAN2
11h
04h
12h
02h
FAN3
12h
04h
13h
03h
FAN4
13h
04h
14h
04h
FAN5
14h
04h
15h
05h
FAN6
15h
04h
16h
06h
FAN7
16h
04h
17h
07h
FAN8
17h
04h
18h
08h
FAN9
18h
04h
19h
09h
FAN10
19h
04h
1Ah
0Ah
FAN11
1Ah
04h
1Bh
0Bh
FAN12
1Bh
04h
1Ch
0Ch
05h
(Physical
Security)
1Dh
Case OPEN
1Ch
/ Intrusion
Entity ID
(Programmable)
23h
(System Chassis)
Entity Instance
(Programmable)
01h
The channels in light-green can be disabled by multi-function pin selection or control registers.
The channels are described in the following terms according to the status of each channel.
Description
Status
Event Sensor
Type
Event Type
Event
Offset
Event Severity
TEMPERATURE SENSORS
Upper-Critical
High
Going
Upper-Critical
Low
Going
Upper-Non-critical Going
High
09h
01h
Temperature
Upper-Non-critical Going
Low
Lower-Non-critical Going
High
Lower-Non-critical Going
Low
08h
3h
Assert
01h
ThresholdBased
07h
06h
01h
2h
Deassert
00h
10h
Critical
08h
Non-critical
01h
Monitor
VOLTAGE SENSORS
Generic Over Voltage
3h
02h
07h
- 108 –7
02h
10h
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Status
Event Sensor
Type
Event Type
Event
Offset
Event Severity
Normal Voltage
2h
Voltage
07h
01h
Generic Under Voltage
Problem
GenericSeverity
3h
02h
10h
07h
01h
02h
10h
00h
10h
80h
01h
Description
Problem
FAN SENSORS
Normal FAN Speed
2h
Generic FAN Failure
3h
04h
Fan
07h
05h
Physical
Security
6Fh
Sensor
Specific
CASEOPEN/ CASE INTRUSION
Case Intruded
3h
Case Normal
2h
8.13.1.3. ASF Remote Control Definition Registers
ASF function in the W83793G also supports Remote Control. This function enables Management
Information System (MIS) to remotely power on, power down, or reset the client’s computer when
there is abnormal operation.
Mnemonic
Register Name
Type
PwrOnOption.
Power On Control Option Register
RW
PwrOnCmd.
Remote Control Power On Command Register
RW
PwrOffCmd.
Remote Control Power Down Command Register
RW
RstCmd.
Remote Control Reset Command Register
RW
The Remote Control function in the W83793G enables MIS to use side-band of Network Interface
Controller to send ASF commands with SMBus. The format looks like
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address
Wr
A
Command
A
Write Data
A
PEC
A
P
Control Device
Address
0
0
Control
Command
0
Control
Value
0
CRC
Checksum
0
Data
”S“ represents “Start” Cycle of SMBus transaction; ”Wr“ means “Write” Flag; ”A“ means
“Acknowledge” from the W83793G, and ”P“ indicates a “Stop” Cycle. Letters in shadow mean
responses from the W83793G. Otherwise, it is a host transmitted signal.
- 109 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
The last row above shows the meaning of each data. Control Device Address is the address assigned
in the ARP process; Control Command is specified in the above registers. Control Data option is not
supported in the W83793G. Thus with any value in this field, the W83793G will perform the same
action.
Please refer to Section 5.4 in page 76 and Section 3.2.4.1 in page 33 in Alert Standard Format
Specification v2.0 for more details.
- 110 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
8.13.2 ASF Register Details
8.13.2.1. UDID Device Capability Register (UDIDDevCap)
SMBus Specification Working Group intends to use device capability to distinguish the arbitration
priority of GeneralGetUDID() first. Thus the very first byte of the UDID is device capability, because
SMBus is a MSB first serial protocol and if the client was pulled low, it wins the arbitration. It is set as
C1 HEX .
Location: UDIDVersion - Bank 1 Address 20 HEX
Type:
Read Only
Reset:
No Reset.
UDIDDEVCAP
Bit
7
Name
6
5
4
3
1
1
0
Reserved
Address Type
Reset
2
1
0
0
PEC
0
0
0
1
Bit
Description
7-6
Address Type.
00 BIN : Fixed address device. It’s the highest priority device.
01 BIN : Dynamic and persistent address device.
10 BIN : Dynamic and volatile address device. If powered-down, the address needs to
be reassigned at next power on. The W83793G ASF address will be lost if 5VSB does
not exist.
11 BIN : Random number device.
5-1
Reserved.
0
PEC Support.
0: PEC (Packet Error Code) is not supported on this device.
1: PEC is supported on this device.
8.13.2.2. UDID Version Number Register (UDIDVersion)
This field defines the version of UDID and Silicon for the W83793G. It is 08 HEX .
Location: UDIDVersion - Bank 1 Address 21 HEX
Type:
Read Only
Reset:
No Reset
UDIDVERSION
Bit
Name
7
6
Reserved
5
4
3
UDID Version
2
1
0
Silicon Version
- 111 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Fixed
0
0
0
0
1
0
0
Bit
Description
7-6
Reserved.
5-3
UDID Version.
000 BIN : Reserved.
001 BIN : UDID version 1.
010 BIN -111 BIN : Reserved for future use.
2-0
Silicon Version.
For the identification of the W83793G silicon version. 000 BIN stands for Version A/B.
0
8.13.2.3. UDID Vendor ID High/Low Byte Register (UDIDVendorH/L)
This field defines Nuvoton vendor ID. The default is 1050 HEX.
Location: UDIDVendorH - Bank 1 Address 22 HEX
UDIDVendorL - Bank 1 Address 23 HEX
Type:
Read Only
Reset:
No Reset
UDIDVENDORH
Bit
7
6
5
4
Name
3
2
1
0
Vendor ID High Byte
Fixed
0
0
0
1
0
0
0
0
UDIDVENDORL
Bit
7
6
5
4
Name
2
1
0
Vendor ID Low Byte
Fixed
Bit
3
0
1
0
1
0
0
0
0
Description
15-0
Nuvoton Vendor ID.
8.13.2.4. UDID Device ID High/Low Byte Register (UDIDDevH/L)
This field defines Nuvoton device ID. The default is 0100 HEX.
Location:
- 112 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
UDIDDevH - Bank 1 Address 24 HEX
UDIDDevL - Bank 1 Address 25 HEX
Read Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set.
Type:
Reset:
UDIDDEVH
Bit
7
6
5
4
Name
3
2
1
0
Device ID High Byte
Reset
0
0
0
0
0
0
0
1
UDIDDEVL
Bit
7
6
5
4
Name
2
1
0
Device ID Low Byte
Reset
Bit
3
0
0
0
0
0
0
0
0
Description
15-0
Nuvoton Device ID.
8.13.2.5. UDID Interface High/Low Byte Register (UDIDIFH/L)
This field defines SMBus version and the supported protocol. It is reset to 0024 HEX.
Location:
UDIDIFH - Bank 1 Address 26 HEX
UDIDIFL - Bank 1 Address 27 HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set.
UDIDIFH
Bit
7
6
5
4
3
Name
2
1
0
Reserved
Reset
0
0
0
0
0
0
0
0
UDIDIFL
Bit
7
6
5
4
3
2
1
0
- 113 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Name
Reserved
IPMI
ASF
OEM
0
0
1
0
Reset
SMBus Version
0
1
0
0
Bit
Description
15-7
Reserved.
6
IPMI. This device supports additional interface access capability per IPMI
specification.
0: Not supported.
1: Supported.
5
ASF. This device supports additional interface access capability per ASF specification.
0: Not supported.
1: Supported.
4
OEM. Device supports vendor specific access capability per Subsystem Vendor ID
and Subsystem Device ID.
0: Not supported.
1: Supported.
3-0
SMBus Version
0 HEX : SMBus 1.0, not ARPable.
1 HEX : SMBus 1.1, not ARPable.
4 HEX : SMBus 2.0.
8.13.2.6. UDID Subsystem Vendor ID High/Low Byte Register (UDIDSubVenH/L)
This field defines UDID support for Subsystems. If no subsystem is supported, it must be written with
0000 HEX . It is reset to 0000 HEX.
Location: UDIDSubVenH - Bank 1 Address 28 HEX
UDIDSubVenL - Bank 1 Address 29 HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set.
UDIDSUBVENH
Bit
7
6
5
Name
4
3
2
1
0
UDID Subsystem Vendor ID High Byte
Reset
0
0
0
0
0
0
0
0
UDIDSUBVENL
Bit
Name
7
6
5
4
3
2
1
0
UDID Subsystem Vendor ID Low Byte
- 114 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset
Bit
0
0
0
0
0
0
0
0
Description
15-0
UDID subsystem Vendor.
8.13.2.7. UDID Subsystem Device ID High/Low Byte Register (UDIDSubDevH/L)
This field defines UDID support for Subsystems. If no subsystem is supported, it must be written with
0000 HEX . It is reset to 0000 HEX.
Location: UDIDSubDevH - Bank 1 Address 2A HEX
UDIDSubDevL - Bank 1 Address 2B HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set.
UDIDSUBVENH
Bit
7
6
5
Name
4
3
2
1
0
UDID Subsystem Device ID High Byte
Reset
0
0
0
0
0
0
0
0
UDIDSUBVENL
Bit
7
6
5
Name
Reset
Bit
15-0
4
3
2
1
0
UDID Subsystem Device ID Low Byte
0
0
0
0
0
0
0
0
Description
UDID subsystem Device ID.
8.13.2.8. UDID Vendor-Specific ID Register (UDIDSpecID1/2/3/4)
This field defines unique Vendor-Specific ID for different versions of the W83793G. With this field,
different W83793G will be identified on the same SMBus interface. This register will be loaded with
a random number when receiving the reset signal.
Location:
UDIDSpecID1 - Bank 1 Address 2C HEX
UDIDSpecID2 - Bank 1 Address 2D HEX
UDIDSpecID3 - Bank 1 Address 2E HEX
UDIDSpecID4 - Bank 1 Address 2F HEX
- 115 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Type:
Reset:
Read Write
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
ARP ResetDevice Command.
UDIDSPECID1~UDIDSPECID4
Bit
7
6
5
4
Name
3
2
1
0
UDID Specific Vendor ID
Reset
0
0
0
Bit
Description
31-0
UDID Vendor-Specific ID.
0
0
0
0
0
8.13.2.9. Random Number Generator Register (RNG1/2/3/4)
The W83793G internally generates pseudo random numbers by using CRC generator and internal
clock. Due to the deviations of the internal clock, different IC and different power-on time will affect the
results of the random numbers. It is reset to FFFF HEX.
Location:
RNG4 - Bank 1 Address 30 HEX
RNG3 - Bank 1 Address 31 HEX
Type:
Read Only
Reset:
None.
RNG2 - Bank 1 Address 32 HEX
RNG1 - Bank 1 Address 33 HEX
RNG1~RNG4
Bit
7
6
5
4
Name
Reset
3
2
1
0
Random Number Code
0
0
Bit
Description
31-0
Random Number Code.
0
0
0
0
0
0
8.13.2.10. ASF Assigned Address Register (ASFAddr)
After the ARP host obtains related device UDID, it will start to assign each device for later use. The
W83793G will record this assigned address and set it as the default address for ASF transactions. It
is reset to 00 HEX.
Location: ASFAddr - Bank 1 Address 4F HEX
- 116 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Type:
Reset:
Read Only
VSB5V (Pin 7) Rising,
Init Reset (CR40.Bit7) is set,
ASFADDR
Bit
7
6
5
4
Name
3
2
1
0
ASF Address
Reset
0
0
0
0
0
0
0
Bit
Description
31-0
ASF Address. This register will be assigned while ARP AssignAddress command
issued.
0
8.13.2.11. ASF Entity/Instance Registers (ENITIY/ENTINS)
The W83793G supports various channels which can be reported to the host through ASF protocol.
Each sensor channel is associated with an entity (or location on the motherboard) and entity instance.
The Table provides an overall look for these registers.
Location:
VCA_ENTY - Bank 1 Address 50 HEX
VCB_ENTY - Bank 1 Address 51 HEX
Vtt_ENTY - Bank 1 Address 52 HEX
VDD_ENTY - Bank 1 Address 53 HEX
VSB_ENTY - Bank 1 Address 54 HEX
VBAT_ENTY - Bank 1 Address 55 HEX
VSEN1_ENTY - Bank 1 Address 56 HEX
VSEN2_ENTY - Bank 1 Address 57 HEX
VSEN3_ENTY - Bank 1 Address 58 HEX
VSEN4_ENTY- Bank 1 Address 59 HEX
FAN1_ENTY - Bank 1 Address 5A HEX
FAN2_ENTY - Bank 1 Address 5B HEX
FAN3_ENTY - Bank 1 Address 5C HEX
FAN4_ENTY - Bank 1 Address 5D HEX
FAN5_ENTY - Bank 1 Address 5E HEX
FAN6_ENTY - Bank 1 Address 5F HEX
FAN7_ENTY - Bank 1 Address 60 HEX
FAN8_ENTY - Bank 1 Address 61 HEX
FAN9_ENTY - Bank 1 Address 62 HEX
FAN10_ENTY - Bank 1 Address 63 HEX
FAN11_ENTY - Bank 1 Address 64 HEX
FAN12_ENTY - Bank 1 Address 65 HEX
TD1_ENTY - Bank 1 Address 66 HEX
TD2_ENTY - Bank 1 Address 67 HEX
TD3_ENTY - Bank 1 Address 68 HEX
TD4_ENTY - Bank 1 Address 69 HEX
TR1_ENTY - Bank 1 Address 6A HEX
TR2_ENTY - Bank 1 Address 6B HEX
CHS_ENTY - Bank 1 Address 6C HEX
ENTINS1
ENTINS2
ENTINS3
ENTINS4
ENTINS5
ENTINS6
ENTINS7
ENTINS8 - Bank 1 Address 77 HEX
ENTINS9 - Bank 1 Address 78 HEX
ENTINS10 - Bank 1 Address 79 HEX
ENTINS11 - Bank 1 Address 7A HEX
ENTINS12 - Bank 1 Address 7B HEX
ENTINS13 - Bank 1 Address 7C HEX
ENTINS14 - Bank 1 Address 7D HEX
- Bank 1 Address 70 HEX
- Bank 1 Address 71 HEX
- Bank 1 Address 72 HEX
- Bank 1 Address 73 HEX
- Bank 1 Address 74 HEX
- Bank 1 Address 75 HEX
- Bank 1 Address 76 HEX
- 117 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
ENTINS15 - Bank 1 Address 7E HEX
Type:
Reset:
Read / Write
5VSB (Pin 7) Rising.
VCA_ENTITY
Bit
7
6
5
Name
4
3
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
VCore A Entity ID.
Reset
03 HEX
VCB_ENTITY
Bit
7
6
5
Name
Reset
4
3
VCore B Entity ID.
03 HEX
VTT_ENTITY
Bit
7
6
5
4
Name
3
Vtt Entity ID.
Reset
03 HEX
VDD_ENTITY
Bit
7
6
5
4
Name
3
VDD Entity ID.
Reset
07 HEX
VSB_ENTITY
Bit
7
6
5
4
Name
3
VSB Entity ID.
Reset
07 HEX
VBAT_ENTITY
Bit
7
6
5
4
3
- 118 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Name
VBAT Entity ID.
Reset
07 HEX
VSEN1_ENTITY
Bit
7
6
5
Name
4
3
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
VSEN1 Entity ID.
Reset
07 HEX
VSEN2_ENTITY
Bit
7
6
5
Name
4
3
VSEN2 Entity ID.
Reset
07 HEX
VSEN3_ENTITY
Bit
7
6
5
Name
4
3
VSEN3 Entity ID.
Reset
07 HEX
VSEN4_ENTITY
Bit
7
6
5
Name
4
3
VSEN4 Entity ID.
Reset
07 HEX
FAN1_ENTITY
Bit
7
6
5
4
Name
3
FAN1 Entity ID.
Reset
07 HEX
FAN2_ENTITY
Bit
Name
Reset
7
6
5
4
3
FAN2 Entity ID.
07 HEX
- 119 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
FAN3_ENTITY
Bit
7
6
5
4
Name
3
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
FAN3 Entity ID.
Reset
07 HEX
FAN4_ENTITY
Bit
7
6
5
4
Name
3
FAN4 Entity ID.
Reset
07 HEX
FAN5_ENTITY
Bit
7
6
5
4
Name
3
FAN5 Entity ID.
Reset
07 HEX
FAN6_ENTITY
Bit
7
6
5
4
Name
3
FAN6 Entity ID.
Reset
07 HEX
FAN7_ENTITY
Bit
7
6
5
4
Name
3
FAN7 Entity ID.
Reset
07 HEX
FAN8_ENTITY
Bit
Name
Reset
7
6
5
4
3
FAN8 Entity ID.
07 HEX
FAN9_ENTITY
- 120 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
7
6
5
4
Name
3
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
FAN9 Entity ID.
Reset
07 HEX
FAN10_ENTITY
Bit
7
6
5
Name
4
3
FAN10 Entity ID.
Reset
07 HEX
FAN11_ENTITY
Bit
7
6
5
Name
4
3
FAN11 Entity ID.
Reset
07 HEX
FAN12_ENTITY
Bit
7
6
5
Name
4
3
FAN12 Entity ID.
Reset
07 HEX
TD1_ENTITY
Bit
7
6
5
4
Name
3
TD1 Entity ID.
Reset
07 HEX
TD2_ENTITY
Bit
7
6
5
4
Name
3
TD2 Entity ID.
Reset
07 HEX
TD3_ENTITY
Bit
Name
7
6
5
4
3
TD3 Entity ID.
- 121 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset
07 HEX
TD4_ENTITY
Bit
7
6
5
4
Name
3
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
TD4 Entity ID.
Reset
07 HEX
TR1_ENTITY
Bit
7
6
5
4
Name
3
TR1 Entity ID.
Reset
07 HEX
TR2_ENTITY
Bit
7
6
5
4
Name
3
TR2 Entity ID.
Reset
07 HEX
CHS_ENTITY
Bit
7
6
5
Name
4
3
Chassis Entity ID.
Reset
23 HEX
ENTINS1
Bit
7
Name
6
5
4
3
VCoreB Entity Instance
VCoreA Entity Instance
02 HEX
01 HEX
Reset
ENTINS2
Bit
Name
Reset
7
6
5
4
3
2
1
VDD Entity Instance
Vtt Entity Instance
01 HEX
03 HEX
0
- 122 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
ENTINS3
Bit
7
Name
6
5
4
3
2
1
VBAT Entity Instance
VSB Entity Instance
03 HEX
02 HEX
Reset
0
ENTINS4
Bit
7
Name
6
5
4
3
2
1
VSEN2 Entity Instance
VSEN1 Entity Instance
05 HEX
04 HEX
Reset
0
ENTINS5
Bit
7
Name
6
5
4
3
2
1
VSEN4 Entity Instance
VSEN3 Entity Instance
07 HEX
06 HEX
Reset
0
ENTINS6
Bit
7
Name
6
5
4
3
2
1
FAN2 Entity Instance
FAN1 Entity Instance
02 HEX
01 HEX
Reset
0
ENTINS7
Bit
7
Name
6
5
4
3
2
1
FAN4 Entity Instance
FAN3 Entity Instance
04 HEX
03 HEX
Reset
0
ENTINS8
Bit
7
Name
6
5
4
3
2
1
FAN6 Entity Instance
FAN5 Entity Instance
06 HEX
05 HEX
Reset
0
ENTINS9
Bit
Name
7
6
5
FAN8 Entity Instance
4
3
2
1
0
FAN7 Entity Instance
- 123 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset
08 HEX
07 HEX
ENTINS10
Bit
7
Name
6
5
4
3
2
1
FAN10 Entity Instance
FAN9 Entity Instance
0A HEX
09 HEX
Reset
0
ENTINS11
Bit
7
Name
6
5
4
3
2
1
FAN12 Entity Instance
FAN11 Entity Instance
0C HEX
0B HEX
Reset
0
ENTINS12
Bit
7
6
Name
Reset
5
4
3
2
1
TD2 Entity Instance
TD1 Entity Instance
02 HEX
01 HEX
0
ENTINS13
Bit
7
6
Name
Reset
5
4
3
2
1
TD4 Entity Instance
TD3 Entity Instance
04 HEX
03 HEX
0
ENTINS14
Bit
7
6
Name
Reset
5
4
3
2
1
TR2 Entity Instance
TR1 Entity Instance
06 HEX
05 HEX
0
ENTINS15
Bit
Name
Reset
7
6
5
4
3
2
1
0
Reserved
Chassis Entity Instance
00 HEX
01 HEX
- 124 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Bit
Description
7-0
ENTITY. Entity of each sensor channel.
03 HEX : Processor
07 HEX : System Board.
23 HEX : Chassis Back Panel Board.
For other entity types, please refer to PET Spec. page 13.
8.13.2.12. Power on Control Option Register (PwrOnOption)
The W83793G supports 2 ways to power the system. One is to power the system only one time, no
matter 5VDD rises or not. The other is the W83793G continues to issues power-on cycles until it
detects VDD is already powered on.
Location: PwrOnOption - Bank 1 Address 7F HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising.
PWRONOPTION
Bit
7
6
5
Name
4
3
2
1
0
Nuvoton Test Modes
Reset
0
0
0
0
PWR1T
0
0
0
0
Bit
Description
7-1
Nuvoton Test Mode. Test modes for production. Nuvoton strongly suggests the
customer not use these registers to avoid system malfunction.
0
PWR1T (Power on One Time).
0: Continues to issue power-on cycles (PWRBTN_N assert 0.1sec every 1sec) until
VDD is powered-on.
1: Issues power-on cycle for only once.
8.13.2.13. Power on Command Register (PwrOnCmd)
ASF Remote Control Command supports Remote Power on features. Here defines the Power on
commands supported by the W83793G.
Location: PwrOnCmd - Bank 1 Address 80 HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising.
PWRONCMD
Bit
Name
7
6
5
4
3
2
1
0
Remote Power On Command
- 125 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Reset
11 HEX
Bit
Description
7-0
Remote Power On Command.
8.13.2.14. Power down Command Register (PwrOffCmd)
ASF Remote Control Command supports Remote Power Down features. Here defines the Power off
commands supported by the W83793G.
Location: PwrOffCmd - Bank 1 Address 81 HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising.
PWROFFCMD
Bit
7
6
5
Name
4
3
2
1
0
Remote Power Off Command
Reset
12 HEX
Bit
Description
7-0
Remote Power Off Command.
8.13.2.15. Reset Command Register (Rst Cmd)
ASF Remote Control Command supports Remote Reset features. Here defines the Reset commands
supported by the W83793G.
Location: RstCmd - Bank 1 Address 82 HEX
Type:
Read Write
Reset:
VSB5V (Pin 7) Rising.
RSTCMD
Bit
7
6
5
Name
4
3
2
1
0
Remote Reset Command
Reset
10 HEX
Bit
Description
7-0
Remote Reset Command.
- 126 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
9. SPECIFICATIONS
9.1
9.2
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage
-0.5 to 7.0
V
Input Voltage
-0.5 to VDD+0.5
V
Operating Temperature
0 to +70
°C
Storage Temperature
-55 to +150
°C
DC Characteristics
(Ta = 0° C to 70° C, 5VDD = 5V ± 10%, 5VSB =5V ± 5%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OUT/OD 12 – Output buffer or Open-drain output pin with source-sink capability of 12 mA
Output Low Voltage
V OL
Output High Voltage
V OH
0.4
2.4
V
V
I OL = 12 mA
I OH = -12 mA, OB
mode
IN/ODB 12v1sB - bi-directional pin with sink capability of 12 mA and schmitt-trigger level input
Input Low Voltage
V IL
0.4
V
5VDD = 5 V
Input High Voltage
V IH
0.6
V
5VDD = 5 V
Hysteresis
V TH
0.2
V
5VDD = 5 V
Output Low Voltage
V OL
0.4
V
Input High Leakage
I LIH
+10
μA
V IN = VDD
Input Low Leakage
I LIL
-10
μA
V IN = 0V
I OL = 12 mA
IN/ODB 12tsB - TTL level bi-directional pin with sink capability of 12 mA and schmitt-trigger level input
Input Low Voltage
V IL
Input High Voltage
V IH
Hysteresis
V TH
0.8
V
5VDD = 5 V
2.0
V
5VDD = 5 V
1.2
V
5VDD = 5 V
- 127 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PARAMETER
SYM.
Output Low Voltage
MIN.
TYP.
MAX.
UNIT
CONDITIONS
V OL
0.4
V
Input High Leakage
I LIH
+10
μA
V IN = VDD
Input Low Leakage
I LIL
-10
μA
V IN = 0V
I OL = 12 mA
OUTB 12B - TTL level output pin with source-sink capability of 12 mA
Output Low Voltage
V OL
Output High Voltage
V OH
0.4
2.4
V
V
I OL = 12 mA
I OH = -12 mA
ODB 12B - Open-drain output pin with sink capability of 12 mA
Output Low Voltage
V OL
0.4
V
I OL = 12 mA
AOUT – Analog output
N.A.
INB V1SB - VID input pin
for INTEL
TM
VRM10.0, and VRM11 design
Input Low Voltage
V IL
Input High Voltage
V IH
0.4
0.6
V
V
IN tV2SB - VID input pin
TM
for AMD
VRM design
Input Low Voltage
V IL
Input High Voltage
V IH
0.8
1.4
V
V
IN/OB V3B – Bi-direction pin with source capability of 6 mA and sink capability of 1 mA
for INTELTM PECI
Input Low Voltage
V IL
0.275V tt
0.5V tt
V
Input High Voltage
V IH
0.55V tt
0.725V tt
V
Output Low Voltage
V OL
0.25V tt
V
Output High Voltage
V OH
0.75V tt
V
Hysterisis
V Hys
0.1V tt
V
INB tsB
- TTL level Schmitt-triggered input pin
- 128 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
PARAMETER
SYM.
Input Low Voltage
V IL
Input High Voltage
V IH
Hysteresis
V TH
Input High Leakage
I LIH
Input Low Leakage
I LIL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
0.8
V
5VDD = 5 V
2.0
V
5VDD = 5 V
1.2
V
5VDD = 5 V
+10
μA
V IN = VDD
-10
μA
V IN = 0 V
- 129 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
9.3
AC Characteristics
- 130 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
9.3.1
Access Interface
t SCL
tR
t
R
SCL
t HD;SDA
SDA IN
t
t SU;STO
SU;DAT
VALID DATA
t HD;DAT
SDA OUT
Serial Bus Timing Diagram
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
SCL clock period
t- SCL
10
uS
Start condition hold time
t HD;SDA
4.7
uS
Stop condition setup-up time
t SU;STO
4.7
uS
DATA to SCL setup time
t SU;DAT
150
nS
DATA to SCL hold time
t HD;DAT
270
nS
SCL and SDA rise time
tR
1.0
uS
SCL and SDA fall time
tF
300
nS
- 131 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
9.3.2 Dynamic Vcore Limit Setting
If the dynamic VID function is enabled, the Vcore channel high/low limit will change in accordance with
the VID table. When the VIDIN value changes, the internal VIDCHG signal will be set, until the VIDIN
value is stable for more than 1ms. New Vcore high/low limit will be set at the falling edge of VIDCHG
and the Vcore channel will enable the monitoring at the same time.
VIDIN
VIDCHG
Vcore High/Low limit
Vcore Disable Monitor
~1ms
- 132 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
9.3.3 Power on Reset
The power-on reset threshold is 4.3V (typical). When VCC exceeds this threshold, the internal reset
signal will be asserted for 3uS. During this time period, the W83793G is in the reset state. When the
internal reset signal is de-asserted, the W83793G is in the operating state.
In the operating state, if VCC drops below 4.0V and then rises above 4.3V, the internal reset signal will
be asserted immediately. Fig 1 illustrates the reset mechanism.
5V
VSB
4.3V
4.0V
0V
5.0V
4.3V
Internal Reset Signal
3us
3us
Figure 1.
- 133 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
10. ORDERING INFORMATION
PART NO.
W83793G
PACKAGE
SSOP56
REMARKS
Pb-free Package
- 134 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
11. TOP MARKING SPECIFICATION
W83793R
28201234
606GCUB
Left
First Line
Nuvoton Logo.
IC part number: W83793R; R means SSOP, leaded package.
Second Line
Third Line
Serial number
Tracking Code: 6 06 G C UB for Package information
6
Package is made in 2006
06
G
C
Week: 06
Assembly house ID; G means Greatek; A means ASE; O means OSE
IC version
UB
Mask version
W83793G
28201234
606GCUB
Left
First Line
Nuvoton Logo.
IC part number: W83793G; G means Pb-free package.
Second Line
Third Line
Serial number
Tracking Code: 6 06 G C UB for Package information
6
Package is made in 2006
06
G
C
Week: 06
Assembly house ID; G means Greatek; A means ASE; O means OSE
IC version
UB
Mask version
W83793AG
28201234
606GCUB
Left
First Line
Nuvoton Logo.
IC part number: W83793AG; G means Pb-free package.
Second Line
Third Line
Serial number
Tracking Code: 6 06 G
C UB for Package information
- 135 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
6
Package is made in 2006
06
G
C
Week: 06
Assembly house ID; G means Greatek; A means ASE; O means OSE
IC version
UB
Mask version
- 136 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
12. PACKAGE DRAWING AND DIMENSIONS
(56-pin SSOP 300mil)
.035
.045
DIMENSION IN MM
SYMBOL
.045
.055
0.40/0.50 DIA
E
END VIEW
HE
TOP VIEW
SEE DETAIL "A"
c
D
θ
A2
SEATING PLANE
A
A1
e
b
SIDE VIEW
θ
MAX.
0.110
0.016
0.092
0.0135
c
0.13
0.005
0.010
D
HE
18.2
18.42 18.54
910.16 10.31 10.41
E
7.42
0.51
7.52
0.64
0.61
0.81
1.40
0.720
0.400
0.292
0.020
0.024
0.725 0.730
0.406 0.410
0.296 0.299
0.025 0.030
0.032 0.040
0.055
A
A1
A2
b
e
L
L1
Y
DIMENSION IN INCH
MIN. NOM MAX. MIN. NOM
0.095 0.101
2.41
2.57 2.79
0.41 0.008 0.012
0.20 0.30
0.088 0.090
2.34
2.24 2.29
0.25
0.20
0.34 0.008 0.010
PARTING LINE
Y
c
θ
0
0.25
7.59
0.76
1.02
0.08
8
0.003
0
8
L
L1
DETAIL"A"
- 137 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
13. APPENDIX
13.1 Register Summary
BANK 0
Index
Register Name
Index
Register Name
BANK 0 ADDRESS 00-1F
00 HEX
Bank Selection
10 HEX
VCore A Readout
01 HEX
Watch Dog Lock
11 HEX
VCore B Readout
02 HEX
Watch Dog Enable
12 HEX
Vtt Readout
03 HEX
Watch Dog Status
13 HEX
04 HEX
Watch Dog Timer
14 HEX
VSEN1 Readout
05 HEX
VIDA Input Value
15 HEX
VSEN2 Readout
06 HEX
VIDB Input Value
16 HEX
VSEN3 Readout
07 HEX
VIDA Latch
17 HEX
VSEN4 Readout
08 HEX
VIDB Latch
18 HEX
5VDD Readout
09 HEX
VCore High Tolerance
19 HEX
5VSB Readout
0A HEX
VCore Low Tolerance
1A HEX
VBAT Readout
0B HEX
I2C Address
1B HEX
VIN Low Bit
0C HEX
Sensor 1/2 Address
1C HEX
TD1 Readout
0D HEX
Nuvoton Vendor ID
1D HE X
TD2 Readout
0E HEX
Nuvoton Chip ID
1E HEX
TD3 Readout
0F HEX
Nuvoton Device ID
1F HEX
TD4 Readout
BANK 0 ADDRESS 20-3F
20 HEX
TR1 Readout
30 HEX
Fan7 Count Low Byte
21 HEX
TR2 Readout
31 HEX
Fan8 Count High Byte
22 HEX
Temp Low Bit Readout
32 HEX
Fan8 Count Low Byte
- 138 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Index
Register Name
Index
Register Name
23 HEX
Fan1 Count High Byte
33 HEX
Fan9 Count High Byte
24 HEX
Fan1 Count Low Byte
34 HEX
Fan9 Count Low Byte
25 HEX
Fan2 Count High Byte
35 HEX
Fan10 Count High Byte
26 HEX
Fan2 Count Low Byte
36 HEX
Fan10 Count Low Byte
27 HEX
Fan3 Count High Byte
37 HEX
Fan11 Count High Byte
28 HEX
Fan3 Count Low Byte
38 HEX
Fan11 Count Low Byte
29 HEX
Fan4 Count High Byte
39 HEX
Fan12 Count High Byte
2A HEX
Fan4 Count Low Byte
3A HEX
Fan12 Count Low Byte
2B HEX
Fan5 Count High Byte
3B HEX
2C HEX
Fan5 Count Low Byte
3C HEX
2D HEX
Fan6 Count High Byte
3D HEX
2E HEX
Fan6 Count Low Byte
3E HEX
2F HEX
Fan7 Count High Byte
3F HEX
BANK 0 ADDRESS 40-5F
40 HEX
Configuration
50 HEX
SMI/IRQ Control
41 HEX
Interrupt Status 1
51 HEX
OVT Control
42 HEX
Interrupt Status 2
52 HEX
OVT/Beep Global Enable
43 HEX
Interrupt Status 3
53 HEX
Beep Control 1
44 HEX
Interrupt Status 4
54 HEX
Beep Control 2
45 HEX
Interrupt Status 5
55 HEX
Beep Control 3
46 HEX
Interrupt Mask 1
56 HEX
Beep Control 4
47 HEX
Interrupt Mask 2
57 HEX
Beep Control 5
48 HEX
Interrupt Mask 3
58 HEX
Multi-Function Pin Control
49 HEX
Interrupt Mask 4
59 HEX
VID Control
4A HEX
Interrupt Mask 5
5A HEX
TD1 Configuration
- 139 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Index
Register Name
Index
Register Name
4B HEX
Real Time Status 1
5B HEX
TD2 Configuration
4C HEX
Real Time Status 2
5C HEX
FanIn Control
4D HEX
Real Time Status 3
5D HEX
FanIn Redirection
4E HEX
Real Time Status 4
5E HEX
TD Mode Select
4F HEX
Real Time Status 5
5F HEX
TR Mode Select
BANK 0 ADDRESS 60-7F
60 HEX
VCoreA High Limit
70 HEX
VSEN4 High Limit
61 HEX
VCoreA Low Limit
71 HEX
VSEN4 Low Limit
62 HEX
VCoreB High Limit
72 HEX
5VDD High Limit
63 HEX
VCoreB Low Limit
73 HEX
5VDD Low Limit
64 HEX
Vtt High Limit
74 HEX
5VSB High Limit
65 HEX
Vtt Low Limit
75 HEX
5VSB Low Limit
66 HEX
76 HEX
VBAT High Limit
67 HEX
77 HEX
VBAT Low Limit
68 HEX
High Limit Low Bit
78 HEX
TD1 Critical
69 HEX
Low Limit Low Bit
79 HEX
TD1 Critical Hysterisis
6A HEX
VSEN1 High Limit
7A HEX
TD1 Warning
6B HEX
VSEN1 Low Limit
7B HEX
TD1 Warning Hysterisis
6C HEX
VSEN2 High Limit
7C HEX
TD2 Critical
6D HEX
VSEN2 Low Limit
7D HEX
TD2 Critical Hysterisis
6E HEX
VSEN3 High Limit
7E HEX
TD2 Warning
6F HEX
VSEN3 Low Limit
7F HEX
TD2 Warning Hysterisis
BANK 0 ADDRESS 80-9F
80 HEX
TD3 Critical
90 HEX
Fan1 Limit High Byte
81 HEX
TD3 Critical Hysterisis
91 HEX
Fan1 Limit Low Byte
- 140 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Index
Register Name
Index
Register Name
82 HEX
TD3 Warning
92 HEX
Fan2 Limit High Byte
83 HEX
TD3 Warning Hysterisis
93 HEX
Fan2 Limit Low Byte
84 HEX
TD4 Critical
94 HEX
Fan3 Limit High Byte
85 HEX
TD4 Critical Hysterisis
95 HEX
Fan3 Limit Low Byte
86 HEX
TD4 Warning
96 HEX
Fan4 Limit High Byte
87 HEX
TD4 Warning Hysterisis
97 HEX
Fan4 Limit Low Byte
88 HEX
TR1 Critical
98 HE X
Fan5 Limit High Byte
89 HEX
TR1 Critical Hysterisis
99 HEX
Fan5 Limit Low Byte
8A HEX
TR1 Warning
9A HEX
Fan6 Limit High Byte
8B HEX
TR1 Warning Hysterisis
9B HEX
Fan6 Limit Low Byte
8C HEX
TR2 Critical
9C HEX
Fan7 Limit High Byte
8D HEX
TR2 Critical Hysterisis
9D HEX
Fan7 Limit Low Byte
8E HEX
TR2 Warning
9E HEX
Fan8 Limit High Byte
8F HEX
TR2 Warning Hysterisis
9F HEX
Fan8 Limit Low Byte
BANK 0 ADDRESS A0-BF
A0 HEX
Fan9 Limit High Byte
B0 HEX
Fan Output Style 1
A1 HEX
Fan9 Limit Low Byte
B1 HEX
Fan Output Style 2
A2 HEX
Fan10 Limit High Byte
B2 HEX
Fan Default Speed
A3 HEX
Fan10 Limit Low Byte
B3 HEX
Fan1 Duty
A4 HEX
Fan11 Limit High Byte
B4 HEX
Fan2 Duty
A5 HEX
Fan11 Limit Low Byte
B5 HEX
Fan3 Duty
A6 HEX
Fan12 Limit High Byte
B6 HEX
Fan4 Duty
A7 HEX
Fan12 Limit Low Byte
B7 HEX
Fan5 Duty
A8 HEX
TD1 Temperature Offset
B8 HEX
Fan6 Duty
A9 HEX
TD2 Temperature Offset
B9 HEX
Fan7 Duty
- 141 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Index
Register Name
Index
Register Name
AA HEX
TD3 Temperature Offset
BA HEX
Fan8 Duty
AB HEX
TD4 Temperature Offset
BB HEX
Fan1 Output Prescalar
AC HEX
TR1 Temperature Offset
BC HEX
Fan2 Output Prescalar
AD HEX
TR2 Temperature Offset
BD HEX
Fan3 Output Prescalar
AE HEX
BE HEX
Fan4 Output Prescalar
AF HEX
BF HEX
Fan5 Output Prescalar
BANK 0 ADDRESS C0-DF
C0 HEX
Fan6 Output Prescalar
D5 HEX
PECI Return Domain
C1 HEX
Fan7 Output Prescalar
D6 HEX
PECI Warning Flags
C2 HEX
Fan8 Output Prescalar
D7 HEX
C3 HEX
Step Up Time
D8 HEX
PECI Agent1 RelTempH
C4 HEX
Step Down Time
D9 HEX
PECI Agent1 RelTempL
C5 HEX
Critical Temperature
DA HEX
PECI Agent2 RelTempH
D0 HEX
PECI Agent Configure
DB HEX
PECI Agent2 RelTempL
D1 HEX
PECI Agent1 Tcase
DC HEX
PECI Agent3 RelTempH
D2 HEX
PECI Agent2 Tcase
DD HEX
PECI Agent3 RelTempL
D3 HEX
PECI Agent3 Tcase
DE HEX
PECI Agent4 RelTempH
D4 HEX
PECI Agent4 Tcase
DF HEX
PECI Agent4 RelTempL
BANK 1
Index
Register Name
Index
Register Name
BANK 1 ADDRESS 00-1F
00 HEX
Bank Select
0E HEX
Nuvoton Chip ID
0D HEX
Nuvoton Vendor ID
0F HEX
Nuvoton Device ID
BANK 1 ADDRESS 20-33
20 HEX
UDID Device Capability
2A HEX
UDID SubDevice ID High
- 142 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Index
Register Name
Index
Register Name
21 HEX
UDID Version Number
2B HEX
UDID SubDevice ID Low
22 HEX
UDID Vendor ID High
2C HEX
UDID Specific Vendor ID1
23 HEX
UDID Vendor ID Low
2D HEX
UDID Specific Vendor ID2
24 HEX
UDID Device ID High
2E HEX
UDID Specific Vendor ID3
25 HEX
UDID Device ID Low
2F HEX
UDID Specific Vendor ID4
26 HEX
UDID Interface High Byte
30 HEX
Random Number 1
27 HEX
UDID Interface Low Byte
31 HEX
Random Number 2
28 HEX
UDID SubVendor ID High
32 HEX
Random Number 3
29 HEX
UDID SubVendor ID Low
33 HEX
Random Number 4
BANK 1 ADDRESS 40
40 HEX
ARP Assigned Address
BANK 1 ADDRESS 50-6F
50 HEX
VCoreA Entity ID
60 HEX
Fan7 Entity ID
51 HEX
VCoreB Entity ID
61 HEX
Fan8 Entity ID
52 HEX
Vtt Entity ID
62 HEX
Fan9 Entity ID
53 HEX
VDD Entity ID
63 HEX
Fan10 Entity ID
54 HEX
VSB5V Entity ID
64 HEX
Fan11 Entity ID
55 HEX
VBAT Entity ID
65 HEX
Fan12 Entity ID
56 HEX
VSEN1 Entity ID
66 HEX
TD1 Entity ID
57 HEX
VSEN2 Entity ID
67 HEX
TD2 Entity ID
58 HEX
VSEN3 Entity ID
68 HEX
TD3 Entity ID
59 HEX
VSEN4 Entity ID
69 HEX
TD4 Entity ID
5A HEX
Fan1 Entity ID
6A HEX
TR1 Entity ID
5B HEX
Fan2 Entity ID
6B HEX
TR2 Entity ID
5C HE X
Fan3 Entity ID
6C HEX
Chassis Entity ID
- 143 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Index
Register Name
Index
5D HEX
Fan4 Entity ID
6D HEX
5E HEX
Fan5 Entity ID
6E HEX
5F HEX
Fan6 Entity ID
6F HEX
Register Name
BANK 1 ADDRESS 70-8F
70 HEX
VCoreA/VCoreB EntityID
80 HEX
Remote PowerOn Command
71 HEX
VDD/Vtt EntityID
81 HEX
Remote Power Off Command
72 HEX
VBAT/VSB EntityID
82 HEX
Remote Reset Command
73 HEX
VCoreA/VCoreB EntityID
83 HEX
74 HEX
VSEN1/VSEN2 EntityID
84 HEX
75 HEX
VSEN4/VSEN3 EntityID
85 HEX
76 HEX
Fan1/2 EntityID
86 HEX
77 HEX
Fan3/4 EntityID
87 HEX
78 HEX
Fan5/6 EntityID
88 HEX
79 HEX
Fan7/8 EntityID
89 HEX
7A HEX
Fan9/10 EntityID
8A HEX
7B HEX
Fan11/12 EntityID
8B HEX
7C HEX
TD1/2 EntityID
8C HEX
7D HEX
TD3/4 EntityID
8D HEX
7E HEX
Chassis EntityID
8E HEX
7F HEX
Power On Option
8F HEX
BANK 2
Index
Register Name
Index
Register Name
BANK 2 ADDRESS 00-1F
00 HEX
Bank Select
10 HEX
TD1 Target Temperature
01 HEX
TD1 Fan Mapping Select
11 HEX
TD2 Target Temperature
- 144 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
02 HEX
TD2 Fan Mapping Select
12 HEX
TD3 Target Temperature
03 HEX
TD3 Fan Mapping Select
13 HEX
TD4 Target Temperature
04 HEX
TD4 Fan Mapping Select
14 HEX
TR1 Target Temperature
05 HEX
TR1 Fan Mapping Select
15 HEX
TR2 Target Temperature
06 HEX
TR2 Fan Mapping Select
16 HEX
07 HEX
Fan Control Mode Select
17 HEX
08 HEX
TD1/2 Temp Tolerance
18 HEX
Fan1 Nonstop Duty Cycle
09 HEX
TD3/4 Temp Tolerance
19 HEX
Fan2 Nonstop Duty Cycle
0A HEX
TR1/2 Temp Tolerance
1A HEX
Fan3 Nonstop Duty Cycle
0B HEX
1B HEX
Fan4 Nonstop Duty Cycle
0C HEX
1C HEX
Fan5 Nonstop Duty Cycle
0D HEX
Nuvoton Vendor ID
1D HEX
Fan6 Nonstop Duty Cycle
0E HEX
Nuvoton Chip ID
1E HEX
Fan7 Nonstop Duty Cycle
0F HEX
Nuvoton Device ID
1F HEX
Fan8 Nonstop Duty Cycle
BANK 2 ADDRESS 20-3F
20 HEX
Fan1 Start Duty Cycle
30 HEX
TD1 Temp Level01
21 HEX
Fan2 Start Duty Cycle
31 HEX
TD1 Temp Level12
22 HEX
Fan3 Start Duty Cycle
32 HEX
TD1 Temp Level23
23 HEX
Fan4 Start Duty Cycle
33 HEX
TD1 Temp Level34
24 HEX
Fan5 Start Duty Cycle
34 HEX
TD1 Temp Level45
25 HEX
Fan6 Start Duty Cycle
35 HEX
TD1 Temp Level56
26 HEX
Fan7 Start Duty Cycle
36 HEX
TD1 Temp Level67
27 HEX
Fan8 Start Duty Cycle
37 HEX
28 HEX
Fan1 Stop Time
38 HEX
TD1 Fan Level0
29 HEX
Fan2 Stop Time
39 HEX
TD1 Fan Level1
2A HEX
Fan3 Stop Time
3A HEX
TD1 Fan Level2
- 145 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
2B HEX
Fan4 Stop Time
3B HEX
TD1 Fan Level3
2C HEX
Fan5 Stop Time
3C HEX
TD1 Fan Level4
2D HEX
Fan6 Stop Time
3D HEX
TD1 Fan Level5
2E HEX
Fan7 Stop Time
3E HEX
TD1 Fan Level6
2F HEX
Fan8 Stop Time
3F HEX
BANK 2 ADDRESS 40-5F
40 HEX
TD2 Temp Level01
50 HEX
TD3 Temp Level01
41 HEX
TD2 Temp Level12
51 HEX
TD3 Temp Level12
42 HEX
TD2 Temp Level23
52 HEX
TD3 Temp Level23
43 HEX
TD2 Temp Level34
53 HEX
TD3 Temp Level34
44 HEX
TD2 Temp Level45
54 HEX
TD3 Temp Level45
45 HEX
TD2 Temp Level56
55 HEX
TD3 Temp Level56
46 HEX
TD2 Temp Level67
56 HEX
TD3 Temp Level67
47 HEX
57 HEX
48 HEX
TD2 Fan Level0
58 HEX
TD3 Fan Level0
49 HEX
TD2 Fan Level1
59 HEX
TD3 Fan Level1
4A HEX
TD2 Fan Level2
5A HEX
TD3 Fan Level2
4B HEX
TD2 Fan Level3
5B HEX
TD3 Fan Level3
4C HEX
TD2 Fan Level4
5C HEX
TD3 Fan Level4
4D HEX
TD2 Fan Level5
5D HEX
TD3 Fan Level5
4E HEX
TD2 Fan Level6
5E HEX
TD3 Fan Level6
4F HEX
5F HEX
BANK 2 ADDRESS 60-7F
60 HEX
TD4 Temp Level01
70 HEX
TR1 Temp Level01
61 HEX
TD4 Temp Level12
71 HEX
TR1 Temp Level12
62 HEX
TD4 Temp Level23
72 HEX
TR1 Temp Level23
- 146 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
63 HEX
TD4 Temp Level34
73 HEX
TR1 Temp Level34
64 HEX
TD4 Temp Level45
74 HEX
TR1 Temp Level45
65 HEX
TD4 Temp Level56
75 HEX
TR1 Temp Level56
66 HEX
TD4 Temp Level67
76 HEX
TR1 Temp Level67
67 HEX
77 HEX
68 HEX
TD4 Fan Level0
78 HEX
TR1 Fan Level0
69 HEX
TD4 Fan Level1
79 HEX
TR1 Fan Level1
6A HEX
TD4 Fan Level2
7A HEX
TR1 Fan Level2
6B HEX
TD4 Fan Level3
7B HEX
TR1 Fan Level3
6C HEX
TD4 Fan Level4
7C HEX
TR1 Fan Level4
6D HEX
TD4 Fan Level5
7D HEX
TR1 Fan Level5
6E HEX
TD4 Fan Level6
7E HEX
TR1 Fan Level6
6F HEX
7F HEX
BANK 2 ADDRESS 80-8F
80 HEX
TR2 Temp Level01
88 HEX
TR2 Fan Level0
81 HEX
TR2 Temp Level12
89 HEX
TR2 Fan Level1
82 HEX
TR2 Temp Level23
8A HEX
TR2 Fan Level2
83 HEX
TR2 Temp Level34
8B HEX
TR2 Fan Level3
84 HEX
TR2 Temp Level45
8C HEX
TR2 Fan Level4
85 HEX
TR2 Temp Level56
8D HEX
TR2 Fan Level5
86 HEX
TR2 Temp Level67
8E HEX
TR2 Fan Level6
87 HEX
8F HEX
- 147 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
14. REVISION HISTORY
VERSION
DATE
0.1
0.2
06/06/05
0.3
08/01/05
0.32
0.33
01/20/06
PAGE
DESCRIPTION
N.A.
Preliminary
N.A.
Modify the pin types for VID pins in section 4.1 and
5.2.
N.A.
Add Vtt and PECI pin.
N.A.
1. Modify Chapter 4 Block Diagram) and Chapter 5
Pin Configuration.
N.A.
Modify Registers for B version.
1. Modify the formula to calculate the RPM.
0.34
01/06/06
N.A.
0.35
02/27/06
9, 13, 14
2. Add information of “The Top Marking”.
3. Change the part name to W83793G
Add the descriptions of FANIN9~FANIN12.
1. Modify 8.8.2.3 register descriptions.
2. Update 8.9.2.1 voltage reading formula.
1.0
07/21/06
N.A.
3. Remove the AMD SI descriptions.
4. Update 8.3.2.2 Index 0Ch I2CADDR75B registers.
Update AC Characteristic in Chap 9.3.
1.1
1.2
12/03/06
05/21/07
N.A.
N.A.
Add W83793AG
1.
Correct grammar mistakes.
2.
Update 3VSEN and 12VSEN to VSEN3 and
VSEN4.
3.
Update “Tcontrol” to “Tcase”.
4.
Update the descriptions of Chapter 1, Chapter 2
and Chapter 4.
Update the information of the W83793AG.
1.3
05/08/08
8,9,12.
1.4
12/12/08
NA
1. Update VSEN3 and VSEN4
2. Move the revision history to the last chapter.
Change Nuvoton logo to Nuvoton
- 148 –7
Publication Release Date: December 12, 2008
Revision 1.4
W83793G / W83793AG
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
- 149 –7
Publication Release Date: December 12, 2008
Revision 1.4
