NCT7904D
H/W Monitor
Date: 2017/07/25
Revision: 1.45
NCT7904D
Table of Content1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 7
FEATURES ................................................................................................................................. 8
2.1
Equipped Specific Interfaces .......................................................................................... 8
2.2
Monitoring Items ............................................................................................................. 8
2.3
PECI (Platform Environment Control Interface) .............................................................. 8
TM
2.4
SMART FAN PWM Output Control ............................................................................. 9
2.5
Alarm Output ................................................................................................................... 9
2.6
Self-initialization .............................................................................................................. 9
2.7
SMBus Master ................................................................................................................ 9
2.8
General ........................................................................................................................... 9
KEY SPECIFICATIONS ............................................................................................................ 10
PIN CONFIGURATION ............................................................................................................. 11
PIN DESCRIPTION................................................................................................................... 12
5.1
Pin Type Description ..................................................................................................... 12
5.2
Pin Description List ....................................................................................................... 12
FUNCTIONAL DESCRIPTION.................................................................................................. 17
6.1
Access Interface ........................................................................................................... 17
6.1.1
6.1.2
6.2
6.3
Data write to the internal register ............................................................................. 17
Data read from the internal register ......................................................................... 17
Address Setting............................................................................................................. 18
Temperature Monitor Data Format ............................................................................... 18
The temperature data with 11-bit 2`s complement format ........................................................... 18
6.4
6.5
6.6
6.7
Voltage Sense Data Format ......................................................................................... 18
FAN_IN Count Calculation ............................................................................................ 19
FAN_OUT Duty Cycle/DC output Calculation .............................................................. 19
Fan Speed Control ........................................................................................................ 19
6.7.1
6.7.2
6.7.3
6.7.4
6.8
PECI .............................................................................................................................. 22
6.8.1
6.8.2
6.8.3
6.8.4
6.9
Temperature ............................................................................................................ 25
Voltage .................................................................................................................... 27
Fan .......................................................................................................................... 27
EEPROM Self-Initialization ........................................................................................... 28
6.10.1
6.10.2
6.11
Operation Mode ....................................................................................................... 22
CPU Temperature and Power Reporting ................................................................. 22
DRAM Thermal Data Reporting ............................................................................... 23
PECI Listening ......................................................................................................... 24
SMI# Output .................................................................................................................. 25
6.9.1
6.9.2
6.9.3
6.10
Step Up Time / Step Down Time ............................................................................. 19
Fan Output Nonstop Value ...................................................................................... 19
Smart Fan Control Table ......................................................................................... 19
DTS (Sensor) Based Fan Control ............................................................................ 21
EEPROM Format ..................................................................................................... 28
Chip Initialization...................................................................................................... 28
PCH Thermal Data Report ............................................................................................ 29
6.11.1
6.11.2
Nuvoton Confidential
PCH Thermal Read ................................................................................................. 29
PCH Thermal Data Format ...................................................................................... 29
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NCT7904D
6.12
SMBus Master Auto Read External Thermal Sensor ................................................... 29
6.12.1
6.12.2
6.13
PROCHOT# Behavior ................................................................................................... 29
6.13.1
6.13.2
6.14
Output Signaling ...................................................................................................... 30
BEEP Activation....................................................................................................... 30
THERMTRIP# Function ................................................................................................ 30
6.16.1
6.16.2
7.
Event Trigger LED ................................................................................................... 30
Programmable LED ................................................................................................. 30
BEEP Function.............................................................................................................. 30
6.15.1
6.15.2
6.16
PROCHOT# Input .................................................................................................... 29
PROCHOT# Output ................................................................................................. 29
LED Behavior ................................................................................................................ 30
6.14.1
6.14.2
6.15
External Thermal Sensor Setting ............................................................................. 29
Temperature Read Process ..................................................................................... 29
Power by VSB.......................................................................................................... 30
Power Only by VBAT ............................................................................................... 30
REGISTER DESCRIPTION ...................................................................................................... 31
7.1
Bank 0 REGISTER DETAIL.......................................................................................... 31
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.1.18
7.1.19
7.1.20
7.1.21
7.1.22
7.1.23
7.1.24
7.1.25
7.1.26
7.1.27
7.1.28
7.1.29
7.1.30
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Global Control Register ........................................................................................... 31
SMB Slave Address Register................................................................................... 31
Nuvoton Vendor ID Register .................................................................................... 32
Nuvoton Chip ID Register ........................................................................................ 32
Nuvoton Device ID Register..................................................................................... 32
Programmable LED Register ................................................................................... 32
Event Control LED Register ..................................................................................... 33
Monitor Enable Control Register .............................................................................. 33
Monitor Configuration Register ................................................................................ 38
Voltage Channel and Temperature Monitored Value Register ................................ 41
PROCHOT Monitored Value Register ..................................................................... 42
Nuvoton Vendor ID Register .................................................................................... 43
Nuvoton Chip ID Register ........................................................................................ 43
Nuvoton Device ID Register..................................................................................... 43
FAN Tachometer Monitored Value Register ............................................................ 43
DTS Temperature Monitored Value Register ........................................................... 44
Virtual Temperature Value Register......................................................................... 46
External and Virtual Temperature Value Register.................................................... 47
SMI Control Register ............................................................................................... 48
SMI Status Register ................................................................................................. 48
SMI Mask Register .................................................................................................. 50
Beep Control Register ............................................................................................. 52
Beep Source Selection Register .............................................................................. 52
Lock Watch Dog Register ........................................................................................ 54
Watch Dog Enable Register .................................................................................... 54
Watch Dog Status Register ..................................................................................... 54
Watch Dog Timer Register ...................................................................................... 55
GPIO Control Register ............................................................................................. 55
PCH DTS Monitored Value Register........................................................................ 57
Bank Select Register ............................................................................................... 60
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NCT7904D
7.2
Bank 1 REGISTER DETAIL.......................................................................................... 61
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.3
Voltage and Temperature Channel Limitation Register ........................................... 61
PROCHOT Limitation Register ................................................................................ 64
FAN Input Channel Limitation Register.................................................................... 64
DTS Temperature Power Limitation Registers......................................................... 65
PROCHOT Control Registers .................................................................................. 67
PROCHOT Source Selection Registers................................................................... 68
Voltage Fault Control Registers ............................................................................... 70
Voltage Fault Source Selection Registers ............................................................... 70
Fan Fault Control Registers ..................................................................................... 72
Fan Fault Source Selection Registers ..................................................................... 72
Temperature Fault Control Registers....................................................................... 74
Temperature Fault Source Selection Registers ....................................................... 74
THERMTRIP Control and Status Register ............................................................... 75
Bank 2 REGISTER DETAIL.......................................................................................... 77
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.3.14
7.3.15
7.3.16
7.3.17
7.3.18
7.3.19
7.3.20
7.3.21
7.3.22
7.3.23
7.3.24
7.3.25
7.3.26
7.3.27
7.3.28
7.3.29
7.3.30
7.3.31
7.3.32
7.3.33
Nuvoton Confidential
PECI Function Enable Register (PFE) ..................................................................... 77
PECI Timing Configure Register (PTC) ................................................................... 77
PECI Agent and Domain Configure Register (PADC).............................................. 78
PECI Relative Temperature Scale Register (PRTS) ................................................ 79
DTS Power Source Control Register ....................................................................... 80
TBit Width Register ( TBW )..................................................................................... 80
PECI Listening Mode Configuration Register ( PLMC ) ........................................... 81
PECI VTT Power Detect Configuration Register ( PVCR ) ...................................... 81
PECI Agent Tbase Temperature Register (PATB)................................................... 82
PECI Power Averaging Configure Register (PPAC) ................................................ 83
Averaging DTS Based Thermal Spec Configure Register (ADBTSC) ..................... 84
PECI Manual Mode Configure Register (PMMC)..................................................... 85
PECI Manual Mode Write Data Register (PMMWD) ................................................ 86
PECI Manual Mode Read Data Register (PMMRD) ................................................ 86
Agent Relative Temperature Registers (ARTR) ....................................................... 89
TSI Control Registers .............................................................................................. 91
TSI Client Enable Registers ..................................................................................... 91
TSI Manual Configuration Registers ........................................................................ 91
TSI Test Mode Registers ......................................................................................... 92
TSI Manual Address Registers ................................................................................ 92
TSI Manual Command Registers ............................................................................. 92
TSI Manual Write Data Registers ............................................................................ 93
TSI Manual Read Data Registers ............................................................................ 93
PCH Read Control Registers ................................................................................... 93
PCH Client Address Registers ................................................................................. 93
PCH Command Registers ....................................................................................... 94
PCH Read Byte Count Registers ............................................................................. 94
SMBUS Master Manual Configuration Registers ..................................................... 94
SMBUS Master Manual Address Registers ............................................................. 95
SMBUS Master Manual Command Registers .......................................................... 95
SMBUS Master Manual Write Data Registers ......................................................... 95
SMBUS Master Manual Read Data Registers ......................................................... 95
External Read Control Registers ............................................................................. 95
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NCT7904D
7.3.34
7.3.35
7.3.36
7.3.37
7.3.38
7.3.39
7.3.40
7.3.41
7.3.42
7.3.43
7.3.44
7.4
Bank 3 REGISTER DETAIL........................................................................................ 112
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
7.4.13
7.4.14
7.4.15
7.4.16
7.4.17
7.4.18
7.4.19
7.4.20
7.4.21
7.4.22
7.4.23
7.4.24
7.4.25
7.4.26
7.4.27
7.5
Temperature to Fan Mapping Relationships (TFMR) ............................................. 112
Default Fan Speed at Power-on (DFSP)................................................................ 112
SmartFan Output Step Up Time (SFOSUT) .......................................................... 113
SmartFan Output Step Down Time (SFOSDT) ...................................................... 113
3-Wire Fan Enable and Fan Output Mode Control (FOMC) ................................... 113
Close-Loop Fan control RPM mode and Tolerance (CLFR) .................................. 114
Temperature Source Selection (TSS) .................................................................... 114
Power Accumulate Enable (PAE) .......................................................................... 116
Close-Loop Fan Control RPM mode for High Speed Fan Register (RHSF) .......... 117
PROCHOT Fan Select (PFS) ................................................................................ 117
Fan Output Value (FOV) ........................................................................................ 118
Fan Output PWM Frequency Prescalar (FOPFP) .................................................. 118
Fan Output Nonstop Enable (FONE) ..................................................................... 119
Fan Tachometer Source Selection (FTSS) ............................................................ 119
Fan Tachometer Source Selection (FTSS) ............................................................ 120
Critical Temperature to Full Speed all fan (CTFS) ................................................. 121
Hysteresis of Temperature (HT) ............................................................................ 121
Fan Output Nonstop Value(FONV) ........................................................................ 122
TM
SMART FAN IV Temperature and DC/PWM Table (SFIV)................................. 122
Configure Register of PECI Error (CRPE) ............................................................. 123
Fan Output Min Value when PECI Error (FOMV) .................................................. 124
Mask Register of PECI Error (MRPE) .................................................................... 124
PECI T_DTS Slope Value (PTSV) ......................................................................... 124
PECI T_DTS Offset Value (PTOV) ........................................................................ 125
Tcontrol_Offset Value for CPU Agent (Address : 30h ~ 33h) (TOV) ...................... 125
DTS Delta Tolerance Value (DDTV) ...................................................................... 126
DTS Margin Divisor (DMD) .................................................................................... 127
Bank 4 REGISTER DETAIL........................................................................................ 128
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
8.
External Read Address and Command Register ..................................................... 96
Power Unit Status .................................................................................................... 97
Energy Unit Status ................................................................................................... 98
Retrieving Margin Status Control Registers ............................................................. 98
Tjmax Temperature Target Read/Write for CPU Agent (Address : 30h ~ 33h) ........ 99
Tcontrol Temperature Target Read/Write for CPU Agent (Address : 30h ~ 33h)... 100
Thermal Design Power (TDP) Status for CPU Agent (Address : 30h ~ 33h) ......... 100
Margin Status for CPU Agent (Address : 30h ~ 33h) ............................................. 101
Power Reporting Factor for CPU Agent (Address : 30h ~ 33h) ............................. 101
DTS DRAM Temperature Monitor Enable Control Register................................... 102
DRAM Temperature Value Register (Reterived by PECI RdPkgConfig command)
104
Temperature to Fan Mapping Relationships (TFMR) ............................................. 128
Temperature Source Selection (TSS) .................................................................... 128
Critical Temperature to Full Speed all fan (CTFS) ................................................. 130
Hysteresis of Temperature (HT) ............................................................................ 131
TM
SMART FAN IV Temperature and DC/PWM Table (SFIV)................................. 131
ELECTRICAL CHARACTERISTICS ....................................................................................... 133
8.1
Absolute Maximum Ratings ........................................................................................ 133
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NCT7904D
9.
10.
11.
12.
DC Specification ......................................................................................................... 133
8.2
8.3
AC Specification.......................................................................................................... 134
ORDER INFORMATION ......................................................................................................... 136
TOP MARKING SPECIFICATIONS ........................................................................................ 137
PACKAGE DRAWING AND DIMENSIONS ............................................................................ 138
REVISION HISTORY .............................................................................................................. 139
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NCT7904D
1. GENERAL DESCRIPTION
NCT7904D is an evolving version of the Nuvoton popular Hardware Monitor IC family. NCT7904D
provides several innovative features, Intel PECI1.1/2.0/3.0 interface, and PROCESSOR HOT feature.
Conventionally, NCT7904D can be used to monitor several critical hardware parameters of the system,
including power supply voltages, fan speeds, and temperatures, which are very important for a
high-end computer system, such as server, workstation…etc, to work stably and efficiently.
A 10-bit analog-to-digital converter (ADC) is built inside NCT7904D. NCT7904D can
simultaneously monitor 20 analog voltage inputs (including power 3VDD / 3VSB / VBAT / VTT
monitoring), 12 fan tachometer inputs, 4 fan output control, and 4 remote temperature sensor inputs, 2
of which support current mode (dual current source) temperature measurement method, it also
supports caseopen detection, Watch Dog Timer function, and GPIO pins. The sense of remote
temperature can be performed by thermistors, or directly from thermal diode. NCT7904D provides
PWM (pulse width modulation) for each fan control output pin, and DC fan output mode is supported on
TM
PWM4 pin. Meanwhile, the NCT7904D provides SMART FAN
TM
control, the SMART FAN
IV mode
equips with 4 sets of temperatures setting point each could control fan’s duty cycle, to make the fans
could be operated at the lowest possible speed and the acoustic could be balanced. As for warning
mechanism, NCT7904D provides SMI#, TEMP_ALM#, VOLT_ALM#, and FAN_ALM# to protect the
system. NCT7904D has 1 specific pin to provide address selection so that 2 NCT7904D could be wired
through SMBus interface at the same time.
All of the monitored parameters of the system could be read from time to time through the BIOS or
any management application software. Nuvoton supports the software – “Health Manager” to provide
an easy way to monitor and show the hardware parameters, such as temperature, voltage and fan
speed inputs, furthermore, it provides a convenient method to do the fan control. It can also show the
alarm message when the monitored hardware parameter exceeds the limit, and recodes the history
events.
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NCT7904D
2. FEATURES
2.1
Equipped Specific Interfaces
2
I C / SMBus2.0 Serial Bus Master (max. 400KHz Clock)
2
I C / SMBus2.0 Serial Bus Slave (max. 400KHz Clock)
Intel® PECI (PLATFORM ENVIRONMENT CONTROL INTERFACE) 1.0 / 2.0 / 3.0
AMD SB-TSI
2.2
Monitoring Items
VOLTAGE
Up to 20 voltage sensing inputs
16 general voltage inputs
4 power pins. (3VDD, 3VSB, VBAT and VTT)
4 multi-functions with thermistor temperature inputs (on VSEN2, VSEN4, VSEN6, VSEN8)
2 multi-functions with thermal diode pair (on VSEN2, VSEN3, VSEN4 and VSEN5)
TEMPERATURE
Up to 4 methodologies for capturing temperature information
ADC
=> 2-pair thermal diode channel (current mode) / 4-channel thermistor mode temperature
=> 1 channel on-chip temperature sensor
Intel® PECI interface
=> Automatically retrieving CPU temperature
AMD SB-TSI interface
=> Automatically retrieving CPU temperature
SMBus Master
=> Reading MCH, PCH, CPU and DIMMs temperature through PCH
=> Reading specific external at most 4 thermal sensors.
FAN SPEED
Up to 12 fan tachometer inputs
2.3
PECI (Platform Environment Control Interface)
Support PECI 1.0 / 2.0 / 3.0 full commands
Automatically retrieve CPU temperature and power status
Automatically retrieve DRAM thermal data which is provided by CPU0 and CPU1 only
(Address: 30h and 31h)
Support 4 CPU sockets (eq. 4 PECI address) and 2 domains per CPU address
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NCT7904D
SMART FANTM PWM Output Control
2.4
Up to 4 PWM Outputs
TM
Support 2 modes of fan speed control: SMART FAN
Mode ( RPM mode)
TM
Provide up to 10 SMART FAN
and output fan speed
IV mode and Closed Loop Fan Control
tables to characterize 10 relationships between temperature
The temperature source of table could come from any of temperature information captured
from ADC, PECI, TSI and SMBus Master
Multiple temperature sources could affect multiple fan control outputs
Up to 4 virtual temperature sources feed by host as the parts of fan temperature sources
Up to 4 external temperature sources read from SMBus master I/F which can be the part of
fan temperature sources
Support Fan Control for Intel Sandy Bridge-EP/EX DTS specification
Support DTS (Sensor) Based Thermal Ver. 1.0/2.0 Spec to optimize fan speed control and
acoustics at processor run time
2.5
Alarm Output
Issue SMI# signal to activate system protection
Issue voltage, temperature and fan alarm signals to activate system protection
2.6
Self-initialization
2.7
Self-configuration by reading external EEPROM with SMBus interface
SMBus Master
Support SMBus master function to read EEPROM configuration data and other SMBus
devices
Support SMBus master manual byte read and byte write
Support accessing PCH Thermal Reporting
Support accessing external thermal sensors
2.8
General
Provide up to 11 GPIO pins (GPIO13~16, GPIOA~G, multi-function with other function pins)
LED indication with programmable blinking frequency
Event trigger LED by the external signal with programmable blinking frequency
2
I C / SMBus2.0 serial bus interface (max. 400KHz Clock)
Watch Dog Timer function with an output signal(WDT_RSTOUT#)
1 address selection pins provide 2 selectable SMBus addresses
3.3V operationPackage
Packaged in 48-LQFP(7mm x 7mm) type, RoHS-Compliant and Halogen free
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NCT7904D
3. KEY SPECIFICATIONS
Voltage monitoring accuracy
VSEN inputs
±10mV
Power inputs and VSEN17,18,19 inputs
±60mV
Temperature Sensor Accuracy
Remote Diode Sensor Accuracy (25~85°C)
± 1°C typ.
On-chip Temperature Sensor Accuracy (25~70°C)
± 1°C typ.
Remote Diode Sensor Resolution
0.125 ℃
On-chip Temperature Sensor Resolution
0.125 ℃
Supply Voltage
3.3V ± 5%
Operating Supply Current
15 mA typ.
Operating Temperature Range
-40°C ~ 120°C
*1
*1 Guaranteed by design from -40~120 °C, 100% tested at 85°C.
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NCT7904D
4. PIN CONFIGURATION
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NCT7904D
5. PIN DESCRIPTION
5.1
Pin Type Description
SYMBOL
DESCRIPTION
TTL
TTL level
GTL
VTT level
TSI
TSI level
I
Input
O
Output ( Push-pull )
OD
Open-drain output
AIN
Input pin(Analog)
5.2
Pin Description List
PIN NAME
PIN
NO.
POWER
PLANE
TYPE
DESCRIPTION
VREF
1
3VSB
AOUT
Reference voltage output. This pin is for
thermistor application
TR1
D1+
Thermistor 1 sensing input
2
3VSB
AIN
Voltage sensing input. Detection range is
0~2.048V. (default)
VSEN2
D1-
Thermal diode 1 D3
3VSB
AIN
4
3VSB
AIN
VSEN3
TR2
D2+
Thermistor 2 sensing input
Voltage sensing input. Detection range is
0~2.048V.(default)
D2-
Thermal diode 2 D5
3VSB
AIN
6
3VSB
AIN
VSEN5
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Voltage sensing input. Detection range is
0~2.048V
Thermal diode 2 D+
VSEN4
TR3
Thermal diode 1 D+
Voltage sensing input. Detection range is
0~2.048V
Thermistor 3 sensing input
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NCT7904D
PIN NAME
PIN
NO.
POWER
PLANE
TYPE
Voltage sensing input. Detection range is
0~2.048V
VSEN6
VSEN7
DESCRIPTION
7
3VSB
AIN
TR4
Voltage sensing input. Detection range is
0~2.048V
Thermistor 4 sensing input
8
3VSB
AIN
VSEN9
9
3VSB
AIN
Voltage sensing input. Detection range is
0~2.048V
VSEN10
10
3VSB
AIN
Voltage sensing input. Detection range is
0~2.048V
VSEN11
11
3VSB
AIN
Voltage sensing input. Detection range is
0~2.048V
VSEN12
12
3VSB
AIN
Voltage sensing input. Detection range is
0~2.048V
VSEN13
13
3VSB
AIN
Voltage sensing input. Detection range is
0~2.048V
VSEN14
14
3VSB
AIN
Voltage sensing input. Detection range is
0~2.048V
VSEN8
3VDD
15
3VSB
16
GPIOF
POWE
R
+3V VDD power. It is also a voltage monitor
channel
Bypass with the parallel combination of 10µF
(electrolytic or tantalum) and 0.1µF (ceramic)
bypass capacitors
+3V VSB power. It is also a voltage monitor
channel
Bypass with the parallel combination of 10µF
(electrolytic or tantalum) and 0.1µF (ceramic)
bypass capacitors
-
POWE
R
3VSB
TTL
I/OD
General Purpose I/O F (default)
3VSB
TTL
OD
System Management Interrupt.
CPU1 PROCHOT# signal
17
SMI#
Voltage sensing input. Detection range is
0~2.048V
P1_PROCHOT#
18
3VSB
GTL
I/O
VTT
(VSEN1)
19
--
POWE
R
VTT power pin. This power will be also
monitored as VSEN1
VTT
GTL
I/O
Intel PECI interface signal. The power source
is pin 19 (VTT)
3VSB
TTL
I/OD
General Purpose I/O 16
PECI
20
GPIO16
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NCT7904D
POWER
PLANE
TYPE
SCL_TSI
3VSB
TSI
OD
P1_THERMTRIP#
3VSB
GTL I
CPU1 THERMTRIP# signal. Pull-down it when
unused.
3VSB
TSI
I/OD
Data line of AMD SB_TSI interface
PIN NAME
PIN
NO.
21
SDA_TSI
DESCRIPTION
®
Clock line of AMD SB_TSI interface
®
CLKIN(33M,
14.318M, 48M)
22
3VSB
TTL I
Clock input. 14.318MHz or 33MHz or 48MHz
could be applied to this pin with corresponding
register configuration. Default setting is for
33MHz
This clock is for PECI and fan speed monitor
S_SMB_CLK
23
3VSB
TTL I
SMBus clock line for this device being slave
device
S_SMB_DATA
24
3VSB
TTL
I/OD
SMBus data line for this device being slave
device
TTL
OD
SMBus clock line for this device being master
device
TTL I
Fan tachometer input
LED_EVNT_IN#
TTL I
An input event to trigger LED_OUT
M_SMB_DATA
TTL
I/OD
SMBus data line for this device being master
device
TTL I
Fan tachometer input
M_SMB_CLK
FANIN_11
FANIN_12
25
26
3VSB
3VSB
TTL
OD
LED_OUT
ADDR
27
3VSB
WDT_RSTOUT#
GPIOG
28
3VSB
VSEN17
TTL I
When pin LED_EVNT_IN is asserted a low
pulse, this pin will output a pulse to drive LED
on or blinking
SMBus slave address strap selection pin
Strapped to low, the 7-bit address is 0101101
Strapped to high, the 7-bit address is 0101110
TTL
OD
Watch dog timer reset output
TTL
I/OD
General Purpose I/O G (default)
AIN
Voltage sensing input. Detection range is
0~3.3V
FANIN_1
29
3VSB
TTL I
Fan tachometer input
PWM1
30
3VSB
TTL
OD
Fan speed control PWM output. This is 5V
tolerant
FANIN_2
31
3VSB
TTL I
Fan tachometer input
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NCT7904D
PIN NAME
PIN
NO.
POWER
PLANE
TYPE
DESCRIPTION
PWM2
32
3VSB
TTL
OD
Fan speed control PWM output. This is 5V
tolerant
FANIN_3
33
3VSB
TTL I
Fan tachometer input
TTL
OD
Fan speed control PWM output. This is 5V
tolerant
AIN
Voltage sensing input. Detection range is
0~3.3V
PWM3
34
3VSB
VSEN18
FANIN_4
35
3VSB
TTL I
Fan tachometer input
3VSB
TTL
OD
AOUT
Fan speed control PWM or DC output. A
register bit could be programmed to select
PWM or DC mode. DC output is default mode.
This is without 5V tolerant
AIN
Voltage sensing input. Detection range is
0~3.3V
PWM4/DCOUT
36
VSEN19
FANIN_5
3VSB
TTL I
Fan tachometer input.(default)
GPIO13
3VSB
TTL
I/OD
General Purpose I/O 13
FANIN_6
3VSB
TTL I
Fan tachometer input (default)
GPIO14
3VSB
TTL
I/OD
General Purpose I/O 14
FANIN_7
3VSB
TTL I
Fan tachometer input (default)
GPIO15
3VSB
TTL
I/OD
General Purpose I/O 15
FANIN_8
3VSB
TTL I
Fan tachometer input (default)
GPIOA
3VSB
TTL
I/OD
General Purpose I/O A
VOLT_ALM#
3VSB
TTL
OD
Voltage abnormal alert output signal ( active
low )
3VSB
TTL I
Fan tachometer input (default)
GPIOB
3VSB
TTL
I/OD
General Purpose I/O B
FAN_ALM#
3VSB
TTL
OD
Fan speed abnormal alert output signal ( active
low )
3VSB
TTL I
Fan tachometer input (default)
37
38
39
40
FANIN_9
41
42
FANIN_10
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PIN NAME
PIN
NO.
GPIOC
GND
POWER
PLANE
TYPE
3VSB
TTL
I/OD
POWE
R
43
DESCRIPTION
General Purpose I/O C
GROUND
TTL
OD
Temperature abnormal alert output signal
( active low )
GPIOD
TTL
I/OD
General Purpose I/O D (default)
LED
TTL
OD
Programmable frequency LED output signal
TTL
I/OD
General Purpose I/O E (default)
TTL
OD
Beeper signal output when over heat event
happens
TTL I
System reset input
TTL I
Case Open detection input signal. An active
low input from an external device when case is
opened. This event will be latched even when
the case is closed. Pull-down it when unused.
POWE
R
VBAT power for Case Open detection and
status log
TEMP_ALM#
44
GPIOE
45
3VSB
3VSB
BEEP
RESETIN#
46
CASEOPEN#
47
VBAT
48
3VSB
VBAT
* The recommended connection for Unused Pin
(1) For digital input pin, pull down to GND.
(2) For digital output pin, keep floating.
(3) For analog input pin, keep floating.
(4) For analog output pin, keep floating.
(5) For VTT pin, keep floating.
(6) For VBAT pin, connect to 3VSB.
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6. FUNCTIONAL DESCRIPTION
6.1
Access Interface
NCT7904D provides SMBus interface, which is compliant with SMBus 2.0 specification. The 7-bit
serial address is selected to be 0101101 or 0101110 by pin ADDR. When pin ADDR is strapped to
low, the SMBus address is 0x5A(write)/0x5B(read) ; when pin ADDR is strapped to high, the SMBus
address is 0x5C(write)/0x5D(read).
NCT7904D supports the bus speed with 0~400KHz.
6.1.1
Data write to the internal register
6.1.2 Data read from the internal register
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6.2
Address Setting
NCT7904D has one address selection pin, the SMBus address will be strapped when 3VSB ready.
The address will be retained as long as the 3VSB of NCT7904D is maintained. The pull-up power
plane must be the same as the 3VSB power of NCT7904D.
ADDR
ADDRESS
0
0101 101X
1
0101 110X
X=Read/Write Bit
6.3
Temperature Monitor Data Format
The temperature data with 11-bit 2`s complement format
TEMPERATURE
8-BIT DIGITAL OUTPUT HIGH BYTE
3-BIT DIGITAL OUTPUT LOW BYTE
+127.875°C
0111,1111
XXXX,X111
+25.750°C
0001,1001
XXXX,X110
+2.250°C
0000,0010
XXXX,X010
+1.125°C
0000,0001
XXXX,X001
+0.000°C
0000,0000
XXXX,X000
- 1.125°C
1111,1110
XXXX,X111
- 2.250°C
1111,1101
XXXX,X110
- 25.750°C
1110,0110
XXXX,X010
- 127.875°C
1000,0000
XXXX,X001
6.4
Voltage Sense Data Format
VSEN Low Byte together with VSEN High Byte forms the 11-bit count value. If VSEN High Byte
readout is read successively, the NCT7904D will latch the VSEN Low Byte for next read. Then
voltage readout high byte and low byte are combined to 11-bitVoltageValue.
For voltage monitoring, real voltage calculations should follow the formula:
VSEN1~14 : Voltage(V) =
11bitCountValue× 0.002
3VSB,3VDD,VBAT,VSEN17,18,19 : Voltage(V)
= 11bitCountValue× 0.006
* VSEN17,18,19 are embedded internal voltage divider resistors.
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6.5
FAN_IN Count Calculation
The FAN_IN tachometer high byte and low byte are combined to 13-bitCountValue. Real RPM
(Rotate per Minute) calculation should follow the formula:
FanSpeed ( RPM ) =
1.35 × 10 6
(13 − bitCountValue) × ( FanPoles )
4
In this formula, FanPole stands for the number of NS pole pairs inside the fan. Normally an N-S-N-S
Fan (FanPole=4) generates 2 pulses after completing one rotation.
6.6
FAN_OUT Duty Cycle/DC output Calculation
The NCT7904D provides 4 set of PWM and 1 set of DC output for fan speed control. The duty cycle
of PWM can be programmed by an 8-bit register. The expression of duty cycle can be represented as
follow formula:
Programmed 8 - bit Register Value
Duty − cycle(%) =
× 100%
255
The DC output can be programmed by an 8-bit register. The expression of DC level can be
represented as follow formula:
Programmed 8 - bit Register Value
DC output (V) = 3VDD ×
255
6.7
Fan Speed Control
Except for traditional Fan Duty control, the latest closed loop fan control (RPM Mode) has been
provided by the NCT7904D. Due to PECI negative temperature format, the fan control also supports
negative temperature representation. It would be much easy to implement fan control by PECI
reading. In addition to PECI CPU temperature, the NCT7904D also supports fan control, which is
responded to CPU power.
In Smart Fan Mode, there are some Fan control parameters as below descriptions:
6.7.1 Step Up Time / Step Down Time
Smart Fan is designed for the smooth operation of the fan. The Up Time / Down Time register
defines the time interval between successive duty increases or decreases. If this value is set too
small, the fan will not have enough time to speed up after tuning the duty and sometimes may result
in unstable fan speed. On the other hand, if Up Time / Down Time is set too large, the fan may not
work fast enough to dissipate the heat. This register should never be set to 0, otherwise, the fan
duty will be abnormal.
6.7.2 Fan Output Nonstop Value
It takes some time to bring a fan from still to working state. Therefore, Nonstop value are designed
with a minimum fan output to keep the fan working when the system does not require the fan to help
reduce heat but still want to keep the fast response time to speed up the fan.
6.7.3 Smart Fan Control Table
TM
SMART FAN IV and Close Loop Fan Control Mode offer 4 slopes to control the fan speed. The 3
slopes can be obtained by setting FanDuty/RPM1~FanDuty/RPM4 and T1~T4 through the registers.
When the temperature rises, FAN Output will calculate the target Fan Duty/RPM based on the
current slope. For example, assuming Tx is the current temperature and Fan Duty/RPMy is the
target, then the slope:
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X2 =
Fan Output:
(FanDuty3 / RPM 3) − (FanDuty 2 / RPM 2)
(T 3 − T 2)
T arg et FanDuty or RPM = (FanDuty 2 or RPM 2 ) + (Tx − T 2 ) ⋅ X 2
SMART FAN
TM
IV & Close Loop Fan Control Mechanism
Fanduty/RPM
(unit RPM = 50 )
Critical Hyst.
Operation Hyst.
FullSpeed (FF, 100%)
Fanduty4/RPM4
Fanduty3/RPM3
Ty
Fanduty2/RPM2
X3
X2
X1
Fanduty1/RPM1
Temperature
T1
T2
Tx
T3
T4 TRCritical
In
TM
addition, SMART FAN IV & Close Loop Fan Control can also set up Critical Temperature and
Hysteresis. If the current temperature exceeds Critical Temperature, external fan will be forced by
maximum Fan Duty to meet the largest target Fan Duty or RPM, Which is 0xFF. The target Fan Duty
& RPM value will be determined in accordance to the slope only when the temperature falls below
(TCritical – Critical Hyst.)
NCT7904D provides several temperature sources selects to map the fan, the algorithm will make a
decision to control the fan as below figure:
Any Temp request
faster Fan??
Yes
Speed Up
Yes
Hold current
Speed
No
Any Temp request f
hold current speed??
Slow Down
No
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6.7.4 DTS (Sensor) Based Fan Control
NCT7904D fully follows Intel latest DTS Based Thermal Spec to come out an easy used fan speed
control algorithm which has involved traditional thermal cruise mode concept. Users are supposed
to have related document to capture Intel’s concept.
The principle of DTS based fan control behavior will be described with the figure in the below. First
of all, there are two mainly behaviors, which is distinguished by whether Tsensor is larger than
Tcontrol_spec.
If Tcontrol_spec is larger than Tsensor, the fan control behavior will obey left plane and thermal
cruise mode’s Target_Temp is set as Target_Reg. Once Tsensor > Target_Reg, the fan out duty
will continuously increases by one duty until Tsensor is under Target_Reg. In contrary, if Tsensor <
(Target_Reg – Tolerance), the fan out duty will continuously decreases by one duty until Tsensor is
over (Target_Reg – Tolerance).
If Tcontrol_spec is smaller than Tsensor, the fan control behavior will obey right plane and thermal
cruise mode’s Target_Temp is set as TDTS which just is Intel’s DTS thermal profile. Once Tsensor
> TDTS, the fan out duty will continuously increases by (1+|M|) duty until Tsensor is under TDTS.
The symbol of M represents “Margin”. It could be provided by NCT7904D itself. In contrary, if
Tsensor < (TDTS – Tolerance), the fan out duty will continuously decreases by (1+|M|) duty until
Tsensor is over (TDTS – Tolerance).
For both of plane, the gray region means that the fan out duty is unchanged at this moment.
Tsensor
+1+|M|, +1+|M|, +1+|M|, … or
+1+|M|/2, +1+|M|/2, +1+|M|/2, …
+1, +1, +1, ...
Target_Temp
TDTS
Keep Fan
Target_Reg
Tolerance
-1, -1, -1, ...
Tcontrol_spec > Tsensor
=> Target_Temp = Target_Reg
-1-|M|, -1-|M|, -1-|M|, … or
-1-|M|/2, -1-|M|/2, -1-|M|/2, …
Tsensor > Tcontrol_spec
=> Target_Temp =
TDTS
Thermal Cruise Mode
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6.8
PECI
PECI (Platform Environment Control Interface) is a new digital interface to read plentiful information
of Intel® CPUs. With a bandwidth ranging from 2 Kbps to 2 Mbps, PECI uses a single wire for
self-clocking and data transfer.
6.8.1
Operation Mode
NCT7904D provides two operation modes. One is active mode, the other is passive.
For active mode, NCT7904D serves as a host to initiate a message transaction. NCT7904D provides
automatic polling procedure for CPU temperature, CPU power and DRAM temperature. These
thermal data could be continuously updated without any firmware intervention. In contrarily, except
for what mentioned above, user still could write out or read in data to / from CPU by practicing
manual commands which are pre-configured by external firmware.
In passive mode, NCT7904D just monitor the message over the PECI bus with silence and then only
extract CPU’s DTS thermal data for its fan speed control purpose.
6.8.2
CPU Temperature and Power Reporting
In NCT7904D, it supports CPU temperature and power reporting. And both of reading could be
associated to NCT7904D’s fan control algorithm.
®
For CPU temperature, by interfacing to the Digital Thermal Sensor (DTS) in the Intel CPU, PECI
reports a negative temperature (in counts) relative to the processor’s temperature at which the
thermal control circuit (TCC) is activated. At the TCC Activation temperature, the Intel CPU will
operate at reduced performance to prevent the device from thermal damage.
The PECI temperature values returning from the CPU are in “counts” which are approximately linear
in relation to changes in temperature in degrees centigrade. However, this linearity is approximate
and cannot be guaranteed over the entire range of PECI temperatures. For further information, refer
to the PECI specification. However NCT7904D has a biasing factor for customer to characterize the
relation between “counts” and “temperature”.
Figure A shows a typical fan speed (PWM duty cycle) and PECI temperature relationship. SMART
TM
FAN IV
Fan Speed
(PWM Duty Cycle)
Tcontrol
TCC Activation
Duty1
Duty2
-20
-10
0
PECI Temperature (counts)
Fig. A PECI Temperature
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In this illustration, when PECI temperature is -20, the PWM duty cycle for fan control is at Duty2.
When CPU is getting hotter and the PECI temperature is -10, the PWM duty cycle is at Duty1.
At Tcontrol PECI temperature, the recommendation from Intel is to operate the CPU fan at full speed.
Therefore Duty1 is 100% if this recommendation is followed. The value of Tcontrol can be obtained
by reading the related Machine Specific Register (MSR) in the Intel CPU. The Tcontrol MSR address
is usually in the BIOS Writer’s guide for the CPU family in question. Refer to the relevant CPU
documentation from Intel for more information. In this example, Tcontrol is -10.
When the PECI temperature is below -20, the duty cycle is fixed at Duty2 to maintain a minimum
(and constant) RPM for the CPU fan.
For CPU power reporting, the NCT7904D routinely retrieves CPU energy and then convert it to
power. The refreshing rate of power is 0.3 sec. In order to minimize the effect of suddenly huge
power changing, the running time average algorithm has been implemented.
6.8.3
DRAM Thermal Data Reporting
NCT7904D can automatically report all 24 DIMMs thermal status which are provided by Intel CPU0
and CPU1 agent. In addition to each DIMM temperature, NCT7904D also records the highest DIMM
temperature in the specific channel. Here is the relationship among CPU, Channel and DIMM.
Both the Channel Index and DIMM Index follow PECI3.0 RdPkgConfig() command
format.
Agent Address
Channel_Index
Channel_0
Channel_1
CPU0_30h
Channel_2
Channel_3
Channel_0
CPU1_31h
Channel_1
Channel_2
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DIMM Index
Register Location
DIMM_0
T_D0C0_C0
DIMM_1
T_D1C0_C0
DIMM_2
T_D2C0_C0
DIMM_0
T_D0C1_C0
DIMM_1
T_D1C1_C0
DIMM_2
T_D2C1_C0
DIMM_0
T_D0C2_C0
DIMM_1
T_D1C2_C0
DIMM_2
T_D2C2_C0
DIMM_0
T_D0C2_C0
DIMM_1
T_D1C2_C0
DIMM_2
T_D2C2_C0
DIMM_0
T_D0C0_C1
DIMM_1
T_D1C0_C1
DIMM_2
T_D2C0_C1
DIMM_0
T_D0C1_C1
DIMM_1
T_D1C1_C1
DIMM_2
T_D2C1_C1
DIMM_0
T_D0C2_C1
DIMM_1
T_D1C2_C1
DIMM_2
T_D2C2_C1
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Agent Address
Channel_Index
Channel_3
6.8.4
DIMM Index
Register Location
DIMM_0
T_D0C3_C1
DIMM_1
T_D1C3_C1
DIMM_2
T_D2C3_C1
PECI Listening
It provides another way to obtain CPU’s DTS thermal data. NCT7904D only recognizes GetTemp()
command. Once GetTemp() appears on PECI bus and entire message is without FCS error, the
CPU’s DTS temperature will be extracted and recorded. These data could be temperature source of
fan speed control.
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6.9
SMI# Output
6.9.1 Temperature
SMI# for temperature monitoring provides 3 modes.
6.9.1.1. Comparator Interrupt Mode
Temperature exceeding Twarning causes an interrupt and this interrupt will be reset when
reading all of the Interrupt Status Registers. Once an interrupt event has occurred by exceeding
Twarning, then reset, if the temperature remains above the Twarning Hysteresis, the interrupt will
occur again when the next conversion has completed. If an interrupt event has occurred by
exceeding Twarning and not reset, the interrupts will not occur again. The interrupts will continue
to occur in this manner until the temperature goes below Twarning Hysteresis.
6.9.1.2. Two-Times Interrupt Mode
Temperature exceeding Tcritical / Twarning causes an interrupt and then temperature going
below Tcritical Hysteresis / Twarning Hysteresis will also cause an interrupt if the previous
interrupt has been reset by reading all the Interrupt Status Register. Once an interrupt event has
occurred by exceeding Tcritical / Twarning, then reset, if the temperature remains above the
Tcritical Hysteresis / Twarning Hysteresis, the interrupt will not occur.
6.9.1.3. One-Time Interrupt Mode
Temperature exceeding Tcritical / Twarning causes an interrupt and then temperature going
below Tcritical Hysteresis / Twarning Hysteresis will not cause an interrupt. Once an interrupt
event has occurred by exceeding Tcritical / Twarning, then going below Tcritical Hysteresis /
Twarning Hysteresis, an interrupt will not occur again until the temperature exceeding Tcritical /
Twarning.
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SMI comparator mode
SMI two time mode
SMI one time mode
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6.9.2 Voltage
SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeds high limit or going below
low limit, it will causes an interrupt if the previous interrupt has been reset by reading all the interrupt
Status Register.
6.9.3 Fan
SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeds the limit, or exceeding and
then going below the limit, it will cause an interrupt if the previous interrupt has been reset by
reading all the interrupt Status Register.
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6.10 EEPROM Self-Initialization
6.10.1 EEPROM Format
The content of the EEPROM can be loaded to the registers of NCT7904D for self-initialization
should obey this data format.
An example for Default Fan Speed set to FF(hex) in bank 2 :
Address
Data
Example
00h
ID_1
79h
01h
ID_2
61h
02h
Register Address 1
FFh
03h
Register Data 1
02h
04h
Register Address 2
04h
05h
Register Data 2
FFh
…
…
…
…
…
…
ID_1
79h
ID_2
61h
6.10.2 Chip Initialization
When NCT7904D detects power-on-reset, initialization process will start loading data from
EEPROM. NCT7904D SMBUS (M_SMB_CLK, M_SMB_DATA) will be a master and issue
consecutive read byte commands (EEPROM address is A0h). NCT7904D will check receive data to
decide that which actions should be followed.
Case 1 : No acknowledge in first transaction, NCT7904D will terminate the initialization process to
normal. And set LD_FAIL and LD_FINISH to 1 to note host the load status.
Case 2 : NCT7904D will check first two bytes by ID_1 and ID_2. If match, the process will continue.
Otherwise, the process will terminate like Case 1.
Case 3 : Two bytes as a unit. NCT7904D will see first as the address of the register and second as
the data. Sequentially, NCT7904D will write the data to the specific address.
Case 4 : When receiving the unit which store the data (ID_2 following ID_1), NCT7904D will stop
initialization and back to normal and set LD_FAIL to 0 and LD_FINISH to 1 to note host the load
status. Otherwise, the access will keep going.
The EEPROM loading would be started from NCT7904D power-on immediately, when implements
the EEPROM self-initialization, the requested 3VSB power rising time must less than 60uS.
Note:
1. LD_FAIL and LD_FINISH are in address 00h in bank 0.
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6.11 PCH Thermal Data Report
6.11.1 PCH Thermal Read
When enable PCH read function (set EN_PCH_RD to 1), NCT7904D SMBUS (M_SMB_CLK,
M_SMB_DATA) will be a master and issue consecutive block read commands (PCH address can
be configuration). NCT7904D will store the received data to the registers (F0h~FDh in bank 0) by
PCH data format.
6.11.2 PCH Thermal Data Format
The PCH Thermal data may appear in either Byte 0 or Byte 1 depending on the specific ME
firmware in use. Please contact Intel directly for information on your specific ME Firmware
implementation.
6.12 SMBus Master Auto Read External Thermal Sensor
6.12.1 External Thermal Sensor Setting
Before using this function, there are several registers must be set:
1. Configuration external sensor SMBus address and command where temperature store in. (6Ch
~ 73h in bank 2).
2. Set relative port enable and enable external temperature read (6Ah in bank 2).
6.12.2 Temperature Read Process
After proper setting, NCT7904D will auto read, by setting, external sensor temperature from SMBus
master I/F. The read temperature will be stored in the registers (BCh ~ BFh in bank 0), respectively.
These temperatures can be the sources of the fan controller in NCT7904D. Any not enable port can
normally be the virtual temperature simply written by host to do advanced fan control.
6.13 PROCHOT# Behavior
6.13.1 PROCHOT# Input
When enable PROCHOT# input monitor function (set EN_PH1 to 1 in bank 0, PH1_MD to 1 in bank
1), NCT7904D will monitor P1_PROCHOT# pin, count the time between two falling edge as
P1_PROCHOT#_DVAL[7:0] and the time between one rising edge to one falling edge
P1_PROCHOT#_NVAL[7:0], and stores these two to the registers. System management can
monitor these two values to know the thermal status for relative CPU. The timer to the counter is
settable from register, and the default is 22us.
6.13.2 PROCHOT# Output
When enable PROCHOT# output function (set EN_PH1 to 1 in bank 0, PH1_MD to 0 in bank 1),
NCT7904D will drive low to P1_PROCHOT# pin based on several thermal events over heat.
There are three temperature sources listed as blow,
Source 1 : 4 remote temperature inputs or build-in thermal diode temperature
Source 2 : Up to 8 CPU temperatures
Source 3 : Up to 4 CPU Powers (by PECI)
The frequency and duty cycle of PROCHOT# output are settable by PH1_FSEL[1:0] and
PH1_DC[3:0], respectively.
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6.14 LED Behavior
6.14.1 Event Trigger LED
When enable LED function (set EN_E_LED to 1), NCT7904D will detect LED_EVNT_IN# pin as the
drive condition for LED_OUT. LED pin will be float when LED_EVNT_IN# pin is detected high, and
LED pin will drive low when LED_EVNT_IN# is detected low. LED driving low frequency and polarity
can be settable.
6.14.2 Programmable LED
When enable programmable LED function (set EN_P_LED to 1), NCT7904D will drive register data
P_LED_DATA to LED pin. Drive low frequency and polarity can be settable.
6.15 BEEP Function
6.15.1 Output Signaling
Output signaling for BEEP is controlled by an internal signal mixer. The baseband signal is a period
signal which is at frequency 1Hz with duty cycle 50% (i.e. the period for high and low level is 500ms.)
The high level of the baseband signal will mix the signal which is at frequency 700Hz with duty cycle
50%, and the low level of the baseband signal will mix the signal which is at frequency 350Hz with
duty cycle 50%, causing the ambulance sound for alarm to users.
6.15.2 BEEP Activation
When enable BEEP function (set EN_BEEP to 1), NCT7904D will drive the signal to BEEP pin
when BEEP sources selected and over limitation. Otherwise, NCT7904D will float the pin. The
sources are defined in relative registers.
6.16 THERMTRIP# Function
6.16.1 Power by VSB
When enable THERMTRIP function (set EN_THRM to 1), NCT7904D will detect low and log the
signal to THRM_STS register. The THRM_STS register will be cleared by setting the CLR_THRM
register to 1 and the CLR_THRM will be auto cleared.
6.16.2 Power Only by VBAT
NCT7904D will keep the THRM_STS register when VBAT power-on, losing the data when VBAT
power-off.
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7. REGISTER DESCRIPTION
7.1
Bank 0 REGISTER DETAIL
7.1.1 Global Control Register
Location: Bank 0 Address 00HEX
Type:
Read/Write
Reset:
Power On Reset
Default Value: 01HEX
BIT
DESCRIPTION
7
INIT_RST
Registers initial reset (Auto be cleared when reset process completed)
6
Reserved
5
LD_FAIL
0 = EEPROM present and no error happened
1 = EEPROM not present or error happened
4
LD_FINISH
0 = EEPROM data load processing
1 = EEPROM data load finished
3
LOCK
0 = RESETIN# will reset registers
1 = RESETIN# will not reset registers
(This bit will be also cleared when set INIT_RST)
2
Reserved
1-0
CLKIN_SEL[1:0]
00BIN = 14.318MHz
01BIN = 33MHz (default)
10BIN = 48MHz
11BIN = Reserved
7.1.2 SMB Slave Address Register
Location: Bank 0 Address 0CHEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 5AHEX/5CHEX
BIT
7-0
DESCRIPTION
SMB_SLV_ADDR[7:0]
5AHEX = ADDR pin strapped low
5CHEX = ADDR pin strapped high
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7.1.3 Nuvoton Vendor ID Register
Location: Bank 0 Address 0DHEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 50HEX
BIT
7-0
DESCRIPTION
VENDOR_ID[7:0]
7.1.4 Nuvoton Chip ID Register
Location: Bank 0 Address 0EHEX
Type:
Read Only
Reset:
Power On Reset
Default Value: C5HEX
BIT
7-0
DESCRIPTION
CHIP_ID[7:0]
7.1.5 Nuvoton Device ID Register
Location: Bank 0 Address 0FHEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 5xHEX
BIT
7-0
DESCRIPTION
DEVICE_ID[7:0]
7.1.6 Programmable LED Register
Location: Bank 0 Address 18HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
DESCRIPTION
4-3
EN_P_LED
0 = Disable
1 = Enable
P_LED_POL
0 = LED output active low
1 = LED output active high
P_LED_DATA
0 = Output don’t drive
1 = Output drive
Reserved
2-0
P_LED_FSEL[2:0]
7
6
5
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BIT
DESCRIPTION
000BIN = 4Hz
001BIN = 2Hz
010BIN = 1Hz
011BIN = 0.5Hz
100BIN = 0.25Hz
101BIN = 0.125Hz
110BIN = 0.0625Hz
111BIN = 0Hz
7.1.7 Event Control LED Register
Location: Bank 0 Address 19HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
DESCRIPTION
7
EN_E_LED
0 = Disable
1 = Enable (LED_OUT will controlled by LED_EVNT_IN#)
6
E_LED_POL
0 = LED output active low
1 = LED output active high
5-3
Reserved
2-0
E_LED_FSEL[2:0]
000BIN = 4Hz
001BIN = 2Hz
010BIN = 1Hz
011BIN = 0.5Hz
100BIN = 0.25Hz
101BIN = 0.125Hz
110BIN = 0.0625Hz
111BIN = 0Hz
7.1.8 Monitor Enable Control Register
Location:
VT_ADC_CTRL0
VT_ADC_CTRL1
VT_ADC_CTRL2
PH_CTRL0
FANIN_CTRL0
FANIN_CTRL1
DTS_T_CTRL0
DTS_T_CTRL1
DTS_P_CTRL0
Nuvoton Confidential
- Bank 0 Address 20HEX
- Bank 0 Address 21HEX
- Bank 0 Address 22HEX
- Bank 0 Address 23HEX
- Bank 0 Address 24HEX
- Bank 0 Address 25HEX
- Bank 0 Address 26HEX
- Bank 0 Address 27HEX
- Bank 0 Address 28HEX
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Type:
Reset:
Read / Write
Power On Reset
RESETIN# with LOCK=0
VT_ADC_CTRL0 – Voltage Temperature Monitoring Control Register
Location: Bank 0 Address 20HEX
Default Value: FFHEX
BIT
DESCRIPTION
7
EN_VSEN8 – Enable VSEN8 voltage monitoring.
0 = Disable
1 = Enable
6
EN_VSEN7 – Enable VSEN7 voltage monitoring.
0 = Disable
1 = Enable
5
EN_VSEN6 – Enable VSEN6 voltage monitoring.
0 = Disable
1 = Enable
4
EN_VSEN5 – Enable VSEN5 voltage monitoring.
0 = Disable
1 = Enable
3
EN_VSEN4 – Enable VSEN4 voltage monitoring.
0 = Disable
1 = Enable
2
EN_VSEN3 – Enable VSEN3 voltage monitoring.
0 = Disable
1 = Enable
1
EN_VSEN2 – Enable VSEN2 voltage monitoring.
0 = Disable
1 = Enable
0
EN_VSEN1 – Enable VSEN1 voltage monitoring.
0 = Disable
1 = Enable
VT_ADC_CTRL1 – Voltage Temperature Monitoring Control Register
Location: Bank 0 Address 21HEX
Default Value: 7FHEX
BIT
DESCRIPTION
7
EN_VBAT – Enable VBAT voltage monitoring.
0 = Disable
1 = Enable
6
EN_3VDD – Enable 3VDD voltage monitoring.
0 = Disable
1 = Enable
5
EN_VSEN14 – Enable VSEN14 voltage monitoring.
0 = Disable
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BIT
DESCRIPTION
1 = Enable
4
EN_VSEN13 – Enable VSEN13 voltage monitoring.
0 = Disable
1 = Enable
3
EN_VSEN12 – Enable VSEN12 voltage monitoring.
0 = Disable
1 = Enable
2
EN_VSEN11 – Enable VSEN11 voltage monitoring.
0 = Disable
1 = Enable
1
EN_VSEN10 – Enable VSEN10 voltage monitoring.
0 = Disable
1 = Enable
0
EN_VSEN9 – Enable VSEN9 voltage monitoring.
0 = Disable
1 = Enable
VT_ADC_CTRL2 – Voltage Temperature Monitoring Control Register
Location: Bank 0 Address 22HEX
Default Value: 03HEX
BIT
7-5
DESCRIPTION
Reserved
4
EN_VSEN19 – Enable VSEN19 voltage monitoring.
0 = Disable (This pin will change to PWM4/DCOUT)
1 = Enable
3
EN_VSEN18 – Enable VSEN18 voltage monitoring.
0 = Disable (This pin will change to PWM3)
1 = Enable
2
EN_VSEN17 – Enable VSEN17 voltage monitoring.
0 = Disable (This pin will change to WDT_RSTOUT#/GPIOG)
1 = Enable
1
EN_LTD – Enable local temperature monitoring.
0 = Disable
1 = Enable
0
EN_V3VSB – Enable V3VSB voltage monitoring.
0 = Disable
1 = Enable
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PH_CTRL0 – PROCHOT Monitoring Control Register
Location: Bank 0 Address 23HEX
Default Value: 01HEX
BIT
7-1
0
DESCRIPTION
Reserved
EN_PH1 – Enable P1_PROCHOT# monitoring.
0 = Disable
1 = Enable
FANIN_CTRL0 – FANIN Monitoring Control Register
Location: Bank 0 Address 24HEX
Default Value: FFHEX
BIT
DESCRIPTION
7
EN_FANIN_8 – Enable FANIN_8 monitoring.
0 = Disable
1 = Enable
6
EN_FANIN_7 – Enable FANIN_7 monitoring.
0 = Disable
1 = Enable
5
EN_FANIN_6 – Enable FANIN_6 monitoring.
0 = Disable
1 = Enable
4
EN_FANIN_5 – Enable FANIN_5 monitoring.
0 = Disable
1 = Enable
3
EN_FANIN_4 – Enable FANIN_4 monitoring.
0 = Disable
1 = Enable
2
EN_FANIN_3 – Enable FANIN_3 monitoring.
0 = Disable
1 = Enable
1
EN_FANIN_2 – Enable FANIN_2 monitoring.
0 = Disable
1 = Enable
0
EN_FANIN_1 – Enable FANIN_1 monitoring.
0 = Disable
1 = Enable
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FANIN_CTRL1 – FANIN Monitoring Control Register
Location: Bank 0 Address 25HEX
Default Value: 03HEX
BIT
7-4
DESCRIPTION
Reserved
3
EN_FANIN_12 – Enable FANIN_12 monitoring.
0 = Disable
1 = Enable
2
EN_FANIN_11 – Enable FANIN_11 monitoring.
0 = Disable
1 = Enable
1
EN_FANIN_10 – Enable FANIN_10 monitoring.
0 = Disable
1 = Enable
0
EN_FANIN_9 – Enable FANIN_9 monitoring.
0 = Disable
1 = Enable
DTS_T_CTRL0 – Digital Temperature Monitoring Control Register
Location: Bank 0 Address 26HEX
Default Value: 0FHEX
BIT
7-4
DESCRIPTION
Reserved
3
EN_TCPU4 – Enable DTS CPU4 temperature monitoring (PECI/TSI).
0 = Disable
1 = Enable
2
EN_TCPU3 – Enable DTS CPU3 temperature monitoring (PECI/TSI).
0 = Disable
1 = Enable
1
EN_TCPU2 – Enable DTS CPU2 temperature monitoring (PECI/TSI).
0 = Disable
1 = Enable
0
EN_TCPU1 – Enable DTS CPU1 temperature monitoring (PECI/TSI).
0 = Disable
1 = Enable
DTS_T_CTRL1 – Digital Temperature Monitoring Control Register
Location: Bank 0 Address 27HEX
Default Value: 0FHEX
BIT
7-4
DESCRIPTION
Reserved
3
EN_TCPU8 – Enable DTS CPU8 temperature monitoring (TSI).
0 = Disable
1 = Enable
2
EN_TCPU7 – Enable DTS CPU7 temperature monitoring (TSI).
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BIT
DESCRIPTION
0 = Disable
1 = Enable
1
EN_TCPU6 – Enable DTS CPU6 temperature monitoring (TSI).
0 = Disable
1 = Enable
0
EN_TCPU5 – Enable DTS CPU5 temperature monitoring (TSI).
0 = Disable
1 = Enable
DTS_P_CTRL0 – Digital Power Monitoring Control Register
Location: Bank 0 Address 28HEX
Default Value: 0FHEX
BIT
7-4
DESCRIPTION
Reserved
3
EN_PCPU4 – Enable DTS CPU4 power monitoring (PECI).
0 = Disable
1 = Enable
2
EN_PCPU3 – Enable DTS CPU3 power monitoring (PECI).
0 = Disable
1 = Enable
1
EN_PCPU2 – Enable DTS CPU2 power monitoring (PECI).
0 = Disable
1 = Enable
0
EN_PCPU1 – Enable DTS CPU1 power monitoring (PECI).
0 = Disable
1 = Enable
7.1.9 Monitor Configuration Register
Location:
VT_ADC_VOL_PO - Bank 0 Address 2CHEX
VT_ADC_LTD_PO - Bank 0 Address 2DHEX
VT_ADC_MD
- Bank 0 Address 2EHEX
VT_ADC_PO0
- Bank 0 Address 2FHEX
VT_ADC_PO1
- Bank 0 Address 30HEX
VT_ADC_PO2
- Bank 0 Address 31HEX
VT_ADC_PO3
- Bank 0 Address 32HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
VT_ADC_VOL_PO – Voltage Post Offset Register
Location: Bank 0 Address 2CHEX
Default Value: 00HEX
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BIT
7-0
DESCRIPTION
VT_ADC_VOL_PO[7:0]
Post offset adjustment in voltage
VT_ADC_LTD_PO – LTD Temperature Post Offset Register
Location: Bank 0 Address 2DHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
VT_ADC_LTD_PO[7:0]
Post offset adjustment in LTD temperature
VT_ADC_MD – Voltage Temperature Mode Control Register
Location: Bank 0 Address 2EHEX
Default Value: 00HEX
BIT
7-6
5-4
3-2
1-0
DESCRIPTION
VSEN89_MD[1:0]
00BIN = Voltage monitoring
01BIN = Reserved
10BIN = Reserved
11BIN = Temperature monitoring (thermistor)
When set to thermistor mode, the Pin.8 will be TR4 function,
function.
VSEN67_MD[1:0]
00BIN = Voltage monitoring
01BIN = Reserved
10BIN = Reserved
11BIN = Temperature monitoring (thermistor)
When set to thermistor mode, the Pin.6 will be TR3 function,
function.
VSEN45_MD[1:0]
00BIN = Voltage monitoring
01BIN = Temperature monitoring (thermal diode current mode)
10BIN = Reserved
11BIN = Temperature monitoring (thermistor)
When set to thermistor mode, the Pin.4 will be TR2 function,
function.
VSEN23_MD[1:0]
00BIN = Voltage monitoring
01BIN = Temperature monitoring (thermal diode current mode)
10BIN = Reserved
11BIN = Temperature monitoring (thermistor)
When set to thermistor mode, the Pin.2 will be TR1 function,
function.
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the Pin.9 will be VSEN9
the Pin.7 will be VSEN7
the Pin.5 will be VSEN5
the Pin.3 will be VSEN3
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NCT7904D
VT_ADC_PO0 – Voltage Temperature Post Offset Register
Location: Bank 0 Address 2FHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
VSEN23_PO[7:0]
Post offset adjustment when VSEN23_MD[1:0] in temperature mode
VT_ADC_PO1 – Voltage Temperature Post Offset Register
Location: Bank 0 Address 30HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
VSEN45_PO[7:0]
Post offset adjustment when VSEN45_MD[1:0] in temperature mode
VT_ADC_PO2 – Voltage Temperature Post Offset Register
Location: Bank 0 Address 31HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
VSEN67_PO[7:0]
Post offset adjustment when VSEN67_MD[1:0] in temperature mode
VT_ADC_PO3 – Voltage Temperature Post Offset Register
Location: Bank 0 Address 32HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
VSEN89_PO[7:0]
Post offset adjustment when VSEN89_MD[1:0] in temperature mode
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7.1.10
Voltage Channel and Temperature Monitored Value Register
Location:
VSEN1_HV
VSEN1_LV
VSEN2_HV / TEMP_CH1_HV
VSEN2_LV / TEMP_CH1_LV
VSEN3_HV
VSEN3_LV
VSEN4_HV / TEMP_CH2_HV
VSEN4_LV / TEMP_CH2_LV
VSEN5_HV
VSEN5_LV
VSEN6_HV / TEMP_CH3_HV
VSEN6_LV / TEMP_CH3_LV
VSEN7_HV
VSEN7_LV
VSEN8_HV / TEMP_CH4_HV
VSEN8_LV / TEMP_CH4_LV
VSEN9_HV
VSEN9_LV
VSEN10_HV
VSEN10_LV
VSEN11_HV
VSEN11_LV
VSEN12_HV
VSEN12_LV
VSEN13_HV
VSEN13_LV
VSEN14_HV
VSEN14_LV
3VDD_HV
3VDD_LV
VBAT_HV
VBAT_LV
V3VSB_HV
V3VSB_LV
LTD_HV
LTD_LV
VSEN17_HV
VSEN17_LV
VSEN18_HV
VSEN18_LV
VSEN19_HV
VSEN19_LV
Nuvoton Confidential
- Bank 0 Address 40HEX
- Bank 0 Address 41HEX
- Bank 0 Address 42HEX
- Bank 0 Address 43HEX
- Bank 0 Address 44HEX
- Bank 0 Address 45HEX
- Bank 0 Address 46HEX
- Bank 0 Address 47HEX
- Bank 0 Address 48HEX
- Bank 0 Address 49HEX
- Bank 0 Address 4AHEX
- Bank 0 Address 4BHEX
- Bank 0 Address 4CHEX
- Bank 0 Address 4DHEX
- Bank 0 Address 4EHEX
- Bank 0 Address 4FHEX
- Bank 0 Address 50HEX
- Bank 0 Address 51HEX
- Bank 0 Address 52HEX
- Bank 0 Address 53HEX
- Bank 0 Address 54HEX
- Bank 0 Address 55HEX
- Bank 0 Address 56HEX
- Bank 0 Address 57HEX
- Bank 0 Address 58HE
- Bank 0 Address 59HEX X
- Bank 0 Address 5AHEX
- Bank 0 Address 5BHEX
- Bank 0 Address 5CHEX
- Bank 0 Address 5DHEX
- Bank 0 Address 5EHEX
- Bank 0 Address 5FHEX
- Bank 0 Address 60HEX
- Bank 0 Address 61HEX
- Bank 0 Address 62HEX
- Bank 0 Address 63HEX
- Bank 0 Address 64HEX
- Bank 0 Address 65HEX
- Bank 0 Address 66HEX
- Bank 0 Address 67HEX
- Bank 0 Address 68HEX
- Bank 0 Address 69HEX
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Type:
Reset:
Read Only
Power On Reset
VOLTAGE HIGH VALUE
BIT
7
NAME
6
5
4
3
2
1
0
2
1
0
Voltage High Value
11-bit voltage value bit[10:3]
VOLTAGE LOW VALUE
BIT
7
6
NAME
5
4
3
Reserved
Voltage Low Value
11-bit voltage value bit[2:0]
TEMPERATURE HIGH VALUE
BIT
7
NAME
6
5
4
3
2
1
0
Temperature High Value. The real temperature value calculation is referred to
Temperature Monitor Data Format description.
11-bit 2’s complement bit[10:3]
VALUE
SIGN
64
32
16
8
4
2
1
2
1
0
TEMPERATURE LOW VALUE
BIT
7
6
5
NAME
Reserved
VALUE
Reserved
7.1.11
4
3
Temperature Low Value
11-bit 2’s complement bit[2:0]
0.5
0.25
0.125
PROCHOT Monitored Value Register
Location: P1_PH_NV
- Bank 0 Address 70HEX
P1_PH_DV
- Bank 0 Address 71HEX
Type:
Read Only
Reset:
Power On Reset
P1_PH_NV – CPU1 PROCHOT# Numerator Value Register
Location: Bank 0 Address 70HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
P1_PROCHOT#_NVAL[7:0]
CPU1 PROCHOT# Numerator Value
P1_PH_DV – CPU1 PROCHOT# Denominator Value Register
Location: Bank 0 Address 71HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
P1_PROCHOT#_DVAL[7:0]
CPU1 PROCHOT# Denominator Value
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7.1.12 Nuvoton Vendor ID Register
Location: Bank X Address 7AHEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 50HEX
BIT
DESCRIPTION
7-0
VENDOR_ID[7:0]
Duplicate of data found in Bank 0 Address 0Dh. Data at Address 7Ah is available in
all Bank Settings.
7.1.13 Nuvoton Chip ID Register
Location: Bank X Address 7BHEX
Type:
Read Only
Reset:
Power On Reset
Default Value: C5HEX
BIT
DESCRIPTION
7-0
CHIP_ID[7:0]
Duplicate of data found in Bank 0 Address 0Eh. Data at Address 7Bh is available in
all Bank Settings.
7.1.14 Nuvoton Device ID Register
Location: Bank X Address 7CHEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 5xHEX
BIT
DESCRIPTION
7-0
DEVICE_ID[7:0]
Duplicate of data found in Bank 0 Address 0Fh. Data at Address 7Ch is available in
all Bank Settings.
7.1.15
FAN Tachometer Monitored Value Register
Location: FANIN1_HV
FANIN1_LV
FANIN2_HV
FANIN2_LV
FANIN3_HV
FANIN3_LV
FANIN4_HV
FANIN4_LV
FANIN5_HV
FANIN5_LV
FANIN6_HV
FANIN6_LV
FANIN7_HV
Nuvoton Confidential
- Bank 0 Address 80HEX
- Bank 0 Address 81HEX
- Bank 0 Address 82HEX
- Bank 0 Address 83HEX
- Bank 0 Address 84HEX
- Bank 0 Address 85HEX
- Bank 0 Address 86HEX
- Bank 0 Address 87HEX
- Bank 0 Address 88HEX
- Bank 0 Address 89HEX
- Bank 0 Address 8AHEX
- Bank 0 Address 8BHEX
- Bank 0 Address 8CHEX
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FANIN7_LV
- Bank 0 Address 8DHEX
FANIN8_HV
- Bank 0 Address 8EHEX
FANIN8_LV
- Bank 0 Address 8FHEX
FANIN9_HV
- Bank 0 Address 90HEX
FANIN9_LV
- Bank 0 Address 91HEX
FANIN10_HV - Bank 0 Address 92HEX
FANIN10_LV - Bank 0 Address 93HEX
FANIN11_HV - Bank 0 Address 94HEX
FANIN11_LV - Bank 0 Address 95HEX
FANIN12_HV - Bank 0 Address 96HEX
FANIN12_LV - Bank 0 Address 97HEX
Read Only
Power On Reset
Type:
Reset:
FANIN HIGH VALUE
BIT
7
NAME
6
5
4
3
2
1
0
3
2
1
0
Fan Input Count High Value
13-bit fan count value bit[12:5]
FANIN LOW VALUE
BIT
7
6
NAME
7.1.16
Location:
T_CPU1_HV
T_CPU1_LV
T_CPU2_HV
T_CPU2_LV
T_CPU3_HV
T_CPU3_LV
T_CPU4_HV
T_CPU4_LV
T_CPU5_HV
T_CPU5_LV
T_CPU6_HV
T_CPU6_LV
T_CPU7_HV
T_CPU7_LV
T_CPU8_HV
T_CPU8_LV
P_CPU1
P_CPU2
P_CPU3
P_CPU4
5
Reserved
4
Fan Input Count Low Value
13-bit fan count value bit[4:0]
DTS Temperature Monitored Value Register
- Bank 0 Address A0HEX
- Bank 0 Address A1HEX
- Bank 0 Address A2HEX
- Bank 0 Address A3HEX
- Bank 0 Address A4HEX
- Bank 0 Address A5HEX
- Bank 0 Address A6HEX
- Bank 0 Address A7HEX
- Bank 0 Address A8HEX
- Bank 0 Address A9HEX
- Bank 0 Address AAHEX
- Bank 0 Address ABHEX
- Bank 0 Address ACHEX
- Bank 0 Address ADHEX
- Bank 0 Address AEHEX
- Bank 0 Address AFHEX
- Bank 0 Address B0HEX
- Bank 0 Address B1HEX
- Bank 0 Address B2HEX
- Bank 0 Address B3HEX
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Type:
Reset:
Read/Write (Writable DTS Source Selection is host)
Power On Reset
TEMPERATURE HIGH VALUE
BIT
NAME
VALUE
7
6
5
4
3
2
1
0
Temperature High Value. The real temperature value calculation is referred to
Temperature Monitor Data Format description.
11-bit 2’s complement bit[10:3]
(From PECI, TSI, or Host)
SIGN
64
32
16
8
4
2
1
2
1
0
TEMPERATURE LOW VALUE
BIT
7
6
5
NAME
Reserved
VALUE
Reserved
4
3
Temperature Low Value
11-bit 2’s complement bit[2:0]
(From PECI, TSI, or Host)
0.5
0.25
0.125
P_CPU1 – CPU1 Power Value Register
Location: Bank 0 Address B0HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
POWER_CPU1[7:0]
CPU1 Power Value (From PECI or Host)
P_CPU2 – CPU2 Power Value Register
Location: Bank 0 Address B1HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
POWER_CPU2[7:0]
CPU2 Power Value (From PECI or Host)
P_CPU3 – CPU3 Power Value Register
Location: Bank 0 Address B2HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
POWER_CPU3[7:0]
CPU3 Power Value (From PECI or Host)
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P_CPU4 – CPU4 Power Value Register
Location: Bank 0 Address B3HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
POWER_CPU4[7:0]
CPU4 Power Value (From PECI or Host)
7.1.17
Virtual Temperature Value Register
Location:
VRT_TEMP1_V
- Bank 0 Address B8HEX
VRT_TEMP2_V
- Bank 0 Address B9HEX
VRT_TEMP3_V
- Bank 0 Address BAHEX
VRT_TEMP4_V
- Bank 0 Address BBHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
VRT_TEMP1_V[7:0]
Virtual Temperature 1 Value
(It can be one of temperature sources for the FAN controller)
BIT
7-0
DESCRIPTION
VRT_TEMP2_V[7:0]
Virtual Temperature 2 Value
(It can be one of temperature sources for the FAN controller)
BIT
7-0
DESCRIPTION
VRT_TEMP3_V[7:0]
Virtual Temperature 3 Value
(It can be one of temperature sources for the FAN controller)
BIT
7-0
DESCRIPTION
VRT_TEMP4_V[7:0]
Virtual Temperature 4 Value
(It can be one of temperature sources for the FAN controller)
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7.1.18 External and Virtual Temperature Value Register
Location:
EXT_VRT_TEMP1_V
- Bank 0 Address BCHEX
EXT_VRT_TEMP2_V
- Bank 0 Address BDHEX
EXT_VRT_TEMP3_V
- Bank 0 Address BEHEX
EXT_VRT_TEMP4_V
- Bank 0 Address BFHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
EXT_VRT_TEMP1_V[7:0]
External Temperature 1 or Virtual Temperature 5 Value
(It can be one of temperature sources for the FAN controller)
BIT
7-0
DESCRIPTION
EXT_VRT_TEMP2_V[7:0]
External Temperature 2 or Virtual Temperature 6 Value
(It can be one of temperature sources for the FAN controller)
BIT
7-0
DESCRIPTION
EXT_VRT_TEMP3_V[7:0]
External Temperature 3 or Virtual Temperature 7 Value
(It can be one of temperature sources for the FAN controller)
BIT
7-0
DESCRIPTION
EXT_VRT_TEMP4_V[7:0]
External Temperature 4 or Virtual Temperature 8 Value
(It can be one of temperature sources for the FAN controller)
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NCT7904D
7.1.19 SMI Control Register
Location: Bank 0 Address C0HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 10HEX
BIT
7
6-5
4
3-2
DESCRIPTION
RTSACS.
0 = Read Interrupt status from CRC1~CRCA. (Default)
1 = Read real-time status from CRC1~CRCA.
Reserved.
SMI_MD.
0 = SMI# outputs low level signal and active high.
1 = SMI# outputs 200 us low pulse signal. (Default)
TEMP_SMI_MD.
Temperature SMI Mode Select.
00BIN = Comparator Interrupt Mode. (Default)
01BIN = Two Time Interrupt Mode.
10BIN = One Time Interrupt Mode.
11BIN = Two Time Non-related Interrupt Mode.
1
EN_SMI.
0 = disable SMI# signal output. (Default)
1 = enable SMI# signal output.
0
SMI_POL.
0 = SMI# polarity follows SMI_MD. (Default)
1 = SMI# polarity is inverted.
7.1.20
SMI Status Register
Location:
SMI_STS1
- Bank 0 Address C1HEX
SMI_STS2
- Bank 0 Address C2HEX
SMI_STS3
- Bank 0 Address C3HEX
SMI_STS4
- Bank 0 Address C4HEX
SMI_STS5
- Bank 0 Address C5HEX
SMI_STS6
- Bank 0 Address C6HEX
SMI_STS7
- Bank 0 Address C7HEX
SMI_STS8
- Bank 0 Address C8HEX
SMI_STS9
- Bank 0 Address C9HEX
SMI_STS10
- Bank 0 Address CAHEX
Type:
Read Only
Reset:
Power On Reset
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NCT7904D
SMI_STS1
BIT
7
6
5
4
3
2
1
0
NAME
S_VSEN8
S_VSEN7
S_VSEN6
S_VSEN5
S_VSEN4
S_VSEN3
S_VSEN2
S_VSEN1
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS2
BIT
7
6
5
4
3
2
1
0
NAME
S_VBAT
S_3VDD
S_VSEN1
4
S_VSEN1
3
S_VSEN1
2
S_VSEN1
1
S_VSEN1
0
S_VSEN9
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS3
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
S_VSEN1
9
S_VSEN1
8
S_VSEN1
7
S_LTD
S_V3VSB
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS4
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
S_PH1
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS5
BIT
7
6
5
4
3
2
1
0
NAME
S_FANIN
8
S_FANIN
7
S_FANIN
6
S_FANIN
5
S_FANIN
4
S_FANIN
3
S_FANIN
2
S_FANIN
1
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS6
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
S_FANIN
12
S_FANIN
11
S_FANIN
10
S_FANIN
9
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS7
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
S_TCPU4
S_TCPU3
S_TCPU2
S_TCPU1
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS8
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
S_TCPU8
S_TCPU7
S_TCPU6
S_TCPU5
DEFAULT
0
0
0
0
0
0
0
0
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NCT7904D
SMI_STS9
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
S_PCPU4
S_PCPU3
S_PCPU2
S_PCPU1
DEFAULT
0
0
0
0
0
0
0
0
SMI_STS10
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
S_CHAS
SIS
Reserved
Reserved
S_TART4
S_TART3
S_TART2
S_TART1
DEFAULT
0
0
0
0
0
0
0
0
*TART: When the Smart fan is driving the fan in full speed over 3 minutes, the TART will be asserted.
7.1.21
SMI Mask Register
Location:
SMI_MSK1
- Bank 0 Address CBHEX
SMI_MSK2
- Bank 0 Address CCHEX
SMI_MSK3
- Bank 0 Address CDHEX
SMI_MSK4
- Bank 0 Address CEHEX
SMI_MSK5
- Bank 0 Address CFHEX
SMI_MSK6
- Bank 0 Address D0HEX
SMI_MSK7
- Bank 0 Address D1HEX
SMI_MSK8
- Bank 0 Address D2HEX
SMI_MSK9
- Bank 0 Address D3HEX
SMI_MSK10
- Bank 0 Address D4HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
SMI_MSK1
BIT
7
6
5
4
3
2
1
0
NAME
M_VSEN
8
M_VSEN
7
M_VSEN
6
M_VSEN
5
M_VSEN
4
M_VSEN
3
M_VSEN
2
M_VSEN
1
DEFAULT
1
1
1
1
1
1
1
1
SMI_MSK2
BIT
7
6
5
4
3
2
1
0
NAME
M_VBAT
M_3VDD
M_VSEN
14
M_VSEN
13
M_VSEN
12
M_VSEN
11
M_VSEN
10
M_VSEN
9
DEFAULT
1
1
1
1
1
1
1
1
SMI_MSK3
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
M_VSEN
19
M_VSEN
18
M_VSEN
17
M_LTD
M_V3VS
B
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NCT7904D
DEFAULT
0
0
0
1
1
1
1
1
SMI_MSK4
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M_PH1
DEFAULT
0
0
0
0
0
0
0
1
SMI_MSK5
BIT
7
6
5
4
3
2
1
0
NAME
M_FANIN
8
M_FANIN
7
M_FANIN
6
M_FANIN
5
M_FANIN
4
M_FANIN
3
M_FANIN
2
M_FANIN
1
DEFAULT
1
1
1
1
1
1
1
1
SMI_MSK6
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
M_FANIN
12
M_FANIN
11
M_FANIN
10
M_FANIN
9
DEFAULT
0
0
0
0
1
1
1
1
SMI_MSK7
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
M_TCPU
4
M_TCPU
3
M_TCPU
2
M_TCPU
1
DEFAULT
0
0
0
0
1
1
1
1
SMI_MSK8
BIT
NAME
DEFAULT
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
M_TCPU
8
M_TCPU
7
M_TCPU
6
M_TCPU
5
0
0
0
0
1
1
1
1
SMI_MSK9
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
M_PCPU
4
M_PCPU
3
M_PCPU
2
M_PCPU
1
DEFAULT
0
0
0
0
1
1
1
1
SMI_MSK10
BIT
7
6
5
4
3
2
1
0
NAME
CLR_CH
ASSIS
M_CHAS
SIS
Reserved
Reserved
M_TART4
M_TART3
M_TART2
M_TART1
DEFAULT
0
1
0
0
1
1
1
1
CLR_CHASSIS is clear chassis event. When write 1 , the internal chassis event will be cleared.
M_CHASSIS is mask chassis event. When set to 1 , the chassis SMI event will be masked.
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NCT7904D
7.1.22 Beep Control Register
Location: Bank 0 Address D6HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
DESCRIPTION
7
EN_BEEP
0 = Disable
1 = Enable
6
BEEP_WNC
0 = Temperature BEEP boundary is critical level (Default)
1 = Temperature BEEP boundary is warning level
Reserved
5-0
7.1.23
Beep Source Selection Register
Location:
BEEP_SEL1 - Bank 0 Address D7HEX
BEEP_SEL 2 - Bank 0 Address D8HEX
BEEP_SEL 3 - Bank 0 Address D9HEX
BEEP_SEL 4 - Bank 0 Address DAHEX
BEEP_SEL 5 - Bank 0 Address DBHEX
BEEP_SEL 6 - Bank 0 Address DCHEX
BEEP_SEL 7 - Bank 0 Address DDHEX
BEEP_SEL 8 - Bank 0 Address DEHEX
BEEP_SEL 9 - Bank 0 Address DFHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
BEEP_SEL1
BIT
7
6
5
4
3
2
1
0
NAME
B_VSEN8
B_VSEN7
B_VSEN6
B_VSEN5
B_VSEN4
B_VSEN3
B_VSEN2
B_VSEN1
DEFAULT
0
0
0
0
0
0
0
0
BEEP_SEL2
BIT
NAME
DEFAULT
7
6
5
4
3
2
1
0
B_VBAT
B_3VDD
B_VSEN1
4
B_VSEN1
3
B_VSEN1
2
B_VSEN1
1
B_VSEN1
0
B_VSEN9
0
0
0
0
0
0
0
0
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NCT7904D
BEEP_SEL3
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
B_VSEN1
9
B_VSEN1
8
B_VSEN1
7
B_LTD
B_V3VSB
DEFAULT
0
0
0
0
0
0
0
0
BEEP_SEL4
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B_PH1
DEFAULT
0
0
0
0
0
0
0
0
BEEP_SEL5
BIT
7
6
5
4
3
2
1
0
NAME
B_FANIN
8
B_FANIN
7
B_FANIN
6
B_FANIN
5
B_FANIN
4
B_FANIN
3
B_FANIN
2
B_FANIN
1
DEFAULT
0
0
0
0
0
0
0
0
BEEP_SEL6
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
B_FANIN
12
B_FANIN
11
B_FANIN
10
B_FANIN
9
DEFAULT
0
0
0
0
0
0
0
0
BEEP_SEL7
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
B_TCPU4
B_TCPU3
B_TCPU2
B_TCPU1
DEFAULT
0
0
0
0
0
0
0
0
BEEP_SEL8
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
Reserved
Reserved
Reserved
B_TCPU8
B_TCPU7
B_TCPU6
B_TCPU5
DEFAULT
0
0
0
0
0
0
0
0
BEEP_SEL9
BIT
7
6
5
4
3
2
1
0
NAME
Reserved
B_CHAS
SIS
Reserved
Reserved
B_PCPU4
B_PCPU3
B_PCPU2
B_PCPU1
DEFAULT
0
0
0
0
0
0
0
0
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NCT7904D
7.1.24
Lock Watch Dog Register
Location: Bank 0 Address E0HEX
Type:
Write Only
Reset:
Power On Reset
Default Value: 00HEX
BIT
7-0
DESCRIPTION
UNLOCK CODE
Write 55HEX, Enables Soft Watch Dog Timer
Write AAHEX, Disables Soft Watch Dog Timer
Write 33HEX, Enables Hard Watch Dog Timer
Write CCHEX, Disables Hard Watch Dog Timer
7.1.25
Watch Dog Enable Register
Location: Bank 0 Address E1HEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 00HEX
BIT
7-2
DESCRIPTION
Reserved.
1
HARD
0 = Hard Watch Dog is disabled
1 = Hard Watch Dog is enabled
0
SOFT
0 = Soft Watch Dog is disabled
1 = Soft Watch Dog is enabled
7.1.26
Watch Dog Status Register
Location: Bank 0 Address E2HEX
Type: Read Only
Reset: Power On Reset
Default Value: 00HEX
BIT
DESCRIPTION
7-4
Reserved
3-2
WDT_ST
These 2 bits record last WDT stage for BIOS readout. The information is used to help
BIOS to identify WDT timeout issuance
1
HARD_TO
1 = A hard timeout occurs. This bit will be cleared after reading
0
SOFT_TO
1 = A soft timeout occurs. This bit will be cleared after reading
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NCT7904D
7.1.27
Watch Dog Timer Register
Location: Bank 0 Address E3HEX
Type: Read / Write
Reset: Power On Reset
Default Value: 00HEX
BIT
7-0
DESCRIPTION
WDT TIMER – Timeout timer
To write 00HEX can disable the timer while in Hard Watch Dog Timer mode.
To set Timeout Time for SOFT Watch Dog Timer, the unit is minute
7.1.28
Reset:
GPIO Control Register
Power On Reset
RESETIN# with LOCK=0
GPIO G0 EN – GPIO Group 0 I/O Enable Control Register
Location: Bank 0 Address E8HEX
Default Value: 60HEX
Type: Read / Write
BIT
7
6-0
DESCRIPTION
Reserved
GPIO G0 EN – Select GPIOG-GPIOA I/O Enable.
0 = GPIOG-A are disable.
1 = GPIOG-A are enable.
GPIO G0 DIR – GPIO Group 0 I/O Direction Control Register
Location: Bank 0 Address E9HEX
Default Value: 7FHEX
Type: Read / Write
BIT
7
6-0
DESCRIPTION
Reserved
GPIO G0 DIR – Select GPIOG-GPIOA I/O Direction.
0 = GPIOG-A are programming as output pins.
1 = GPIOG-A are programming as input pins. (default)
GPIO G0 OUT – GPIO Group 0 Output Data Register
Location: Bank 0 Address EAHEX
Default Value: 00HEX
Type: Read / Write
BIT
DESCRIPTION
7-0
GPIO G0 OUT – Output GPIOG-GPIOA Data. For output ports, it needs to set
GPIO_G0_EN register and the respective bits can be read/written and produced to pins.
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NCT7904D
GPIO G0 IN – GPIO Group 0 Input Data Register
Location: Bank 0 Address EBHEX
Default Value: N.A.
Type: Read Only
BIT
DESCRIPTION
7-0
GPIO G0 IN – Input GPIOG-GPIOA Data. The respective bits can be read only from pins.
Write accesses will be ignored.
GPIO G1 EN – GPIO Group 1 I/O Enable Control Register
Location: Bank 0 Address ECHEX
Default Value: 00HEX
Type: Read / Write
BIT
DESCRIPTION
7-4
Reserved
3-0
GPIO G1 EN – Select GPIO16-GPIO13 I/O Enable.
0 = GPIO16-13 are disable.
1 = GPIO16-13 are enable.
GPIO G1 DIR – GPIO Group 1 I/O Direction Control Register
Location: Bank 0 Address EDHEX
Default Value: 0FHEX
Type: Read / Write
BIT
7-4
3-0
DESCRIPTION
Reserved
GPIO G1 DIR – Select GPIO16-GPIO13 I/O Direction.
0 = GPIO16-13 are programming as output pins.
1 = GPIO16-13 are programming as input pins. (default)
GPIO G1 OUT – GPIO Group 1 Output Data Register
Location: Bank 0 Address EEHEX
Default Value: 00HEX
Type: Read / Write
BIT
DESCRIPTION
3-0
GPIO G1 OUT – Output GPIO16-GPIO13 Data. For output ports, it needs to set
GPIO_G1_EN register and the respective bits can be read/written and produced to pins.
GPIO G1 IN – GPIO Group 1 Input Data Register
Location: Bank 0 Address EFHEX
Default Value: N.A.
Type: Read Only
BIT
DESCRIPTION
3-0
GPIO G1 IN – Input GPIO16-GPIO13 Data. The respective bits can be read only from
pins. Write accesses will be ignored.
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NCT7904D
7.1.29
PCH DTS Monitored Value Register
Location: PCH_MAX
PCH_PCH
PCH_CPU_F
PCH_CPU_I
PCH_MCH
PCH_DIMM0
PCH_DIMM1
PCH_DIMM2
PCH_DIMM3
PCH_SN
PCH_CPU_EG0
PCH_CPU_EG1
PCH_CPU_EG2
PCH_CPU_EG3
Type:
Read Only
Reset:
Power On Reset
- Bank 0 Address F0HEX
- Bank 0 Address F1HEX
- Bank 0 Address F2HEX
- Bank 0 Address F3HEX
- Bank 0 Address F4HEX
- Bank 0 Address F5HEX
- Bank 0 Address F6HEX
- Bank 0 Address F7HEX
- Bank 0 Address F8HEX
- Bank 0 Address F9HEX
- Bank 0 Address FAHEX
- Bank 0 Address FBHEX
- Bank 0 Address FCHEX
- Bank 0 Address FDHEX
According to different Intel ME firmware version, the PCH temperature could be placed in either
address F0h or F1h.
PCH_MAX – PCH PCH_0 Temperature Value Register
Location: Bank 0 Address F0HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_PCH_0_TEMP[7:0]
PCH PCH_0 Temperature Value
(It can be one of temperature sources for the FAN controller)
PCH_PCH – PCH PCH_1 Temperature Value Register
Location: Bank 0 Address F1HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_PCH_1_TEMP[7:0]
PCH PCH_1 Temperature Value
(It can be one of temperature sources for the FAN controller)
PCH_CPU_F – PCH CPU Fractional Temperature Value Register
Location: Bank 0 Address F2HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_CPU_FRA_TEMP[7:0]
PCH CPU Fractional Temperature Value
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NCT7904D
PCH_CPU_I – PCH CPU Integer Temperature Value Register
Location: Bank 0 Address F3HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_CPU_INT_TEMP[7:0]
PCH CPU Integer Temperature Value
(It can be one of temperature sources for the FAN controller)
PCH_MCH – PCH MCH Temperature Value Register
Location: Bank 0 Address F4HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_MCH_TEMP[7:0]
PCH MCH Temperature Value
(It can be one of temperature sources for the FAN controller)
PCH_DIMM0 – PCH DIMM0 Temperature Value Register
Location: Bank 0 Address F5HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_DIMM0_TEMP[7:0]
PCH DIMM0 Temperature Value
(It can be one of temperature sources for the FAN controller)
PCH_DIMM1 – PCH DIMM1 Temperature Value Register
Location: Bank 0 Address F6HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_DIMM1_TEMP[7:0]
PCH DIMM1 Temperature Value
(It can be one of temperature sources for the FAN controller)
PCH_DIMM2 – PCH DIMM2 Temperature Value Register
Location: Bank 0 Address F7HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_DIMM2_TEMP[7:0]
PCH DIMM2 Temperature Value
(It can be one of temperature sources for the FAN controller)
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NCT7904D
PCH_DIMM3 – PCH DIMM3 Temperature Value Register
Location: Bank 0 Address F8HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_DIMM3_TEMP[7:0]
PCH DIMM3 Temperature Value
(It can be one of temperature sources for the FAN controller)
PCH_SN – PCH Sequence Number Value Register
Location: Bank 0 Address F9HEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_SEQ_NUM[7:0]
PCH Sequence Number Value
PCH_CPU_EG0 – PCH CPU Latest Energy Value Register
Location: Bank 0 Address FAHEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_CPU_ERG[7:0]
PCH CPU Latest Energy Value
PCH_CPU_EG1 – PCH CPU Latest Energy Value Register
Location: Bank 0 Address FBHEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_CPU_ERG[15:8]
PCH CPU Latest Energy Value
PCH_CPU_EG2 – PCH CPU Latest Energy Value Register
Location: Bank 0 Address FCHEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_CPU_ERG[23:16]
PCH CPU Latest Energy Value
PCH_CPU_EG3 – PCH CPU Latest Energy Value Register
Location: Bank 0 Address FDHEX
Default Value: N/A
BIT
7-0
DESCRIPTION
PCH_CPU_ERG[31:24]
PCH CPU Latest Energy Value
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NCT7904D
7.1.30
Bank Select Register
Location: Bank 0, 1, 2, 3 Address FFHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
DESCRIPTION
7-3
Reserved.
2-0
BANK_SEL[2:0]
000BIN = Bank 0
001BIN = Bank 1
010BIN = Bank 2
011BIN = Bank 3
100BIN = Bank 4
101BIN ~ 111BIN = Reserved
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NCT7904D
7.2
Bank 1 REGISTER DETAIL
7.2.1 Voltage and Temperature Channel Limitation Register
Location:
VSEN1_HV_HL
VSEN1_LV_HL
VSEN1_HV_LL
VSEN1_LV_LL
VSEN2_HV_HL / TEMP_CH1_C
VSEN2_LV_HL / TEMP_CH1_CH
VSEN2_HV_LL / TEMP_CH1_W
VSEN2_LV_LL / TEMP_CH1_WH
VSEN3_HV_HL
VSEN3_LV_HL
VSEN3_HV_LL
VSEN3_LV_LL
VSEN4_HV_HL / TEMP_CH2_C
VSEN4_LV_HL / TEMP_CH2_CH
VSEN4_HV_LL / TEMP_CH2_W
VSEN4_LV_LL / TEMP_CH2_WH
VSEN5_HV_HL
VSEN5_LV_HL
VSEN5_HV_LL
VSEN5_LV_LL
VSEN6_HV_HL / TEMP_CH3_C
VSEN6_LV_HL / TEMP_CH3_CH
VSEN6_HV_LL / TEMP_CH3_W
VSEN6_LV_LL / TEMP_CH3_WH
VSEN7_HV_HL
VSEN7_LV_HL
VSEN7_HV_LL
VSEN7_LV_LL
VSEN8_HV_HL / TEMP_CH4_C
VSEN8_LV_HL / TEMP_CH4_CH
VSEN8_HV_LL / TEMP_CH4_W
VSEN8_LV_LL / TEMP_CH4_WH
VSEN9_HV_HL
VSEN9_LV_HL
VSEN9_HV_LL
VSEN9_LV_LL
VSEN10_HV_HL
VSEN10_LV_HL
VSEN10_HV_LL
VSEN10_LV_LL
VSEN11_HV_HL
Nuvoton Confidential
- Bank 1 Address 00HEX
- Bank 1 Address 01HEX
- Bank 1 Address 02HEX
- Bank 1 Address 03HEX
- Bank 1 Address 04HEX
- Bank 1 Address 05HEX
- Bank 1 Address 06HEX
- Bank 1 Address 07HEX
- Bank 1 Address 08HEX
- Bank 1 Address 09HEX
- Bank 1 Address 0AHEX
- Bank 1 Address 0BHEX
- Bank 1 Address 0CHEX
- Bank 1 Address 0DHEX
- Bank 1 Address 0EHEX
- Bank 1 Address 0FHEX
- Bank 1 Address 10HEX
- Bank 1 Address 11HEX
- Bank 1 Address 12HEX
- Bank 1 Address 13HEX
- Bank 1 Address 14HEX
- Bank 1 Address 15HEX
- Bank 1 Address 16HEX
- Bank 1 Address 17HEX
- Bank 1 Address 18HEX
- Bank 1 Address 19HEX
- Bank 1 Address 1AHEX
- Bank 1 Address 1BHEX
- Bank 1 Address 1CHEX
- Bank 1 Address 1DHEX
- Bank 1 Address 1EHEX
- Bank 1 Address 1FHEX
- Bank 1 Address 20HEX
- Bank 1 Address 21HEX
- Bank 1 Address 22HEX
- Bank 1 Address 23HEX
- Bank 1 Address 24HEX
- Bank 1 Address 25HEX
- Bank 1 Address 26HEX
- Bank 1 Address 27HEX
- Bank 1 Address 28HEX
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NCT7904D
VSEN11_LV_HL
VSEN11_HV_LL
VSEN11_LV_LL
VSEN12_HV_HL
VSEN12_LV_HL
VSEN12_HV_LL
VSEN12_LV_LL
VSEN13_HV_HL
VSEN13_LV_HL
VSEN13_HV_LL
VSEN13_LV_LL
VSEN14_HV_HL
VSEN14_LV_HL
VSEN14_HV_LL
VSEN14_LV_LL
3VDD_HV_HL
3VDD_LV_HL
3VDD_HV_LL
3VDD_LV_LL
VBAT_HV_HL
VBAT_LV_HL
VBAT_HV_LL
VBAT_LV_LL
V3VSB_HV_HL
V3VSB_LV_HL
V3VSB_HV_LL
V3VSB_LV_LL
LTD_HV_HL
LTD_LV_HL
LTD_HV_LL
LTD_LV_LL
VSEN17_HV_HL
VSEN17_LV_HL
VSEN17_HV_LL
VSEN17_LV_LL
VSEN18_HV_HL
VSEN18_LV_HL
VSEN18_HV_LL
VSEN18_LV_LL
VSEN19_HV_HL
VSEN19_LV_HL
VSEN19_HV_LL
VSEN19_LV_LL
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Nuvoton Confidential
- Bank 1 Address 29HEX
- Bank 1 Address 2AHEX
- Bank 1 Address 2BHEX
- Bank 1 Address 2CHEX
- Bank 1 Address 2DHEX
- Bank 1 Address 2EHEX
- Bank 1 Address 2FHEX
- Bank 1 Address 30HEX
- Bank 1 Address 31HEX
- Bank 1 Address 32HEX
- Bank 1 Address 33HEX
- Bank 1 Address 34HEX
- Bank 1 Address 35HEX
- Bank 1 Address 36HEX
- Bank 1 Address 37HEX
- Bank 1 Address 38HEX
- Bank 1 Address 39HEX
- Bank 1 Address 3AHEX
- Bank 1 Address 3BHEX
- Bank 1 Address 3CHEX
- Bank 1 Address 3DHEX
- Bank 1 Address 3EHEX
- Bank 1 Address 3FHEX
- Bank 1 Address 40HEX
- Bank 1 Address 41HEX
- Bank 1 Address 42HEX
- Bank 1 Address 43HEX
- Bank 1 Address 44HEX
- Bank 1 Address 45HEX
- Bank 1 Address 46HEX
- Bank 1 Address 47HEX
- Bank 1 Address 80HEX
- Bank 1 Address 81HEX
- Bank 1 Address 82HEX
- Bank 1 Address 83HEX
- Bank 1 Address 84HEX
- Bank 1 Address 85HEX
- Bank 1 Address 86HEX
- Bank 1 Address 87HEX
- Bank 1 Address 88HEX
- Bank 1 Address 89HEX
- Bank 1 Address 8AHEX
- Bank 1 Address 8BHEX
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NCT7904D
HIGH VALUE HIGH LIMITATION
Default Value: FFHEX
BIT
NAME
7
6
5
4
3
2
1
0
2
1
0
High Value High Limitation
11-bit voltage value bit[10:2]
LOW VALUE HIGH LIMITATION
Default Value: 07HEX
BIT
7
6
NAME
5
4
3
Reserved
High Value High Limitation
11-bit voltage value bit[2:0]
HIGH VALUE LOW LIMITATION
Default Value: 00HEX
BIT
NAME
7
6
5
4
3
2
1
0
2
1
0
High Value Low Limitation
11-bit voltage value bit[10:2]
LOW VALUE LOW LIMITATION
Default Value: 00HEX
BIT
7
6
NAME
5
4
3
Reserved
High Value Low Limitation
11-bit voltage value bit[2:0]
CRITICAL TEMPERATURE
Default Value: FFHEX
BIT
NAME
7
6
5
4
3
2
1
0
Critical Temperature
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
CRITICAL TEMPERATURE HYSTERESIS
Default Value: 07HEX
BIT
NAME
7
6
5
4
3
2
1
0
Critical Temperature Hysteresis
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
WARNING TEMPERATURE
Default Value: 00HEX
BIT
NAME
7
6
5
4
3
2
1
0
Warning Temperature
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
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NCT7904D
WARNING TEMPERATURE HYSTERESIS
Default Value: 00HEX
BIT
7
NAME
6
5
4
3
2
1
0
Warning Temperature Hysteresis
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
7.2.2 PROCHOT Limitation Register
Location: Bank 1 Address 50HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: FFHEX
BIT
7-0
DESCRIPTION
P1_PROCHOT#_NV_HL[7:0]
CPU1 PROCHOT# Numerator High Limitation
7.2.3 FAN Input Channel Limitation Register
Location: FANIN1_HV_HL
- Bank 1 Address 60HEX
FANIN1_LV_HL
- Bank 1 Address 61HEX
FANIN2_HV_HL
- Bank 1 Address 62HEX
FANIN2_LV_HL
- Bank 1 Address 63HEX
FANIN3_HV_HL
- Bank 1 Address 64HEX
FANIN3_LV_HL
- Bank 1 Address 65HEX
FANIN4_HV_HL
- Bank 1 Address 66HEX
FANIN4_LV_HL
- Bank 1 Address 67HEX
FANIN5_HV_HL
- Bank 1 Address 68HEX
FANIN5_LV_HL
- Bank 1 Address 69HEX
FANIN6_HV_HL
- Bank 1 Address 6AHEX
FANIN6_LV_HL
- Bank 1 Address 6BHEX
FANIN7_HV_HL
- Bank 1 Address 6CHEX
FANIN7_LV_HL
- Bank 1 Address 6DHEX
FANIN8_HV_HL
- Bank 1 Address 6EHEX
FANIN8_LV_HL
- Bank 1 Address 6FHEX
FANIN9_HV_HL
- Bank 1 Address 70HEX
FANIN9_LV_HL
- Bank 1 Address 71HEX
FANIN10_HV_HL
- Bank 1 Address 72HEX
FANIN10_LV_HL
- Bank 1 Address 73HEX
FANIN11_HV_HL
- Bank 1 Address 74HEX
FANIN11_LV_HL
- Bank 1 Address 75HEX
FANIN12_HV_HL
- Bank 1 Address 76HEX
FANIN12_LV_HL
- Bank 1 Address 77HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
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NCT7904D
FANIN HIGH VALUE HIGH LIMITATION
BIT
7
NAME
6
5
4
3
2
1
0
2
1
0
Fan Input Count High Value High Limitation
13-bit voltage value bit[12:5]
FANIN LOW VALUE HIGH LIMITATION
BIT
7
NAME
6
5
Reserved
4
3
Fan Input Count Low Value High Limitation
13-bit voltage value bit[4:0]
7.2.4 DTS Temperature Power Limitation Registers
Location:
DTS_T_CPU1_C
DTS_T_CPU1_CH
DTS_T_CPU1_W
DTS_T_CPU1_WH
DTS_T_CPU2_C
DTS_T_CPU2_CH
DTS_T_CPU2_W
DTS_T_CPU2_WH
DTS_T_CPU3_C
DTS_T_CPU3_CH
DTS_T_CPU3_W
DTS_T_CPU3_WH
DTS_T_CPU4_C
DTS_T_CPU4_CH
DTS_T_CPU4_W
DTS_T_CPU4_WH
DTS_T_CPU5_C
DTS_T_CPU5_CH
DTS_T_CPU5_W
DTS_T_CPU5_WH
DTS_T_CPU6_C
DTS_T_CPU6_CH
DTS_T_CPU6_W
DTS_T_CPU6_WH
DTS_T_CPU7_C
DTS_T_CPU7_CH
DTS_T_CPU7_W
DTS_T_CPU7_WH
DTS_T_CPU8_C
DTS_T_CPU8_CH
DTS_T_CPU8_W
DTS_T_CPU8_WH
DTS_P_CPU1_C
Nuvoton Confidential
- Bank 1 Address 90HEX
- Bank 1 Address 91HEX
- Bank 1 Address 92HEX
- Bank 1 Address 93HEX
- Bank 1 Address 94HEX
- Bank 1 Address 95HEX
- Bank 1 Address 96HEX
- Bank 1 Address 97HEX
- Bank 1 Address 98HEX
- Bank 1 Address 99HEX
- Bank 1 Address 9AHEX
- Bank 1 Address 9BHEX
- Bank 1 Address 9CHEX
- Bank 1 Address 9DHEX
- Bank 1 Address 9EHEX
- Bank 1 Address 9FHEX
- Bank 1 Address A0HEX
- Bank 1 Address A1HEX
- Bank 1 Address A2HEX
- Bank 1 Address A3HEX
- Bank 1 Address A4HEX
- Bank 1 Address A5HEX
- Bank 1 Address A6HEX
- Bank 1 Address A7HEX
- Bank 1 Address A8HEX
- Bank 1 Address A9HEX
- Bank 1 Address AAHEX
- Bank 1 Address ABHEX
- Bank 1 Address ACHEX
- Bank 1 Address ADEX
- Bank 1 Address AEHEX
- Bank 1 Address AFHEX
- Bank 1 Address B0HEX
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NCT7904D
DTS_P_CPU1_CH
- Bank 1 Address B1HEX
DTS_P_CPU1_W
- Bank 1 Address B2HEX
DTS_P_CPU1_WH
- Bank 1 Address B3HEX
DTS_P_CPU2_C
- Bank 1 Address B4HEX
DTS_P_CPU2_CH
- Bank 1 Address B5HEX
DTS_P_CPU2_W
- Bank 1 Address B6HEX
DTS_P_CPU2_WH
- Bank 1 Address B7HEX
DTS_P_CPU3_C
- Bank 1 Address B8HEX
DTS_P_CPU3_CH
- Bank 1 Address B9HEX
DTS_P_CPU3_W
- Bank 1 Address BAHEX
DTS_P_CPU3_WH
- Bank 1 Address BBHEX
DTS_P_CPU4_C
- Bank 1 Address BCHEX
DTS_P_CPU4_CH
- Bank 1 Address BDHEX
DTS_P_CPU4_W
- Bank 1 Address BEEX
DTS_P_CPU4_WH
- Bank 1 Address BFHEX
Reset:
Power On Reset
RESETIN# with LOCK=0
CRITICAL TEMPERATURE
BIT
NAME
VALUE
7
6
5
4
3
2
1
0
Critical Temperature
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
SIGN
64
32
DEFAULT
16
8
4
2
1
2
1
0
64HEX (100℃)
CRITICAL TEMPERATURE HYSTERESIS
BIT
NAME
VALUE
7
6
5
4
3
Critical Temperature Hysteresis
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
SIGN
64
32
DEFAULT
16
8
4
2
1
5FHEX (95℃)
WARNING TEMPERATURE
BIT
NAME
VALUE
7
6
5
4
3
2
1
0
Warning Temperature
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
SIGN
DEFAULT
64
32
16
8
55HEX (85 ℃)
4
2
1
WARNING TEMPERATURE HYSTERESIS
BIT
NAME
7
6
5
4
3
2
1
0
Warning Temperature Hysteresis
The format of Temperature is 8-bit 2’s complement and the range is –128℃~127℃.
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NCT7904D
VALUE
SIGN
64
32
DEFAULT
16
8
4
2
1
50HEX (80 ℃)
7.2.5 PROCHOT Control Registers
Location: Bank 1 Address D0HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 4FHEX
BIT
7
6
5-4
3-0
DESCRIPTION
Reserved
PH1_MD – Set the PROCHOT1# mode.
0 = Output mode
1 = Input mode (default)
PH1_FSEL – Set the PROCHOT1# sample period time.
00 = 22us (default)
01 = 44us
10 = 88us
11 = 176us
PH1_DC – Set the PROCHOT1# output duty cycle.
0000 = 1 sample time low
0001 = 2 sample times low
0010 = 3 sample times low
0011 = 4 sample times low
0100 = 5 sample times low
0101 = 6 sample times low
0110 = 7 sample times low
0111 = 8 sample times low
1000 = 9 sample times low
1001 = 10 sample times low
1010 = 11 sample times low
1011 = 12 sample times low
1100 = 13 sample times low
1101 = 14 sample times low
1110 = 15 sample times low
1111 = all low (default)
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NCT7904D
7.2.6 PROCHOT Source Selection Registers
Location:
PH1_VT_ADC
- Bank 1 Address D1HEX
PH1_DTS_T0
- Bank 1 Address D2HEX
PH1_DTS_T1
- Bank 1 Address D3HEX
PH1_DTS_P
- Bank 1 Address D4HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
PH1_VT_ADC – P1_PROCHOT Temperature Select Register
Location: Bank 1 Address D1HEX
Default Value: 20HEX
BIT
7-5
4
3
2
1
0
DESCRIPTION
Reserved
PH1_LTD – Enable P1_PROCHOT# for LTD
0 = Disable
1 = Enable
PH1_VSEN89 – Enable P1_PROCHOT# for VSEN89
0 = Disable
1 = Enable
PH1_VSEN67 – Enable P1_PROCHOT# for VSEN67
0 = Disable
1 = Enable
PH1_VSEN45 – Enable P1_PROCHOT# for VSEN45
0 = Disable
1 = Enable
PH1_VSEN23 – Enable P1_PROCHOT# for VSEN23
0 = Disable
1 = Enable
PH1_DTS_T0 – P1_PROCHOT DTS Temperature 0 Select Register
Location: Bank 1 Address D2HEX
Default Value: 00HEX
BIT
7-4
3
2
1
DESCRIPTION
Reserved
PH1_TCPU4 – Enable P1_PROCHOT# for TCPU4
0 = Disable
1 = Enable
PH1_TCPU3 – Enable P1_PROCHOT# for TCPU3
0 = Disable
1 = Enable
PH1_TCPU2 – Enable P1_PROCHOT# for TCPU2
0 = Disable
1 = Enable
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NCT7904D
BIT
0
DESCRIPTION
PH1_TCPU1 – Enable P1_PROCHOT# for TCPU1
0 = Disable
1 = Enable
PH1_DTS_T1 – P1_PROCHOT DTS Temperature 1 Select Register
Location: Bank 1 Address D3HEX
Default Value: 00HEX
BIT
7-4
3
2
1
0
DESCRIPTION
Reserved
PH1_TCPU8 – Enable P1_PROCHOT# for TCPU8
0 = Disable
1 = Enable
PH1_TCPU7 – Enable P1_PROCHOT# for TCPU7
0 = Disable
1 = Enable
PH1_TCPU6 – Enable P1_PROCHOT# for TCPU6
0 = Disable
1 = Enable
PH1_TCPU5 – Enable P1_PROCHOT# for TCPU5
0 = Disable
1 = Enable
PH1_DTS_P – P1_PROCHOT DTS Power Select Register
Location: Bank 1 Address D4HEX
Default Value: 00HEX
BIT
7-4
3
2
1
0
DESCRIPTION
Reserved
PH1_PCPU4 – Enable P1_PROCHOT# for PCPU4
0 = Disable
1 = Enable
PH1_PCPU3 – Enable P1_PROCHOT# for PCPU3
0 = Disable
1 = Enable
PH1_PCPU2 – Enable P1_PROCHOT# for PCPU2
0 = Disable
1 = Enable
PH1_PCPU1 – Enable P1_PROCHOT# for PCPU1
0 = Disable
1 = Enable
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NCT7904D
7.2.7 Voltage Fault Control Registers
Location: Bank 1 Address D8HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7
6-0
DESCRIPTION
EN_VFAULT – Enable voltage fault function.
0 = Disable
1 = Enable
Reserved
7.2.8 Voltage Fault Source Selection Registers
Location:
VF_SEL0
- Bank 1 Address D9HEX
VF_SEL1
- Bank 1 Address DAHEX
VF_SEL2
- Bank 1 Address DBHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
VF_SEL0 – Voltage Fault Select Register
Location: Bank 1 Address D9HEX
Default Value: 00HEX
BIT
DESCRIPTION
7
VF_VSEN8 – Enable VOLT_ALM# for VSEN8
0 = Disable
1 = Enable
6
VF_VSEN7 – Enable VOLT_ALM# for VSEN7
0 = Disable
1 = Enable
5
VF_VSEN6 – Enable VOLT_ALM# for VSEN6
0 = Disable
1 = Enable
4
VF_VSEN5 – Enable VOLT_ALM# for VSEN5
0 = Disable
1 = Enable
3
VF_VSEN4 – Enable VOLT_ALM# for VSEN4
0 = Disable
1 = Enable
2
VF_VSEN3 – Enable VOLT_ALM# for VSEN3
0 = Disable
1 = Enable
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NCT7904D
BIT
DESCRIPTION
1
VF_VSEN2 – Enable VOLT_ALM# for VSEN2
0 = Disable
1 = Enable
0
VF_VSEN1 – Enable VOLT_ALM# for VSEN1
0 = Disable
1 = Enable
VF_SEL1 – Voltage Fault Select Register
Location: Bank 1 Address DAHEX
Default Value: 00HEX
BIT
7
6
5
4
3
2
1
0
DESCRIPTION
VF_VBAT – Enable VOLT_ALM# for VBAT
0 = Disable
1 = Enable
VF_3VDD – Enable VOLT_ALM# for 3VDD
0 = Disable
1 = Enable
VF_VSEN14 – Enable VOLT_ALM# for VSEN14
0 = Disable
1 = Enable
VF_VSEN13 – Enable VOLT_ALM# for VSEN13
0 = Disable
1 = Enable
VF_VSEN12 – Enable VOLT_ALM# for VSEN12
0 = Disable
1 = Enable
VF_VSEN11 – Enable VOLT_ALM# for VSEN11
0 = Disable
1 = Enable
VF_VSEN10 – Enable VOLT_ALM# for VSEN10
0 = Disable
1 = Enable
VF_VSEN9 – Enable VOLT_ALM# for VSEN9
0 = Disable
1 = Enable
VF_SEL2 – Voltage Fault Select Register
Location: Bank 1 Address DBHEX
Default Value: 00HEX
BIT
7-5
4
3
DESCRIPTION
Reserved
VF_VSEN19 – Enable VOLT_ALM# for VSEN19
0 = Disable
1 = Enable
VF_VSEN18 – Enable VOLT_ALM# for VSEN18
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NCT7904D
BIT
2
1
0
DESCRIPTION
0 = Disable
1 = Enable
VF_VSEN17 – Enable VOLT_ALM# for VSEN17
0 = Disable
1 = Enable
Reserved
VF_V3VSB – Enable VOLT_ALM# for 3VSB
0 = Disable
1 = Enable
7.2.9 Fan Fault Control Registers
Location: Bank 1 Address DCHEX
Type:
Read / Write
Reset:
Power On Reset
Default Value: 00HEX
BIT
7
6-0
DESCRIPTION
EN_FFAULT – Enable fan fault function.
0 = Disable
1 = Enable
Reserved
7.2.10
Fan Fault Source Selection Registers
Location:
FF_SEL0
- Bank 1 Address DDHEX
FF_SEL1
- Bank 1 Address DEHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
FF_SEL0 – Fan Fault Select Register
Location: Bank 1 Address DDHEX
Default Value: 00HEX
BIT
DESCRIPTION
7
FF_FANIN8 – Enable FAN_ALM# for FANIN8
0 = Disable
1 = Enable
6
FF_FANIN7 – Enable FAN_ALM# for FANIN7
0 = Disable
1 = Enable
5
FF_FANIN6 – Enable FAN_ALM# for FANIN6
0 = Disable
1 = Enable
4
FF_FANIN5 – Enable FAN_ALM# for FANIN5
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NCT7904D
BIT
DESCRIPTION
0 = Disable
1 = Enable
3
FF_FANIN4 – Enable FAN_ALM# for FANIN4
0 = Disable
1 = Enable
2
FF_FANIN3 – Enable FAN_ALM# for FANIN3
0 = Disable
1 = Enable
1
FF_FANIN2 – Enable FAN_ALM# for FANIN2
0 = Disable
1 = Enable
0
FF_FANIN1 – Enable FAN_ALM# for FANIN1
0 = Disable
1 = Enable
FF_SEL1 – Fan Fault Select Register
Location: Bank 1 Address DEHEX
Default Value: 00HEX
BIT
7-4
3
2
1
0
DESCRIPTION
Reserved
FF_FANIN12 – Enable FAN_ALM# for FANIN12
0 = Disable
1 = Enable
FF_FANIN11 – Enable FAN_ALM# for FANIN11
0 = Disable
1 = Enable
FF_FANIN10 – Enable FAN_ALM# for FANIN10
0 = Disable
1 = Enable
FF_FANIN9 – Enable FAN_ALM# for FANIN9
0 = Disable
1 = Enable
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NCT7904D
7.2.11 Temperature Fault Control Registers
Location: Bank 1 Address E0HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
DESCRIPTION
7
EN_TFAULT – Enable temperature fault function.
0 = Disable (Default)
1 = Enable
6
TF_WNC
0 = Temperature fault boundary is critical level (Default)
1 = Temperature fault boundary is warning level
5-0
Reserved.
7.2.12
Temperature Fault Source Selection Registers
Location:
TF_SEL0
- Bank 1 Address E1HEX
TF_SEL1
- Bank 1 Address E2HEX
TF_SEL2
- Bank 1 Address E3HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
TF_SEL0 – Temperature Fault Select Register
Location: Bank 1 Address E1HEX
Default Value: 00HEX
BIT
7-5
4
3
2
1
0
DESCRIPTION
Reserved
TF_LTD – Enable TEMP_ALM# for LTD
0 = Disable
1 = Enable
TF_VSEN89 – Enable TEMP_ALM# for VSEN89
0 = Disable
1 = Enable
TF_VSEN67 – Enable TEMP_ALM# for VSEN67
0 = Disable
1 = Enable
TF_VSEN45 – Enable TEMP_ALM# for VSEN45
0 = Disable
1 = Enable
TF_VSEN23 – Enable TEMP_ALM# for VSEN23
0 = Disable
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NCT7904D
BIT
DESCRIPTION
1 = Enable
TF_SEL1 – Temperature Fault Select Register
Location: Bank 1 Address E2HEX
Default Value: 00HEX
BIT
7-4
3
2
1
0
DESCRIPTION
Reserved
TF_TCPU4 – Enable TEMP_ALM# for TCPU4
0 = Disable
1 = Enable
TF_TCPU3 – Enable TEMP_ALM# for TCPU3
0 = Disable
1 = Enable
TF_TCPU2 – Enable TEMP_ALM# for TCPU2
0 = Disable
1 = Enable
TF_TCPU1 – Enable TEMP_ALM# for TCPU1
0 = Disable
1 = Enable
TF_SEL2 – Temperature Fault Select Register
Location: Bank 1 Address E3HEX
Default Value: 00HEX
BIT
7-4
3
2
1
0
DESCRIPTION
Reserved
TF_TCPU8 – Enable TEMP_ALM# for TCPU8
0 = Disable
1 = Enable
TF_TCPU7 – Enable TEMP_ALM# for TCPU7
0 = Disable
1 = Enable
TF_TCPU6 – Enable TEMP_ALM# for TCPU6
0 = Disable
1 = Enable
TF_TCPU5 – Enable TEMP_ALM# for TCPU5
0 = Disable
1 = Enable
7.2.13
THERMTRIP Control and Status Register
Location: Bank 1 Address E8HEX
Default Value: 00HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
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BIT
7-3
DESCRIPTION
Reserved.
2
CLR_THRM – Clear the thermal trip status.
If write 1, to clear thermal trip status.
1
EN_THRM – Enable thermal trip event.
0 = Disable
1 = Enable
0
THRM_STS – Thermal trip event status. (Read Only) (Power by VBAT)
0 = Thermal trip event not occurred or be cleared.
1 = Thermal trip event occurred.
(It will always be shown no matter what EN_THRM is)
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7.3
Bank 2 REGISTER DETAIL
7.3.1 PECI Function Enable Register (PFE)
Location:
PFE - Bank 2 Address 00HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
Type:
Reset:
PFE
BIT
7
NAME
PECI_En
6
5
4
3
Reserved
2
1
0
Manual_En
BiasRTH_En
GetPower_En
DEFAULT
18HEX
BIT
DESCRIPTION
Enable PECI Host Function. (PECI_En)
7
6-3
Reserved
2
Enable PECI Manual Mode Transaction (Manual_En)
Fill in command content into PMMC and PMMWD registers defined in 7.3.8 and
7.3.9 section before enable this bit.
1
Enable function of weighting “Count” retrieved from GetTemp() to form CPU
temperature
0BIN => Disable ( It means that Temperature = “Count” )
1BIN => Enable
( It means that Temperature = “Count” * Scale, Scale is defined by Scale_Sel[2:0] in
Bank2 Index03)
0
Get Power Function (GetPower_En)
This function can routinely return the total energy consumed by the processor.
0BIN = Disable get CPU Power Function.
1BIN = Enable get CPU Power Function.
7.3.2 PECI Timing Configure Register (PTC)
Location:
Type:
Reset:
PTC - Bank 2 Address 01HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
PTC
BIT
7
6
NAME
RtHigher
Clamp
5
4
3
ATR
1
0
Reserved
DEFAULT
01HEX
BIT
DESCRIPTION
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BIT
DESCRIPTION
7
Return Higher Temperature between Doamin0 and domain1.(RtHigher)
0BIN = The temperature of each agent is returned from domain 0 or domain 1.
It depends on control register Bit[3:0] in Bank 2 Address 03HEX.
1BIN = Return the higher temperature between domain 0 and domain 1
6
PECI clamping function to filter the unreasonable DTS “count” value. (Clamp)
0 = DTS values are fully transparent.
1 = DTS values are clamped in -128 ~ 0.
Adjust Transaction Tbit Rate. (ATR)
5-4
3-0
CLKIN
14.318MHz
33MHz
48MHz
00BIN
Tbit = 1.1us
Tbit = 0.5us
Tbit = 0.5us
01BIN
Tbit = 2.2us
Tbit = 1us
Tbit = 1us
10BIN
Tbit = 4.5us
Tbit = 2us
Tbit = 2us
11BIN
Tbit = 8.9us
Tbit = 4us
Tbit = 4us
Reserved
7.3.3 PECI Agent and Domain Configure Register (PADC)
Location:
Type:
Reset:
PADC - Bank 2 Address 02HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
PADC
BIT
7
NAME
6
5
4
3
En_Agt[3:0]
1
0
Dmn1_Agt[3:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Assign which agent will be approached by PECI host
[Bit7] = CPU agent 3
[Bit6] = CPU agent 2
[Bit5] = CPU agent 1
[Bit4] = CPU agent 0
3-0
Indicate which agent equips with domain1.
[Bit3] = Agent 3 with / without Domain1
[Bit2] = Agent 2 with / without Domain1
[Bit1] = Agent 1 with / without Domain1
[Bit0] = Agent 0 with / without Domain1
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7.3.4 PECI Relative Temperature Scale Register (PRTS)
Location:
Type:
Reset:
PRTS - Bank 2 Address 03HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
PRTS
BIT
7
NAME
Reserved
6
5
4
3
Scale_Sel[2:0]
1
0
RtDmn_Agt[3:0]
DEFAULT
40HEX
BIT
DESCRIPTION
7
2
Reserved
6-4
Weighting “count” to form temperature. It is available only while BIASRTH (Bank 2
Address 00HEX Bit[1]=1) is asserted,
Through this, the final Temperature = “count” * Scale_Sel[2:0].
000BIN = 0.78125
001BIN = 0.84375
010BIN = 0.90625
011BIN = 0.96875
100BIN = 1.03125
101BIN = 1.09375
110BIN = 1.15625
111BIN = 1.21875
3-0
Agent 3 – Agent 0 always return relative temperature in ARTR registers defined by
7.3.11.
These bits specify that these relative temperatures are come from domain 0 or
domain1.
However this configuration is available only while RtHigher (Bank 2
Address 01HEX Bit[7]) is de-asserted.
[bit3] = 0 / 1 => Agent3 will return the relative temperature from domain 0 / domain 1.
[bit2] = 0 / 1 => Agent2 will return the relative temperature from domain 0 / domain 1.
[bit1] = 0 / 1 => Agent1 will return the relative temperature from domain 0 / domain 1.
[bit0] = 0 / 1 => Agent0 will return the relative temperature from domain 0 / domain 1.
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7.3.5 DTS Power Source Control Register
Location: Bank 2 Address 04HEX
Default Value: 01HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
DPSC
BIT
7
6
NAME
5
4
3
2
Reserved
1
0
DTS_SRC_SEL
DEFAULT
01HEX
BIT
DESCRIPTION
T_RTA_EN
7-3
Reserved.
2-1
DTS_SRC_SEL – DTS Source Selection
00 = All from PECI
01 = All from Host (LSN_EN must be disable)
10 = Reserved
11 = Temperature from PECI and Power from Host (LSN_EN must be enable)
T_RTA_EN – PECI Temperature Running Time Average Enable
0 = Disable
1 = Enable (Default)
0
7.3.6 TBit Width Register ( TBW )
Location: Bank 2 Address 05HEX
Type:
Read
Reset:
Power On Reset
RESETIN# with LOCK=0
TBW
BIT
7
6
5
4
3
2
1
0
NAME
LSN_RST_CNT[6:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7-0
Record TBit time in PECI Listening mode. The allowable lowest PECI transaction speed
is 125Kz.
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7.3.7 PECI Listening Mode Configuration Register ( PLMC )
Location: Bank 2 Address 06HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
TBW
BIT
7
NAME
6
5
Reserved
4
3
2
LSN_CMD_ERR
Reserved
LSN_EN
DEFAULT
01HEX
BIT
DESCRIPTION
7-5
1
0
LSN_TBIT_LW[1:0]
Reserved
4
LSN_CMD_ERR: Indicator for command error while PECI listening mode is active
3
Reserved
2
LSN_EN: Enable PECI listening mode
1-0
LSN_TBIT_LW: Idle state period selection
00b = 2-TBit
01b = 3-TBit
10b = 4-TBit
11b = 5-TBit
7.3.8 PECI VTT Power Detect Configuration Register ( PVCR )
Location: Bank 2 Address 07HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
TBW
BIT
7
NAME
VTT_OK
6
5
4
Reserved
3
2
1
0
VTT_CRC
VTT_CLR
VTT_INIT_STS
DEFAULT
03HEX
BIT
DESCRIPTION
7
6-3
VTT_OK : VTT power OK indicator. (read only)
‘0’ : VTT is not OK.
‘1’ : VTT is OK.
Reserved
2
VTT_CRC : CRC input source selection
‘0’ : The input source of CRC is purely from PECI physical bus
‘1’ : The input source of CRC comes from host’s internal write-out data and PECI
physical bus
1
VTT_CLR : Retention control for absolute temperature data
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BIT
DESCRIPTION
‘0’ : Keep last data while VTT is loss
‘1’ : Clear absolute temperature data to default value while VTT is loss
0
VTT_INIT_STS : PECI transaction control while VTT is shut off
‘0’ : PECI transaction never stop even though VTT is loss
‘1’ : Suspend PECI transaction while VTT is power loss
7.3.9 PECI Agent Tbase Temperature Register (PATB)
Location:
PATB 0
- Bank 2 Address 08HEX
PATB 1
- Bank 2 Address 09HEX
PATB 2
- Bank 2 Address 0AHEX
PATB 3
- Bank 2 Address 0BHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
PATB0
BIT
7
NAME
Reserved
6
5
4
3
2
1
0
2
1
0
2
1
0
2
1
0
Tbase0[6:0]
DEFAULT
00HEX
PATB1
BIT
7
NAME
Reserved
6
5
4
3
Tbase1[6:0]
DEFAULT
00HEX
PATB2
BIT
7
NAME
Reserved
6
5
4
3
Tbase2[6:0]
DEFAULT
00HEX
PATB3
BIT
7
NAME
Reserved
6
5
4
3
Tbase3[6:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7
6-0
Reserved
Agent0 ~ Agent3 Tbase Temperature setting.
With these setting, the PECI negative temperature format could be translated into
positive format.
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7.3.10
PECI Power Averaging Configure Register (PPAC)
Location:
Address
- Bank 2 Address 0CHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
PPAC
BIT
7
6
5
4
NAME
RST_PECI
DTS_En
IvyBridge_
En
GetDRAM_
En
DEFAULT
0FHEX
BIT
DESCRIPTION
3
2
Reserved
1
0
P_AVG_SE
L[1:0]
7
Reset PECI Function
6
Enabling DTS (Sensor) Based Thermal Spec supporting; in addition to PECI
transaction, it also affects fan speed control.
1: Enable supporting DTS based thermal spec
0: Disable supporting
5
Margin source selection of DTS (Sensor) Based fan control.
1: Margin is provided by CPU directly
0: Margin is calculated by NCT7904D
4
Enable Get DRAM Temperature
1: Enable
0: Disable (Default)
3-2
Reserved
1-0
Running Time Average algorithm has been involved in CPU power reporting.
00BIN =
PowerN +1 = Power _ Inst
1
1
PowerN +1 = ( PowerN ⋅ ) + ( Power _ Inst ⋅ )
2
2
1
3
10BIN = PowerN +1 = ( PowerN ⋅ ) + ( Power _ Inst ⋅ )
4
4
7
1
11BIN = PowerN +1 = ( PowerN ⋅ ) + ( Power _ Inst ⋅ )
8
8
01BIN =
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7.3.11
Averaging DTS Based Thermal Spec Configure Register (ADBTSC)
Location:
Alpha_f
Alpha_s
Factor_C
Type:
Reset:
- Bank 2 Address 0DHEX
- Bank 2 Address 0EHEX
- Bank 2 Address 0FHEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
Alpha_f / Alpha_s / Factor_C
BIT
7
NAME
5
4
3
2
1
0
Alpha_f / Alpha_s / Factor_C
DEFAULT
FFHEX /
BIT
7-0
6
12HEX /
62HEX
DESCRIPTION
Alpha_f / Alpha_s: the time constant coefficient ( unit : 1/second )
Factor_C: The scale factor for each average
The averaging formula is as following.
Tdts_f = Alpha_f X Tdts_max + Tdts_f_previous X ( 1 – Alpha_f )
Tdts_s = Alpha_s X Tdts_max + Tdts_s_previous X ( 1 – Alpha_s )
Tdts_ave = Factor_C X Tdts_f + ( 1 – Factor_C ) X Tdts_s
Where:
Tdts_max is the instantaneous DTS Based Thermal Spec. NCT7904D will
automatically calculate it.
Tdts_f_previous is the previous value of Tdts_f.
Tdts_s_previous is the previous value of Tdts_s.
The parameter value is to sum up each bit weighting. The weighting of each bit is
defined as following.
[7] = 0.5
[6] = 0.25
[5] = 0.125
[4] = 0.0625
[3] = 0.03125
[2] = 0.015625
[1] = 0.0078125
[0] = 0.00390625
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7.3.12
PECI Manual Mode Configure Register (PMMC)
Location:
Address
- Bank 2 Address 10HEX
Write_Length
- Bank 2 Address 11HEX
Read_Length
- Bank 2 Address 12HEX
Command_Code
- Bank 2 Address 13HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
PMMC
BIT
7
6
5
4
NAME
Address
DEFAULT
00HEX
BIT
7
6
5
4
3
2
1
0
3
2
1
0
2
1
0
2
1
0
NAME
Write Length
DEFAULT
00HEX
BIT
7
6
5
4
3
NAME
Read Length
DEFAULT
00HEX
BIT
7
6
5
4
3
NAME
Command Code
DEFAULT
00HEX
BIT
DESCRIPTION
7-0
These settings are necessary while manual mode transaction is required. Please refer
to formal PECI spec for more information on them.
It should be setup in advance before Manual Mode enable ( Bank 2 Address 00HEX
Bit[2] =1),
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7.3.13
PECI Manual Mode Write Data Register (PMMWD)
Location:
PMMWD 1
- Bank 2 Address 14HEX
PMMWD 2
- Bank 2 Address 15HEX
PMMWD 3
- Bank 2 Address 16HEX
PMMWD 4
- Bank 2 Address 17HEX
PMMWD 5
- Bank 2 Address 18HEX
PMMWD 6
- Bank 2 Address 19HEX
PMMWD 7
- Bank 2 Address 1AHEX
PMMWD 8
- Bank 2 Address 1BHEX
PMMWD 9
- Bank 2 Address 1CHEX
PMMWD 10
- Bank 2 Address 1DHEX
PMMWD 11
- Bank 2 Address 1EHEX
PMMWD 12
- Bank 2 Address 1FHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
PMMWD1 ~ PMMWD12
BIT
7
6
5
4
3
2
1
0
NAME
Write Data 1 ~ Write Data 12
DEFAULT
00HEX
BIT
DESCRIPTION
7-0
These settings are necessary while manual mode transaction is required. Please refer
to formal PECI spec for more information on them.
It should be setup in advance before Manual Mode enable ( Bank 2 Address 00HEX
Bit[2] =1),
7.3.14
PECI Manual Mode Read Data Register (PMMRD)
Location:
PMMRD 1
- Bank 2 Address 20HEX
PMMRD 2
- Bank 2 Address 21HEX
PMMRD 3
- Bank 2 Address 22HEX
PMMRD 4
- Bank 2 Address 23HEX
PMMRD 5
- Bank 2 Address 24HEX
PMMRD 6
- Bank 2 Address 25HEX
PMMRD 7
- Bank 2 Address 26HEX
PMMRD 8
- Bank 2 Address 27HEX
PMMRD 9
- Bank 2 Address 28HEX
Type:
Read Only
Reset:
Power On Reset
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PMMRD1 ~ PMMRD9
BIT
7
6
5
4
3
2
1
0
NAME
Read Data 1 ~ Read Data 9
DEFAULT
00HEX
BIT
DESCRIPTION
7-0
These data are meaningful just after manual mode transaction is finished. Please refer
to formal PECI spec for more information on them.
PECI Manual Mode Support Command and Data
Write Length
CR 11HEX
Read Length
CR 12HEX
Ping
00
00
Get DIB
01
08
F7
Get Temp
01
02
01
06
02 / 03 / 05
61
08 / 09 / 0B
01
65
05
02 / 03 / 05
E1
07 / 08 / 0A
01
E5
PKGRd30
05
02 / 03 / 05
A1
PKGWr30
07 / 08 / 0A
01
A5
IAMSRRd30
05
02 / 03 / 05 / 09
B1
IAMSRWr30
07 / 08 / 0A / 0E
01
B5
Command
Bank 2
Address
CR 10HEX
PCIRd30
30/
31/
32/
33
PCIWr30
PCIRdLocal30
PCIWrLocal30
Command Code
CR 13HEX
PECI Manual Mode Read Data Table
Command
PCI
Rd30
PCI
Wr30
PCIRd
Local3
0
PCIWr
Local30
PKG
Rd30
PKG
Wr30
IAMSR
Rd30
IAMSR
Wr30
GetDIB
GetTe
mp
Command
Code
61
65
E1
E5
A1
A5
B1
B5
F7
01
RdData 1
CR 20HEX
Ccode
Ccode
Ccode
Ccode
Ccode
Ccod
e
Ccode
Ccode
*
*
RdData 2
CR 21HEX
*
*
*
*
*
*
Data
LSB_1
*
Device
Info
*
RdData 3
CR 22HEX
*
*
*
*
*
*
Data
LSB_2
*
Revision
Number
*
RdData 4
CR 23HEX
*
*
*
*
*
*
Data
LSB_3
*
Reserved
1
*
RdData 5
*
*
*
*
*
*
Data
*
Reserved
*
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Command
PCI
Rd30
PCIRd
Local3
0
PCI
Wr30
PCIWr
Local30
PKG
Rd30
PKG
Wr30
IAMSR
Rd30
IAMSR
Wr30
LSB_4
CR 24HEX
GetTe
mp
GetDIB
2
RdData 6
CR 25HEX
Data
LSB_1
*
Data
LSB_1
*
Data
LSB_1
*
Data
LSB_5
*
Reserved
3
*
RdData 7
CR 26HEX
Data
LSB_2
*
Data
LSB_2
*
Data
LSB_2
*
Data
LSB_6
*
Reserved
4
*
RdData 8
CR 27HEX
Data
LSB_3
*
Data
LSB_3
*
Data
LSB_3
*
Data
LSB_7
*
Reserved
5
Temp_
LB
RdData 9
CR 28HEX
Data
MSB
*
Data
MSB
*
Data
MSB
*
Data
MSB
*
Reserved
6
Temp_
HB
*mean do not care
PECI Manual Command
Write Data Table
Command
PCI
Rd30
PCI
Wr30
PCIRd
Local30
PCIWr
Local30
PKG
Rd30
PKG
Wr30
IAMSR
Rd30
IAMSR
Wr30
Command
Code
61
65
E1
E5
A1
A5
B1
B5
WrData 1
CR 14HEX
Host
ID
Host
ID
Host
ID
Host
ID
Host
ID
Host
ID
Host
ID
Host
ID
WrData 2
CR 15HEX
Addr
LSB_1
Addr
LSB_1
Addr
LSB_1
Addr
LSB_1
Index
Index
Processor
ID
Processor
ID
WrData 3
CR 16HEX
Addr
LSB_2
Addr
LSB_2
Addr
LSB_2
Addr
LSB_2
Param
LSB
Param
LSB
Addr
LSB
Addr
LSB
WrData 4
CR 17HEX
Addr
LSB_3
Addr
LSB_3
Addr
MSB
Addr
MSB
Param
MSB
Param
MSB
Addr
MSB
Addr
MSB
WrData 5
CR 18HEX
Addr
MSB
Addr
MSB
*
Data
LSB_1
*
Data
LSB_1
*
Data
LSB_1
WrData 6
CR 19HEX
*
Data
LSB_1
*
Data
LSB_2
*
Data
LSB_2
*
Data
LSB_2
WrData 7
CR 1AHEX
*
Data
LSB_2
*
Data
LSB_3
*
Data
LSB_3
*
Data
LSB_3
WrData 8
CR 1BHEX
*
Data
LSB_3
*
Data
MSB
*
Data
MSB
*
Data
LSB_4
WrData 9
CR 1CHEX
*
Data
MSB
*
*
*
*
*
Data
LSB_5
WrData10
CR 1DHEX
*
*
*
*
*
*
*
Data
LSB_6
WrData11
CR 1EHEX
*
*
*
*
*
*
*
Data
LSB_7
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Command
PCI
Rd30
PCI
Wr30
PCIRd
Local30
PCIWr
Local30
PKG
Rd30
PKG
Wr30
IAMSR
Rd30
IAMSR
Wr30
WrData12
CR 1FHEX
*
*
*
*
*
*
*
Data
MSB
*mean do not care
7.3.15
Agent Relative Temperature Registers (ARTR)
Location:
A0D0RTH
- Bank 2 Address 30HEX
A0D0RTL
- Bank 2 Address 31HEX
A0D1RTH
- Bank 2 Address 32HEX
A0D1RTL
- Bank 2 Address 33HEX
A1D0RTH
- Bank 2 Address 34HEX
A1D0RTL
- Bank 2 Address 35HEX
A1D1RTH
- Bank 2 Address 36HEX
A1D1RTL
- Bank 2 Address 37HEX
A2D0RTH
- Bank 2 Address 38HEX
A2D0RTL
- Bank 2 Address 39HEX
A2D1RTH
- Bank 2 Address 3AHEX
A2D1RTL
- Bank 2 Address 3BHEX
A3D0RTH
- Bank 2 Address 3CHEX
A3D0RTL
- Bank 2 Address 3DHEX
A3D1RTH
- Bank 2 Address 3EHEX
A3D1RTL
- Bank 2 Address 3FHEX
Type:
Read Only
Reset:
Power On Reset
BIT
NAME
15
14
13
12
9
8
Temperature[8:2]
DEFAULT
NAME
10
A0D0RTH – A3D0RTH : Agent 0- Agent 3 Domain0 Relative Temperature High byte
A0D1RTH – A3D1RTH : Agent 0- Agent 3 Domain1 Relative Temperature High byte
Refer the PECI Temperature format to calculate temperature data.
Sign
BIT
11
F8HEX
7
6
5
4
3
2
1
0
A0D0RTL – A3D0RTL : Agent 0- Agent 3 Domain0 Relative Temperature Low byte
A0D1RTL – A3D1RTL : Agent 0- Agent 3 Domain1 Relative Temperature Low byte
Refer the PECI Temperature format to calculate temperature data.
Temperature[1:0]
DEFAULT
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TEMP_2
TEMP_4
TEMP_8
TEMP_1
6
TEMP_3
2
TEMP_6
4
80HEX
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GetTemp() PECI Temperature format:
BIT
DESCRIPTION
15
Sign Bit. (Sign) In PECI Protocol, this bit should always be 1 to represent a negative
temperature.
14-6
The integer part of the relative temperature. (Temperature[8:0])
5
TEMP_2. 0.5℃ unit.
4
TEMP_4. 0.25℃ unit.
3
TEMP_8. 0.125℃ unit.
2
TEMP_16. 0.0625℃ unit.
1
TEMP_32. 0.03125℃ unit.
0
TEMP_64. 0.015625℃ unit.
GetTemp() Response Definition:
RESPONSE
MEANING
General Sensor Error
(GSE)
Thermal scan did not complete in time. Retry is appropriate.
0x0000
Processor is running at its maximum temperature or is currently being reset.
All other data
Valid temperature reading, reported as a negative offset from the TCC
activation temperature.
The valide temperature reading is referred to GetTemp() PECI Temperature
format
On some occasions, PECI will return the abnormal states of the PECI bus in addition to the
temperature. All the information will be recorded. In some cases, the NCT7904D will also do further
processing for the alert mechanism. The following describes these codes and their effects to the
NCT7904D.
Error Code
Description
NCT7904D host operation
8000HEX
General Sensor Error
8001HEX
Sensing Device Missing
8002HEX
Operational, but the temperature is
lower than the sensor operation range
(underflow).
Compulsorily write -128℃ back to the
temperature readouts.
8003HEX
Operational, but the temperature is
higher than the sensor operation range.
(overflow)
compulsorily write 127℃ back to the
temperature readouts.
Reserved.
No further operation.
No further processing.
8004HEX
≀
81FFHEX
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7.3.16
TSI Control Registers
Location: Bank 2 Address 50HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
DESCRIPTION
7
EN_TSI – Enable TSI function
0 = Disable
1 = Enable
(* Set Bank2 Addr[53h] to 00h , before set EN_TSI=1)
6
LSN_MD – Enable TSI Listening function
0 = Disable
1 = Enable
(Listened temperatures will override the CPU temperatures)
5-4
TSI_SPD[1:0] – TSI channel speed
00BIN = 250KHz
01BIN = 100KHz
10BIN = 50KHz
11BIN = 10KHz
3-0
Reserved
7.3.17
TSI Client Enable Registers
Location: Bank 2 Address 51HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: FFHEX
BIT
7-0
DESCRIPTION
EN_CLIENT[7:0] – Enable TSI clients
0 = Disable
1 = Enable
7.3.18
TSI Manual Configuration Registers
Location: Bank 2 Address 52HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 08HEX
BIT
DESCRIPTION
7
EN_MANU – Enable TSI manual mode
0 = Disable
1 = Enable
6
MANU_RNW – TSI manual read / write
0 = Write
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BIT
DESCRIPTION
1 = Read
5
MANU_STEP – Enable TSI manual mode
Set to do manual command one time then auto be cleared
4
MANU_STS – Report TSI Status (Read Only)
0 = Transaction OK
1 = Transaction fail
3
MANU_DONE – TSI Manual Done Status (Read Only)
0 = Transaction done
1 = Transaction still processing
2-0
Reserved
7.3.19
TSI Test Mode Registers
Location: Bank 2 Address 53HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 02HEX
BIT
7-0
DESCRIPTION
Internal Test Mode Register[7:0] – Set this register to 00h before enable TSI function.
7.3.20
TSI Manual Address Registers
Location: Bank 2 Address 54HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
DESCRIPTION
7-0
MANU_ADDR[7:0] – TSI manual command address
7.3.21
TSI Manual Command Registers
Location: Bank 2 Address 55HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MANU_CMD[7:0] – TSI manual command data
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7.3.22
TSI Manual Write Data Registers
Location: Bank 2 Address 56HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MANU_WDATA[7:0] – TSI manual write data
7.3.23
TSI Manual Read Data Registers
Location: Bank 2 Address 57HEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MANU_RDATA[7:0] – TSI manual read data
7.3.24
PCH Read Control Registers
Location: Bank 2 Address 60HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 20HEX
BIT
DESCRIPTION
7
EN_PCH_RD – Enable PCH read function
0 = Disable
1 = Enable
6
Reserved
5-4
PCH_RD_SPD[1:0] – PCH channel read speed
00BIN = 250KHz
01BIN = 100KHz
10BIN = 50KHz
11BIN = 10KHz
3-0
Reserved
7.3.25
PCH Client Address Registers
Location: Bank 2 Address 61HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
PCH_ADDR[7:0] – PCH client address
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7.3.26
PCH Command Registers
Location: Bank 2 Address 62HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
PCH_CMD[7:0] – PCH command data
7.3.27
PCH Read Byte Count Registers
Location: Bank 2 Address 63HEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 00HEX
BIT
7-0
DESCRIPTION
PCH_BYTE_CNT[7:0] – PCH read byte count
7.3.28
SMBUS Master Manual Configuration Registers
Location: Bank 2 Address 64HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 08HEX
BIT
DESCRIPTION
7
EN_SM_MANU – Enable SMBUS Master manual mode
0 = Disable
1 = Enable
6
SM_RNW – SMBUS Master manual read / write
0 = Write
1 = Read
5
SM_STEP – Enable SMBUS Master manual mode
Set to do manual command one time then auto be cleared
4
SM_STS – Report SMBUS Master Status (Read Only)
0 = Transaction OK
1 = Transaction fail
3
SM_DONE – SMBUS Master Manual Done Status (Read Only)
0 = Transaction done
1 = Transaction still processing
2-0
Reserved
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7.3.29
SMBUS Master Manual Address Registers
Location: Bank 2 Address 65HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
SM_ADDR[7:0] – SMBUS Master manual command address
7.3.30
SMBUS Master Manual Command Registers
Location: Bank 2 Address 66HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
SM_CMD[7:0] – SMBUS Master manual command data
7.3.31
SMBUS Master Manual Write Data Registers
Location: Bank 2 Address 67HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7-0
DESCRIPTION
SM_WDATA[7:0] – SMBUS Master manual write data
7.3.32
SMBUS Master Manual Read Data Registers
Location: Bank 2 Address 68HEX
Type:
Read Only
Reset:
Power On Reset
Default Value: 00HEX
BIT
7-0
DESCRIPTION
SM_RDATA[7:0] – SMBUS Master manual read data
7.3.33 External Read Control Registers
Location: Bank 2 Address 6AHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Default Value: 00HEX
BIT
7
DESCRIPTION
EN_EXT_RD – Enable External Read function.
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BIT
DESCRIPTION
0 = Disable
1 = Enable
6-4
Reserved
3
EN_EXT_P3 – Enable EXT_P3 read function.
0 = Disable
1 = Enable
2
EN_EXT_P2 – Enable EXT_P2 read function.
0 = Disable
1 = Enable
1
EN_EXT_P1 – Enable EXT_P1 read function.
0 = Disable
1 = Enable
0
EN_EXT_P0 – Enable EXT_P0 read function.
0 = Disable
1 = Enable
7.3.34 External Read Address and Command Register
Location:
EXT_ADDR_P0
- Bank 0 Address 6CHEX
EXT_CMD_P0
- Bank 0 Address 6DHEX
EXT_ADDR_P1
- Bank 0 Address 6EHEX
EXT_CMD_P1
- Bank 0 Address 6FHEX
EXT_ADDR_P2
- Bank 0 Address 70HEX
EXT_CMD_P2
- Bank 0 Address 71HEX
EXT_ADDR_P3
- Bank 0 Address 72HEX
EXT_CMD_P3
- Bank 0 Address 73HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
EXT_ADDR_P0 – Port 0 external SMBUS address
Location: Bank 2 Address 6CHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
EXT_ADDR_P0 – Port 0 external SMBUS address
EXT_CMD_P0 – Port 0 external SMBUS command
Location: Bank 2 Address 6DHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
EXT_CMD_P0 – Port 0 external SMBUS command
EXT_ADDR_P1 – Port 1 external SMBUS address
Location: Bank 2 Address 6EHEX
Default Value: 00HEX
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BIT
DESCRIPTION
EXT_ADDR_P1 – Port 1 external SMBUS address
7-0
EXT_CMD_P1 – Port 1 external SMBUS command
Location: Bank 2 Address 6FHEX
Default Value: 00HEX
BIT
DESCRIPTION
EXT_CMD_P1 – Port 1 external SMBUS command
7-0
EXT_ADDR_P2 – Port 2 external SMBUS address
Location: Bank 2 Address 70HEX
Default Value: 00HEX
BIT
DESCRIPTION
EXT_ADDR_P2 – Port 2 external SMBUS address
7-0
EXT_CMD_P2 – Port 2 external SMBUS command
Location: Bank 2 Address 71HEX
Default Value: 00HEX
BIT
DESCRIPTION
EXT_CMD_P2 – Port 2 external SMBUS command
7-0
EXT_ADDR_P3 – Port 3 external SMBUS address
Location: Bank 2 Address 72HEX
Default Value: 00HEX
BIT
DESCRIPTION
EXT_ADDR_P3 – Port 3 external SMBUS address
7-0
EXT_CMD_P3 – Port 3 external SMBUS command
Location: Bank 2 Address 73HEX
Default Value: 00HEX
BIT
DESCRIPTION
EXT_CMD_P3 – Port 3 external SMBUS command
7-0
7.3.35 Power Unit Status
Location: Bank 2 Address 80HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Power_Unit
BIT
7
NAME
5
4
3
Reserved
DEFAULT
BIT
7-4
6
2
1
0
Power_Unit[3:0]
03HEX
DESCRIPTION
Reserved
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BIT
DESCRIPTION
Power_Unit[3:0] – Unit index for power data retrieved from CPU over PECI
The calculation of unit is 1W / 2^Power_Unit. Default is 03h.
The manufacture setting will be loaded into as soon as PECI_En assertion.
However user could override it by anytime.
3-0
7.3.36
Energy Unit Status
Location: Bank 2 Address 81HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
Energy_Unit
BIT
7
NAME
6
5
4
3
Reserved
2
1
0
Energy_Unit[4:0]
DEFAULT
10HEX
BIT
DESCRIPTION
7-5
Reserved
4-0
Energy_Unit[4:0] – Unit index for energy data retrieved from CPU over PECI
The calculation of unit is 1J / 2^Energy_Unit. Default is 10h.
The manufacture setting will be loaded into as soon as PECI_En assertion.
However user could override it by anytime.
7.3.37
Retrieving Margin Status Control Registers
Location:
Type:
Reset:
CFG - Bank 2 Address 84HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
CFG
BIT
7
NAME
6
5
4
3
Reserved
DEFAULT
BIT
2
1
0
MARGIN_BSEL[1:0]
00HEX
DESCRIPTION
7-2
Reserved
1-0
MARGIN_BSEL[1:0]: Pick-up selection of margin value among returned four bytes data
from RdPkgConfig(). The pick-up data will be put into CR98 ~ CR9B
Bit[1:0] = 11 => Select last retrieved byte, MSB
rd
Bit[1:0] = 10 => Select 3 retrieved byte
Bit[1:0] = 01 => Select second retrieved byte
Bit[1:0] = 00 => Select first retrieved byte, LSB
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Location:
Type:
Reset:
Default:
MARGIN_INDEX - Bank 2 Address 85HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
00HEX
BIT
7-0
DESCRIPTION
MARGIN_INDEX: Index data for executing RdPkgConfig()
Location:
Type:
Reset:
Default:
MARGIN_PARA_L - Bank 2 Address 86HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
00HEX
BIT
7-0
DESCRIPTION
MARGIN_PARA_L: Low byte of parameter data for executing RdPkgConfig()
Location:
Type:
Reset:
Default:
MARGIN_PARA_H - Bank 2 Address 87HEX
Read / Write
Power On Reset
RESETIN# with LOCK=0
00HEX
BIT
7-0
DESCRIPTION
MARGIN_PARA_H: High byte of parameter data for executing RdPkgConfig()
7.3.38 Tjmax Temperature Target Read/Write for CPU Agent (Address : 30h ~ 33h)
Location:
Tjmax_CPU0
- Bank 2 Address 88HEX
Tjmax_CPU1
- Bank 2 Address 89HEX
Tjmax_CPU2
- Bank 2 Address 8AHEX
Tjmax_CPU3
- Bank 2 Address 8BHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
BIT
7-0
DESCRIPTION
Tjmax_CPU0[7:0] – Tjmax data for agent address 30h
Tjmax_CPU1[7:0] – Tjmax data for agent address 31h
Tjmax_CPU2[7:0] – Tjmax data for agent address 32h
Tjmax_CPU3[7:0] – Tjmax data for agent address 33h
The manufacture setting will be loaded into as soon as PECI_En assertion.
However user could override it by anytime.
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BIT
DESCRIPTION
Default
00HEX
7.3.39
33h)
Tcontrol Temperature Target Read/Write for CPU Agent (Address : 30h ~
Location:
Tjmax_CPU0
- Bank 2 Address 8CHEX
Tjmax_CPU1
- Bank 2 Address 8DHEX
Tjmax_CPU2
- Bank 2 Address 8EHEX
Tjmax_CPU3
- Bank 2 Address 8FHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
BIT
DESCRIPTION
Tcontrol_CPU0[7:0] – Tcontrol data for agent address 30h
Tcontrol_CPU1[7:0] – Tcontrol data for agent address 31h
Tcontrol_CPU2[7:0] – Tcontrol data for agent address 32h
Tcontrol_CPU3[7:0] – Tcontrol data for agent address 33h
The manufacture setting will be loaded into as soon as PECI_En assertion.
However user could override it by anytime.
7-0
Default
00HEX
7.3.40
Thermal Design Power (TDP) Status for CPU Agent (Address : 30h ~ 33h)
Location:
TDP_HB_CPU0 - Bank 2 Address 90HEX
TDP_LB_CPU0 - Bank 2 Address 91HEX
TDP_HB_CPU1 - Bank 2 Address 92HEX
TDP_LB_CPU1 - Bank 2 Address 93HEX
TDP_HB_CPU2 - Bank 2 Address 94HEX
TDP_LB_CPU2 - Bank 2 Address 95HEX
TDP_HB_CPU3 - Bank 2 Address 96HEX
TDP_LB_CPU3 - Bank 2 Address 97HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
TDP_HB_CPUx
BIT
7
NAME
Reserved
6
5
DEFAULT
BIT
7
6-0
4
3
2
1
0
TDP_HB_CPUx[6:0]
00HEX
DESCRIPTION
Reserved
High Byte Data of TDP[14:8]
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BIT
DESCRIPTION
The manufacture setting will be loaded into as soon as PECI_En assertion.
However user could override it by anytime.
TDP_LB_CPUx
BIT
7
6
5
4
3
NAME
TDP_HB_CPUx
DEFAULT
00HEX
BIT
2
1
0
DESCRIPTION
Low Byte Data of TDP[7:0]
The manufacture setting will be loaded into as soon as PECI_En assertion.
However user could override it by anytime.
7-0
7.3.41
Margin Status for CPU Agent (Address : 30h ~ 33h)
Location:
Margin_CPU1
- Bank 2 Address 98HEX
Margin_CPU2
- Bank 2 Address 99HEX
Margin_CPU3
- Bank 2 Address 9AHEX
Margin_CPU4
- Bank 2 Address 9BHEX
Type:
Read
Reset:
Power On Reset
RESETIN# with LOCK=0
Margin_CPUx
BIT
7
6
5
4
3
NAME
Margin_CPUx
DEFAULT
00HEX
BIT
7-0
2
1
0
DESCRIPTION
Margin status for DTS (Sensor) Based Thermal Spec.
If Margin is positive, then CPU die temperature is in relative safe operating region.
If margin is negative, then CPU is working with higher temperature risk.
7.3.42
Power Reporting Factor for CPU Agent (Address : 30h ~ 33h)
Location:
Factor_CPU1
- Bank 2 Address 9CHEX
Factor_CPU2
- Bank 2 Address 9DHEX
Factor_CPU3
- Bank 2 Address 9EHEX
Factor_CPU4
- Bank 2 Address 9FHEX
Type:
Read
Reset:
Power On Reset
RESETIN# with LOCK=0
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Factor_CPUx
BIT
7
6
5
4
3
NAME
Factor_CPUx
DEFAULT
FFHEX
2
1
0
BIT
DESCRIPTION
7-0
Factor_CPUx : Power reporting factor.
Power reported over PECI is always higher than actual power.
The Factor is to sum up each bit weighting. The weighting of each bit is defined as
following.
[7] = 0.5
[6] = 0.25
[5] = 0.125
[4] = 0.0625
[3] = 0.03125
[2] = 0.015625
[1] = 0.0078125
[0] = 0.00390625
7.3.43
DTS DRAM Temperature Monitor Enable Control Register
Location:
EN_MT_CTRL0
- Bank 2 Address C0HEX
EN_MT_CTRL1
- Bank 2 Address C1HEX
EN_T_DM_CTRL
- Bank 2 Address C2HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
EN_MT_CTRL0 – Digital Channel Highest Temperature Monitoring Control Register
Location: Bank 2 Address C0HEX
Default Value: 00HEX
BIT
DESCRIPTION
7
EN_MT_C3_C1 – Enable DTS CPU1 Channel3 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
6
EN_MT_C2_C1 – Enable DTS CPU1 Channel2 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
5
EN_MT_C1_C1 – Enable DTS CPU1 Channel1 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
4
EN_MT_C0_C1 – Enable DTS CPU1 Channel0 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
3
EN_MT_C3_C0 – Enable DTS CPU0 Channel3 highest DIMM temperature monitoring.
0 = Disable
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BIT
DESCRIPTION
1 = Enable
2
EN_MT_C2_C0 – Enable DTS CPU0 Channel2 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
1
EN_MT_C1_C0 – Enable DTS CPU0 Channel1 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
0
EN_MT_C0_C0 – Enable DTS CPU0 Channel0 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
EN_MT_CTRL1 – Digital Channel Highest Temperature Monitoring Control Register
Location: Bank 2 Address C1HEX
Default Value: 00HEX
BIT
7-3
DESCRIPTION
Reserved
2
EN_MT_SYS – Enable DTS CPU0 and CPU1 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
1
EN_MT_C1 – Enable DTS CPU1 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
0
EN_MT_C0 – Enable DTS CPU0 highest DIMM temperature monitoring.
0 = Disable
1 = Enable
EN_T_DM_CTRL – Digital DIMM Temperature Monitoring Control Register
Location: Bank 2 Address C2HEX
Default Value: 00HEX
BIT
DESCRIPTION
7
EN_T_C3_C1 – Enable DTS CPU1 Channel3 DIMMs temperature monitoring.
0 = Disable
1 = Enable
6
EN_T_C2_C1 – Enable DTS CPU1 Channel2 DIMMs temperature monitoring.
0 = Disable
1 = Enable
5
EN_T_C1_C1 – Enable DTS CPU1 Channel1 DIMMs temperature monitoring.
0 = Disable
1 = Enable
4
EN_T_C0_C1 – Enable DTS CPU1 Channel0 DIMMs temperature monitoring.
0 = Disable
1 = Enable
3
EN_T_C3_C0 – Enable DTS CPU0 Channel3 DIMMs temperature monitoring.
0 = Disable
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BIT
DESCRIPTION
1 = Enable
2
EN_T_C2_C0 – Enable DTS CPU0 Channel2 DIMMs temperature monitoring.
0 = Disable
1 = Enable
1
EN_T_C1_C0 – Enable DTS CPU0 Channel1 DIMMs temperature monitoring.
0 = Disable
1 = Enable
0
EN_T_C0_C0 – Enable DTS CPU0 Channel0 DIMMs temperature monitoring.
0 = Disable
1 = Enable
7.3.44 DRAM Temperature Value Register (Reterived by PECI RdPkgConfig
command)
Location:
MT_C0_C0
MT_C1_C0
MT_C2_C0
MT_C3_C0
MT_C0_C1
MT_C1_C1
MT_C2_C1
MT_C3_C1
MT_C0
MT_C1
MT_SYS
T_D0C0_C0
T_D1C0_C0
T_D2C0_C0
EN_C0_C0
T_D0C1_C0
T_D1C1_C0
T_D2C1_C0
EN_C1_C0
T_D0C2_C0
T_D1C2_C0
T_D2C2_C0
EN_C2_C0
T_D0C3_C0
T_D1C3_C0
T_D2C3_C0
EN_C3_C0
T_D0C0_C1
T_D1C0_C1
T_D2C0_C1
EN_C0_C1
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- Bank 2 Address C4HEX
- Bank 2 Address C5HEX
- Bank 2 Address C6HEX
- Bank 2 Address C7HEX
- Bank 2 Address C8HEX
- Bank 2 Address C9HEX
- Bank 2 Address CAHEX
- Bank 2 Address CBHEX
- Bank 2 Address CCHEX
- Bank 2 Address CDHEX
- Bank 2 Address CEHEX
- Bank 2 Address D0HEX
- Bank 2 Address D1HEX
- Bank 2 Address D2HEX
- Bank 2 Address D3HEX
- Bank 2 Address D4HEX
- Bank 2 Address D5HEX
- Bank 2 Address D6HEX
- Bank 2 Address D7HEX
- Bank 2 Address D8HEX
- Bank 2 Address D9HEX
- Bank 2 Address DAHEX
- Bank 2 Address DBHEX
- Bank 2 Address DCHEX
- Bank 2 Address DDHEX
- Bank 2 Address DEHEX
- Bank 2 Address DFHEX
- Bank 2 Address E0HEX
- Bank 2 Address E1HEX
- Bank 2 Address E2HEX
- Bank 2 Address E3HEX
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T_D0C1_C1
- Bank 2 Address E4HEX
T_D1C1_C1
- Bank 2 Address E5HEX
T_D2C1_C1
- Bank 2 Address E6HEX
EN_C1_C1
- Bank 2 Address E7HEX
T_D0C2_C1
- Bank 2 Address E8HEX
T_D1C2_C1
- Bank 2 Address E9HEX
T_D2C2_C1
- Bank 2 Address EAHEX
EN_C2_C1
- Bank 2 Address EBHEX
T_D0C3_C1
- Bank 2 Address ECHEX
T_D1C3_C1
- Bank 2 Address EDHEX
T_D2C3_C1
- Bank 2 Address EEHEX
EN_C3_C1
- Bank 2 Address EFHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
MT_C0_C0 – CPU0 Channel0 Highest DIMM Temperature Value Register
Location: Bank 2 Address C4HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C0_C0 [7:0]
CPU0 Channel0 Highest DIMM Temperature
MT_C1_C0 – CPU0 Channel1 Highest DIMM Temperature Value Register
Location: Bank 2 Address C5HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C1_C0 [7:0]
CPU0 Channel1 Highest DIMM Temperature
MT_C2_C0 – CPU0 Channel2 Highest DIMM Temperature Value Register
Location: Bank 2 Address C6HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C2_C0 [7:0]
CPU0 Channel2 Highest DIMM Temperature
MT_C3_C0 – CPU0 Channel3 Highest DIMM Temperature Value Register
Location: Bank 2 Address C7HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C3_C0 [7:0]
CPU0 Channel3 Highest DIMM Temperature
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MT_C0_C1 – CPU1 Channel0 Highest DIMM Temperature Value Register
Location: Bank 2 Address C8HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C0_C1 [7:0]
CPU1 Channel0 Highest DIMM Temperature
MT_C1_C1 – CPU1 Channel1 Highest DIMM Temperature Value Register
Location: Bank 2 Address C9HEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C1_C1 [7:0]
CPU1 Channel1 Highest DIMM Temperature
MT_C2_C1 – CPU1 Channel2 Highest DIMM Temperature Value Register
Location: Bank 2 Address CAHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C2_C1 [7:0]
CPU1 Channel2 Highest DIMM Temperature
MT_C3_C1 – CPU1 Channel3 Highest DIMM Temperature Value Register
Location: Bank 2 Address CBHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C3_C1 [7:0]
CPU1 Channel3 Highest DIMM Temperature
MT_C0 – CPU0 Highest DIMM Temperature Value Register
Location: Bank 2 Address CCHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C0 [7:0]
CPU0 Highest DIMM Temperature
MT_C1 – CPU1 Highest DIMM Temperature Value Register
Location: Bank 2 Address CDHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_C1 [7:0]
CPU1 Highest DIMM Temperature
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MT_SYS – CPU0 and CPU1 Highest DIMM Temperature Value Register
Location: Bank 2 Address CEHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
MT_SYS [7:0]
CPU0 and CPU1 Highest DIMM Temperature
T_DxC0_C0 – CPU0 Channel0 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address D0HEX ~ D2HEX
Default Value: 00HEX
BIT
DESCRIPTION
7-0
T_D0C0_C0 [7:0] ~ T_D2C0_C0 [7:0]
T_D0C0_C0 : CPU0 Channel0 DIMM0 Temperature
T_D1C0_C0 : CPU0 Channel0 DIMM1 Temperature
T_D2C0_C0 : CPU0 Channel0 DIMM2 Temperature
EN_C0_C0 – Enable Read CPU0 Channel0 DIMM Temperature Register
Location: Bank 2 Address D3HEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH0_C0 – Enable DTS CPU0 Channel0 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH0_C0 – Enable DTS CPU0 Channel0 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH0_C0 – Enable DTS CPU0 Channel0 DIMM0 temperature monitoring.
0 = Disable
1 = Enable
T_DxC1_C0 – CPU0 Channel1 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address D4HEX ~ D6HEX
Default Value: 00HEX
BIT
DESCRIPTION
7-0
T_D0C1_C0 [7:0] ~ T_D2C1_C0 [7:0]
T_D0C1_C0 : CPU0 Channel1 DIMM0 Temperature
T_D1C1_C0 : CPU0 Channel1 DIMM1 Temperature
T_D2C1_C0 : CPU0 Channel1 DIMM2 Temperature
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EN_C1_C0 – Enable Read CPU0 Channel1 DIMM Temperature Register
Location: Bank 2 Address D7HEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH1_C0 – Enable DTS CPU0 Channel1 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH1_C0 – Enable DTS CPU0 Channel1 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH1_C0 – Enable DTS CPU0 Channel1 DIMM0 temperature monitoring.
0 = Disable
1 = Enable
T_DxC2_C0 – CPU0 Channel2 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address D8HEX ~ DAHEX
Default Value: 00HEX
BIT
DESCRIPTION
7-0
T_D0C2_C0 [7:0] ~ T_D2C2_C0 [7:0]
T_D0C2_C0 : CPU0 Channel2 DIMM0 Temperature
T_D1C2_C0 : CPU0 Channel2 DIMM1 Temperature
T_D2C2_C0 : CPU0 Channel2 DIMM2 Temperature
EN_C2_C0 – Enable Read CPU0 Channel2 DIMM Temperature Register
Location: Bank 2 Address DBHEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH2_C0 – Enable DTS CPU0 Channel2 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH2_C0 – Enable DTS CPU0 Channel2 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH2_C0 – Enable DTS CPU0 Channel2 DIMM0 temperature monitoring.
0 = Disable
1 = Enable
T_DxC3_C0 – CPU0 Channel3 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address DCHEX ~ DEHEX
Default Value: 00HEX
BIT
7-0
DESCRIPTION
T_D0C3_C0 [7:0] ~ T_D2C3_C0 [7:0]
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BIT
DESCRIPTION
T_D0C3_C0 : CPU0 Channel3 DIMM0 Temperature
T_D1C3_C0 : CPU0 Channel3 DIMM1 Temperature
T_D2C3_C0 : CPU0 Channel3 DIMM2 Temperature
EN_C3_C0 – Enable Read CPU0 Channel3 DIMM Temperature Register
Location: Bank 2 Address DFHEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH3_C0 – Enable DTS CPU0 Channel3 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH3_C0 – Enable DTS CPU0 Channel3 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH3_C0 – Enable DTS CPU0 Channel3 DIMM0 temperature monitoring.
0 = Disable
1 = Enable
T_DxC0_C1 – CPU1 Channel0 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address E0HEX ~ E2HEX
Default Value: 00HEX
BIT
DESCRIPTION
7-0
T_D0C0_C1 [7:0] ~ T_D2C0_C1 [7:0]
T_D0C0_C1 : CPU1 Channel0 DIMM0 Temperature
T_D1C0_C1 : CPU1 Channel0 DIMM1 Temperature
T_D2C0_C1 : CPU1 Channel0 DIMM2 Temperature
EN_C0_C1 – Enable Read CPU1 Channel0 DIMM Temperature Register
Location: Bank 2 Address E3HEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH0_C1 – Enable DTS CPU1 Channel0 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH0_C1 – Enable DTS CPU1 Channel0 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH0_C1 – Enable DTS CPU1 Channel0 DIMM0 temperature monitoring.
0 = Disable
1 = Enable
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T_DxC1_C1 – CPU1 Channel1 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address E4HEX ~ E6HEX
Default Value: 00HEX
BIT
DESCRIPTION
7-0
T_D0C1_C1 [7:0] ~ T_D2C1_C1 [7:0]
T_D0C1_C1 : CPU1 Channel1 DIMM0 Temperature
T_D1C1_C1 : CPU1 Channel1 DIMM1 Temperature
T_D2C1_C1 : CPU1 Channel1 DIMM2 Temperature
EN_C1_C1 – Enable Read CPU1 Channel1 DIMM Temperature Register
Location: Bank 2 Address E7HEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH1_C1 – Enable DTS CPU1 Channel1 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH1_C1 – Enable DTS CPU1 Channel1 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH1_C1 – Enable DTS CPU1 Channel1 DIMM0 temperature monitoring.
0 = Disable
1 = Enable
T_DxC2_C1 – CPU1 Channel2 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address E8HEX ~ EAHEX
Default Value: 00HEX
BIT
DESCRIPTION
7-0
T_D0C2_C1 [7:0] ~ T_D2C2_C1 [7:0]
T_D0C2_C1 : CPU1 Channel2 DIMM0 Temperature
T_D1C2_C1 : CPU1 Channel2 DIMM1 Temperature
T_D2C2_C1 : CPU1 Channel2 DIMM2 Temperature
EN_C2_C1 – Enable Read CPU1 Channel2 DIMM Temperature Register
Location: Bank 2 Address EBHEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH2_C1 – Enable DTS CPU1 Channel2 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH2_C1 – Enable DTS CPU1 Channel2 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH2_C1 – Enable DTS CPU1 Channel2 DIMM0 temperature monitoring.
0 = Disable
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BIT
DESCRIPTION
1 = Enable
T_DxC3_C1 – CPU1 Channel3 DIMM0~DIMM2 Temperature Value Register
Location: Bank 2 Address ECHEX ~ EEHEX
Default Value: 00HEX
BIT
DESCRIPTION
7-0
T_D0C3_C1 [7:0] ~ T_D2C3_C1 [7:0]
T_D0C3_C1 : CPU1 Channel3 DIMM0 Temperature
T_D1C3_C1 : CPU1 Channel3 DIMM1 Temperature
T_D2C3_C1 : CPU1 Channel3 DIMM2 Temperature
EN_C3_C1 – Enable Read CPU1 Channel3 DIMM Temperature Register
Location: Bank 2 Address EFHEX
Default Value: 07HEX
BIT
7-3
2
1
0
DESCRIPTION
Reserved
EN_T_DIMM2_CH3_C1 – Enable DTS CPU1 Channel3 DIMM2 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM1_CH3_C1 – Enable DTS CPU1 Channel3 DIMM1 temperature monitoring.
0 = Disable
1 = Enable
EN_T_DIMM0_CH3_C1 – Enable DTS CPU1 Channel3 DIMM0 temperature monitoring.
0 = Disable
1 = Enable
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7.4
Bank 3 REGISTER DETAIL
7.4.1 Temperature to Fan Mapping Relationships (TFMR)
Location:
T1FMR - Bank 3 Address 00HEX
T2FMR - Bank 3 Address 01HEX
T3FMR - Bank 3 Address 02HEX
T4FMR - Bank 3 Address 03HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
T1FMR – T4FMR
BIT
7
NAME
6
5
4
Reserved
3
2
1
0
F4SF
F3SF
F2SF
F1SF
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Reserved
3-0
F4SF – F1SF setting involves two purposes. The one is building up the relation between
temperature source 1~4 and FANCTL1~4, the other is Fan Control mode assignment.
0 = Related FANCTL will operate in manual mode and have no relationship with
temperature (Default)
1 = Related FANCTL will operate with SmartFan control mode and be linked to relative
temperature source 1 ~ 4.
7.4.2 Default Fan Speed at Power-on (DFSP)
Location: DFSP - Bank 3 Address 04HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
DFSP
BIT
7
6
5
4
3
NAME
DefaultSpeed
DEFAULT
7FHEX
BIT
7-0
2
1
0
DESCRIPTION
Specify default fan output duty cycle after 3VDD is available
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7.4.3 SmartFan Output Step Up Time (SFOSUT)
Location: SFOSUT - Bank 3 Address 05HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
SFOSUT
BIT
7
6
5
4
NAME
3
2
1
0
1
0
1
0
UpTime
DEFAULT
0AHEX
BIT
DESCRIPTION
7-0
The update rate for increasing fan output duty cycle.
Unit: 0.1sec.
7.4.4 SmartFan Output Step Down Time (SFOSDT)
Location: SFOSDT - Bank 3 Address 06HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
SFOSUT
BIT
7
6
5
4
3
NAME
DownTime
DEFAULT
0AHEX
BIT
DESCRIPTION
7-0
The update rate for decreasing fan output duty cycle.
2
Unit: 0.1sec.
7.4.5 3-Wire Fan Enable and Fan Output Mode Control (FOMC)
Location: FOMC - Bank 3 Address 07HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
FOMC
BIT
7
NAME
6
5
3WireFan_En[3:0]
4
3
F4OMC
2
Reserved
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Enable ultra-low speed DC fan control. It means that DC fan could be driven by very
small PWM output frequency or fewer duty cycles.
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BIT
DESCRIPTION
3WireFan_En[3]: Enable FANCTL4 with this function
3WireFan_En[2]: Enable FANCTL3 with this function
3WireFan_En[1]: Enable FANCTL2 with this function
3WireFan_En[0]: Enable FANCTL1 with this function
F4OMC: FANCTL4 output mode control.
0 = PWM output (Default)
1 = DC output
3
2-0
Reserved
7.4.6 Close-Loop Fan control RPM mode and Tolerance (CLFR)
Location: CLFR - Bank 3 Address 08HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
CLFR
BIT
7
NAME
6
5
4
3
RPM_En[3:0]
2
1
0
Generic_Tol_RPM
DEFAULT
02HEX
BIT
DESCRIPTION
7-4
Close loop (RPM) or Open loop (Fan Duty) Smart Fan control mode selection
RPM_En[3] = 1 => Configure FANCTL4 as Close Loop mode, otherwise, it is open loop
mode.
RPM_En[2] = 1 => Configure FANCTL3 as Close Loop mode, otherwise, it is open loop
mode.
RPM_En[1] = 1 => Configure FANCTL2 as Close Loop mode, otherwise, it is open loop
mode.
RPM_En[0] = 1 => Configure FANCTL1 as Close Loop mode, otherwise, it is open loop
mode.
3-0
RPM tracking target tolerance. It could suppress the oscillation phenomenon in target
RPM lock period.
Generic_Tol_RPM: Tolerance of RPM mode, unit is 50 RPMs.
If Enable RHSF - Bank 3 Address 0EHEX, unit is 100 RPM.
7.4.7 Temperature Source Selection (TSS)
Location:
F1TSS - Bank 3 Address 09HEX
F2TSS - Bank 3 Address 0AHEX
F3TSS - Bank 3 Address 0BHEX
F4TSS - Bank 3 Address 0CHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
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F1TSS – F4TSS
BIT
NAME
7
6
5
4
3
Reserved
2
00HEX
BIT
DESCRIPTION
7-6
Reserved
5-0
TSS: Temperature source selection
00_0000: VSEN2_HV/TEMP_CH1_HV
- Bank 0 Address 42HEX
00_0001: VSEN4_HV/TEMP_CH2_HV
- Bank 0 Address 46HEX
00_0010: VSEN6_HV/TEMP_CH3_HV
- Bank 0 Address 4AHEX
00_0011: VSEN8_HV/TEMP_CH4_HV
- Bank 0 Address 4EHEX
-Bank 0 Address 62HEX
00_0101: T_CPU1_HV
- Bank 0 Address A0HEX
00_0110: T_CPU2_HV
- Bank 0 Address A2HEX
00_0111: T_CPU3_HV
- Bank 0 Address A4HEX
00_1000: T_CPU4_HV
- Bank 0 Address A6HEX
00_1001: T_CPU5_HV
- Bank 0 Address A8HEX
00_1010: T_CPU6_HV
- Bank 0 Address AAHEX
00_1011: T_CPU7_HV
- Bank 0 Address ACHEX
00_1100: PCH_PCH_0
- Bank 0 Address F0HEX
00_1101: PCH_PCH_1
- Bank 0 Address F1HEX
00_1110: PCH_CPU_I
- Bank 0 Address F3HEX
00_1111: PCH_MCH
- Bank 0 Address F4HEX
01_0000: PCH_DIMM0
- Bank 0 Address F5HEX
01_0001: PCH_DIMM1
- Bank 0 Address F6HEX
01_0010: PCH_DIMM2
- Bank 0 Address F7HEX
01_0011: PCH_DIMM3
- Bank 0 Address F8HEX
01_0100: VRT_TEMP1_V
- Bank 0 Address B8HEX
01_0101: VRT_TEMP2_V
- Bank 0 Address B9HEX
01_0110: VRT_TEMP3_V
- Bank 0 Address BAHEX
01_0111: VRT_TEMP4_V
- Bank 0 Address BBHEX
01_1000: MT_C0_C0
- Bank 2 Address C4HEX
01_1001: MT_C1_C0
- Bank 2 Address C5HEX
01_1010: MT_C2_C0
- Bank 2 Address C6HEX
01_1011: MT_C3_C0
- Bank 2 Address C7HEX
01_1100: MT_C0_C1
- Bank 2 Address C8HEX
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TSS[5:0]
DEFAULT
00_0100: LTD_HV
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BIT
DESCRIPTION
01_1101: MT_C1_C1
- Bank 2 Address C9HEX
01_1110: MT_C2_C1
- Bank 2 Address CAHEX
01_1111: MT_C3_C1
- Bank 2 Address CBHEX
10_0000: MT_C0
- Bank 2 Address CCHEX
10_0001: MT_C1
- Bank 2 Address CDHEX
10_0010: MT_SYS
- Bank 2 Address CEHEX
10_0011: EXT_VRT_TEMP1_V
- Bank 0 Address BCHEX
10_0100: EXT_VRT_TEMP2_V
- Bank 0 Address BDHEX
10_0101: EXT_VRT_TEMP3_V
- Bank 0 Address BEHEX
10_0110: EXT_VRT_TEMP4_V
- Bank 0 Address BFHEX
10_0111 ~ 11_1111: Reserved
7.4.8 Power Accumulate Enable (PAE)
Location: PAE - Bank 3 Address 0DHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
PAE
BIT
7
NAME
6
5
4
3
Reserved
1
0
PWR_MD[3:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Reserved.
3-0
Sensor based fan control mode enabling.
PWR_MD[3] = 1 => FANCTL4 supports sensor
driven by other traditional fan control mode.
PWR_MD[2] = 1 => FANCTL3 supports sensor
driven by other traditional fan control mode.
PWR_MD[1] = 1 => FANCTL2 supports sensor
driven by other traditional fan control mode.
PWR_MD[0] = 1 => FANCTL1 supports sensor
driven by other traditional fan control mode.
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based fan control. Otherwise, it is
based fan control. Otherwise, it is
based fan control. Otherwise, it is
based fan control. Otherwise, it is
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7.4.9 Close-Loop Fan Control RPM mode for High Speed Fan Register (RHSF)
Location: RHSF - Bank 3 Address 0EHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
RHSF
BIT
7
NAME
SF_TM_U
6
5
4
3
Reserved
2
1
0
RPM_HS[3:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7
Smart FAN IV PWM values update rate.
SF_TM_U = 0 => Update rate is 10 times/sec.
SF_TM_U = 1 => Update rate is 20 times/sec.
6-4
Reserved.
3-0
Changing default unit of all RPM setting from 50 RPMs to 100 RPMs. It benefits to control
ultra-high RPM fan.
RPM_HS[3] = 1 => FANCTL4 supports ultra-high RPM fan control.
RPM_HS[2] = 1 => FANCTL3 supports ultra-high RPM fan control.
RPM_HS[1] = 1 => FANCTL2 supports ultra-high RPM fan control.
RPM_HS[0] = 1 => FANCTL1 supports ultra-high RPM fan control.
7.4.10 PROCHOT Fan Select (PFS)
Location: PFS - Bank 3 Address 0FHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
PFS
BIT
7
NAME
6
5
4
3
Reserved
2
1
0
PHOT_FAN_SEL[3:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Reserved.
3-0
Select targeted FANCTL to react to specific thermal alert event.
PHOT_FAN_SEL[3] = 1 => FANCTL4 will respond to specific thermal alert event.
PHOT_FAN_SEL[2] = 1 => FANCTL3 will respond to specific thermal alert event.
PHOT_FAN_SEL[1] = 1 => FANCTL2 will respond to specific thermal alert event.
PHOT_FAN_SEL[0] = 1 => FANCTL1 will respond to specific thermal alert event.
These settings are available only while asserting PH_CTRL0 defined in Bank 0 Address
23HEX
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7.4.11 Fan Output Value (FOV)
Location:
F1OV - Bank 3 Address 10HEX
F2OV - Bank 3 Address 11HEX
F3OV - Bank 3 Address 12HEX
F4OV - Bank 3 Address 13HEX
Type:
Read / Write (in Manual Mode)
Read Only (in the Smart Fan mode)
Reset:
Power On Reset
RESETIN# with LOCK=0
F1OV – F4OV
BIT
7
6
5
4
3
2
1
0
NAME
Output Value
DEFAULT
Depend on DefaultSpeed. 7FHEX.
BIT
DESCRIPTION
7-0
Output Value involves two meaning. The one is current out fan duty in Smart Fan
mode, the other is fixed fan output duty cycle in manual mode.
If 3VDD is loss, these registers are set back to zero by hardware.
7.4.12 Fan Output PWM Frequency Prescalar (FOPFP)
Location:
F1OPFP - Bank 3 Address 14HEX
F2OPFP - Bank 3 Address 15HEX
F3OPFP - Bank 3 Address 16HEX
F4OPFP - Bank 3 Address 17HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
F1OPFP – F4OPFP
BIT
7
NAME
CKSEL
DEFAULT
1
6
5
4
1
0
0
0
0
0
1
0
0
DESCRIPTION
CKSEL – Clock source select.
CLKSEL
0
1
6-0
2
Divisor
BIT
7
3
14.318MHz
1.024KHz
55.93Kz
CLKIN Frequency
33MHz
1.024KHz
130.21KHz
48MHz
1KHz
125KHz
Divisor – Clock frequency Divisor.
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The clock source selected by CKSEL will be divided by the divisor and used as a fan PWM output
frequency. There are 2 divisors depending on CKSEL.
If CKSEL equals 1, then the output clock is simply equal to 130.21/ (Divisor+1) KHz (@ frequency of
CLKIN is 33MHz).
If CKSEL equals 0, the output clock is 1KHz/MappedDivisor. MappedDivisor depends on Divisor[3:0]
and is described in the table below.
Divisor[3:0]
Mapped
Divisor
Output
Frequency
Divisor[3:0]
Mapped
Divisor
Output
Frequency
0000
1
1024Hz
1000
12
85Hz
0001
2
512Hz
1001
16
64Hz
0010
3
341Hz
1010
32
32Hz
0011
4
256Hz
1011
64
16Hz
0100
5
205Hz
1100
128
8Hz
0101
6
171Hz
1101
256
4Hz
0110
7
146Hz
1110
512
2Hz
0111
8
128Hz
1111
1024
1Hz
7.4.13
Fan Output Nonstop Enable (FONE)
Location: FONE - Bank 3 Address 18HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
FONE
BIT
7
NAME
6
5
4
3
Reserved
2
1
0
NON_STOP_En[3:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Reserved.
3-0
Enabling the feature that fan could be stopped with special condition. This feature also
requires other setting, including Bank 3 Address 2CHEX , 2DHEX , 2EHEX and 2FHEX in
FONV (Fan Output Nonstop Value)
NON_STOP_En[3] = 1 => Enable FANCTL4 stop function.
NON_STOP_En[2] = 1 => Enable FANCTL3 stop function.
NON_STOP_En[1] = 1 => Enable FANCTL2 stop function.
NON_STOP_En[0] = 1 => Enable FANCTL1 stop function.
7.4.14 Fan Tachometer Source Selection (FTSS)
Location: FTSS - Bank 3 Address 1BHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
FTSS
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BIT
7
NAME
6
5
4
3
FAN2_SEL
2
1
0
FAN1_SEL
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
F2FTSS: Fan2 Tachometers Source Selection
3-0
F1FTSS: Fan1 Tachometers Source Selection
0000: Source Select FANIN_1
0001: Source Select FANIN_2
0010: Source Select FANIN_3
0011: Source Select FANIN_4
0100: Source Select FANIN_5
0101: Source Select FANIN_6
0110: Source Select FANIN_7
0111: Source Select FANIN_8
1000: Source Select FANIN_9
1001: Source Select FANIN_10
1010: Source Select FANIN_11
1011: Source Select FANIN_12
7.4.15 Fan Tachometer Source Selection (FTSS)
Location: FTSS - Bank 3 Address 1CHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
FTSS
BIT
7
NAME
6
5
4
3
FAN4_SEL
1
0
FAN3_SEL
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
F4FTSS: Fan4 Tachometers Source Selection
3-0
F3FTSS: Fan3 Tachometers Source Selection
0000: Source Select FANIN_1
0001: Source Select FANIN_2
0010: Source Select FANIN_3
0011: Source Select FANIN_4
0100: Source Select FANIN_5
0101: Source Select FANIN_6
0110: Source Select FANIN_7
0111: Source Select FANIN_8
1000: Source Select FANIN_9
1001: Source Select FANIN_10
1010: Source Select FANIN_11
1011: Source Select FANIN_12
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7.4.16 Critical Temperature to Full Speed all fan (CTFS)
Location:
T1CTFS - Bank 3 Address 20HEX
T2CTFS - Bank 3 Address 21HEX
T3CTFS - Bank 3 Address 22HEX
T4CTFS - Bank 3 Address 23HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
T1CTFS – T4CTFS
BIT
7
6
5
4
3
2
1
0
NAME
Critical Temperature
DEFAULT
5AHEX (90℃)
BIT
DESCRIPTION
7-0
Critical Temperature setting for each Smart Fan Table.
While temperature source exceeds the critical temperature, the relative FANCTL will
output full duty cycle.
Unit in ℃.
7.4.17 Hysteresis of Temperature (HT)
Location:
HT1 - Bank 3 Address 24HEX
HT2 - Bank 3 Address 25HEX
HT3 - Bank 3 Address 26HEX
HT4 - Bank 3 Address 27HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
HT1 – HT4
BIT
7
NAME
Reserved
DEFAULT
6-4
3
5
4
Hysteresis of Critical
Temperature
3
Reserved
5HEX (5℃)
BIT
7
6
2
1
0
Hysteresis of Operation
Temperature
3HEX (3℃)
DESCRIPTION
Reserved
Hysteresis of Critical Temperature:
Hysteresis for critical temperature on Smart Fan Table 1 ~ 4. The range is 0℃~7℃
Reserved
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BIT
DESCRIPTION
2-0
Hysteresis of Operation Temperature:
Hysteresis for normal temperature on Smart Fan Table 1 ~ 4. The range is 0℃~7℃
7.4.18 Fan Output Nonstop Value(FONV)
Location:
FONV1 - Bank 3 Address 2CHEX
FONV2 - Bank 3 Address 2DHEX
FONV3 - Bank 3 Address 2EHEX
FONV4 - Bank 3 Address 2FHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
FONV1 –FONV4
BIT
7
6
5
4
3
2
1
0
NAME
Fan Output Nonstop Value
DEFAULT
14HEX
BIT
DESCRIPTION
7-0
Fan Output Nonstop Value for each FANCTL output.
If enable FONE - Bank 3 Address 18HEX, the relative FANCTL will output FONV duty
cycle.
7.4.19
SMART FANTM IV Temperature and DC/PWM Table (SFIV)
Location:
Relative Register-at SMART FAN
RELATIVE
TEMPERAUTRE
Temp1
Temp2
Temp3
Temp4
Type:
Reset:
TM
IV Control Mode Table
NNEMONIC
ADD (Hex)
TYPE
T1 – T4
30-33
RW
PWM1 – PWM4
34-37
RW
T1 – T4
38-3B
RW
PWM1 – PWM4
3C-3F
RW
T1 – T4
40-43
RW
PWM1 – PWM4
44-47
RW
T1 – T4
48-4B
RW
DC/PWM1 – DC/PWM4
4C-4F
RW
Read / Write
Power On Reset
RESETIN# with LOCK=0
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T1 – T4
BIT
7
6
5
NAME
4
SMART FAN
3
TM
2
1
0
2
1
0
2
1
0
IV Temperature
Table T1 = 19HEX (25℃)
DEFAULT
Table T2 = 23HEX (35℃)
Table T3 = 2DHEX (45℃)
Table T4 = 37HEX (55℃)
DC/PWM1 – DC/PWM4
BIT
7
6
5
NAME
4
3
SMART FAN
TM
IV DC/PWM
Table P1 = 8CHEX (140 Duty)
DEFAULT
Table P2 = AAHEX (170 Duty)
Table P3 = C8HEX (200 Duty)
Table P4 = E6HEX (230 Duty)
7.4.20
Configure Register of PECI Error (CRPE)
Location: CRPE - Bank 3 Address 50HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
CRPE
BIT
NAME
7
6
5
PECI_ERR_FAN4
BIT[1-0]
4
3
PECI_ERR_FAN3
BIT[1-0]
PECI_ERR_FAN2
BIT[1-0]
PECI_ERR_FAN1
BIT[1-0]
Refer to PECI Error Condition Table for fan output value.
DEFAULT
00HEX
BIT
DESCRIPTION
7-6
FANCTL4 output state selection while PECI served as temperature source happens any
abnormal condition.
5-4
FANCTL3 output state selection while PECI served as temperature source happens any
abnormal condition.
3-2
FANCTL2 output state selection while PECI served as temperature source happens any
abnormal condition.
1-0
FANCTL1 output state selection while PECI served as temperature source happens any
abnormal condition.
PECI Error Condition Table:
BIT [1-0]
00BIN
01BIN
1xBIN
PECI Error Condition
Fan output value keeps at its current value.
Fan output value will be set to FOMV (Fan Output Min Value when PECI
Error).
Fan output value will be set to the full speed value (FFh).
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7.4.21 Fan Output Min Value when PECI Error (FOMV)
Location: FOMV - Bank 3 Address 51HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
FOMV
BIT
7
6
5
4
3
2
1
0
NAME
FanMin
DEFAULT
80HEX
BIT
DESCRIPTION
7-0
FanMin: control the FANCTL1-FANCTL4 fan output min value when PECI error
condition is occurred. Also see CRPE (Configure Register of PECI Error)
7.4.22
Mask Register of PECI Error (MRPE)
Location: MRPE - Bank 3 Address 52HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
MRPE
BIT
7
NAME
6
5
4
3
Reserved
2
1
0
PECI_ERR_MSK[3:0]
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Reserved.
3-0
PECI_ERR_MSK[3:0]: Mask CRPE setting for FANCTL1-FANCTL4. It means that Fan
output value keeps at its current value.
7.4.23
PECI T_DTS Slope Value (PTSV)
Location:
P1TSV - Bank 3 Address 64HEX
P2TSV - Bank 3 Address 65HEX
P3TSV - Bank 3 Address 66HEX
P4TSV - Bank 3 Address 67HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
P1TSV – P4TSV
BIT
7
NAME
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6
5
4
3
2
1
0
PECI T_DTS_Slope
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DEFAULT
00HEX
BIT
DESCRIPTION
7-0
This setting is used to define slope of specific CPU’s DTS Thermal Profile. DTS
Thermal profile need to be configured before enabling sensor based fan control
algorithm.
PECI T_DTS_Slope:
Slope[7]=0.5
Slope[3]=0.03125
Slope[6]=0.25
Slope[2]=0.015625
Slope[5]=0.125
Slope[1]=0.0078125
Slope[4]=0.0625
Slope[0]=0.00390625
Example:
PECI T_DTS_Slope[7:0]=8’h46, mean slope=0.273
7.4.24 PECI T_DTS Offset Value (PTOV)
Location:
P1TOV - Bank 3 Address 68HEX
P2TOV - Bank 3 Address 69HEX
P3TOV - Bank 3 Address 6AHEX
P4TOV - Bank 3 Address 6BHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
P1TOV – P4TOV
BIT
7
6
5
4
3
2
1
0
NAME
PECI T_DTS Offset
DEFAULT
00HEX
BIT
DESCRIPTION
7-0
This setting is used to define initial offset temperature of specific CPU’s DTS Thermal
Profile. DTS Thermal profile need to be configured before enabling sensor based fan
control algorithm.
7.4.25 Tcontrol_Offset Value for CPU Agent (Address : 30h ~ 33h) (TOV)
Location:
TOV1 - Bank 3 Address 70HEX
TOV2 - Bank 3 Address 71HEX
TOV3 - Bank 3 Address 72HEX
TOV4 - Bank 3 Address 73HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
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TOV1 – TOV4
BIT
7
6
5
4
3
2
1
0
NAME
Tcontrol_Offset
DEFAULT
00HEX
BIT
DESCRIPTION
7-0
Tcontrol_Offset value is required to adjust the Tcontrol_spec desined in DTS(Sensor)
Based Thermal Spec.
Tcontrol_Offset: Unit in ℃ and 2’s complement representation.
7.4.26 DTS Delta Tolerance Value (DDTV)
Location:
DDTV1 - Bank 3 Address 80HEX
DDTV2 - Bank 3 Address 81HEX
DDTV3 - Bank 3 Address 82HEX
DDTV4 - Bank 3 Address 83HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
DDTV1 – DDTV4
BIT
7
6
5
4
3
NAME
DTS Delta Tolerance Value
DEFAULT
00HEX
BIT
DESCRIPTION
7-0
2
1
0
This setting is used to define Tolerance of DTS (Sensor) Based Fan Control.
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7.4.27 DTS Margin Divisor (DMD)
Location: DMD - Bank 3 Address 84HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
DMD
BIT
7
NAME
6
5
4
3
DTS_M_DIV[3:0]
1
0
Reserved
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Enabling the DTS Margin Divisor.
DTS_M_DIV [3] = 1 => Enable FANCTL4 Margin/2.
DTS_M_DIV [2] = 1 => Enable FANCTL3 Margin/2.
DTS_M_DIV [1] = 1 => Enable FANCTL2 Margin/2.
DTS_M_DIV [0] = 1 => Enable FANCTL1 Margin/2.
3-0
Reserved.
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7.5
Bank 4 REGISTER DETAIL
7.5.1 Temperature to Fan Mapping Relationships (TFMR)
Location:
T5FMR - Bank 4 Address 00HEX
T6FMR - Bank 4 Address 01HEX
T7FMR - Bank 4 Address 02HEX
T8FMR - Bank 4 Address 03HEX
T9FMR - Bank 4 Address 04HEX
T10FMR - Bank 4 Address 05HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
T5FMR – T10FMR
BIT
7
6
NAME
5
4
Reserved
3
2
1
0
F4SF
F3SF
F2SF
F1SF
DEFAULT
00HEX
BIT
DESCRIPTION
7-4
Reserved
3-0
F4SF – F1SF setting involves two purposes. The one is building up the relation between
temperature source 5~10 and FANCTL1~4, the other is Fan Control mode assignment.
0 = Related FANCTL will operate in manual mode and have no relationship with
temperature (Default)
1 = Related FANCTL will operate with SmartFan control mode and be linked to relative
temperature source 5 ~ 10.
7.5.2 Temperature Source Selection (TSS)
Location:
TSS5 - Bank 4 Address 08HEX
TSS6 - Bank 4 Address 09HEX
TSS7 - Bank 4 Address 0AHEX
TSS8 - Bank 4 Address 0BHEX
TSS9 - Bank 4 Address 0CHEX
TSS10 - Bank 4 Address 0DHEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
F5TSS – F10TSS
BIT
NAME
7
6
5
4
3
Reserved
DEFAULT
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2
1
0
TSS[5:0]
00HEX
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BIT
DESCRIPTION
7-6
Reserved.
5-0
TSS: Temperature source selection
00_0000: VSEN2_HV/TEMP_CH1_HV
- Bank 0 Address 42HEX
00_0001: VSEN4_HV/TEMP_CH2_HV
- Bank 0 Address 46HEX
00_0010: VSEN6_HV/TEMP_CH3_HV
- Bank 0 Address 4AHEX
00_0011: VSEN8_HV/TEMP_CH4_HV
- Bank 0 Address 4EHEX
00_0100: LTD_HV
-Bank 0 Address 62HEX
00_0101: T_CPU1_HV
- Bank 0 Address A0HEX
00_0110: T_CPU2_HV
- Bank 0 Address A2HEX
00_0111: T_CPU3_HV
- Bank 0 Address A4HEX
00_1000: T_CPU4_HV
- Bank 0 Address A6HEX
00_1001: T_CPU5_HV
- Bank 0 Address A8HEX
00_1010: T_CPU6_HV
- Bank 0 Address AAHEX
00_1011: T_CPU7_HV
- Bank 0 Address ACHEX
00_1100: PCH_PCH_0
- Bank 0 Address F0HEX
00_1101: PCH_PCH_1
- Bank 0 Address F1HEX
00_1110: PCH_CPU_I
- Bank 0 Address F3HEX
00_1111: PCH_MCH
- Bank 0 Address F4HEX
01_0000: PCH_DIMM0
- Bank 0 Address F5HEX
01_0001: PCH_DIMM1
- Bank 0 Address F6HEX
01_0010: PCH_DIMM2
- Bank 0 Address F7HEX
01_0011: PCH_DIMM3
- Bank 0 Address F8HEX
01_0100: VRT_TEMP1_V
- Bank 0 Address B8HEX
01_0101: VRT_TEMP2_V
- Bank 0 Address B9HEX
01_0110: VRT_TEMP3_V
- Bank 0 Address BAHEX
01_0111: VRT_TEMP4_V
- Bank 0 Address BBHEX
01_1000: MT_C0_C0
- Bank 2 Address C4HEX
01_1001: MT_C1_C0
- Bank 2 Address C5HEX
01_1010: MT_C2_C0
- Bank 2 Address C6HEX
01_1011: MT_C3_C0
- Bank 2 Address C7HEX
01_1100: MT_C0_C1
- Bank 2 Address C8HEX
01_1101: MT_C1_C1
- Bank 2 Address C9HEX
01_1110: MT_C2_C1
- Bank 2 Address CAHEX
01_1111: MT_C3_C1
- Bank 2 Address CBHEX
10_0000: MT_C0
- Bank 2 Address CCHEX
10_0001: MT_C1
- Bank 2 Address CDHEX
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BIT
DESCRIPTION
10_0010: MT_SYS
- Bank 2 Address CEHEX
10_0011: EXT_VRT_TEMP1_V
- Bank 0 Address BCHEX
10_0100: EXT_VRT_TEMP2_V
- Bank 0 Address BDHEX
10_0101: EXT_VRT_TEMP3_V
- Bank 0 Address BEHEX
10_0110: EXT_VRT_TEMP4_V
- Bank 0 Address BFHEX
10_0111 ~ 11_1111: Reserved
7.5.3 Critical Temperature to Full Speed all fan (CTFS)
Location:
T5CTFS - Bank 4 Address 10HEX
T6CTFS - Bank 4 Address 11HEX
T7CTFS - Bank 4 Address 12HEX
T8CTFS - Bank 4 Address 13HEX
T9CTFS - Bank 4 Address 14HEX
T10CTFS - Bank 4 Address 15HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
T5CTFS – T10CTFS
BIT
7
6
5
4
3
2
1
0
NAME
Critical Temperature
DEFAULT
5AHEX (90℃)
BIT
DESCRIPTION
7-0
Critical Temperature setting for each Smart Fan Table 5 ~ 10.
While temperature source exceeds the critical temperature, the relative FANCTL will
output full duty cycle.
Unit in ℃.
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7.5.4 Hysteresis of Temperature (HT)
Location:
HT5 - Bank 4 Address 20HEX
HT6 - Bank 4 Address 21HEX
HT7 - Bank 4 Address 22HEX
HT8 - Bank 4 Address 23HEX
HT9 - Bank 4 Address 24HEX
HT10 - Bank 4 Address 25HEX
Type:
Read / Write
Reset:
Power On Reset
RESETIN# with LOCK=0
HT5 – HT10
BIT
7
NAME
Reserved
DEFAULT
6
5
Hysteresis of Critical
Temperature
6-4
3
2-0
3
2
Reserved
1
0
Hysteresis of Operation
Temperature
5HEX (5℃)
BIT
7
4
3HEX (3℃)
DESCRIPTION
Reserved
Hysteresis of Critical Temperature:
Hysteresis for critical temperature on Smart Fan Table 5 ~ 10. The range is 0℃~7℃
Reserved
Hysteresis of Operation Temperature:
Hysteresis for normal temperature on Smart Fan Table 5 ~ 10. The range is 0℃~7℃
7.5.5 SMART FANTM IV Temperature and DC/PWM Table (SFIV)
Location:
Relative Register-at SMART FAN
Temp6
Temp7
Temp8
Temp9
Nuvoton Confidential
IV Control Mode Table
ADD
(Hex)
TYPE
T1 – T4
30-33
RW
PWM1 – PWM4
34-37
RW
T1 – T4
38-3B
RW
PWM1 – PWM4
3C-3F
RW
T1 – T4
40-43
RW
PWM1 – PWM4
44-47
RW
T1 – T4
48-4B
RW
DC/PWM1 – DC/PWM4
4C-4F
RW
T1 – T4
50-53
RW
DC/PWM1 – DC/PWM4
54-57
RW
RELATIVE
TEMPERAUTRE
Temp5
TM
NNEMONIC
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NCT7904D
ADD
(Hex)
TYPE
T1 – T4
58-5B
RW
DC/PWM1 – DC/PWM4
5C-5F
RW
RELATIVE
TEMPERAUTRE
Temp10
Type:
Reset:
NNEMONIC
Read / Write
Power On Reset
RESETIN# with LOCK=0
T1 – T4
BIT
7
6
5
NAME
4
SMART FAN
DEFAULT
3
TM
2
1
0
2
1
0
IV Temperature
Table T1 = 19HEX (25℃)
Table T2 = 23HEX (35℃)
Table T3 = 2DHEX (45℃)
Table T4 = 37HEX (55℃)
DC/PWM1 – DC/PWM4
BIT
7
NAME
DEFAULT
6
5
4
SMART FAN
3
TM
IV DC/PWM
Table P1 = 8CHEX (140 Duty)
Table P2 = AAHEX (170 Duty)
Table P3 = C8HEX (200 Duty)
Table P4 = E6HEX (230 Duty)
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8. ELECTRICAL CHARACTERISTICS
8.1
Absolute Maximum Ratings
PARAMETER
Power Supply Voltage
RATING
UNIT
3VSB,3VDD,VBAT
3.3 ± 5%
V
VTT
2.048
Input Voltage
-0.3 to +3.6
Operating Temperature
-40 to +120
Storage Temperature
V
*1
°C
°C
-55 to +150
*1 Guaranteed by design from -40~120 degree C, 100% tested at 85 degree C.
8.2
DC Specification
(Ta = 0° C to 70° C, 3VDD = 3.3V ± 5%, 3VSB =3.3V ± 5%, GND = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
OD – Open-drain output pin with source-sink capability of 12 mA
Output Low Voltage
VOL
0.4
TSI – For AMD
TM
V
IOL = 12 mA
TSI design
Input Low Voltage
VIL
0.6
V
Input High Voltage
VIH
1
V
Output Low Voltage
VOL
0.285
TM
PECI – Bi-direction pin for INTEL
V
PECI
Input Low Voltage
VIL
0.275Vtt
0.5Vtt
V
Input High Voltage
VIH
0.55Vtt
0.725Vtt
V
Output Low Voltage
VOL
0.25Vtt
V
Output High Voltage
VOH
0.75Vtt
V
GTL –For PROCHOT,THERMTRIP
Input Low Voltage
VIL
Input High Voltage
VIH
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0.4
0.8
V
V
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PARAMETER
SYM.
Output Low Voltage
VOL
I-
Input Low Voltage
VIL
Input High Voltage
VIH
Input High Leakage
ILIH
Input Low Leakage
ILIL
MIN.
TYP.
MAX.
UNIT
0.2
V
CONDITIONS
TTL level Schmitt-triggered input pin
0.8
V
3VSB = 3.3V
V
3VSB = 3.3V
+10
µA
VIN=3.3V
-10
µA
VIN=0V
2.0
AIN -
Analog input pin
Input High Leakage
ILIH
+1
µA
VIN=3.3V
Input Low Leakage
ILIL
-1
µA
VIN=0V
AIN – VSEN17 , VSEN18 , VSEN19
Input High Leakage
ILIH
+36
µA
VIN=3.3V
Input Low Leakage
ILIL
-10
µA
VIN=0V
8.3
AC Specification
SMBus Interface
t
SCL
tR
t
R
SCL
t HD;SDA
t SU;STO
t SU;DAT
VALID DATA
SDA IN
t
HD;DAT
SDA OUT
Serial Bus Timing Diagram
PARAMETER
SYMBOL
-
MIN.
MAX.
UNIT
SCL clock period
t SCL
10
uS
Start condition hold time
tHD;SDA
4.0
uS
Stop condition setup-up time
tSU;STO
4.0
uS
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DATA to SCL setup time
tSU;DAT
150
nS
DATA to SCL hold time
tHD;DAT
270
nS
SCL and SDA rise time
tR
1.0
uS
SCL and SDA fall time
tF
300
nS
Clock Input Timing
DESCRIPTION
CLKIN
MIN
TYP
MAX
Clock cycle time
(1/CLKIN)
x0.97
1/CLKIN
(1/CLKIN)
x1.03
Duty cycle
45%
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9. ORDER INFORMATION
PART NO.
PACKAGE
NCT7904D
48 LQFP (Halogen free)
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10. TOP MARKING SPECIFICATIONS
NCT7904D
28201234-01
138GBBA
1st line: Nuvoton logo
2nd line: part number: NCT7904D
3rd line: wafer production series lot number: 28201234-01
4th line: tracking code: 138GBBA
138: packages made in '11, week 38
G: assembly house ID
B: Chip Version
BA: Nuvoton internal use
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11. PACKAGE DRAWING AND DIMENSIONS
48-pin LQFP (7 mm X7 mm X1.4mm)
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12. REVISION HISTORY
VERSION
DATE
0.2
08/17/2010
0.3
10/12/2010
ALL
Fixed the typos.
0.4
02/25/2011
ALL
Updated for new A2 version sample.
0.8
05/04/2011
ALL
Updated Top Marketing & Part No.
0.9
08/08/2011
ALL
Update for new A3 version sample.
0.91
09/21/2011
The content is the same as v0.9.
Just update the version to v0.91 for new A4
version sample.
0.95
11/15/2011
29, 31, 32, 39,
40, 43, 114,
127, 134
1. Update PCH thermal data description
(section 6.11.2)
2. Update Device ID information
3. Update LOCK description
4. Update Bank0 Addr[2Eh] Mode Control
Register description.
5. Change Temperature Source Selection
Table configuration of 00_1100 : from Bank0
Address AEh to F0h
6. Update Order Information
(Item 1, 2, 5 are updated for rev.B chip)
1.0
1/5/2012
ALL
Public Released.
All versions before 1.0 are preliminary versions
1.1
5/31/2012
11,93
1. Fixed the typo.
2. Added External Read Control Register
description.
1.2
7/20/2012
114
1.3
2/4/2013
87,88
1.41
4/11/2013
10,14,15,18,12
9
1.42
4/29/2013
27,128
1.Added power ramp request on EEPROM
self-initialization function.
2.Modified Absolute Maximum Ratings.
1.43
6/24/2013
13,16
Added recommendations for unused pin.
1.44
2/10/2014
80
Updated description of PECI Power Averaging
Configure Register Bit[5].
1.45
07/25/2017
10
Update the operating temperature range
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PAGE
DESCRIPTION
Preliminary Released.
1.Updated Fan Output
Pre-scalar register.
PWM
Frequency
1. Fixed typo.
2. Updated TSI register descriptions.
1.Modified descriptions for VSEN17,18,19.
2.Fixed typo of VSEN17,18,19 formula.
3.Added DC specification for VSEN17,18,19.
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Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
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