AS3712-BQFP-00

austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: ams_sales@ams.com Please visit our website at www.ams.com D ata sh eet A S3 7 1 2 Tri p le B u c k H ig h Cu rr e n t P M IC w i th o u t C h a r g e r HV Backlight Driver 3x step up with external transistor
- e.g. 0.5-1A@5V; 40mA@50V Voltage control mode and over-voltage protection The device offers advanced power management functions. All necessary ICs and peripherals in a battery powered mobile device are supplied by the AS3712. It features 3 DCDC buck converters as well as 8 low noise LDOs. The different regulated supply voltages are programmable via the serial control interface. 4MHz operation with 1uH coils are reducing cost and PCB space.
3 programmable current sinks (max. 40mA)
Possible external PWM dimming input (DLS, CABC) The single supply voltage may vary from 2.7V to 5.5V. 2 Key Features Voltage Generation
Automatic battery monitoring with interrupt generation and selectable warning level
Automatic temperature monitoring with interrupt generation and selectable warning and shutdown levels am lc s on A te G nt st il The three step-up converter generate voltages for e.g.the backlight, classD amplifier, USB host support or LCD display supply. Both constant voltage (for e.g. OLED supply) as well as constant current (white LED backlight) operations with three current sinks are possible. An internal voltage protection is limiting the output voltage in the case of external component failures. Supervisor al id
The AS3712 is a compact System PMU with integrated battery charger and back light driver. lv 1 General Description
3 DCDC step down regulators (2-4MHz)
- DVM (0.6V-3.3V;1x 1.2-1.5A, 2x 0.7-1A) - 60µA quiescent current - 2A with combined DCDC 2 & 3 2 analog low noise LDOs, 6 digital LDOs
- 2x 1.2-3-3V, 6x 0.9-3.3V; 150-300mA - 30µA quiescent current (low power mode) 1 ultra low power always on LDO 2.5V, 10mA
Real Time Clock
Ultra low power 32kHz oscillator
Sec and minute counter, auto wake-up
Programmable alarm
Repeating alarm (seconds, minutes, 2 minutes, or 8 minutes)
32kHz clock output to peripheral
3.0V, VCP=5.2V, Iout300mA 30 mV 1.2 18 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Table 7. Digital LDO (LDO3, LDO4, LDO5, LDO6, LDO7, LDO8) Characteristics VLDOx_IN=3.7V; ILOAD=150mA; Tamb=25ºC; CLOAD =1µF (Ceramic); unless otherwise specified Symbol Parameter Note Min Typ Max Unit ILIMIT_LDO3-8_L low current limit ldoX_ilimit = 0 300 mA ILIMIT_LDO3-8_H high current limit ldoX_ilimit = 1 500 mA Te ch ni ca am lc s on A te G nt st il lv al id 1.Guaranteed by design and verified by laboratory evaluation and characterization; not production tested www.austriamicrosystems.com 1.2 19 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 8.4 Low power LDO V2_5 Regulators 8.4.1 General Description 8.4.2 Parameter al id The low power LDO V2_5 is needed to supply the chip core (analog and digital) of the device. It is designed to get the lowest possible power consumption, and still offering reasonable regulation characteristics. The regulator has two supply inputs selecting automatically the higher one. This gives the possibility to supply the chip core either with the battery or with the charger depending on the conditions. Bulk switch comparators are used to avoid any parasitic current flow. To ensure high PSRR and stability, a low-ESR ceramic capacitor of min. 1µF must be connected to the output. Table 8. Low power LDO (V2_5) Characteristics,VBAT=3.7V; ILOAD_ext=0; Tamb=25ºC; CLOAD =1 µF (Ceramic); unless otherwise specified Parameter VBAT Note 2.7 Supply voltage rage VUSB On resistance IOFF Shut down current IVDD Supply current 4.2 Guaranteed per design Typ Max 5.5 5.5 tstart Guaranteed per design, consider chip internal load for measurements. Startup time Vout 2.4 V 100 nA 3 µA 200 µs 2.5 2.6 V Te ch ni ca Output voltage Unit Ω 50 am lc s on A te G nt st il RON Min lv Symbol www.austriamicrosystems.com 1.2 20 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 8.5 DCDC Step-Up Converter 8.5.1 General Description
5V, 0.5-1A @ 1Mhz
25V, 50mA @ 1MHz
40V, 20mA @ 500kHz A constant switching frequency results in a low noise on supply and output voltage. Te ch ni ca am lc s on A te G nt st il lv Figure 14. DC/DC step-up Converter 1 & 3 al id The DC/DC Step Up converter is a high efficiency current mode PWM regulator, which provides an output voltage dependent on the maximum VDS voltage of the external transistor, and maximum load current selectable by the external shunt resistor. For Example: www.austriamicrosystems.com 1.2 21 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Feedback selection SU1, SU3 ca 8.5.2 am lc s on A te G nt st il lv al id Figure 15. DC/DC step-up Converter 2 For step up SU1, the feedback is always FB_SU1. 8.5.3 ni For step up SU3, the feedback is always FB_SU3. Feedback Selection SU2 ch For step up SU2 following feedback selections are possible (selected by setpup2_fb): (see Figure 15) Current Feedback CURR1, CURR2 or CURR3 can be selected by stepup2_fb as a current feedback pin. Te The step-up converter is regulated such that the required current at the feedback path can be supported. stepup2_fbprot selects the overvoltage protection feedback pin (FB2_SU2, GPIO2, GPIO3 or GPIO4). In this mode the output voltage will be limited by limiting the voltage on the selected feedback pin to 1.25V (select the external resistor network and stepup2_v to adjust this limitation voltage). stepup2_prot_dis has to be set to 0, otherwise the protection is disabled. Always choose the path with the higher voltage drop as feedback to guarantee adequate supply for the other, unregulated path. Current Feedback with Automatic Feedback Selection Same as above, but when currX_ctrl = 10b for the used current sinks, the chip automatically selects the highest string (CURR1, CURR2 or CURR3) as feedback input. www.austriamicrosystems.com 1.2 22 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Voltage Feedback stepup2_fb = 00b. FB2_SU2, GPIO2, GPIO3 or GPIO4 can be selected by stepup2_fbprot as a voltage feedback input. The step-up converter output voltage is regulated by regulating the selected feedback pin voltage to 1.25V. Calculating Resistors for Voltage Feedback or Over-Voltage Protection Bit stepupX_res should be set to 1 in voltage feedback mode using two resistors. al id The output voltage is regulated to a constant value, given by: R1 + R2 V SU = ------------------- × 1, 25 + I FB × R 1 R2 am lc s on A te G nt st il V SU = 1, 25 + I FB × R 1 lv If R2 is not used, the output voltage is: VSU: Step up regulator output voltage R1 Feedback resistor R1 R2 Feedback resistor R2 IFB: Tuning current on DCDC_FB pin: stepupX_v (0..31µA (1µA steps)) Example: Table 9. Step Up Output Voltage (Voltage mode or protection voltage) VSU VSU µA R1=1M Ω,R2 not used R1=500k Ω,R2=64k Ω - 11 - 11.5 - 12 - 12.5 - 13 6.25 13.5 7.25 14 8.25 14.5 8 9.25 15 9 10.25 15.5 10 11.25 16 11 12.25 16.5 12 13.25 17 13 14.25 17.5 14 15.25 18 15 16.25 18.5 0 1 2 3 4 5 6 Te ch ni 7 ca IFB (stepupX_v) Note: The voltage on pin CURR1, CURR2 and CURR3 must never exceed 30V. www.austriamicrosystems.com 1.2 23 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 8.5.4 Output disconnect As the output voltage is always on, an additional output transistor can be added to reduce shutdown current through R1, R2 and the connected output circuit. Note: A similar circuit can be used for step up converter 2. 8.5.5 am lc s on A te G nt st il lv al id Figure 16. StepUp 1 with regulated output voltage (15V), and switch off function of output voltage, to reduce shutdown current StepUp1 Load Detection and Over-current Protection Circuit This circuit protects the DCDC step up1 converter during short circuit and startup, by regulation of the output current. An additional feature is the detection of a minimum output load of the Step-up converter. It is also possible to use this circuit without the DCDC step up converter, by using the sense resistor only: Detection circuit: If the voltage on Rsense exceeds VDETECT for more than 1ms, or the DCDC Step up converter is not in pulse-skip for more than 1ms, the stepup1_det bit will be set.
Over-current protection: If the Over-current voltage VOVCURRENT has been exceeded by more than 5ms the bit stpup1_oc will be set and can only reset, by switching off and on the Protection circuit by writing stpup1_shortprot 0 – 1. If stpup1_oc is set the load will be disconnected, if stpup1_oc_timeout=1 Te ch ni ca
www.austriamicrosystems.com 1.2 24 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s 8.5.6 Parameter am lc s on A te G nt st il lv al id Figure 17. StepUp 1 Load Detection and Over-current Protection Application Circuit Table 10. DC/DC Step-up Controller Parameters Symbol Parameter Note IVDD Quiescent Current Pulse skipping mode VFB1 Feedback voltage for external resistor divider: for constant voltage control VFB2 Feedback voltage for current sink regulation CURR1, CURR2 or CURR3 Additional tuning current at FB_SUx adjustable by software in 1µA steps 0 31 µA Accuracy of feedback current @ full scale -7 7 % ca IDCDC_FB Current limit voltage at Rsense E.g.: 0.65A for 0.15Ω sense resistor RSW switch resistance ON-resistance of external switching transistor Iload Load current at 25V output voltage Switching frequency internal CLK frequency/4, default 1MHz ch fIN ni Vrsense_max Minimum on time MDC Maximum duty cycle Te tMIN_ON Min Typ Max 140 1.20 1.25 1.30 0.6 100 0 @ 1MHz Unit µA V V mV 1 Ω 50 mA fclk_int/4 MHz 130 ns 91 % Table 11. StepUp1 protection/detection circuit parameters Symbol Parameter Note Min Typ Max Unit VDETECT Detection Threshold For Rsense=0.150Ω => 83mA typ. 2 12.5 25 mV VOVCURRENT Over-current Threshold rising For Rsense=0.150Ω => 1.2A typ. 150 180 215 mV www.austriamicrosystems.com 1.2 25 - 85 AS3712 2V1 Datasheet - D e t a i l e d D e s c r i p t i o n - P o w e r M a n a g e m e n t F u n c t i o n s Table 11. StepUp1 protection/detection circuit parameters Parameter VOVhysteresis Over-current Hysteresis tOV_timeout Over-current timeout tdetect Detection de-bounce time Note Min Typ mV Interrupt and/or external PMOS switching off after timeout fclk_int = 2.2MHz 5 ms fclk_int = 2.2MHz 1 ms Parameter Note Cout Output capacitor ceramic, ±20% Min 2.2 Use inductors with small Cparasitic (8V Max 10 µH 4.7 µH QSU Transistor C1 / C2 Feedback capacitor ratio 1.3 1.5 Vout_max +20% VDS max drain to source voltage Unit µF am lc s on A te G nt st il Use inductors with small Cparasitic (ResVoltRise 1 :€Enter power off mode (Startup with ON key or charger insertion) RW Set Delay between I2C command, GPIO or Reset signal for power_off, standby mode or reset and execution of that command. 0 :€No delay 1 :€8 msec 2 :€16 msec 3 :€32 msec 2 - 'b0 res_timer 'b00 n/a do not use RW Set RESTime, after the last regulator has started 0 :€RESTIME = 10ms 1 :€RESTIME = 50ms 2 :€RESTIME = 100ms 3 :€RESTIME = 150ms Te ch ni ca 1:0 'b01 lv off_delay am lc s on A te G nt st il 4:3 Bit Description al id Bit www.austriamicrosystems.com 1.2 62 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w ReferenceControl Register (Address 35h). ReferenceControl Addr: 35h Bit Name Default Access 7 on_reset_delay 0 RW Sets the on reset delay time 0 :€8 sec (if onkey_reset=1) 1 :€4 sec (if onkey_reset=1) 6 reg_low_bias_mode 0 RW Sets the on reset delay time 0 :€normal operation 1 :€reduces the bias for the analog LDO1 and LDO2 RW Divide internal clock oscillator by 2 to reduce quiescent current for low power operation 0 :€Normal mode 1 :€Internal clock frequency divided by two. All timings are increased by two. Switching frequency of all DCDC converters are divided by two. Reduced transient performance of DCDC converters. standby_mode_on clk_int 3:1 0 'b000 low_power_on 0 RW Setting to 1 sets the PMU into standby mode. All regulators are disabled except those regulators enabled by register Reg standby mode. XRES will be pulled to low. A normal startup of all regulators will be done with any interrupt (has to be enabled before entering standby mode). During this startup, regulators defined by Reg standby mode register are continuously on. RW Sets the internal CLK frequency fCLK used for DCDCs, PWM, ... 0 :€4 MHz (default) 1 :€3.8 MHz 2 :€3.6 MHz 3 :€3.4 MHz 4 :€3.2 MHz 5 :€3.0 MHz 6 :€2.8 MHz 7 :€2.6 MHz All frequencies, timings and delays in this datasheet are based on 4MHz clk_int RW Enable low power mode of internal reference. 0 :€Standard mode 1 :€Low power mode - all specification except noise parameters are still valid. Iq reduced by approx. 30µA Te ch ni ca 0 am lc s on A te G nt st il 4 0 lv clk_div2 5 Bit Description al id Bit www.austriamicrosystems.com 1.2 63 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w ResetControl Register (Address 36h). ResetControl Addr: 36h Bit Name Default Access 7 onkey_reset 0 RW Bit Description 0 :€Reset after 4/8 seconds ON pressed disabled 1 :€Reset after 4/8 seconds ON pressed enabled al id Bit 2 on_input 1 power_off 0 force_reset 'b0000 RW lv reset_reason am lc s on A te G nt st il 6:3 Flags to indicate to the software the reason for the last reset .0 :€VPOR has been reached (battery or charger insertion from scratch) .1 :€ResVoltFall was reached (battery voltage drop below 2.75V) .2 :€Software forced by force_reset .3 :€Software forced by power_off and ON was pulled high .4 :€ .5 :€External triggered through the pin XRES .6 :€Reset caused by overtemperature T140 .7 :€Reset caused by watchdog .8 :€Reset caused by 4/8 seconds ON press .9 :€NA 10 :€Reset caused by RTC repeated wakeup or alarm wakeup 11 :€Reset caused by interrupt in standby mode 12 :€Reset caused by ON pulled high in standby mode Read: This flag represents the state of the ON pad directly Write: Setting to 1 resets the 4/8 sec. onkey_reset timer 0 R_PUSH 0 RW Setting to 1 starts a reset cycle, but waits after the Reg_off state for a rising edge on the pin ON or until the charger is detected. 0 RW Setting to 1 starts a complete reset cycle OvertemperatureControl Register (Address 37h). OvertemperatureControl Addr: 37h Bit Name 7:4 - 3 rst_ov_temp_140 2 ov_temp_140 'b0000 n/a do not use 0 RW If the over-temperature threshold 2 has been reached, the flag ov_temp_140 is set and a reset cycle is started. ov_temp_140 should be reset by writing 1 and afterward 0 to rst_ov_temp_140. RO Flag that the over-temperature threshold 2 (T140) has been reached this flag is not reset by a over-temperature caused reset and has to be reset by rst_ov_temp_140. 0 Bit Description ov_temp_110 0 RO Flag that the over-temperature threshold 1 (T110) has been reached temp_pmc_on 1 RO Switch on / off of temperature supervision; default: on - all other bits are only valid if set to 1. Leave at 1, do not disable Te ch 0 Access ni 1 Default ca Bit www.austriamicrosystems.com 1.2 64 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w WatchdogControl Register (Address 38h). WatchdogControl Addr: 38h Bit Name Default Access Bit Description 7:2 - 'b00 0000 n/a do not use 1 wtdg_res_on 0 RW If the watchdog expires and wtdg_res_on = 1 a reset cycle will be started 0 wtdg_on 0 RW Switches on the complete watchdog 0 :€Watchdog off 1 :€Watchdog enabled lv Reg_standby_mod1 Register (Address 39h). Reg_standby_mod1 Bit Bit Name 7 am lc s on A te G nt st il Addr: 39h al id Bit Default Access Bit Description disable_regpd 0 RW This bit disables the pulldown of all regulators 0 :€Normal operation approx. 1kΩ pulldown of all regulators 1 :€Pulldown disabled >100kΩ of all regulators 6:4 - b000 n/a do not use 3 - 0 n/a do not use 2 sd3_stby_on 0 RW Enable Step down 3 in standby mode 1 sd2_stby_on 0 RW Enable Step down 2 in standby mode 0 sd1_stby_on 0 RW Enable Step down 1 in standby mode Reg_standby_mod2 Register (Address 3ah). Reg_standby_mod2 Addr: 3ah Bit Name Default Access 7 ldo8_stby_on 0 RW Enable LDO8 in standby mode 6 ldo7_stby_on 0 RW Enable LDO7 in standby mode 5 ldo6_stby_on 0 RW Enable LDO6 in standby mode 4 ldo5_stby_on 0 RW Enable LDO5 in standby mode Bit Description ldo4_stby_on 0 RW Enable LDO4 in standby mode ldo3_stby_on 0 RW Enable LDO3 in standby mode ch 2 ni 3 ca Bit ldo2_stby_on 0 RW Enable LDO2 in standby mode 0 ldo1_stby_on 0 RW Enable LDO1 in standby mode Te 1 www.austriamicrosystems.com 1.2 65 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w curr_control Register (Address 40h). curr_control Bit Default curr3_ctrl 'b0000 Access RW Bit Description On/Off control of the pad CURR3 ...0 :€Current sink is turned off ...1 :€Current sink is active .. .2 :€Current sink is active and LED string connected to SU2. Required for automatic feedback selection. .3 :€Controlled by internal PWM generator, or external, if gpioX_iosf=4 .4 :€XINT output (active low interrupt output) .5 :€VSUP_low output .6 :€Charger active output .7 :€EOC output .8 :€Inverted signal of ON pin as output .9 :€Signal of ON pin as output 10: Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) .11 :€PWM output .12 :€PWRGOOD output 13-15 :€NA 3:2 1:0 curr2_ctrl curr1_ctrl am lc s on A te G nt st il lv 7:4 Bit Name al id Addr: 40h 'b00 'b00 RW On/Off control of the pad CURR2 0 :€Current sink is turned off 1 :€Current sink is active 2 :€Current sink is active and LED string connected to SU2. Required for automatic feedback selection. 3 :€Controlled by internal PWM generator, or external, if gpioX_iosf=4 RW On/Off control of the pad CURR1 0 :€Current sink is turned off 1 :€Current sink is active 2 :€Current sink is active and LED string connected to SU2. Required for automatic feedback selection. 3 :€Controlled by internal PWM generator, or external, if gpioX_iosf=4 pwm_control_l Register (Address 41h). pwm_control_l pwm_l_time Default 'b00000000 Access RW Bit Description This bit defines the low time of the PWM generator in 1MHz units. .0 :€pwm_div * 1µsec .1 :€pwm_div * 2µsec .2 :€pwm_div * 3µsec ... :€... 255 :€pwm_div * 256µsec Te ch 7:0 Bit Name ni Bit ca Addr: 41h www.austriamicrosystems.com 1.2 66 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w pwm_control_h Register (Address 42h). pwm_control_h 7:0 Bit Name Default pwm_h_time 'b00000000 Access RW Bit Description This bit defines the high time of the PWM generator in 1MHz units. ..0 :€pwm_div * 1µsec ..1 :€pwm_div * 2µsec ..2 :€pwm_div * 3µsec ... :€... 255 :€pwm_div * 256µsec al id Bit curr1_value Register (Address 43h). curr1_value Bit 7:0 Bit Name Default Access Bit Description am lc s on A te G nt st il Addr: 43h lv Addr: 42h curr1_current 'b00000000 RW Defines the current into CURR1, if enabled by curr1_ctrl ..0 :€Power down (default state) ..1 :€0.15mA (LSB) ... :€... 255 :€38.25mA curr2_value Register (Address 44h). curr2_value Addr: 44h Bit 7:0 Bit Name curr2_current Default 'b00000000 Access RW Bit Description Defines the current into CURR2, if enabled by curr2_ctrl ..0 :€Power down (default state) ..1 :€0.15mA (LSB) ... :€... 255 :€38.25mA curr3_value Register (Address 45h). ca curr3_value Addr: 45h curr3_current Default 'b00000000 Access RW Bit Description Defines the current into CURR3, if enabled by curr3_ctrl ..0 :€Power down (default state) ..1 :€0.15mA (LSB) ... :€... 255 :€38.25mA Te ch 7:0 Bit Name ni Bit www.austriamicrosystems.com 1.2 67 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w Watchdog_min_timer Register (Address 46h). Watchdog_min_timer Bit Bit Name Default Access 7:0 wtdg_min_timer 'b00000000 RW Bit Description Defines the minimum watchdog trigger time (LSB=7.5ms, range: 0 - 1.9s) al id Addr: 46h Watchdog_max_timer Register (Address 47h). Bit Name Default Access 7:0 wtdg_max_timer 'b11111111 RW Bit Description Defines the maximum watchdog trigger time (LSB=7.5ms, range: 7.5ms - 1.9s), do not set to (00)h am lc s on A te G nt st il Bit lv Watchdog_max_timer Addr: 47h WatchdogSoftwareSignal Register (Address 48h). WatchdogSoftwareSignal Addr: 48h Bit Bit Name 7:6 pwm_div 0 wtdg_sw_sig Default Access Bit Description This bit defines the divider ratio of the prescaler for the PWM generator. 0 :€Divide by 1 1 :€Divide by 2 2 :€Divide by 4 3 :€Divide by 16 'b00 RW 0 PUSH Trigger input by the serial interface if gpioX_iosf9 Access Bit Description Stepup_control1 Register (Address 50h). Stepup_control1 Addr: 50h stepup1_v stepup1_res ch 2 stepup1_freq Te 1 0 Default RW Defines the tuning current at FB_SU1 pin; ..0 :€0 µA ..1 :€1 µA ... :€... .31 :€31 µA 0 RW Gain selection for DCDC SU1 0 :€If FB_SU1 is used with current feedback only (Only R1,C1 connected) 1 :€If FB_SU1 is used with external resistor divider (2 resistors) 0 RW Selects SU1 frequency 0 :€1 MHz 1 :€0.5 MHz 0 RW On/Off control of SU1 0 :€SU1 off 1 :€SU1 on ca 7:3 Bit Name 'b0000 ni Bit stepup1_on www.austriamicrosystems.com 1.2 68 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w Stepup_control2 Register (Address 51h). Stepup_control2 Bit 7:3 Bit Name Default stepup2_v 'b00000 Access Bit Description RW Defines the tuning current at FB_SU2 pin ..0 :€0 µA ..1 :€1 µA ... :€... .31 :€31 µA al id Addr: 51h stepup2_res 0 RW 1 stepup2_freq 0 RW Selects SU3 frequency 0 :€1 MHz 1 :€0.5 MHz 0 stepup2_on am lc s on A te G nt st il lv 2 Gain selection for DCDC SU2 0 :€If DCDC is used with current feedback (CURR1,CURR2,CURR3) or if FB_SU2 is used with current feedback only (Only R1,C1 connected) 1 :€If FB_SU2 is used with external resistor divider (2 resistors) 0 RW On/Off control of SU2 0 :€SU2 off 1 :€SU2 on Stepup_control3 Register (Address 52h). Stepup_control3 Addr: 52h Bit 7:3 Bit Name stepup3_v Default 'b00000 Access Bit Description RW Defines the tuning current at FB_SU3 pin ..0 :€0 µA ..1 :€1 µA ... :€... .31 :€31 µA RW Gain selection for DCDC SU3 0 :€If FB_SU3 is used with current feedback only (Only R1,C1 connected) 1 :€If FB_SU3 is used with external resistor divider (2 resistors) 2 stepup3_res 1 stepup3_freq 0 RW Selects SU3 frequency 0 :€1 MHz 1 :€0.5 MHz 0 stepup3_on 0 RW On/Off control of SU3. 0 :€SU3 off 1 :€SU3 on Te ch ni ca 0 www.austriamicrosystems.com 1.2 69 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w Stepup_control4 Register (Address 53h). Stepup_control4 Addr: 53h Bit Bit Name Default Access Bit Description stpup1_det 0 RO 6 stpup1_oc 0 RO SU1 overcurrent status bit 0 :€VRsense < VOVCURRENT 1 :€VRsense > VOVCURRENT for more than 5ms (latched state) RW Controls GPIOx switch-off, after overcurrent timeout (5ms) for DCDC SU1 0 :€Disabled 1 :€Enabled 4 stpup1_shortprot 3 2 0 lv stpup1_oc_timeout am lc s on A te G nt st il 5 al id 7 SU1 detection status register 0 :€VRsense < VDETECT for more than 1ms, and DCDC SU1 converter is in pulseskip for more than 1ms. 1 :€VRsense > VDETECT for more than 1ms, or the DCDC SU1 converter is not in pulseskip for more than 1ms. stpup2_pwm_lowf stepup2_prot_dis 0 0 0 RW Enables Protection and Detection circuit for DCDC SU1 0 :€No protection and load detection 1 :€Short protection and load detection enabled RW Selects PWM operation of SU2 0 :€High frequency operation PWM>20kHz** 1 :€Low frequency PWM operation: stepup2_on and curr1…3_on (if PWM enabled) switched off during PWM low time ** Step_up switched on all the time. (current sinks are not switched off (currX_on=1 all the time), but currX_current masked to 00h during PWM low time.). During PWM off-time then feedback voltage is sampled. RW DCDC SU2 overvoltage protection to prevent damage of external NFET, if CURR1, CURR2 or CURR3 feedback selected, and no LED string connected. 0 :€Switch off DCDC SU2 if the voltage on FB_SU2 exceeds 1.25V 1 :€Overvoltage protection disabled Controls the feedback source 0 :€voltage feedback (external resistor divider) selected by stepup2_fb 'b00 RW stepup2_fbprot 1 :€CURR1 feedback enabled (feedback through white LEDs) 2 :€CURR2 feedback enabled (feedback through white LEDs) 3 :€CURR3 feedback enabled (feedback through white LEDs) Te ch ni ca 1:0 www.austriamicrosystems.com 1.2 70 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w Stepup_control5 Register (Address 54h). Stepup_control5 Addr: 54h Bit Name Default Access 7:4 - 'b0000 n/a do not use 3 stepup2_pwm_mode 0 RW Enable PWM mode 0 :€Normal operation 1 :€PWM mode operation. Feedback is sampled during PWM off-time, if stpup2_lowf=0. 2 stepup12_clkinv 0 RW Invert input clock of SU1 and SU2 converter 0 :€Use positive edge of internal clk 1 :€Use negative edge of internal clk RW Controls the feedback protection of SU2 with external resistor divider (regulated to 0.8V). 0 : FB_SU2 enabled as input 1 : GPIO2 enabled as input 2 : GPIO3 enabled as input 3 : GPIO4 enabled as input 'b00 lv stepup2_fbprot am lc s on A te G nt st il 1:0 Bit Description al id Bit RTCcontrol Register (Address 60h). RTCcontrol Addr: 60h Bit Bit Name 7:5 - Default Access 'b000 n/a Bit Description do not use 0 :€Generates an interrupt every second 1 :€Generates an interrupt every minute 2 :€Generates an interrupt every 2 minute 3 :€Generates an interrupt every 8 minute rtc_irq_mode 'b00 RW 2 rtc_on 0 RW 1 rtc_alarm_wakeup_en 0 RW 0 :€Disables RTC alarm wake-up in power off mode 1 :€Enable RTC alarm wake-up in power off mode 0 rtc_rep_wakeup_en RW 0 :€Disables RTC repeated wake-up in power off mode 1 :€Enable RTC repeated wake-up in power off mode ca 4:3 0 Switch on the 32kHz RTC oscillator 0 :€32kHz oscillator disabled 1 :€32kHz oscillator enabled RTCSecond ch Addr: 61h ni RTCSecond Register (Address 61h). Bit Name Default Access 7:0 second 00h RW Te Bit Bit Description - RTCMinute1 Register (Address 62h). RTCMinute1 Addr: 62h Bit Bit Name Default Access 7:0 minute0 00h RW www.austriamicrosystems.com Bit Description - 1.2 71 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w RTCMinute2 Register (Address 63h). RTCMinute2 Bit Bit Name Default Access 7:0 minute1 00h RW Bit Description - RTCMinute3 Register (Address 64h). RTCMinute3 Bit Bit Name Default Access 7:0 minute2 00h RW Bit Description lv Addr: 64h - RTCAlarmSecond Addr: 65h 7:0 am lc s on A te G nt st il RTCAlarmSecond Register (Address 65h). Bit al id Addr: 63h Bit Name alarmsecond Default 3Fh Access RW Bit Description AlarmMinute2 has to be written to latch the whole alarm register RTCAlarmMinute Register (Address 66h). RTCAlarmMinute Addr: 66h Bit Bit Name 7:0 alarmminute0 Default Access FFh RW Bit Description AlarmMinute2 has to be written to latch the whole alarm register RTCAlarmMinute2 Register (Address 67h). RTCAlarmMinute2 Addr: 67h Bit Name 7:0 alarmminute1 Default ca Bit FFh Access RW Bit Description AlarmMinute2 has to be written to latch the whole alarm register RTCAlarmMinute3 ch Addr: 68h ni RTCAlarmMinute3 Register (Address 68h). Bit Name Default Access 7:0 alarmminute2 FFh RW Te Bit Bit Description - SRAM Register (Address 69h). SRAM Addr: 69h Bit Bit Name Default Access 7:0 SRAM 00h RW www.austriamicrosystems.com Bit Description - 1.2 72 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w ADC_control Register (Address 70h). ADC_control Addr: 70h Bit Name Default Access 7 start_conversion 0 RW Writing a 1 into this bit starts one ADC conversion 6 adc_on 0 RW Writing a 1 into this bit continuously activates the ADC S/H and the input multiplexer. The ADC and the MUX are also activated for a conversion period when start_conversion is set to 1. Useful for high impedance input sources on ADC inputs 5 adc_slow 0 RW Select ADC sampling frequency 0 :€250kHz (conversion time: approx. 60µs) 1 :€62.5kHz (conversion time:approx. 240µs) 4 gpio_lv RW 0 :€High voltage range of GPIO1…4/SENSEN_SU1 (4:1 divider active) 1 :€Low voltage range of GPIO1…4/SENSEN_SU1 (1:1 divider, 1.8V max) adc_select lv am lc s on A te G nt st il 3:0 0 Bit Description al id Bit 'b0000 RW Selects an ADC channel .0 :€ADCIN (1:1) .1 :€Temperature sensor: DIE temperature [C] = adc_result * 0.866 274 (1:1) .2 :€XOUT32K (1:1, 1.8Vmax) .3 :€CURR1 (1:1, 1V max) .4 :€CURR2 (1:1, 1V max) .5 :€CURR3 (1:1, 1V max) .9 :€VSUP (4:1) 10 :€SENSEN_SU1 (4:1 or 1:1 ) 11 :€FB_SU2 (4:1 or 1:1 ) 12 :€GPIO2 (4:1 or 1:1 ) 13 :€GPIO3 (4:1 or 1:1 ) 14 :€GPIO4 (4:1 or 1:1 ) 15 :€NA ADC_MSB_result Register (Address 71h). ADC_MSB_result Addr: 71h Bit Name Default Access 7 result_not_ready 0 RO Indicates end of conversion 0 result is ready 1 conversion is running 6:0 D9_3 'b000 0000 RO ADC result register Bit9..Bit3 Bit Description ni ca Bit ch ADC_LSB_result Register (Address 72h). Addr: 72h ADC_LSB_result Bit Name Default Access 7:3 - 'b0000 0 n/a do not use 2:0 D2_0 'b000 RO ADC result register Bit2…Bit0 Te Bit www.austriamicrosystems.com Bit Description 1.2 73 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w RegStatus Register (Address 73h). RegStatus Addr: 73h Bit Name Default Access Bit Description 7 curr3_lv 0 RO Bit is set when voltage of current sink CURR3 drops below low voltage threshold (1ms debounce time default) 6 curr2_lv 0 RO Bit is set when voltage of current sink CURR2 drops below low voltage threshold (1ms debounce time default) 5 curr1_lv 0 RO Bit is set when voltage of current sink CURR1 drops below low voltage threshold (1ms debounce time default) 4 - 0 n/a do not use 3 - 0 n/a do not use 2 sd3_lv 0 RO Bit is set when voltage of SD3 drops below low voltage threshold (-5%) (1ms debounce time default) 1 sd2_lv 0 sd1_lv lv al id Bit RO Bit is set when voltage of SD2 drops below low voltage threshold (-5%) (1ms debounce time default) 0 RO Bit is set when voltage of SD1 drops below low voltage threshold (-5%) (1ms debounce time default) am lc s on A te G nt st il 0 InterruptMask1 Register (Address 74h). InterruptMask1 Bit Bit Name Access 7 LowBat_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 6 ovtmp_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 5 onkey_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 4 chdet_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 3 eoc_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 2 resume_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 1 Bit Description nobat_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) trickle_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) Te ch 0 ca Default ni Addr: 74h www.austriamicrosystems.com 1.2 74 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w InterruptMask2 Register (Address 75h). InterruptMask2 Default Access Bit Description 7 rtc_rep_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 6 stpup1_det_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 5 stpup1_oc_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 4 bat_temp_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 3 - 1 n/a do not use 2 sd3_lv_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 1 sd2_lv_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 0 sd1_lv_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) al id Bit Name am lc s on A te G nt st il Bit lv Addr: 75h InterruptMask3 Register (Address 76h). InterruptMask3 Addr: 76h Bit Name Default Access 7:3 - 2 Bit Description 'b0000 0 n/a gpio_restart_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 1 gpio_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) 0 rtc_alarm_int_m 1 RW 0 :€interrupt enabled 1 :€interrupt masked (disabled) do not use ca Bit InterruptStatus1 Register (Address 77h). Bit InterruptStatus1 ni Addr: 77h Bit Name Default Access LowBat_int_i 0 POP Bit is set when VSUP drops below ResVoltFall 6 ovtmp_int_i 0 POP Bit is set when 110deg is exceeded 5 onkey_int_i 0 POP Rising and falling edge 4 chdet_int_i 0 POP Rising and falling edge 3 eoc_int_i 0 POP Rising and falling edge 2 resume_int_i 0 POP Rising and falling edge 1 nobat_int_i 0 POP Rising and falling edge 0 trickle_int_i 0 POP Rising and falling edge Te ch 7 www.austriamicrosystems.com Bit Description 1.2 75 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w InterruptStatus2 Register (Address 78h). Default Access Bit Description 7 rtc_rep_int_i 0 POP Rising edge only 6 stpup1_det_i 0 POP Rising edge only 5 stpup1_oc_i 0 POP Rising edge only 4 bat_temp_i 0 POP Rising and falling edge 3 - 0 n/a do not use 2 sd3_lv_int_i 0 POP Rising edge only 1 sd2_lv_int_i 0 POP Rising edge only 0 sd1_lv_int_i 0 POP Rising edge only lv Bit Name am lc s on A te G nt st il Bit al id InterruptStatus2 Addr: 78h InterruptStatus3 Register (Address 79h). InterruptStatus3 Addr: 79h Bit Bit Name Default Access 7:3 - 2 Bit Description 'b0000 0 n/a do not use gpio_restart_int_i 0 POP Falling edge 1 gpio_int_i 0 POP Rising and falling edge 0 rtc_alarm_int_i 0 POP Rising edge only Default Access Bit Description ‘b0000 0 n/a do not use n/a do not use RW Enables lock of Regulator voltages Bits can only be set. Reset only with full reset cycle 0 :€No lock 1 :€Lock of voltage of LDOs (LDO1..8_vsel) (all bits) and voltage of StepDownBits(sd1..4_vsel) [5:6] only 2 :€Lock voltage of StepDownbits 5:6 only (no LDOs) 3 :€Lock voltage of StepDowns (all bits) and LDOs (all bits). Note: Setting sdx_vsel to 0 is possible all the time to allow switching off the regulator. Writing a non-zero value after that will restore the old value. Lock Register (Address 8eh). Lock Addr: 8eh Bit Name 7:3 - 2 - 0 ni reg_lock Te ch 1:0 ca Bit www.austriamicrosystems.com 'b00 1.2 76 - 85 AS3712 2V1 Datasheet - R e g i s t e r O v e r v i e w ASIC_ID1 Register (Address 90h). ASIC_ID1 Bit Name Default Access 7:0 ID1 0Ah RO Bit Description - ASIC_ID2 Register (Address 91h). ASIC_ID2 Addr: 91h Bit Name Default Access 3:0 revision 'b0000 RO Bit Description Note: Metal fuse!!! Te ch ni ca am lc s on A te G nt st il Bit al id Bit lv Addr: 90h www.austriamicrosystems.com 1.2 77 - 85 D C B A R16 1M 1 3 5 1 3 5 J5 2 4 6 2 4 6 I2C BU4 GND 1 R17 10k VSUP BU3 VSUP S1 RESET R15 10k ON 100nF C28 10uF C23 2.2uF S2 C29 C41 VSUP 1 Q5 D4 1uF R9 1k VSUP Y1 57 25 24 23 22 38 39 37 36 40 34 4 1 2 3 5 35 C2 C8 C3 C4 C5 C6 C7 C1 2 AS3712 C17 D7 D6 D8 2.2uF VSUP D9 NC FB_SU3 GATE_SU3 SENSEN_SU3 FB_SU2 GATE_SU2 SENSEN_SU2 FB_SU1 GATE_SU1 SENSEN_SU1 FB_SD1 LX_SD1 FB_SD2 LX_SD2 FB_SD3 LX_SD3 VSUP_SD1 VSUP_SD2 VSUP_SD3 44 46 42 41 43 49 51 52 48 47 12 13 9 10 8 7 U? AS3712 14 11 6 2.2uF 1µH 1µH 10µH 150m R21 1 Q7 L8 C12 2.2uF 1µH VSUP L4 L2 L1 1uF 1uF 2.2uF 2.2uF 2.2uF 1uF 2.2uF VSUP 2.2uF C37 C25 10µF 3 D5 SD3 C16 2.2uF LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 3 SD2 SD1 1 Q4 1 Q3 Project Title Date 30.09.2011 Originator tka 2.2uF C22 VSUP C31 2.2uF D3 D2 C30 33nF C34 4 SU1 C33 2.2uF SU2 C27 10uF of 1 Revision 1V0 15nF Sheet 1 R14 100k 1M R11 1.5nF C32 R8 15nF C26 330k 1M R6 4 al id lv C38 2.2uF SU3 10µH L6 4.7µH L5 R7 150m VSUP R4 150m C14 10µF AS3712 schematic C40 15nF C39 Size A4 Title 100k R23 1M R22 1.5nF C20 10µF C21 2.2uF am lc s on A te G nt st il 2.2uF VSS(exp) XRES SDA SCL ON XOUT32 XIN32 V2_5 CREF ADCIN VSUP VSUP NC NC NC NC NC 2.2uF C9 C10 C11 2.2uF VSUP ca ni ch 2 31 56 18 VIN_LDO123 VIN_LDO456 VIN_LDO78 CURR1 CURR2 CURR3 15 16 17 CURR1 CURR2 CURR3 26 27 28 29 21 GPIO1 GPIO2 GPIO3 GPIO4 VSUP_GPIO 1 3 2 32 30 33 55 54 53 20 19 VSUP_SU 45 SENSEP 50 3 2 LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 GPIO1 GPIO2 GPIO3 GPIO4 3 2 1.2 3 www.austriamicrosystems.com 2 Te D C B A Datasheet - A p p l i c a t i o n I n f o r m a t i o n AS3712 2V1 11 Application Information Figure 27. AS3712 Application Schematic 78 - 85 AS3712 2V1 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Te ch ni ca am lc s on A te G nt st il lv al id Figure 28. PCB Layout Recommendation for SD1, SD2, SD3 and Switched Mode Charger www.austriamicrosystems.com 1.2 79 - 85 AS3712 2V1 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Te ch ni ca am lc s on A te G nt st il lv al id Figure 29. PCB Layout Recommendation for SU1, SU2, SU3 www.austriamicrosystems.com 1.2 80 - 85 AS3712 2V1 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 12 Package Drawings and Markings Te ch ni ca am lc s on A te G nt st il lv al id Figure 30. Package Drawings and Dimensions www.austriamicrosystems.com 1.2 81 - 85 AS3712 2V1 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s lv al id Figure 31. QFN Marking YY year am lc s on A te G nt st il Table 29. Package Code YWWZZZ WW X ZZ working week assembly / packaging plant identifier free choice Table 30. Start-up Revision Code xx FF 00 engineering samples, no sequence programmed or sequence programmed on request default sequence (no sequence programmed) customer specified sequence programmed during production test Te ch ni ca xx Sequence www.austriamicrosystems.com 1.2 82 - 85 AS3712 2V1 Datasheet - R e v i s i o n H i s t o r y Revision History Revision Date Owner 0.10 3.2011 pkm Description Initial draft typo corrections; updated block diagrams, PCB layout recommendations, charger mode diagrams, application schematics, DCDC performance characteristics added register 2bh and 2ch for chip version 2v1. 10.2011 pkm, cwo 1.0 10.2011 pkm first official release 1.1 12.2011 pkm corrected ntc_on bit description, adjusted max die temperature, updated dcdc mode description pkm corrected “enter standby mode”, GPIO1 input mode description, GPIO block diagram, GPIO IOSF, interrupt signal polarity added switching charger graphs, added step-up external components, ASIC ID lv 4.2012 am lc s on A te G nt st il 1.2 al id 0.20 Te ch ni ca Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com 1.2 83 - 85 AS3712 2V1 Datasheet - O r d e r i n g I n f o r m a t i o n 13 Ordering Information The devices are available as the standard products shown below. Table 31. Ordering Information Marking Sequence Description Delivery Form Package AS3712-BQFR-FF M2V1-FF sequence programmable on request Triple Buck High Current PMIC without Charger Tray QFN56 7x7 0.4mm pitch AS3712-BQFP-00 M2V1-00 default sequence Triple Buck High Current PMIC without Charger Tape & Reel dry pack QFN56 7x7 0.4mm pitch AS3712-BQFP-xx M2V1-xx customer specified Triple Buck High Current PMIC without Charger Tape & Reel dry pack QFN56 7x7 0.4mm pitch am lc s on A te G nt st il Technical Support is available at http://www.austriamicrosystems.com/Technical-Support lv Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect al id Ordering Code Te ch ni ca For further information and requests, please contact us mailto: sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com 1.2 84 - 85 AS3712 2V1 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. al id Disclaimer lv Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. ca am lc s on A te G nt st il The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information ni Headquarters ch austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Te Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com 1.2 85 - 85