AS3715-BWLM-00

AS3715 Dual Power Path PMIC General Description The AS3715 is a compact System PMU supporting two Li-Ion batteries and up to 14 power rails. The device offers advanced power management functions. All necessary ICs and peripherals in a battery powered mobile device are supplied by the AS3715. It features 3 DCDC buck converters, one DCDC buck controller, a 5V HDMI booster, a HV backlight boost controller with 3 current sinks as well as 8 LDOs (2 low noise). The different regulated supply voltages are programmable via the serial control interface. 3-4MHz operation with 0.47uH coils is reducing cost and PCB space. AS3715 contains a linear or switch mode Li-Ion battery charger with constant current and constant voltage operation. The maximum charging current is 1.5A. An internal battery switch and an optional external switch are separating the battery during charging or whenever an external power supply is present. In addition a second external battery path can be controlled. With these switches it is also possible to operate with no or deeply discharged batteries. A dual USB input current limiter can be used to control the current taken form the USB supplies or charger inputs. Additional features are a 30V OV protection and JEITA compliant battery temperature supervision with selectable NTC beta values. The single supply voltage may vary from 2.7V to 5.5V. Ordering Information and Content Guide appear at end of datasheet. Key Benefits and Features Following the general description are key benefits and features for AS3715. Figure 1: Added Value of Using AS3715 Benefits Features Compact design due to small coils for IO and memory voltage generation • DCDC step down regulators (3-4MHz) - Output (0.6V-3.3V; 2x1A, 1x2A) High current generation with external power stages to minimize PMIC power dissipation • DCDC step down controller - DVM (0.6V-1.5V; 1x5A) Multiple independent voltage rails for general purpose IO supplies • 8 universal LDOs - 6x universal IO range(0.8-3.3V; 0.3A) - 2x analog (1.2-3.3V; 0.25A) ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 1 Document Feedback AS3715 − General Description Benefits Features Backlight boost controller for multiple display configurations or fixed voltage supplies Self-contained Li-Ion battery charger with dual battery and USB path control. • Current mode boost controller with two current sinks. • Constant voltage operation and over-voltage protection • 3 programmable current sinks (max. 40mA) • Possible external PWM dimming input (DLS, CABC) • • • • 1.5A max charging current Dual battery control Dual charger input with current limiters Soft-, Trickle-, Constant Current and Constant Voltage operation (3.5 .. 4.44V) • Linear and switch mode charging • Charger timeout and JEITA temperature supervision • NTC beta selection Save supervision in HW which works also without a processor. • Supervisor with interrupt generation and selectable warning levels - Automatic battery monitoring - Automatic temperature monitoring - Power supply supervision for DCDC Flexible multi-purpose IOs for general control tasks. • General Purpose IOs - ADC input - Wake-up/stand-by input - PWM input/output - Low battery and power good status Enables the processor to check the actual system state in detail. • ADC with internal and external sources Flexible and fast adaptation to different processors/applications. • OTP programmable Boot and Power-down sequence Power saving control according to the processor needs. • Stand-by function with programmable sequence and voltages Self-contained start-up and control dual battery and dual USB operation. Safety shutdown feature. • Control Interface - I²C control lines with watchdog - ONKEY with 4/8s emergency shut-down - POR with RESET I/O Dedicated packages for specific applications. Optimization for PCB cost or size. • Package - 81-ball WL-CSP 0.4mm pitch Applications The device is suitable for digital still cameras, outdoor action cameras, digital movie cameras, general Li-Ion battery powered mobile devices. Page 2 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − General Description Block Diagram The functional blocks of this device for reference are shown below: Figure 2: Block Diagram for AS3715 LDO1 ANA 1Ω 1 .2-3 .3V 250 mA VUSB XOFF LDO2 ANA 1 Ω 1.2-3.3V 250 mA LDO3 UIO 1Ω 0.8-3.3V 300mA LDO4 LDO5 UIO 1Ω 0.8-3.3V 300 mA UIO 1Ω 0.8-3.3V 300mA 1uF LDO6 1uF LDO5 1uF LDO4 1uF LDO6 1uF LDO5 1uF VIN_LDO456 2.2uF LDO4 VIN_LDO123 2.2 uF LDO6 UIO 1Ω 0.8 -3.3 V 300 mA LDO7 UIO 1 Ω 0 .8-3 .3V 300 mA 30V Over-Voltage Protection LDO8 CHGIN1 30V OVP optional Power Path & Limiter 4.7uF AS3715 CHGIN2 UIO 1 Ω 0 .8-3 .3V 300 mA 1.5 – 2A 0.6 – 3.35V 3 – 4MHz VSUP_CHG 1 uF LDO8 1uF 2.2uF LX_SD1 FB_SD1 1uH DCDC2 EBATSW 0.7 – 1A 0.6 – 3.35V 2 – 4MHz IBATSW 2.2uF LX_SD2 FB_SD2 1uH 1.5A Li-Ion Charger 0.7 – 1A 0.6 – 3.35V 2 – 4MHz linear or switched mode dual battery control enhanced temp control NTC ß-correction VEBAT 2.2uF LX_SD3 FB_SD3 6A 0.6 – 1.5 V 1.5 – 3MHz CHGOUT BATTEMP 10uF CTRL2_ SD4 CTRL1_ SD4 FB_SD4 (differential) VSUP_CP 5V CP 55 mA 1 MHz 8 GPIOs + 4 Enable CAPP 1uF 470nF CAPN V5_0 VSS_CP Boot ROM 1uH VSS_SD3 TEMP_ SD4 DCDC4 VIBAT Control & Reference 10uF VSS_SD2 VSUP_SD3 DCDC3 20uF VSS_SD1 VSUP_SD2 S2 S1 LDO7 VSUP_SD1 DCDC1 4.7 uF 2.2uF VIN_LDO78 4.7uF Watchdog Stand-by VSUP_SU POR BOOST Supervisor (OTP) (Supply & Temp) I2C ADC 16-ch 3 SINKs HV, 40mA each (controller ) voltage & current mode 0.5 /1MHz SENSP GATE_SU FB_SU VSS_SU Block Diagram: Shows the main function blocks of the AS3715. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 3 Document Feedback AS3715 − Pin Assignments Pin Assignments Figure 3: Pin Assignment 1 2 3 4 5 6 7 8 9 A VSS_SU SENSEN_SU LDO6 LDO5 LDO4 CHGIN1 VSUP_CHG CHGIN2 CHGOUT B FB_SD4_N GATE_SU VIN_LDO456 GPIO8 EN2 CHGIN1 VSUP_CHG CHGIN2 CHGOUT C CTRL1_SD4 TEMP_SD4 VSUP_SU FB_SD4_P FB_SU EN1 IBATSW XOFF VSUP_SD3 D CAPN VSS_CP VEBAT CTRL2_SD4 SENSEP_SU EN4 EBATSW FB_SD3 LX_SD3 E V5_0 CAPP VSUP_CP VIBAT BATTEMP VUSB EN3 FB_SD2 VSS_SD3 F V2_5 LDO3 CREF GPIO7 GPIO6 SDA VSS_ANA VSSA VSS_SD2 G LDO2 VIN_LDO123 GPIO5 GPIO2 GPIO1 CURR3 FB_SD1 VSUP_SD2 LX_SD2 H LDO1 GPIO3 SCL ONKEY VIN_LDO78 CURR2 LX_SD1 VSUP_SD1 VSUP_SD1 J GPIO4 XRES VSUP_GPIO LDO7 LDO8 CURR1 LX_SD1 VSS_SD1 VSS_SD1 Pin Assignment: Shows the top view pin assignment of the AS3715 Page 4 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Pin Assignments Figure 4: Pin Description Max. Voltage If not used SPI digital input in SPI mode; Data IO in I²C mode. VSUP Open DI SPI clock input in SPI mode; SCK input in I²C mode. VSUP Open ONKEY DI Input pin to startup with pull-down 5.5V Define level J2 XRES DIO IO pin for reset during active state VSUP Define level F1 V2_5 AO Output voltage of low power LDO V2_5 2.6V Mandatory F3 CREF AIO Bypass capacitor for the internal voltage reference; connect 100nF 1.8V Mandatory J3 VSUP_GPIO S Supply pin for GPIOs (connect to other VSUP pins) 5.5V Mandatory F7 VSS_ANA AIO Analog sense GND input (connect to VSSA on PCB) - Mandatory G5 GPIO1 DIO General purpose input/output pin VSUP Open G4 GPIO2 DIO General purpose input/output pin VSUP Open H2 GPIO3 DIO General purpose input/output pin VSUP Open J1 GPIO4 DIO General purpose input/output pin VSUP Open G3 GPIO5 DIO General purpose input/output pin VSUP Open F5 GPIO6 DIO General purpose input/output pin / optional current sink VSUP Open F4 GPIO7 DIO General purpose input/output pin / optional current sink VSUP Open B4 GPIO8 DI General purpose input/output pin VSUP Open C6 EN1 DI Input pin to startup with pull-down 5.5V Open B5 EN2 DI Input pin to startup with pull-down 5.5V Open E7 EN3 DI Input pin to startup with pull-down 5.5V Open D6 EN4 DI Input pin to startup with pull-down 5.5V Open G2 VIN_LDO123 S Supply pad for LDOs 5.5V Mandatory B3 VIN_LDO456 S Supply pad for LDOs 5.5V Mandatory H5 VIN_LDO78 S Supply pad for LDOs 5.5V Mandatory H1 LDO1 AO Output voltage of LDO - PMOS_1 3.3V Open Pin # Pin Name I/O F6 SDA DI H3 SCL H4 ams Datasheet, Confidential [v1-00] 2014-Sep-10 Description Page 5 Document Feedback AS3715 − Pin Assignments Max. Voltage If not used Output voltage of LDO - PMOS_1 3.3V Open AO Output voltage of LDO - PMOS_1 3.3V Open LDO4 AO Output voltage of LDO - PMOS_0.6 3.3V Open A4 LDO5 AO Output voltage of LDO - PMOS_0.6 3.3V Open A3 LDO6 AO Output voltage of LDO - PMOS_0.6 3.3V Open J4 LDO7 AO Output voltage of LDO - PMOS_0.6 3.3V Open J5 LDO8 AO Output voltage of LDO - PMOS_1 3.3V Open H9 VSUP_SD1 S System supply voltage input of SD1 (connect to other VSUP pins) 5.5V Mandatory H8 VSUP_SD1 S System supply voltage input of SD1 (connect to other VSUP pins) 5.5V Mandatory J7 LX_SD1 AIO LX node of Stepdown1 VSUP Open H7 LX_SD1 AIO LX node of Stepdown1 VSUP Open G7 FB_SD1 AI Analog Feedback pin of SD1 3.6V Open J9 VSS_SD1 AIO Power GND pin of Stepdown1 - Mandatory J8 VSS_SD1 AIO Power GND pin of Stepdown1 - Mandatory G8 VSUP_SD2 S System supply voltage input of SD2 (connect to other VSUP pins) 5.5V Mandatory G9 LX_SD2 AIO LX node of Stepdown2 VSUP Open E8 FB_SD2 AI Analog Feedback pin of SD2 3.6V Open F9 VSS_SD2 AIO - Mandatory C9 VSUP_SD3 S System supply voltage input of SD3 (connect to other VSUP pins) 5.5V Mandatory D9 LX_SD3 AIO LX node of Stepdown3 VSUP Open D8 FB_SD3 AI Analog Feedback pin of SD3 3.6V Open E9 VSS_SD3 AIO Power GND pin of Stepdown3 - Mandatory C4 FB_SD4_P AIO Positive Feedback of SD1 3.6V Open B1 FB_SD4_N AIO Negative Feedback of SD1 3.6V Open C1 CTRL1_SD4 AIO Bidirectional control pin of SD0, phase 1 VSUP Open D4 CTRL2_SD4 AIO Bidirectional control pin of SD0, phase 2 VSUP Open C2 TEMP_SD4 AIO Temperature control pin of power stage for SD1 VSUP Open Pin # Pin Name I/O G1 LDO2 AO F2 LDO3 A5 Page 6 Document Feedback Description Power GND pin of Stepdown2 ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Pin Assignments Max. Voltage If not used System supply voltage input of CP (connect to other VSUP pins) 5.5V Mandatory AIO Flying cap of charge pump VSUP Open CAPN AIO Flying cap of charge pump VSUP Open E1 V5_0 AIO Output voltage of charge pump - Open D2 VSS_CP AIO Power GND pin of 5V charge pump - Mandatory C3 VSUP_SU S System supply voltage input of SU (connect to other VSUP pins) 5.5V Mandatory D5 SENSEP_SU AI SU positive sense resistor input VSUP Open A2 SENSEN_SU AI SU negative sense resistor input VSUP Open C5 FB_SU AI Analog Feedback pin of SU 3.6V Open B2 GATE_SU AO SU ext. NMOS gate driver output VSUP Open A1 VSS_SU AIO Power GND pin of SU - Mandatory J6 CURR1 AIO Current sink 1 terminal 30V Open H6 CURR2 AIO Current sink 2 terminal 30V Open G6 CURR3 AIO Current sink 3 terminal 30V Open D7 EBATSW AO External battery switch gate driver VSUP Open C7 IBATSW AO Internal battery switch gate driver VSUP Open C8 XOFF AO External OV NMOS gate driver 15V Open A6 CHGIN1 S Charger adapter input (protected) 5.5V Open B6 CHGIN1 S Charger adapter input (protected) 5.5V Open A8 CHGIN2 S 2nd Charger adapter input 5.5V Open B8 CHGIN2 S 2nd Charger adapter input 5.5V Open A7 VSUP_CHG S IO Current limiter output, Charger input VSUP Open B7 VSUP_CHG S IO Current limiter output, Charger input VSUP Open A9 CHG_OUT AO Charger output (liner, switched) 5.5V Open B9 CHG_OUT AO Charger output (liner, switched) 5.5V Open E6 VUSB S Charger adapter input (unprotected) 30V Open E4 VIBAT S Internal Li-Ion battery terminal 5.5V Open D3 VEBAT S External Li-Ion battery terminal 5.5V Open Pin # Pin Name I/O E3 VSUP_CP S E2 CAPP D1 ams Datasheet, Confidential [v1-00] 2014-Sep-10 Description Page 7 Document Feedback AS3715 − Pin Assignments Pin # Pin Name I/O Description E5 BATTEMP AIO Li-Ion battery charger NTC input F8 VSSA AIO Analog GND input Max. Voltage If not used 3.6V Open - Mandatory Pin Description: This table shows the pin description for the CSP package including information of the I/O type, protection and handling if the function block is not used. Page 8 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters Supply Voltage to Ground 30V pins -0.5 32 V Applicable for pins VUSB, CURR1/2/3 Supply Voltage to Ground 15V pins -0.5 17 V Applicable for pins XOFF Supply Voltage to Ground 5V pins -0.5 7.0 V Applicable for pins VSUP_SDx, VSUP_GPIO, VSUP_ANA, VIN_LDOx, LDOx, GPIOx, LX_SDx, GATE_SU, FB_SU, SENSEP/N XRES, SCL, SDA, ONKEY, ENx, VIBAT, VEBAT, E/IBATSW, CTRLx_SD4 Supply Voltage to Ground 3V pins -0.5 5.0 V Applicable for pins V2_5, CREF, FB_SDx, TEMP_SD4, BATTEMP Voltage Difference between Ground Terminals -0.3 0.3 V Applicable for pins VSSx, VSSA Input Current (latch-up immunity) -100 100 mA Norm: JEDEC JESD78 Continuous Power Dissipation (TA = +70°C) PT Continuous power dissipation 1.2 W PT (1) for WL-CSP81 package (RTHJA ~ 45K/W) 0 Electrostatic Discharge Electrostatic Discharge HBM ams Datasheet, Confidential [v1-00] 2014-Sep-10 ±1.5 kV Norm: JEDEC JESD22-A114F Page 9 Document Feedback AS3715 − Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Temperature Ranges and Storage Conditions TA RTHJA TJ Operating Temperature +85 Junction to Ambient Thermal Resistance -55 Package Body Temperature Humidity non-condensing Moisture Sensitive Level °C °C/W Junction Temperature Storage Temperature Range TBODY -40 5 1 +125 °C +125 °C +260 °C 85 % RTHJA typ. 45K/W Norm IPC/JEDEC J-STD-020 (2) Represents an unlimited floor life time Note(s) and/or Footnote(s): 1. Depending on actual PCB layout and PCB used. 2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices”. Page 10 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Electrical Characteristics Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: AS3715 Electrical Characteristics Symbol VUSB CHGINx Parameter Conditions Min Typ Max Unit Charger HV input 0 5 30 V Charger input 0 5 5.5 V VIBAT, VEBAT Battery Voltage 2.5 3.6 5.5 V VSUPx Supply Voltage 2.5 3.6 5.5 V VINLDO123 Supply Voltage for LDO1, 2 & 3 2.7 3.6 5.5 V VINLDO456 Supply Voltage for LDO4, 5 & 6 1.7 3.6 5.5 V VINLDO78 Supply Voltage for LDO7 & 8 1.7 3.6 5.5 V V2_5 Voltage on Pin V2_5 2.4 2.5 2.6 V Ilow_power Low Power current @ VSUPx = 4.2V 220 μA Ipower_off Power-OFF current All regulators OFF, V2_5 ON, supplied via VIBAT only 13 μA Electrical Characteristics: VSUPx=+2.7V...+5.5V, TA =-40ºC...+85ºC. Typical values are at VSUPx=+3.6V, TA=+25ºC, unless otherwise specified. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 11 Document Feedback AS3715 − Typical Operating Characteristics Typical Operating Characteristics Page 12 Document Feedback This page is intentionally left blank. ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Detailed Description – Power Management Functions DCDC Step-Down Converter Description The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 2A (SD1), and 1A for (SD2, SD3), with an output capacitor of only 8-12μF. The implemented current limitation protects the DCDC and the coil during overload condition. Figure 7: Step Down DC/DC Converter Block Diagram IMIN sdX_low_noise 250/600mA + - clk VSUP_SDx 1.2/2.5A + CVS UP_SDx ILIMIT Overvoltage Comparator - LSDx + Ref + 8% ISENSEP Logic LX_SDx COUT_SDx + Ref - 5% VOUT - Σ ISENSEN + VSS_SDx Zero Comparator Skip + PWM Comparator - sdX_lv Ref = 0.6V FB_SDx - Slope Compensation sdX_vsel Softstart DCDC Step Down Converter Block Diagram: Shows the internal structure of the DCDC bucks. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 13 Document Feedback AS3715 − Detailed Description – Power Management Functions Mode Settings Low Ripple, Low Noise Operation: Bit settings: sdX_low_noise=1 In this mode there is no minimum coil current necessary before switching OFF the PMOS. As long as the load current is superior to the ripple current the device operates in continuous mode. Figure 8: DC/DC Buck Continuous Mode DC/DC Buck Continuous Mode: Shows the DC/DC switching waveforms of for SD3 at about 500mA. When the load current gets lower, the discontinuous mode is triggered. As result, the auto-zero comparator stops the NMOS conduction to avoid load discharger and the duty cycle is reduced down to tmin_on to keep the regulation loop stable. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. Figure 9: DC/DC Buck Dis-continuous Mode DC/DC Buck Dis-continuous Mode: Shows the DC/DC switching waveforms of for SD3 at about 60mA. Page 14 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Only in the case the load current gets so small that less than the minimum ON-time of the PMOS would be needed to keep the loop in regulation the regulator will enter low power mode operation and skip pulses during this time. The crossover point is about ~1% of the DCDC current limit. Figure 10: DC/DC Buck Dis-continuous & Low Power Mode DC/DC Buck Dis-continuous & Low Power Mode: Shows the DC/DC switching waveforms of for SD3 at about 10mA.High efficiency operation (default setting). Bit settings: sdX_low_noise=0 In this mode there is a minimum coil current necessary before switching OFF the PMOS. As a result there are less pulses necessary at low output loads, and therefore the efficiency at low output load is increased. As drawback this mode increases the ripple up to higher output currents. The crossover point to low power mode is already reached at reasonable high output currents (~10% of the DCDC current limit). Figure 11: DC/DC Buck Dis-continuous Mode & High Efficiency 1/2 DC/DC Buck Dis-continuous Mode: Shows the DC/DC switching waveforms of for SD5 at about 60mA with the low_noise bit deactivated. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 15 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 12: DC/DC Buck Dis-continuous Mode & High Efficiency 2/2 DC/DC Buck Dis-continuous Mode: Shows the DC/DC switching waveforms of for SD5 at about 10mA with the low_noise bit deactivated. It’s possible to switch between these two modes during operation. Power Save Operation (Automatically Controlled): As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/under-shoots by immediately turning on the output drivers without the normal time delays. This ensures a minimized ripple also in very extreme load conditions. DVM (Dynamic Voltage Management) To minimize the over-/undershoot during a change of the output voltage, the DVM can be enabled. With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. DVM can be selected for all step-down controllers, but only for one at a time. (see dvm_time and sd_dvm_select description) Page 16 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output voltage. This mode needs a bigger output capacitor to guarantee the stability of the regulator. The mode is enabled by setting sdX_fast =1. Selectable Frequency Operation Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. The frequency for SD1 can be set to 3 or 4MHz. SD2 and SD3 have a 2, 3 or 4MHz mode. This mode is selected by setting sdX_freq and sdX_fsel to the appropriate values. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. Step-Down Converter Configuration Modes The step down dc/dc converters have two configuration modes to deliver different output currents for the applications. The operating mode is selected by setting the bit sd2_slave, sd3_slave (the default is set by the Boot-OTP) Parameter Figure 13: DC/DC Buck Converter Parameter Symbol VIN Parameter Input voltage Conditions Pin VSUP_SDx Min Typ Max Unit 2.7 5.5 V 0.6125 3.35 V VOUT Regulated output voltage VOUT_tol Output voltage tolerance min. 30mV -3 +3 % Load current SD2, 3 VSD2, 3 1.8V 0 0.7 A VSD1 1.8V 0 1.2 A ILOAD_SD23 ILOAD_SD1 ILIMIT RPSW Load current SD1 Current limit P-Switch ON resistance incl. bonds, substrate, etc ams Datasheet, Confidential [v1-00] 2014-Sep-10 SD2, 3 1.2 A SD1 2.5 A SD2, SD3; VSUP_SDx=3.0V 250 500 mΩ Page 17 Document Feedback AS3715 − Detailed Description – Power Management Functions Symbol RNSW fSW Parameter N-Switch ON resistance incl. bonds, substrate, etc Switching frequency Conditions Min Typ Max Unit SD1, VSUP_SDx=3.0V 120 200 mΩ SD2, SD3; VSUP_SDx=3.0V 160 500 mΩ SD1; VSUP_SDx=3.0V 63 200 mΩ sdX_frequ=1; sdX_fsel=1; fclk_int =4MHz 4 MHz sdX_frequ=0; sdX_fsel=1; fclk_int =4MHz 3 MHz sdX_frequ=0; sdX_fsel=0; fclk_int =4MHz (SD2/3 only) 2 MHz eff Efficiency see figures below IVDD Current consumption Operating current without load 60 μA RDISCHG Pull-down resistance SD1 disabled 100 Ω SD2 or SD3 disabled 200 Ω % DC/DC Buck Converter Parameter: Shows the key electrical parameter of the internal DC/DC buck converters. Figure 14: DC/DC Buck Converter External Components Symbol COUT_SD2;3 COUT_SD1 CVSUP_SD1;2;3 LSD1-SD3 Parameter Conditions Min Typ Max Unit Output capacitor Ceramic X5R or X7R 8 μF Output capacitor, sd2_fast=1 or sd3_fast=1 Ceramic X5R or X7R 18 μF Output capacitor Ceramic X5R or X7R 12 μF Output capacitor, sd1_fast=1 Ceramic X5R or X7R 27 μF Input capacitor Ceramic X5R or X7R Inductor 4/3MHz operation 4/3MHz; VOUT≤1.8V 2.2 μF 0.5 1 μH 0.3 0.47 μH DC/DC Buck Converter External Components: Shows the external component parameter of the internal DC/DC buck converters. Page 18 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 15: DC/DC Buck SD1 3.7V Efficiency vs. Iout DC/DC Buck SD1 Efficiency: Shows efficiency of the internal SD1 buck converter @ 0.6V, 1.2V & 3.4V with VSUP=3.7V, 2.7MHz operation with TFM252010 1uH coils and TA=+25°C . 100 95 90 Efficiency (%) 85 80 75 70 65 60 55 50 45 40 0.001 AS3715 - SD1 3V7-0.6V TFM252010GHM-1R0M (2.7MHz) AS3715 - SD1 3V7-1.2V TFM252010GHM-1R0M (2.7MHz) AS3715 - SD1 3V7-3.4V TFM252010GHM-1R0M (2.7MHz) AS3715 - SD1 3V7-0.6V TFM252010GHM-1R0M (2.7MHz, low noise) AS3715 - SD1 3V7-1.2V TFM252010GHM-1R0M (2.7MHz, low noise) AS3715 - SD1 3V7-3.4V TFM252010GHM-1R0M (2.7MHz, low noise) 0.01 0.1 1 Output Current (A) Figure 16: DC/DC Buck SD2/3 3.7V Efficiency vs. Iout DC/DC Buck SD2/3 Efficiency: Shows efficiency of the internal SD2/3 buck converter @ 0.6V, 1.8V & 3.4V with VSUP=3.7V, 2.7MHz operation with TFM252010 1uH coils and TA=+25°C. 100 95 90 Efficiency (%) 85 80 75 70 65 60 55 50 45 40 0.001 AS3715 - SD2 3V7-0.6V TFM252010GHM-1R0M (2.7MHz) AS3715 - SD2 3V7-1.8V TFM252010GHM-1R0M (2.7MHz) AS3715 - SD2 3V7-3.4V TFM252010GHM-1R0M (2.7MHz) AS3715 - SD2 3V7-0.6V TFM252010GHM-1R0M (2.7MHz, low noise) AS3715 - SD2 3V7-1.8V TFM252010GHM-1R0M (2.7MHz, low noise) AS3715 - SD2 3V7-3.4V TFM252010GHM-1R0M (2.7MHz, low noise) 0.01 0.1 1 Output Current (A) ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 19 Document Feedback AS3715 − Detailed Description – Power Management Functions DCDC Step-Down Controller Description The Step-Down controller SD4 is a dual phase controller using an external power-stage incorporating 2 phases to achieve higher output currents. The maximum output current is 5A with having 2.5A per phase when using the AS3729 power stage. This allows the use of low profile coils without compromising on performance. Figure 17: SD4 DC/DC Buck Controller 5A Block Diagram AS3729 VSUP 22 uF DCDC 0.6 – 1.5 V 5A 1.5 /3MHz TEMP_SDx TEMP CTRL1_SDx CTRL1 CTRL2_SDx CTRL2 LX1 Vout (0.6-1.5V @5A) DVM, 10mV steps 1 uH 47uF PVSS FB_SDx LX2 FB_SDx 1 uH VSUP 47uF PVSS 22 uF SD4 DC/DC Buck Controller: Shows basic connection of the SD4 controller to the external power stage (AS3729) for 5A output current. Figure 18: SD4 DC/DC Buck Controller 5A Combined Mode AS3729 VSUP 10 uF DCDC 0.6 – 1.5 V 5A 1.5 /3MHz TEMP_SDx TEMP CTRL1_SDx CTRL1 CTRL2_SDx CTRL2 LX1 PVSS 0.47uH 100 uF Vout (0.6-1.5V @6A) DVM, 10mV steps FB_ SDx FB_SDx LX2 VSUP PVSS 10 uF SD4 DC/DC Buck Controller: Shows basic configuration of the SD4 controller to the external power stage (AS3729) for 5A output current using a single coil in combined mode. Page 20 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Mode Settings Low Ripple, Low Noise Operation: Bit settings: sdX_low_noise=1 In this mode there is no minimum coil current necessary before switching OFF the PMOS. As long as the load current is superior to the ripple current the device operates in continuous mode. When the load current gets lower, the discontinuous mode is triggered. As result, the auto-zero comparator stops the NMOS conduction to avoid load discharger and the duty cycle is reduced down to tmin_on to keep the regulation loop stable. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. Only in the case the load current gets so small that less than the minimum ON-time of the PMOS would be needed to keep the loop in regulation the regulator will enter low power mode operation. The crossover point is about ~1% of the DCDC current limit. High efficiency Operation (Default Setting): Bit settings: sdX_low_noise=0 In this mode there is a minimum coil current necessary before switching OFF the PMOS. As a result there are less pulses necessary at low output loads, and therefore the efficiency at low output load is increased. As drawback this mode increases the ripple up to a higher output current. The crossover point to low power mode is already reached at reasonable high output currents (~10% of the DCDC current limit). It’s possible to switch between these two modes during operation. Low Power Operation (sdX_low_power=1): In this mode the controller is only running on a single phase (phase 1). Only one output stage of the external power stage is used to reduce the power consumption for e.g. a stand-by mode operation. Power Save Operation (Automatically Controlled): As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 21 Document Feedback AS3715 − Detailed Description – Power Management Functions Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/under-shoots by immediately turning on the output drivers without the normal time delays. This ensures a minimized ripple also in very extreme load conditions. Force PWM Mode Operation: Even in the case the load current gets so small that less than the minimum ON-time of the PMOS would be needed to keep the loop in regulation the regulator will still stay on the fixed switching frequency without entering low power mode. To guarantee a stable output voltage also negative coil currents are possible. This mode guarantees the lowest possible ripple and a fixed frequency over all load conditions for powering noise sensitive RF circuits, but is compromising on the efficiency. The mode is enabled by setting sdX_force_pwm =1. Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output voltage. This mode needs a bigger output capacitor to guarantee the stability of the regulator. The mode is enabled by setting sdX_fast =1. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. DVM (Dynamic Voltage Management) To minimize the over-/undershoot during a change of the output voltage, the DVM can be enabled. With DVM the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. Without DVM the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. DVM can be selected for all step-down controllers, but only for one at a time. (see dvm_time and sd_dvm_select description) Page 22 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Parameter Figure 19: DC/DC Buck Controller Parameter Symbol VIN Parameter Conditions Input voltage Pin VSUP_SDx Min Typ Max Unit 2.5 5.5 V 0.61 1.5 V -2 +2 % VOUT Regulated output voltage VOUT_tol Output voltage tolerance min. 20mV IVDD Current consumption Dual phase without load 136 fSW Switching frequency fclk_int = 4MHz 2.7 uA 3 MHz DC/DC Buck Controller Parameter: Shows the key electrical parameter of the DC/DC buck controller. Figure 20: DC/DC Buck Controller External Components Symbol Parameter Conditions Min Typ Max Unit External Components 5A AS3729 COUT_SD4 CVSUP_SD4 LSD4 # power stages Output capacitor 1 Ceramic X5R or X7R, high performance 40 47 μF Ceramic X5R or X7R, cost optimized 20 22 μF Input capacitor Ceramic X5R or X7R 6 10 μF Inductor 4A rated, 3MHz operation, low Ron 0.3 0.47 μH External Components 8A (HV) AS3728 COUT_SD4 # power stages Output Capacitor 1 Ceramic X5R or X7R / 6.3V high performance 64 82 μF Ceramic X5R or X7R / 6.3V cost optimized 32 47 μF 10 22 μF CHVSUP_SD4 HV Input Capacitor Ceramic X5R or X7R / 25V CBOOT_SD4 Boost Capacitor Ceramic X5R or X7R / 6.3V 100 nF 5V Supply Capacitor Ceramic X5R or X7R / 6.3V 1 μF Inductor 5A rated, 1MHz operation, low RON 1 μH C5VVSUP_SD4 LSDx_SD4 0.5 DC/DC Buck Controller External Components: Shows the external component parameter of the DC/DC buck controller. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 23 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 21: SD4 3.7V Eff vs. Iout Coil Comparison DC/DC Buck SD4 Efficiency: Shows efficiency of the SD4 buck controller with AS3729 power stage for different coils @ 1.2V in dual phase and combined mode with VSUP=3.7V, 1.35MHz operation and TA=+25°C. 90 85 Efficicncy (%) 80 75 70 65 AS3729 3V7-1V2 TFM252010GHM-R47M dual (1.35MHz) AS3729 3V7-1V2 VLS252010HBX-R47 dual (1.35MHz) AS3729 3V7-1V2 DFE252010P-R47 dual (1.35MHz) 60 AS3729 3V7-1V2 IFSC1008ABERR47M01 dual (1.35MHz) AS3729 3V7-1V2 TFM252010GHM-R47M combined (1.35MHz) 55 50 0.01 AS3729 3V7-1V2 VLS252010HBX-R47 combined (1.35MHz) AS3729 3V7-1V2 DFE252010P-R47 combined (1.35MHz) AS3729 3V7-1V2 IFSC1008ABERR47M01 combined (1.35MHz) 0.1 1 10 Output Current (A) Figure 22: DC/DC Buck SD4 Load Transient Fast Mode DC/DC Buck SD4 Load Transient: Shows the response of the SD4 buck controller to a load transient from 0 to 2.3A @ 1.2V with VSUP=3.7V, 3MHz operation, fast=1, COUT=88uF and TA=+25°C. Page 24 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 23: DC/DC Buck SD4 Low Noise Load Transient Fast Mode DC/DC Buck SD4 Low Noise Load Transient: Shows the response of the SD4 buck controller to a load transient from 0 to 2.3A @ 1.2V with VSUP=3.7V, 3MHz operation, fast=1, COUT=88uF, low_noise=1 and TA=+25°C. Figure 24: DC/DC Buck SD4 Load Transient DC/DC Buck SD4 Load Transient: Shows the response of the SD4 buck controller to a load transient from 0 to 2.3A @ 1.2V with VSUP=3.7V, 3MHz operation, fast=0, COUT=44uF and TA=+25°C. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 25 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 25: DC/DC Buck SD4 Low Noise Load Transient DC/DC Buck SD4 Low Noise Load Transient: Shows the response of the SD0 buck controller to a load transient from 0 to 2.3A @ 1.2V with VSUP=3.7V, 3MHz operation, fast=0, COUT=44uF, low_noise=1 and TA=+25°C. Page 26 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Analog LDO Regulators Description LDO1 and LDO2 are designed to supply sensitive analog circuits like LNA’s, Transceivers, VCO’s and other critical RF components of cellular radios. Another application is the supply of audio devices or as a reference for AD and DA converters. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices. Stability is guaranteed with ceramic output capacitors of 1μF ±20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress the PA-ripple on the battery in TDMA systems at the output. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device to deliver up to IOUT current even at nearly discharged batteries without any decrease of performance. The default guaranteed operating current during start-up is 150mA, but can be set to 250mA with ldoX_ilimit = 1. To save power in low-power states where the full performance is not needed the bias current can be reduce by setting reg_low_bias_mode = 1. Figure 26: Analog IO LDO Block Diagram - Low Gain Ultra High Bandwidth Amplifier + Vr ef 1.8V or 1.2V low noise + High Gain Low Bandwidth Amplifier VIN_LDOx CVI N_LDOx PMOS Power Device LDOx Ccomp (internal) COUT_LDOx VSS_LDOx Analog IO LDO Block Diagram: Shows the internal structure of the analog PMOS linear regulators. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 27 Document Feedback AS3715 − Detailed Description – Power Management Functions Parameter Figure 27: Analog LDO Parameter Symbol VOUT_LDO1;2 Parameter Conditions Min Typ Max Unit Output voltage Iout300mA -10 10 mV Regulator disabled 770 Ω LDO Parameter: Shows the key electrical parameter of the linear regulators. Note(s) and/or Footnote(s): 1. Guaranteed by design and verified by laboratory evaluation and characterization; not production tested. Page 28 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 28: LDO External Components Symbol COUT_LDO1;2 CVIN_LDO12 Parameter Conditions Output capacitor Input capacitor Min Typ Max Unit Ceramic X5R or X7R ldoX_limit = 0 1 5 μF Ceramic X5R or X7R ldoX_limit =1 2 5 μF Ceramic X5R or X7R 2 μF LDO External Components: Shows the external component parameter of the linear regulators. Universal IO LDO Regulators Description 6 universal IO range LDOs offer a wide input (1.8V to 5.5V) as well as a wide output (0.8 to 3.3V) voltage range to be used for general purpose peripheral supply Up to 300mA possible output currents are offered with good noise and regulation performance and very low quiescent current even suitable for stand-by power supply. LDO7 & 8 offer in addition a load switch function, if the lowest possible drop-out without regulation is needed. Figure 29: Universal IO LDO Block Diagram VIN_LDOx + Vr ef 1.8V or 0.8V low noise Er ror Amplifier CVI N_LDOx PMOS Power Device LDOx COUT_LDOx VSS_LDOx Universal IO LDO Block Diagram: Shows the internal structure of the universal IO PMOS linear regulators. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 29 Document Feedback AS3715 − Detailed Description – Power Management Functions Parameter Figure 30: LDO Parameter Symbol Conditions Min Output voltage Iout300mA 30 mV Regulator disabled 730 Ω Transient; Slope: tr=15μs; delta 1V Static VLoadReg mA mA 100 Static Line regulation 300 0.6 f=1kHz Shut down current VLineReg 0 mA 500 IOFF tSTART Typ Load regulation Pull-down resistance LDO Parameter: Shows the key electrical parameter of the linear regulators. Note(s) and/or Footnote(s): 1. Guaranteed by design and verified by laboratory evaluation and characterization; not production tested Page 30 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 31: LDO External Components Symbol Parameter Conditions Min Typ Max Unit COUT_LDO3-8 Output capacitor Ceramic X5R or X7R 0.7 μF CVIN_LDO3-8 Input capacitor Ceramic X5R or X7R 1 μF LDO External Components: Shows the external component parameter of the linear regulators. Low Power LDO V2_5 Regulator Description The low power LDO V2_5 is needed to supply the chip core (analog and digital) of the device. It is designed to get the lowest possible power consumption, and still offering reasonable regulation characteristics. The regulator has three supply inputs selecting automatically the higher one. This gives the possibility to supply the chip core either with the VIBAT, VEBAT, VSUP or VUSBx depending on the conditions. Bulk switch comparators are used to avoid any parasitic current flow. To ensure high PSRR and stability, a low-ESR ceramic capacitor of min. 0.7μF must be connected to the output. Parameter Figure 32: Low Power LDO Parameter Symbol Parameter Conditions Supply voltage rage see VIBAT, VEBAT, VSUP, VUSB1 or VUSB2 RON ON resistance Guaranteed per design IOFF Shut down current IVDD Supply current tSTART Startup time VOUT Output voltage IOUT Output current Min Guaranteed per design, consider chip internal load for measurements. 2.4 VSUP>3.0V in power_off mode Typ Max Unit 50 Ω 100 nA 3 μA 200 μs 2.5 2.6 V 3 mA Low Power LDO Parameter: Shows the key electrical parameter of the low power V2_5 linear regulator. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 31 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 33: Low Power LDO External Components Symbol CV2_5 Parameter Output capacitor Conditions Ceramic X5R or X7R Min Typ Max 0.7 Unit μF Low Power LDO External Components: Shows the external component parameter of the low power V2_5 linear regulator. DCDC Step-up Converter Description The DC/DC Step Up converter is a high efficiency current mode PWM regulator, which provides an output voltage dependent on the maximum VDS voltage of the external transistor, and maximum load current selectable by the external shunt resistor. For Example: • 5V, 0.5-1A @ 1Mhz • 25V, 50mA @ 1MHz • 40V, 20mA @ 500kHz A constant switching frequency results in a low noise on supply and output voltage. Three feedback regulation modes are supported: • Current feedback (all three current sinks can be selected) • Current feedback with automatic feedback selection • Voltage feedback Page 32 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 34: DCDC Step-Up Converter 9683 6(16(3B68 FXUUHQWVHQVH 6(16(1B68 568 Ÿ &68B,1 —) /68 —+6'&RLOWURQLFV '68 30(* SXOVHBVNLS VWHSXSBFONLQY RYBFXUU 9 *$7(B68 RYHUVKRRWFRPS 468 6L YRYBFXUUHQW VHWSXSBY VWHSBSURW ™ UDPS *DWH 'ULYHU 0Ÿ 3:0 /RJLF RYHUVKRRW RYBYROWDJH  Q) Q) &68B287 —)9 )%B68 9 VWHSXSBIESURW FON NŸ VWSXSBRQ 0+] N+] 9 9 9 9 HUURWD VWHSXSBIE +9&XUUHQW6LQNV (DFKP$ $XWRPDWLF IHHGEDFNVHOHFW &855 /('VDVUHTXLUHG E\WKHDSSOLFDWLRQ &855 &855 96833/< &855 2SWLRQDORQO\UHTXLUHG LI&855FDQ H[FHHG9 FXUU;BFWUO   DCDC Step-Up Converter Block Diagram: Shows the internal structure of the DCDC boost controller including external components. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 33 Document Feedback AS3715 − Detailed Description – Power Management Functions Feedback Selection For the step up the following feedback selections are possible (selected by setpup2_fb): (see Figure 34) Current Feedback CURR1, CURR2 and CURR3 can be selected by setpup2_fb as a current feedback pin. The step-up converter is regulated such that the required current at the feedback path can be supported. In this mode the output voltage will be limited by limiting the voltage on the selected feedback pin to 1.25V (select the external resistor network and stepup2_v to adjust this limitation voltage). stepup2_prot_dis has to be set to 0, otherwise the protection is disabled. Always choose the path with the higher voltage drop as feedback to guarantee adequate supply for the other, unregulated path. Current Feedback with Automatic Feedback Selection Same as above, but when currX_ctrl = 10b for the used current sinks, the chip automatically selects the highest string (CURR1, CURR2 or CURR3) as feedback input. Voltage Feedback The step-up converter output voltage is regulated by regulating the selected feedback pin voltage to 1.25V. Calculating Resistors for Voltage Feedback or Over-Voltage Protection Bit stepup_res should be set to 1 in voltage feedback mode using two resistors. The output voltage is regulated to a constant value, given by: (EQ1) R1 + R2 V SU = -------------------  1.25 + I FB  R 1 R2 If R2 is not used, the output voltage is: (EQ2) V SU = 1.25 + I FB  R 1 V SU: Step up regulator output voltage R1 Feedback resistor R1 R2 Feedback resistor R2 I FB: Tuning current on FB_SU pin: stepup2_v (0..31μA (1μA steps)) Page 34 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 35: SU Output Voltage or Protection Voltage SU Output Voltage or Protection Voltage: Shows examples of possible output or protection voltages of the DCDC SU depending on external resistors and FB_SU current settings. ams Datasheet, Confidential [v1-00] 2014-Sep-10 IFB (stepup2_v) VSU VSU µA R1=1MΩ, R2 not used R1=500kΩ, R2 = 64kΩ 0 - 11 1 - 11.5 2 - 12 3 - 12.5 4 - 13 5 6.25 13.5 6 7.25 14 7 8.25 14.5 8 9.25 15 9 10.25 15.5 10 11.25 16 11 12.25 16.5 12 13.25 17 13 14.25 17.5 14 15.25 18 15 16.25 18.5 16 17.25 19 17 18.25 19.5 18 19.25 20 19 20.25 20.5 20 21.25 21 21 22.25 21.5 … … … 30 31.25 26 31 32.25 26.5 Page 35 Document Feedback AS3715 − Detailed Description – Power Management Functions Parameter Figure 36: DCDC SU Parameter Symbol Parameter Conditions Min Typ Max Unit IVDD Quiescent Current Pulse skipping mode VFB Feedback voltage for external resistor divider For constant voltage control VCURR Feedback voltage for current sink regulation CURR1, CURR2, CURR3 Additional tuning current at FB_SU Adjustable by software in 1μA steps 0 31 μA Accuracy of feedback current @ full scale -7 7 % max Current limit voltage at Rsense E.g.: 0.65A for 0.15Ω sense resistor RSW Switch resistance ON-resistance of external switching transistor Iload Load current At 25V output voltage Switching frequency Internal CLK frequency/4, default 1MHz IDCDC_FB Vrsense_ fIN tMIN_ON MDC 140 1.20 1.25 1.30 0.6 0 V V 100 mV 1 Ω 50 mA fclk_int/4 MHz 130 ns 91 % Minimum ON time Maximum duty cycle μA @ 1MHz DCDC SU Parameter: Shows the key electrical parameter of the DCDC boost converter. Page 36 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 37: DCDC SU External Components Symbol Parameter Conditions Min Typ Max Unit Cout Output capacitor ceramic, ±20% 2.2 μF LSU Inductor Use inductors with small Cparasitic (8V 10 μH Use inductors with small Cparasitic (0 and charging time has been exceeded. (Can be reset by unplugging the charger, setting bat_charging_enable=0 or writing charging_tmax=0) • VUSB over-voltage detected • Die temp>140deg (ov_temp_140 set) • All reset reasons ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 45 Document Feedback AS3715 − Detailed Description – Power Management Functions Battery Presence Indication After EOC state is reached a timer for NOBAT detection is started. If there is no battery present, the VBAT voltage will drop to V RESUME. Depending on the load on VBAT and the capacitor on VBAT this might take some milliseconds to 1 second. If the RESUME mode is enabled (bit auto_resume=1), the charger will restart charging (ConstantCurrent charging) after 100msec delay. The 100msec dead time is necessary to get a battery oscillation frequency below 10Hz, if there is no battery present. If the NOBAT detection timer is below 2 seconds after reaching EOC state, and this happens 2 times in serial, the Nobat bit in ChargerStatus register is set. If a battery is inserted the bit will be reset after the timer exceeds the 2 seconds. Charger Overvoltage Protection This blocks checks if the charger voltage VUSB is above VCHOVH. If the VUSB voltage is above VCHOVH , the pin XOFF is pulled to GND immediately, to protect the pin VCHG_IN, and the charger is set into OFF state. If the VUSB voltage is below VCHOVH the XOFF pin is charged up to VXOFF_REG with an integrated charge pump. If the pin exceeds VXOFF_MIN the bit is set and the charger is started. NTC Supervision This charger block also features a supply for an external NTC resistor to measure the battery temperature while charging. If the temperature is too high the charger will stop operation. If needed an interrupt can be generated based on this event. When the battery temperature drops the voltage on BATTEMP pin will rise above VBATTEMP_OFF and the charger will start charging again. This is forming a temperature hysteresis of about 3 to 5°C to avoid an oscillation of the charger. The type of NTC (ntc_10k:10k or 100k) can be selected via register settings. The battery temperature supervision via the NTC can be switched OFF (ntc_on= 0). The supply for the NTC will be on when the ntc_on bit is set, no matter if a charger is detected or not. NTC ß-Correction To keep the voltage drop over the whole temperature range inside of the ADC input range a parallel resistor to the NTC is needed. Page 46 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Figure 45: NTC ß Influence VNTC [V] 1.80 1.60 2750 1.40 3250 1.20 3750 1.00 4250 0.80 4750 0.60 0.40 0.20 0.00 0 10 20 30 40 50 60 Temp [°C] NTC ß Influence Diagram: Shows the voltage drop on the NTC over temperature for different ß using RNTC=10kΩ, Rp=15kΩ and INTC=150uA. The chip is supporting up to 4 temperature levels for supervision. Figure 46: NTC Supervision ß 2750 3250 3750 4250 4750 K T1 e.g.: 0 C 1,37 1,45 1,53 1,60 1,67 V T2 e.g.: 10 C 1,17 1,22 1,27 1,32 1,37 V T3 e.g.: 45 C 0,61 0,57 0,52 0,48 0,44 V T4 e.g.: 60 C 0,45 0,39 0,34 0,29 0,25 V NTC Supervision: Example threshold voltages for different temperatures and ß using RNTC=10kΩ, Rp=15kΩ and INTC=150uA. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 47 Document Feedback AS3715 − Detailed Description – Power Management Functions The base values (T1min, T2min, T3min and T3min) for the comparator levels are marked in the table above. To adjust the comparator levels to the needed temperature levels dedicated adjust bits can be set (32-64 7mV steps). (EQ3) Txlim_upper=Txmin + Tx_adj * 7mV Also the hysteresis of the ON and OFF levels can be programmed (4bits with 16 7mV steps). (EQ4) Txlim_lower=Txlim_upper + (Tx_hyst + 3) * 7mV Charger MIN/MAX Temp Supervision The simpler supervision mode is supervising T1 (0°C) and T4 (60°C) Figure 47: MIN/MAX Temp Supervision Maximum Charge Current: 1C 750mA < Icc_normal(typ) < 1500mA 350mA < Icc_low(typ) < 750mA CHARGE CURRENT 60mA < Itrickle(typ) < 240mA TYPICAL COLD Charger is OFF Typical Charge Voltage: Veoc(typ) HOT Charger is OFF 3.5V < Veoc(typ) < 4.44V CHARGE VOLTAGE T4upper T1upper T1lower TEMPERATURE [°C] T4lower MIN/MAX Temp Supervision Diagram: Shows the voltage and current settings for the MIN/MAX temperature supervision. Page 48 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Charger JEITA Temp Supervision The more complex JEITA temperature supervision is monitoring T1 (0°C), T2 (10°C), T3 (45°C) and T4 (60°C) and adjusting charging current and voltage to it. Figure 48: JEITA Temp Supervision Maximum Charging Current 1C 750mA < Icc_normal(typ) < 1500mA 350mA < Icc_low(typ) < 750mA 60mA < Itrickle(typ) < 240mA CHARGE CURRENT 0.5C 350mA < Icc_normal(cool) < 750mA 350mA < Icc_low(cool) < 750mA 60mA < Itrickle(cool) < 120mA COLD COOL Charger is OFF TYPICAL WARM HOT Charger is OFF Typical Charge Voltage: Veoc(typ) 3.5V < Veoc(typ) < 4.44V CHARGE VOLTAGE Veoc(warm)=Veoc(typ)-100mV 3.5V < Veoc(warm) < 4.34V T1upper T1lower T2upper T2lower T3upper TEMPERATURE [°C] T3lower T4upper T4lower JEITA Temp Supervision Diagram: Shows the voltage and current settings for the JEITA temperature supervision. Dual Battery Switching The charger is only charging the battery connected to CHGOUT/VIBAT, but can handle to batteries and controls the external battery switches accordingly. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 49 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 49: Dual Battery Switching(Flowchart) Dual Battery Switching Diagram: Shows the state diagram for controlling two batteries to the PMIC. Page 50 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Dual Power Path Two charger inputs can be used to hook up two different charger supplies. CHGIN1 as an optional protection function with an external NMOS using VUSB1 as sensing input. Figure 50: Dual Power Path Diagram VUSB1 + VBAT ‐ CHDET_USB1 + ‐ 3.95V CHGIN 2 VUSB2 + VBAT ‐ + VUSB2 3. 95V MAX(CHGIN1,CHGIN 2,VSUP_CHG ) VUSB1 CHDET_USB2 ‐ MAX(CHGIN1,CHGIN 2,VSUP_CHG) XOFF LDO CURRLIM 1 PWRSELECT CHGIN 1 PWRSELECT External OVP optional CURRLIM 2 VSUP_CHG VBAT Dual Power Path Diagram: Shows the internal structure of the dual power path input. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 51 Document Feedback AS3715 − Detailed Description – Power Management Functions Figure 51: USB Input Selection VUSB2 > VBAT+VCHMIN and VUSB2 > 3.95V VUSB2 < VBAT+VCHMIN or VUSB2 < 3.95V en_usb2=0 VUSB1 > VBAT+VCHMIN and VUSB1 > 3.95V Device is powered from VUSB1 VUSB1 < VBAT+VCHMIN or VUSB1 < 3.95V No charge No charge en_usb2=1 VUSB1 > VBAT+VCHMIN and VUSB1 > 3.95V VUSB1 < VBAT+VCHMIN or VUSB1 < 3.95V Device is powered from VUSB1 Device is powered from VUSB2 No charge Dual Power Path Diagram: Shows the priority of the charger input depending on en_usb2 setting and the charger input voltages Parameter Figure 52: Charger Parameter Symbol VCHDET VCHMIN Parameter Charger Detection threshold Conditions VUSB-VBAT Hysteresis is > 40mV Min Typ Max Unit 50 75 105 mV 0 20 35 mV VSOFT Apply ISOFT charging current below that VBAT voltage 1.8 V ISOFT Charging current if VBAT is below VSOFT 22 mA VTRICKLE Trickle to CC current threshold VBAT rising 2.9 V ITRICKLE Trickle/EOC current limit Programmable in 60mA steps 60.. 240 mA Programmable in 20mV steps between 3.5 and 4.44V 3.5.. 4.44 V VCHOFF Charge termination threshold Page 52 Document Feedback @ ChVoltEOC=35 (4.2V) 4.15 4.20 4.242 V @ ChVoltEOC= 47 (4.34V) 4.29 4.34 4.38 V ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – Power Management Functions Symbol Parameter Conditions Min CC current limit Linear charging mode -10 -7% IUSB_limit USB input current limit @ 470mA VRESUME Resume voltage limit to start charger VBAT falling threshold relative to ChVoltEOC (depending on ChVoltResume) VSUP_min VSUP level for charging current regulation (reduction), to avoid voltage drop on VSUP Trickle current (or constant current in linear mode) will be regulated down, if VSUP drops below this level Max 350.. 1500 Programmable in 50mA steps ICC Typ 470 Unit mA +10 % +6% mA -3.3 or -5.6 % 3.9 4.2 -6% 3% V 4.5 4.7 IREV_OFF VDiode RON_BATSW Reverse current shut down VSUP_CHG = 5V, VUSB open Ideal Diode start voltage Battery Switch ON-resistance 5 μA 50 mV 0.20 Ω Temp Supervision IBATTEMP 100kΩ NTC 10kΩ NTC NTC Bias Current -15% 15 150 +15 % 6.2 +3% μA XOFF Overvoltage Protection VCHOVH VUSB Overvoltage Detection monitor voltage on VUSB, disable charging beyond this voltage (200mV hysteresis) V -3% 6.0 VXOFF_min Minimum XOFF voltage for charger startup 7.5 V VXOFF_REG Regulation voltage for XOFF pin 10 V IXOFF External pull down current on XOFF pin Connect XOFF pin to MOSFET gates only 100 nA Charger Parameter: Shows the key electrical parameter of the charger and power paths. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 53 Document Feedback AS3715 − Detailed Description – Power Management Functions 1.2 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 1 Input Current (A) Efficiency (%) Figure 53: Charger Efficiency and Input Current SD charger 4.5V linear charger 4.5V 0.8 0.6 0.4 SD charger 4.5V linear charger 4.5V 0.2 SD charger 5V SD charger 5V linear charger 5V linear charger 5V 0 1 2 3 4 1 5 2 Battery Voltage (V) 3 4 5 Battery Voltage (V) Charger Efficiency and Input Current: Shows the efficiency of the charger in step-down and linear mode as well as the current from the charger input in both modes for 1A charging current. Figure 54: Charger Power Dissipation 2.5 SD charger 4.5V Internal Power Dissipation (W) Charger Power Dissipation: Shows the power dissipation of the charger in step-down and linear mode for 1A charging current. linear charger 4.5V 2 SD charger 5V linear charger 5V 1.5 1 0.5 0 1 2 3 4 5 Battery Voltage (V) Page 54 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – System Functions Detailed Description – System Functions Start-up Figure 55: Start-up flow chart Start-Up Battery or Charger insertion 1. V 2_5 power up 2. Readout ROM fuse VSUP debounce state N auto _off=1 Measuring VSUP Quiesent current ~200uA N Y auto_off=1 or power _off_at_vsuplow =1 Y POWER OFF state ONKEY=RISING OR ENx=RISING OR (chdet =1 && chg_pwr_off_en=0) OR (chdet_rise && chg_pwr_off _en=1) V2_5 power up Quiescent current < 10 uA Pin ONKEY debounce time =20 msec Y ONKEY=1 or Charge detect =1 N N VSUPResVoltRise Y Y N N Y power _off=1 OR (VSUP110°C wait off_delay regulator startup sequnece GPIO programming during sequence startup delay programmable set sdX_sequ_ on=1 or ldoX _sequ_ on=1 if regulator selected during startup Y Reset all Registers Switch off Regulators RESET Timer regulator startup executed waiting time to release XRES pin 10..150ms reset registers and reload fuses 0xA0 to 0xAB except: pwr_ off_at_vsup_low N Y Die temp>140 °C ACTIVE state any state XRES=1 Sequence Down Y force off all regulators not in the sequence; sequence down inverse to start-up sequence; OFF delay wait off_delay Y power_off=1 or force _reset=1 or XRES is low or ONKEY lpress N N VSUP140°C or SD4 overtemp force_reset=1 or (XRES is low if stdby _reset _disable=1) or VSUP140 °C STAND-BY state N V 2_5 stays active, all regulators with regX _stby_ on=1 enabled OFF delay N wait off_delay standby _mode_on=1 or GPIOx =1 if GPIOx _iosf=6 N any interrupt applied or ONKEY=1 or ENx=1 Y remove „stand -by force off“ of all regulators Start-up flow chart: Shows the main state transitions during start-up. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 55 Document Feedback AS3715 − Detailed Description – System Functions Normal Startup The following gives a brief description on a start-up from scratch (battery insertion). More details can be found in the start-up flow charts. • Powering up V2_5 (wait till it’s above V POR) • The external capacitor on CREF is charged to 1.8V. • Check if VSUP is above ResVoltRise • Configuration of Charger (DCDC or linear) and SDx slave modes is read from Boot-OTP • Startup State machine reads out the internal Boot-OTP. The start-up sequence of Step-Down Converter, LDO’s and GPIOs are controlled by the Boot-OTP. • Reset-Timer is set by the Boot-OTP • The reset is released when the Reset Timer expires (external pin XRES) Figure 56: Regulator Power-up Sequence VSUP VSUP > ResVoltRise set in OTP 4ms debounce Reg1_select 0, 1, 4 or 12ms delay depending on Reg1_gpio_sel and del _time 0, 1, 4 or 12ms delay depending on Reg2_gpio_sel and del _time Reg2_select ... ....... 0, 1, 4 or 12ms delay depending on Reg11_gpio_sel and del _time Reg11_select 10..150ms set by res_timer in OTP XRES Regulator Power-up Sequence: Shows timing relationships of the regulators and corresponding control signals during power-up. Page 56 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – System Functions Start-up Reasons A Start-up can be activated from 4 different sources: • VPOR has been reached (VUSB/VSUP/VBAT rising from scratch) • ONKEY or ENx has been pulled high in power_off mode • Reset cycle • ResVoltRise was reached Parameter Figure 57: ONKEY/ENx-input Start-up Conditions Symbol Min Typ Max Unit Voltage in VUSB for system to start 4.2 5.0 30 V VON_IL ONKEY/ENx Low Level input voltage –0.3 0.4 V VON_IH ONKEY/ENx High Level input 1.4 VVSUP_ V ION_PD ONKEY/ENx Pull down current 5 VUSBON Parameter Conditions GPIO 12 20 μA ONKEY-input Start-up Conditions: Shows the electrical parameter for the ONKEY input initiating the start-up. Reset Description XRES is a low active bi-directional pin. An external pull-up to the periphery supply has to be added. During each reset cycle the following states are controlled by the AS3715: • Power-down sequence of the regulators • Pin XRES is forced to GND • All registers are set to their default values after power-ON, except the reset control- and status-registers. • Normal startup with programmable power-ON sequence and regulator voltages (see Start-up) • Reset is active until the programmable reset timer expires (set by register bits res_timer) ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 57 Document Feedback AS3715 − Detailed Description – System Functions Reset Reasons Reset can be activated from 8 different sources: • VPOR has been reached (VSUP/VBAT rising from scratch) • VSUP low, ResVoltFall (2.5V) has been reached • Software forced reset by force_reset • ONKEY or ENx long press has been detected • External triggered through the pin XRES • Over-temperature T140 (die) • Over-temperature T140 SD4 (sub die) • Watchdog Voltage Detection: There are two types of voltage dependent resets: V POR and V RESRISE. V POR monitors the voltage on V2_5 and V RESRISE monitors the voltage on VSUP. The linear regulator for V2_5 is always ON and uses the voltage VUSB/VBAT/VSUP as its source. The pin XRES is only released if V2_5 is above V POR, VSUP is above ResVoltRise. V RESFALL is only accepted if the reset condition is longer than V RESMASK . This guard time is used to avoid a complete reset of the system in case of short drops of VBAT. Figure 58: VSUP Supervision SupResEn power_off_at_vsuplow auto_off Behavior if VSUPResVoltRise 1 0 1 Reset cycle is initiated, PMIC will move to “VSUP debonce” state and try to start-up if VSUP>ResVoltRise, if not it will go to the “Power OFF” state 1 1 x Reset cycle is initiated, PMIC will move to “Power OFF” state VSUP Supervision: Describes the behavior of the PMIC when VSUP drops below ResVoltFall depending on OTP bit settings. Page 58 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – System Functions Power OFF: To put the chip into ultralow power mode, write ‘1’ into power_off. The chip stays in power OFF mode until it gets a wakeup signal from either the ON pin or from a charger insert. For more details see the start-up flowchart (Figure 55). The bit power_off is automatically cleared by this reset cycle. During power_off state all circuits are shut-off except the Low Power LDO (V2_5). Thus the current consumption of AS3715 is reduced to about 13μA (if only supplied via VIBAT). The digital part is supplied by V2_5, all other circuits are turned OFF in this mode, including references and oscillator. Except the reset control registers all other registers are set to their default value after power-ON. Below table show the behavior of the PMIC in terms of USB pre-regulator and battery switch operation supplying VSUP when putting the PMIC into power_off state by setting power_off=1 Figure 59: Pre-Regulator and Battery Switch Operation # Battery USB present chg_pwr_off_en 1 don’t care YES =1 PMIC enter power_off mode. Pre-regulator powered down, VSUP_CHG not powered 2 don’t care YES =0 PMIC enter power_off mode and power ON again. VSUP_CHG powered by the pre-regulator 3a IBAT attached NO don't care PMIC enter power_off mode. VSUP_CHG connected to VIBAT via the internal battery switch 3b EBAT attached NO don’t care PMIC enter power_off mode. VSUP_CHG not powered States of VSUP_CHG Pre-Regulator and Battery Switch Operation: Shows the VSUP behavior under different supply conditions and settings when setting power_off=1. Software Forced Reset Writing ‘1’ into the register bit force_reset immediately starts a reset cycle. The bit force_reset is automatically cleared by this reset. External Triggered Reset: If the pin XRES is pulled from high to low by an external source (e.g. microprocessor or button) a reset cycle is started as well. Over-temperature Reset: The reset cycle can be started by over-temperature conditions. (see Supervisor) ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 59 Document Feedback AS3715 − Detailed Description – System Functions Watchdog Reset: If the watchdog is armed (register bit wtdg_on = 1 and wtdg_res_on= 1) and the timer expires it causes a reset. (see Watchdog). Long ONKEY/ENx Press: When applying a high level on the ONKEY or ENx input pins for 4s/8s (depending on on_reset_delay) a reset or power_off (depending on onkey_lpress_reset) is initiated. This is thought as a safety feature when the SW hangs up and no watchdog is used. Figure 60: ONKEY/ENx Longpress Behavior onkey_lpress_reset on_reset_delay longpress behavior 0 0 power_off after 8s long press delay 0 1 power_off after 4s long press delay 1 0 reset_cycle after 8s long press delay 1 1 long press feature disabled ONKEY/ENx Longpress Behavior: Shows the slectalbe options for behaving on a long press. Reset and Power-OFF Sequence The regulator power-down sequence is inverted to the power-up sequence programmed in the OTP. It can be slightly modified by setting or clearing the sdX_sequ_on and ldoX_sequ_on bits. The bit is set automatically for all the regulators defined in the OTP start-up sequence. • Regulators which have the corresponding sequ_on bit cleared will be shut down before the power-down sequence starts. • Regulators which have the bit set and are in the power-up sequence of the OTP will shut down in an inverted order. • Regulators which have the bit set and are not part of the power-up sequence will shut down after the sequence has been completed. Page 60 Document Feedback ams Datasheet, Confidential [v1-00] 2014-Sep-10 AS3715 − Detailed Description – System Functions Figure 61: Regulator Power-down Sequence VSUP < ResVoltFall or ONKEY lpress or power_off = 1 or force_reset = 1 or XRES = low or die temp >140°C or VSUP 4ms debounce for VSUP only off_delay = 0, 8, 16 or 32ms XRES all regulators not in the sequence Reg11_select Reg10_select ... Reg2_select 0, 1, 4 or 12ms delay depending on Reg11_gpio_sel and del _time 0, 1, 4 or 12ms delay depending on Reg10_gpio_sel and del _time ...... 0, 1, 4 or 12ms delay depending on Reg2_gpio _sel and del_time Reg1_select Regulator Power-down Sequence: Shows timing relationships of the regulators and corresponding control signals during power-down. ams Datasheet, Confidential [v1-00] 2014-Sep-10 Page 61 Document Feedback AS3715 − Detailed Description – System Functions Parameter Figure 62: Reset Levels Symbol Conditions Min Typ Max Unit Overall power ON reset Monitor voltage on V2_5; power ON reset for all internal functions 1.5 2.0 2.3 V VRESRISE Reset level for VSUP rising Monitor voltage on VSUP; rising level ResVoltRise(1) V Monitor voltage on VSUP; falling level 2.7 V VRESFALL Reset level for VSUP falling if SupResEn=1 ResVoltFall V FastResEn = 0 3 ms FastResEn = 1 4 us VPOR VRESMASK Parameter Mask time for VRESFALL. Duration for VBAT