AS3605F-BQFP

Data Sheet AS3605 Multi-Standard Power Management Unit 1 General Description The AS3605 is a highly-integrated CMOS power management device designed specifically for portable devices such as mobile phones, PDAs, CD players, digital cameras and other devices powered by 1-cell Li-Ion battery. It can be used for any mobile phone handset standards such as CDMA, WCDMA, GSM, GPRS, EDGE, UTMS and other Japanese or American standards. The device incorporates low dropout regulators (LDOs), a DC/DC converter, a complete battery charger, and an audio power amplifier on one die. The linear analog LDOs feature extremely high performance regarding: - Noise – typ 30µ VRMS from 100Hz to 100kHz - Line/Load Regulation – < 1mV static, < 10mV transient - Power Supply Rejection – > 70dB @ 1kHz The integrated Step Down DC/DC Converter does not require an external Schottky diode yet provides very high efficiency (up to 95%) throughout the whole operating range. 5 programmable current sources are included to control LED brightness. A low-distortion audio power amplifier (1 Watt @ 8Ω) supports handsfree operation and HiFi ring-tones. The device also features a battery charger including automatic trickle charging, and programmable constant voltage and current charging. The AS3605 is controlled via a serial interface and integrates all necessary system specific functions such as Reset, Watchdog, and Power-On Detection. Output voltages and start-up timings can be programmed via the internal OTP. Battery Charger - Automatic Trickle Charging Programmable Constant Current Charging Programmable Constant Voltage Charging Safety Functions (Low Battery Shutdown) Over- and Under-Temperature Charge Disable Operation without Battery Can Regulate the Current Through the Battery or from the Charger - Charger Input Overvoltage Protection (6V) - Shutdown even with Connected Charger - Charger Resume Operation - Charger Interrupts (Inserted, Removed, Overvoltage, Resume) - No-Battery Detection Momentary Power Loss Detection - Battery Supply Short-Interruption Detection ( 200 @ 0.8A RSENSE Current sense resistor 100mΩ ±1%, 125mW for ICHG < 1.5A e.g. Vishay Dale WSL0805 CCHRG Bypass capacitor on charger pin 10µ F ±20%, X5R or X7R dielectric CBAT Minimum total capacitance parallel to battery 10µ F, X5R or X7R dielectric www.austriamicrosystems.com 1.00 11 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.1.1 Charge Controller Operating Modes and Building Blocks Charge Adapter Detection. The charge controller uses an integrated detection circuit to determine if an external charge adapter has been applied to the VCHARGER pin. If the adapter voltage exceeds the battery voltage at pin VBAT by VCHDET the ChDet bit in the ChargerStatus register will be set. The detection circuit will reset the charge controller (bit ChDet is cleared) as soon as the voltage at the VCHARGER pin drops to only VCHMIN above the battery voltage. In case the AS3605 device is reset the charge controller will also be reset, even if a charge adapter is applied to the VCHARGER pin. Low Current (trickle) Charging. Trickle charge mode is started when an external charge adapter has been detected and the battery voltage at pin VBAT is below the VUVLO threshold; bits ChAct and Trickle will be set in the ChargerStatus register. In this mode the charge current will be limited to TrickleCurrent[1:0] (set in the ChargerControl1 register) to prevent undue stress on either the battery or any of the charger components in case of deeply discharged batteries. Once VUVLO has been exceeded, the charger will change over to constant current charging (Trickle is cleared) and switch on the device. Constant Current Charging. Constant current charging is initiated by setting ChEn in the ChargerControl1 register. Note that ChEn is set by default to enable operation of the device without a battery connected to the system. The ChAct bit is set when the charger has started, and the charge current will be limited to ConstantCurrent[3:0] (set in the ChargerControl1 register) by the battery charge controller. When the battery approaches full charge, its voltage will exceed the charge termination threshold VCHOFF. VCHOFF depends on the Li4v2 bit in the ChargerControl2 register. The charging action will either be terminated (EOC bit will be set) or a top-off charge will be started (CVM will be set). Constant Voltage Charging. Constant voltage charge mode is initiated and the CVM bit will be set when the VCHOFF threshold has been reached. The charge current is monitored during constant voltage charging. It will be decreasing from its initial value during constant current charging and eventually drop below the value set by TrickleCurrent[1:0] in the ChargerControl1 register. If the measured charge current is less than or equal to TrickleCurrent[1:0], the charging cycle is terminated and EOC is set. Battery Presence Indication and Operation Without Battery. After EOC state is reached a timer for NOBAT detection is started. If there is no battery present, the voltage will drop to VNOBAT_REG. Depending on the load on VBAT and the capacitor on VBAT this might take some mseconds to 1 second. If the RESUME mode is enabled (Bit resume_disable=0), the charger will restart charging (ConstantCurrent charging) after 100msec. The 100msec dead time is necessary to get a battery oscillation frequency of below 10Hz, if there is no battery present. If the NOBAT detection timer is below 2 seconds after reaching EOC state, and this happens 2 times in serial, the NOBAT bit in ChargerStatus register is set. If a battery is inserted, then the bit will be reset after the timer exceeds the 2 seconds. Charger Overvoltage Protection. This blocks checks if the charger voltage is above 6.05V or 6.45V if ChOvH is 1. If the status bit ChOv is 1 when ChOvEn is 1, the charger will shut down by clearing the ChEn bit and an interrupt will be generated. Table 5. Charger Parameters Symbol VCHDET VCHMIN Parameter Charger detection threshold VCHOVH VCHARGER overvoltage detection VUVLO Undervoltage lockout threshold VCHOFF Charge termination threshold VNOBATREG “No battery” regulation voltage VRESUME_ON Charger resume on threshold www.austriamicrosystems.com Min Typ Max 50 75 105 0 20 35 6.2 6.45 6.71 5.81 6.05 6.29 3.1 4.20 mV V V 2.8 4.158 Unit 4.242 4.10 3.85 V V 3.75 3.85 V 3.75 1.00 Notes Hysteresis is > 40mV ChOvH = 1 ChOvH = 0 VBAT rising VBAT falling Li+ Battery: Li4v2 = 1 Li+ Battery: Li4v2 = 0 Li+ Battery: Li4v2 = 1 Li+ Battery: Li4v2 = 0 Li4v2 = 1 Li4v2 = 0 12 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 5. Charger Parameters Symbol Parameter VRESUME_OFF Charger resume off threshold IGATE_OFF Current into pin GATE, if charger disabled 0 IGATE_ON Current into pin GATE, if charger enabled and operation in low dropout mode (low VCE) 3.5 7.1.2 Min Typ Max Unit 4.02 V 3.92 0.4 5 Notes Li4v2 = 1 Li4v2 = 0 µA VCHARGER=5V mA VCHARGER=5V Charger Registers Table 6. Charger Register Summary Name Addr. LDO_CHG 10h ChargerControl1 14h b7 b6 b5 b4 b3 b2 b1 b0 EOCCurrent[1:0] ChOvEn TrickleCurrent[1:0] ConstantCurrent[3:0] ChargerControl2 16h ChOv ChOvH NA Li4v2 resume_d isable ChargerStatus 35h NA NoBat EOC CVM Trickle Page 14 ChEn 13 14 NA ChAct ChDet 15 ChargerControl1 Register (Address 14h). ChargerControl1 Addr: 14h Bit Bit Name Default Access 0 ChEn 1b R/W 4:1 ConstantCurrent[3:0] www.austriamicrosystems.com OTP R/W Bit Description 0 Disable charging 1 Enable charging 0 0mA + Trickle_current 1 50mA + Trickle_current 2 100mA + Trickle_current 3 150mA + Trickle_current 4 200mA + Trickle_current 5 250mA + Trickle_current 6 300mA + Trickle_current 7 350mA + Trickle_current 8 400mA + Trickle_current 9 450mA + Trickle_current A 500mA + Trickle_current B 550mA + Trickle_current C 600mA + Trickle_current D 650mA + Trickle_current E 700mA + Trickle_current F 750mA + Trickle_current 1.00 13 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n ChargerControl1 Addr: 14h Bit 6:5 7 Bit Name Default TrickleCurrent[1:0] Access OPT ChOvEn R/W 1 R/W Bit Description 0 50mA 1 100mA 2 150mA 3 200 mA 0 Disable the Charger Overvoltage protection 1 Enable the Charger Overvoltage protection LDO_CHG Register (Address 10h). LDO_CHG Addr: 10h Bit 3:2 Adjusts EOC current of Charger. Bit Name EOCCurrent[1:0] Default Access 00 R/W Bit Description 00 EOC Current = Trickle Current 01 EOC Current = Trickle Current + 18mA 10 do not use 11 EOC Current = Trickle Current + 33mA ChargerControl2 Register (Address 16h). ChargerControl2 Addr: 16h Bit Bit Name Default Access 2:0 - NA NA 3 resume_disable 0 R/W 4 Li4v2 1 R/W 5 - NA NA 6 7 ChOvH ChOv www.austriamicrosystems.com 1 NA Bit Description 0 Enable Resume in EOC state 1 Disable Resume in EOC state 0 VCHOFF = 4.1V for Li+ battery cells with coke anode 1 VCHOFF = 4.2V for Li+ battery cells with graphite anode 0 Sets low threshold for Over voltage protection (typ. 6.05V) 1 Sets high threshold for Over voltage protection (typ. 6.45V) R/W R Indicates Charger overvoltage condition 1.00 14 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n ChargerStatus Register (Address 35h). ChargerStatus Addr: 35h Read only Bit Bit Name Default Access 0 ChDet NA R Bit is set when external charge adapter has been detected 1 ChAct NA R Bit is set when charger is operating 2 - NA 3 Trickle NA R Bit is set when charger is in trickle charge mode 4 CVM NA R Bit is set when charger is in top-off charge mode 5 EOC NA R Bit is set when charging has been terminated. Bit is cleared automatically when ChEn is cleared. 6 NoBat NA R Bit is set when battery detection circuit indicates that no battery is connected to the system. Bit is cleared automatically when a battery is connected or when ChEn is cleared. 7 - NA NA www.austriamicrosystems.com Bit Description 1.00 15 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.2 Step Down DC/DC Converter The step-down converter is a high-efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches, efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 500mA, with an output capacitor of only 10µ F. The implemented current limitation protects the DC/DC Converter and the coil during overload condition. Figure 5. Step Down DC/DC Converter Block Diagram 170mA IMIN buck_dis_curmin 2.2MHz VBAT2 800mA ILIMIT ISENSP C16 1µF Overvoltage Comparator Ref + 8% + Skip – PSW buck_dis_pon LX Ref - 4% Logic L2 2.2µH + – 100% Duty Cycle NSW VOUT C18 10µF PWM Comparator GND_PAD – + ISENSN Zero Comparator Σ VBUCK AS3605 Ref = 0.6V + – buck_v Skip Softstart Slope Compensation www.austriamicrosystems.com 1.00 16 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 7. Step Down DC/DC Converter Parameters Symbol Parameter Min Typ Max Unit VIN Input Voltage VOUT Regulated Output Voltage VOUT_TOL Output Voltage Tolerance ILIMIT Current Limit 3.0 5.5 V Pin VBAT_2 0.6 3.4 V Sense pin VBUCK -50 50 mV -3% 3% RPSW PSW On-Resistance 0.5 Ω RNSW NSW On-Resistance 0.5 Ω ILOAD Load Current 500 mA fSW Switching Frequency 2.2 MHz COUT Output Capacitor 10 µF Lx Inductor 2.2 µH h Efficiency 90 % 900 0 Current Consumption 100 Sense pin VBUCK; Output Voltage < 1.6V Sense pin VBUCK; Output Voltage > 1.6V mA Supply current into PMOS transistor Ceramic ILOAD = 100mA, VOUT = 2.3V, VBAT = 3V Operating Current; No Load 250 IVDD_DCDC Notes µA Quiescent Current; Low-Power Mode Shutdown Current 0.1 tMIN_ON Minimum ON Time 80 ns tMIN_OFF Minimum OFF Time 40 ns To allow optimized performance in different applications, there are bit settings possible, to get the best compromise between high efficiency and low input/output ripple. 7.2.1 Low-Ripple, Low-Noise Operation Low-ripple, low-noise operation can be enabled by setting bit buck_dis_curmin = 1. In this mode there is no minimum coil current necessary before switching OFF the PMOS. As result, the ON time of the PMOS will be reduced down to tMIN_ON at no or light load conditions, even if the coil current is very small or the coil current is inverted. This results in a very low ripple and noise (but decreased efficiency) at light loads, especially at low input-to-output voltage differences. Note: Because of the inverted coil current in that case the regulator will not operate in pulse skip mode. www.austriamicrosystems.com 1.00 17 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 6. Bit buck_dis_curmin = 1 Operation LX Voltage Coil Current (1mV=1mA) VOUT 7.2.2 High-Efficiency Operation (Default Setting) High-efficiency operation is enabled by setting bit buck_dis_curmin = 0. In this mode there is a minimum coil current necessary before switching OFF the PMOS. As result there are less pulses at low output load necessary, and therefore the efficiency at low output load is increased. This results in higher ripple, and noisy pulse skip operation up to a higher output current. Figure 7. Bit buck_dis_curmin = 0 Operation LX Voltage Coil Current (1mV=1mA) VOUT Note: It is possible to switch between these two modes during operation, i.e.: Bit buck_dis_curmin = 0: System is in idle state. No audio or RF signal. Decreased supply current preferred. Increase ripple doesn't effect system performance. www.austriamicrosystems.com 1.00 18 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Bit buck_dis_curmin = 1: System is operating. Audio signal on and/or RF signal used. Decreased ripple and noise preferred. Increased power supply current can be tolerated. 7.2.3 100% PMOS ON Mode for Low Dropout Regulation For low input-to-output voltage difference bit buck_dis_pon can be set to allow 100% duty cycle of the PMOS transistor, if the output voltage drops by more than 4% below regulation. 7.2.4 Low Power Mode Bit buck_lpo can be set all the time. This mode allows internal power down, of not used blocks during pulseskip mode, which results in a better efficiency at light output loads. 7.2.5 Typical Performance Characteristics Figure 8. DC/DC Step-Down Efficiency vs. Output Current (buck_dis_cfm = 0) DCDC buck Efficiency @2MHz, 3.6V VBAT2 100 95 Efficiency [%] 90 85 80 Vbuck @ 1,2V 75 Vbuck @ 1,8V Vbuck @ 2.5V 70 Vbuck @ 1.2V lpo = 1 Vbuck @ 1.8V lpo = 1 65 Vbuck @ 2.5V lpo = 1 60 1 10 100 1000 Output Current [mA] 7.2.6 Step Down DC/DC Converter Registers The Step Down DC/DC Converter is controlled by the registers listed in Table 8. Table 8. Step Down DC/DC Converter Register Summary Name Addr. b7 b6 b5 b4 Step Down Voltage/Test Modes 01h - Reg Power 09h - buck_on ldo_sim_ on Step Down Configuration 17h buck_dis_ buck_ curmin dis_pon buck_lpo - www.austriamicrosystems.com b3 b2 b1 b0 buck_v 1.00 20 ldo_ana2_ ldo_ana1 on _on - buck_ dis_n Page buck_ nsw_on buck_ psw_on 20 20 19 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Step Down Voltage Register (Address 01h). Step Down Voltage/Test Modes Addr: 01h Bit Sets the output voltage of the Step Down DC/DC Converter. Bit Name Default Access Bit Description Controls the voltage selection for the Step Down DC/DC Converter. 000000 0.6V 5:0 buck_v Boot ROM R/W (LSB = 50mV) … 111000- 3.4V 111111 7:6 - NA NA Reg Power Register (Address 09h). Reg Power Addr: 09h Enables/disables voltage regulators. Bit Bit Name Default Access Bit Description 0 ldo_ana1_on Boot ROM RW Refer to page 28 1 ldo_ana2_on Boot ROM RW Refer to page 28 3:2 - NA NA 4 ldo_sim_on Boot ROM RW Refer to page 28 Enables the Step Down DC/DC Converter. 5 buck_on 7:6 Boot ROM - R/W NA 0 Step Down DC/DC Converter is OFF. 1 Step Down DC/DC Converter is ON. NA Step Down Configuration Register (Address 17h). Step Down Configuration Addr: 17h Bit Configures the operation mode of the Step Down DC/DC Converter. Bit Name Default Access Bit Description Activate PSW (0.5Ω PMOS) only if buck_on and buck_nsw_on = 0. 0 buck_psw_on 0 R/W 0 Default setting. P-Channel switching transistor is controlled by the DC/DC Converter. 1 Turns on P-Channel switching transistor. Bits buck_on and buck_nsw_on must both = 0. Activates NSW (0.5Ω NMOS) only if buck_on = 0 and buck_psw_on = 0. 1 buck_nsw_on 0 R/W 2 buck_dis_n 0 R/W 3 - 0 RW www.austriamicrosystems.com 0 Default setting. N-Channel switching transistor is controlled by the DC/DC Converter. 1 Turns on N-Channel switching transistor. Bits buck_on and buck_psw_on must both = 0. 0 Default setting. Normal operation of The synchronous rectifier. 1 The synchronous rectifier is disabled (NSW is always OFF). 0 1 1.00 20 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Step Down Configuration Addr: 17h Configures the operation mode of the Step Down DC/DC Converter. Bit Bit Name Default Access 4 - 0 R/W Bit Description 0 1 5 buck_lpo 0 R/W 0 Low-power mode disabled. 1 Low-power mode enabled. Step down PON feature control. 6 buck_dis_pon 0 R/W 0 PON feature enabled. 100% duty cycle (PMOS always on) if output voltage drops more than 4%. Increased output ripple in that operation. 1 PON feature disabled. Maximum duty cycle = 1 - (tmin_off*fsw) Step down current force mode 7 buck_dis_curmin www.austriamicrosystems.com 0 0 current force mode enabled. Inductor current regulated to min 170mA. Higher efficiency in low dropout and low output current operation. Higher output ripple and noise. 1 current force mode disabled. Decreased efficiency in low dropout mode and at low output current. Small output ripple and noise. R/W 1.00 21 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.3 Low Dropout Regulators The Low Dropout Regulators (LDOs) are linear high performance regulators with programmable output voltages. The LDOs can be controlled by either software (voltage, ON/OFF) or hardware (ON/OFF) using highly configurable GPIO1 to GPIO3 pins. The Low Dropout Regulators include the following: RF and Analog Low Dropout Regulators – Described on page 22 Analog LDO Block Diagram – Described on page 22 SIMCard Low Dropout Regulator – Described on page 23 Low Power Low Dropout Regulator – Described on page 24 7.3.1 RF and Analog Low Dropout Regulators The RF LDOs (VRF_1 - VRF_4) and Analog LDOs (VANA_1 and VANA_2) are designed to supply power to sensitive analog circuits like LNAs, Transceivers, VCOs and other critical RF components of cellular radios. Additionally, these LDOs are suitable for supplying power to audio devices or as a reference for A/D and D/A converters. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices. Stability is guaranteed with ceramic output capacitors (see Figure ) of 1µ F ±20% (X5R) or 2.2µ F +100 / -50% (Z5U). The low ESR of these capacitors ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress ripple on the battery caused by the PA in TDMA systems. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power transistor enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance. The LDOs have a built-in discharge function when switched off. Figure 9. Analog LDO Block Diagram High-Gain Low-Bandwidth Amplifier VREF1.8V Low-Noise DC Reference Low-Gain Ultra High-Bandwidth Amplifier VBAT 3.0 to 5.5V + – – + VOUT 1.8 to 3.35V 250/150mA Load 1µF X5R (External) GND www.austriamicrosystems.com 1.00 22 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 9. RF and Analog LDO Characteristics VBAT = 3.6V; ILOAD = 150mA; TA = 25ºC; CLOAD = 2.2µ F (Ceramic); unless otherwise specified. Symbol Parameter Min VBAT Supply Voltage Range 3 RON On-Resistance PSRR Power Supply Rejection Ratio IOFF Shut Down Current 100 nA IVDD_LDO Supply Current 50 µA Noise Output Noise 50 µ Vrms tSTART Startup Time 200 µs VOUT Output Voltage VOUT_TOL Output Voltage Tolerance VLINEREG Line Regulation VLOADREG Load Regulation ILIMIT Current Limitation 7.3.2 Typ Max Unit 5.5 V 1 VANA_1, VANA_2 Ω 2 Notes VRF_1, VRF_2, VRF_3, VRF_4 f = 1kHz 70 dB 40 30 1.8 2.85 1.8 3.35 -50 50 -1 1 -10 10 -1 1 -10 10 f = 100kHz Without load 10Hz < f < 100kHz VBAT > 3.0V V Full programmable range mV Static mV Transient; Slope: tr = 10µ s Static mV Transient; Slope: tr = 10µ s 250 400 mA VANA_1, VANA_2 150 180 mA VRF_1, VRF_2, VRF_3, VRF_4 SIMCard Low Dropout Regulator The SIMCard LDO (VSIM) is optimized for SIMCard supply. It is designed to achieve the lowest possible power consumption and still provide reasonable regulation characteristics. To ensure high PSRR and stability, a low-ESR ceramic capacitor of 100nF (min.) must be connected to the output. The LDO has a built-in discharge function when switched off. Table 10. LDO VSIM Characteristics VBAT = 3.6V; ILOAD = 20mA; TA = 25ºC; CLOAD = 100nF (Ceramic); unless otherwise specified. Symbol Parameter Min VBAT Supply Voltage Range 3 RON On-Resistance PSRR Power Supply Rejection Ratio IOFF Shut Down Current IVDD_SIMCARD Supply Current tSTART Startup Time VOUT Output Voltage VOUT_TOL Output Voltage Tolerance VLINEREG Line Regulation www.austriamicrosystems.com Typ Max Unit 5.5 V 50 Ω Notes f = 1kHz 40 dB 20 100 40 nA µA 200 µs 1.8 3.0 V -50 50 mV -10 10 -100 100 1.00 f = 100kHz VBAT > 3.2V Static mV Transient; Slope: tr = 10µ s 23 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 10. LDO VSIM Characteristics (Continued) VBAT = 3.6V; ILOAD = 20mA; TA = 25ºC; CLOAD = 100nF (Ceramic); unless otherwise specified. Symbol Parameter VLOADREG 7.3.3 Load Regulation Min Typ Max -10 10 -100 100 Unit Notes Static mV Transient; Slope: tr = 10µ s Low Power Low Dropout Regulator The low-power bootstrap LDO (V2_5) is needed to supply power to the core (analog and digital) of the AS3605. LDO V2_5 is designed to achieve the lowest possible power consumption, and still provide reasonable regulation characteristics. LDO V2_5 has two supply inputs selecting automatically the higher one. This gives the possibility to supply the AS3605 core either with the battery or with the Battery Charger, depending on the conditions. To ensure high PSRR and stability, a low-ESR ceramic capacitor of 1µ F (min.) must be connected to the output. Note: Levelshifters in both directions (input and output) are placed between digital pins (VANA_1) and the digital core (V2_5) of the device, because of the different power supplies. Table 11. LDO V2_5 Characteristics VBAT = 3.6V; CLOAD_EXT = 0; TA = 25ºC; CLOAD = 2.2µ F (Ceramic); unless otherwise specified. Symbol Parameter Min VBAT Supply Voltage Range VCHARGER External Charger Adapter voltage RON On-Resistance IOFF Shut Down Current 100 nA IVDD_LPLDO Supply Current 3 µA tSTART Startup Time 200 µs VOUT Output Voltage 2.6 V www.austriamicrosystems.com Typ Max Unit 2.8 5.5 V 4 15 V Ω 50 2.4 2.5 1.00 Notes Guaranteed per design Guaranteed per design; consider device internal load for measurement 24 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.3.4 Typical Performance Characteristics Figure 10. Load Regulation of LDOs VANA_1, VANA_2 Figure 11. Output Noise of LDOs VANA_1, VANA_2 5mV VOUT = 2.8V, 10mV/Div 3mV 8mV ILoad = 150mA ILoad = 100mA 120mA, Slope: 10μs 1µ s 1mA 10mA Spectral Distribution at 150mA Output Load X-Axis: 40µ s/Div Figure 12. Load Regulation of LDO V2_5 7mV Figure 13. Line Regulation of LDO V2_5 VOUT = 5mV/ VOUT = 1mV/Div ILOAD = 20mA VBAT = 3.1V ILOAD = 1mA VBAT = 3.0V X-Axis: 40µ s/Div X-Axis: 25µ s/Div www.austriamicrosystems.com 10µ s 1.00 25 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.3.5 LDO Registers The Low Dropout Regulators are controlled by the registers listed in Table 12. Table 12. Low Dropout Regulators Register Summary Name Addr. b7 b6 b5 b4 b3 b2 b1 b0 Page LDO_RF1 Voltage 02h - ldo_rf1_v 26 LDO_RF2 Voltage 03h - ldo_rf2_v 27 LDO_RF3 Voltage 04h - ldo_rf3_v 27 LDO_RF4 Voltage 05h - ldo_rf4_v 27 LDO_ANA2_Voltage 06h - ldo_ana2_v 27 LDO_ANA1_Voltage 07h ldo_ana1_v 28 LDO_SIM_Voltage 08h - 28 Reg Power 09h LDO_GPIO Active 0Fh - - LDO_CHG 10h ldo_rf4 _on ldo_rf3 _on LDO_AD GPIOx 11h LDO_RF GPIOx 12h - ldo_sim_v ldo_ana2 ldo_ana1 _on _on 28 ldo_rf4_g ldo_rf3_g ldo_rf2_g ldo_rf1_g ldo_ana2 ldo_buck pio pio pio pio _gpio _gpio 29 - buck_on ldo_sim_ on ldo_rf2 _on ldo_rf1 _on ldo_rf4_gpio_sel ldo_rf3_gpio_sel - - EOCCurrent[1:0] ana2_sw ana1_sw 29 ldo_ana2_gpio_sel buck_gpio_sel 30 ldo_rf2_gpio_sel ldo_rf1_gpio_sel 31 LDO_RF1 Voltage Register (Address 02h). LDO_RF1 Voltage Addr: 02h Bit Sets the voltage for LDO VRF_1. Bit Name Default Access Bit Description 00000 4:0 ldo_rf1_v Boot ROM R/W … 11111 7:5 - www.austriamicrosystems.com NA 1.8V (LSB = 50mV) 3.35V NA 1.00 26 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_RF2 Voltage Register (Address 03h). LDO_RF2 Voltage Addr: 03h Bit Sets the voltage for LDO VRF_2. Bit Name Default Access Bit Description 00000 4:0 ldo_rf2_v Boot ROM R/W … 11111 7:5 - NA 1.8V (LSB = 50mV) 3.35V NA LDO_RF3 Voltage Register (Address 04h). LDO_RF3 Voltage Addr: 04h Bit Sets the voltage for LDO VRF_3. Bit Name Default Access Bit Description 00000 4:0 ldo_rf3_v Boot ROM R/W … 11111 7:5 - NA 1.8V (LSB = 50mV) 3.35V NA LDO_RF4 Voltage Register (Address 05h). LDO_RF4 Voltage Addr: 05h Bit Sets the voltage for LDO VRF_4. Bit Name Default Access Bit Description 00000 4:0 ldo_rf4_v Boot ROM R/W … 11111 7:5 - NA 1.8V (LSB = 50mV) 3.35V NA LDO_ANA2_Voltage Register (Address 06h). LDO_ANA2_Voltage Addr: 06h Bit Sets the voltage for LDO VANA_2. Bit Name Default Access Bit Description Sets the voltage for LDO VANA_2 4:0 ldo_ana2_v Boot ROM R/W 00000 … 11111 7:5 - www.austriamicrosystems.com NA 1.80V (LSB = 50mV) 3.35V NA 1.00 27 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_ANA1_Voltage Register (Address 07h). LDO_ANA1_Voltage Addr: 07h Bit Sets the voltage for LDO VANA_1. Bit Name Default Access Bit Description Sets the voltage for LDO VANA_1 4:0 ldo_ana1_v Boot ROM 00000 R/W … 11111 7:5 - NA 1.8V (LSB = 50mV) 3.35V NA LDO_SIM_Voltage Register (Address 08h). LDO_SIM_Voltage Addr: 08h Sets the voltage for Digital LDO VSIM. Bit Bit Name Default Access 5:0 - NA NA Bit Description Sets the voltage for LDO VSIM. 6 7 ldo_sim_v Boot ROM - NA R/W 0 1.8V 1 3.0V NA Reg Power Register (Address 09h). Reg Power Addr:09h Bit Enables/disables voltage regulators. Bit Name Default Access Bit Description Enables control of LDO VANA_1. Note: Do not set this bit = 0 or serial interface access will be disabled. 0 ldo_ana1_on Boot ROM R/W 0 LDO VANA_1 is OFF. 1 LDO VANA_1 is ON. Enables control of LDO VANA_2. 1 3:2 ldo_ana2_on - Boot ROM NA R/W 0 LDO VANA_2 is OFF. 1 LDO VANA_2 is ON. NA Enables control of LDO VSIM. 4 ldo_sim_on Boot ROM R/W 0 LDO VSIM is OFF. 1 LDO VSIM is ON. Enables the Step Down DC/DC Converter. 5 7:6 buck_on - www.austriamicrosystems.com Boot ROM NA 0 Step Down DC/DC Converter is OFF. 1 Step Down DC/DC Converter is ON. NA 1.00 28 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_GPIO Active Register (Address 0Fh). LDO_GPIO Active Addr: 0Fh Bit Activates GPIO ON/OFF control for voltage regulators. Bit Name Default buck_gpio Boot ROM Access Bit Description Activates GPIO control of Step Down DC/DC Converter. 0 R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit buck_on = 1. Activates GPIO control for LDO VANA_2. 1 ldo_ana2_gpio Boot ROM R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_ana2_on = 1. Activates GPIO control for LDO VRF_1. 2 ldo_rf1_gpio Boot ROM R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_rf1_on = 1. Activates GPIO control for LDO VRF_2. 3 ldo_rf2_gpio Boot ROM R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_rf2_on = 1. Activates GPIO control for LDO VRF_3. 4 ldo_rf3_gpio Boot ROM R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_rf3_on = 1. Activates GPIO control for LDO VRF_4. 5 7:6 ldo_rf4_gpio - Boot ROM R/W NA 0 Controlled by software. 1 LDO VRF_4 is on when assigned GPIO pin = 1 and bit ldo_rf4_on = 1. NA LDO_RF Switch Register (Address 10h). LDO_CHG Addr: 10h Enables LDOs and high-side switches. Bit Bit Name Default Access 0 ana1_sw 0 R/W 1 ana2_sw 0 R/W Bit Description 0 VANA_1 operates as LDO. 1 VANA_1 is operating as high-side switch (RON=1Ω); valid if ldo_ana1_on = 0. 0 VANA_2 operates as LDO. 1 VANA_2 is operating as high-side switch (RON=1Ω); valid if ldo_ana2_on = 0. Enables control of LDO VRF_1. 4 ldo_rf1_on www.austriamicrosystems.com 0 R/W 0 LDO VRF_1 is OFF. 1 LDO VRF_1 is ON. 1.00 29 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_CHG Addr: 10h Enables LDOs and high-side switches. Bit Bit Name Default Access Bit Description Enables control of LDO VRF_2. ldo_rf2_on 5 0 R/W 0 LDO VRF_2 is OFF. 1 LDO VRF_2 is ON. Enables control of LDO VRF_3. ldo_rf3_on 6 0 R/W 0 LDO VRF_3 is OFF. 1 LDO VRF_3 is ON. Enables control of LDO VRF_4. ldo_rf4_on 7 0 R/W 0 LDO VRF_4 is OFF. 1 LDO VRF_4 is ON. ldo_anax_on* anax_sw* ANA LDO Function 0 0 OFF 0 1 Fully ON, RON = 1Ω 1 0 Linear Voltage Regulator 1 1 Not Allowed * Where x = 1-4 LDO_AD GPIOx Register (Address 11h). LDO_AD GPIOx Addr: 11h Bit Selects GPIO pin for power ON/OFF control for DCDC and VANA_2. Bit Name Default Access Bit Description Valid if GPIO activation bit buck_gpio = 1 1:0 buck_gpio_sel 00h R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Valid if GPIO activation bit ldo_ana2_gpio = 1 3:2 7:4 ldo_ana2_gpio_sel 00h R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting NA www.austriamicrosystems.com 1.00 30 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_RF GPIOx Register (Address 12h). LDO_RF GPIOx Addr: 12h Bit Selects GPIO pin for power ON/OFF control for RF LDOs VRF_1 - VRF_4. Bit Name Default Access Bit Description Valid if ldo_rf1_gpio = 1 1:0 ldo_rf1_gpio_sel Boot ROM R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Valid if ldo_rf2_gpio = 1 3:2 ldo_rf2_gpio_sel Boot ROM R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Valid if ldo_rf3_gpio = 1 5:4 ldo_rf3_gpio_sel Boot ROM R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Valid if ldo_rf4_gpio = 1 7:6 ldo_rf4_gpio_sel www.austriamicrosystems.com Boot ROM R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting 1.00 31 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.4 Charge Pump The Charge Pump uses the external flying capacitor C2 (470nF) to generate output voltages higher than the battery voltage. There are two different operating modes of the charge pump itself: 1:1 Bypass Mode - Battery input and output are connected by a low-impedance switch - Battery current = output current 1:2 Mode - The output voltage is up to 2 times the battery voltage (without load), but is limited to VCPOUTmax all the time - Battery current = 2 times output current As the battery voltage decreases, the Charge Pump must be switched from 1:1 mode to 1:2 mode in order to provide enough supply for the current sinks. Depending on the actual current, the mode with best overall efficiency can be automatically or manually selected: The charge pump mode switching can be done manually or automatically with the following possible software settings: Automatic - Start with 1:1 mode - Switch up automatically to 1:2 mode Manual - Set modes 1:1 and 1:2 by software 7.4.1 Charge Pump Mode Switching If automatic mode switching is enabled (cp_mode_switching = 0) the charge pump monitors the current sinks, which are connected via a LED to the output V5_6. To identify these current sources (sinks), the registers CP mode Switch (register bits curr1_on_cp …curr5_on_cp) should be setup before starting the charge pump (cp_on =1). If any of the voltage on these current sources drops below the threshold (currlv_switch, currhv_switch), the 1:2 mode is selected after the debounce time. The CP will not switch back to 1:1 mode. If the currX_on_cp=0 and the according current sink is connected to the charge pump, the current sink will be functional, but there is no up switching of the charge pump, if the voltage compliance is too low for the current sink to supply the specified current. Figure 14. Automatic Mode Switching www.austriamicrosystems.com 1.00 32 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n The Charge Pump requires the external components specified in Table 13. Table 13. Charge Pump External Components Symbol Parameter Min CFLY (C2) External Flying Capacitor CSTORE (C3) External Storage Capacitor Typ Max Unit 470 1 4.7 Notes nF Ceramic low-ESR capacitor between pins CAPP and CAPN (see page 2). µF Ceramic low-ESR capacitor between pins V5_6 and VSS (see page 2). Note: Connections to the two external capacitors should be kept as short as possible. Table 14. Charge Pump Parameters VBAT = 3.6V; TAMB = 25ºC; unless otherwise specified. Symbol Parameter Min ICPOUT Output Current 0 VCPOUTmax Output Voltage RCP Effective Charge Pump Output Resistance currlv_switch if the current sink voltage drops below this threshold it will change from 1:1 to 1:2 mode tdeb start_up debounce time ISHUTDOWN Shutdown Current 7.4.2 Typ Max Unit 60 mA 5.6 V including output ripple 8.8 Ω VBAT = 3.0V, cp_mode[1:0] = 1:1 31 Ω VBAT = 3.0V, cp_mode[1:0] = 1:2 mV cp_mode_switching = automatic 200 240 µs 2000 0.1 Notes cp_start_debounce = 0 cp_start_debounce = 1 µA Charge Pump Registers Table 15. Charge Pump Register Summary Name Addr. b7 b6 b5 b4 b3 cp_freq cp_mode _switchin g b2 b1 b0 Page cp_on 34 Charge Pump Control Onkey Pulldown 18h cp_auto_ cp_start_d onkey_pul on ebounce ld_off CP Mode Switch 36h NA curr5_on curr4_on curr3_on_ curr2_on_ curr1_on_ _cp _cp cp cp cp 35 Curr Low Voltage Status 37h NA curr5_low curr4_low curr3_low curr2_low curr1_low _volt _volt _volt _volt _volt 35 www.austriamicrosystems.com 1.00 cp_mode[1:0] 33 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Charge Pump Control Onkey Pulldown Register (Address 18h). Charge Pump Control Onkey Pulldown Addr: 18h Sets the operation mode of the Charge Pump. Bit Bit Name Default Access 0 cp_on 0b R/W Bit Description 0 Set CP into 1:1 mode (OFF state) unless cp_auto_on is set. 1 Enable manual mode switching CP mode (in manual mode sets this mode, in automatic mode reports the actual mode used) 00 2:1 cp_mode[1:0] 00b R/W 01 10 11 1:1 mode 1:2 mode Set the mode switching algorithm 3 cp_mode_switching 0b R/W 0 Automatic mode switching 1 Manual mode switching; register cp_mode[1:0] defines the actual CP mode used. Clock frequency selection 4 cp_freq 0b R/W 5 onkey_pulld_off 0b R/W 6 cp_start_debounce 0b R/W 7 cp_auto_on www.austriamicrosystems.com 1b R/W 0 1 MHz 1 500 kHz 0 pull down on ON-key active 1 pull down on ON-key deactivated 0 Mode switching debounce timer is always 240µ s. 1 Upon startup (cp_on set to 1) the mode switching debounce time is first started with 2ms then reduced to 240µ s. 0 The CP is swiched ON/OFF with cp_on 1 The CP is automatically switched on if a current sink, which is connected to the CP (defined by registers CP Mode Switch 1&2) is switched ON and detects a low voltage condition. 1.00 34 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CP Mode Switch Register (Address 36h). CP Mode Switch Addr: 36h Setup which current sinks are connected (via LEDs) to the CP; if set to 1 the corresponding current sink is used for automatic mode selection of the CP. Bit Bit Name Default 0 curr1_on_cp 0b 1 curr2_on_cp 0b 2 curr3_on_cp 0b 3 curr4_on_cp 0b 4 curr5_on_cp 0b 5:7 - NA Access R/W R/W R/W R/W R/W Bit Description 0 Current sink CURR1 is not connected to the CP 1 Current sink CURR1 is connected to the CP 0 Current sink CURR2 is not connected to the CP 1 Current sink CURR2 is connected to the CP 0 Current sink CURR3 is not connected to the CP 1 Current sink CURR3 is connected to the CP 0 Current sink CURR4 is not connected to the CP 1 Current sink CURR4 is connected to the CP 0 Current sink CURR5 is not connected to the CP 1 Current sink CURR5 is connected to the CP NA Curr Low Voltage Status Register (Address 37h). Curr Low Voltage Status Addr: 37h Indicates the low voltage status of the current sinks. If the currX_low_v bit is set, the voltage on the current sink is too low, to drive the selected output current. Bit Bit Name Default Access 0 curr1_low_v NA R 1 curr2_low_v NA R 2 curr3_low_v NA R 3 curr4_low_v NA R 4 curr5_low_v NA R 5:7 - NA NA www.austriamicrosystems.com Bit Description 0 The voltage of current sink CURR1 > currlv_switch 1 The voltage of current sink CURR1 < currlv_switch 0 The voltage of current sink CURR2 > currlv_switch 1 The voltage of current sink CURR2 < currlv_switch 0 The voltage of current sink CURR3 > currlv_switch 1 The voltage of current sink CURR3 < currlv_switch 0 The voltage of current sink CURR4 > currlv_switch 1 The voltage of current sink CURR4 < currlv_switch 0 The voltage of current sink CURR5 > currlv_switch 1 The voltage of current sink CURR5 < currlv_switch 1.00 35 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.5 General Purpose Input/Output The general purpose input/output pins (GPIO1 - GPIO3) are highly configurable and independently controlled. Table 16. DC Characteristics Input/Output Pin with Selectable Supply GPIO1:GPIO3 Symbol Parameter Min Max VIH High-Level Input Voltage 0.7 x VANA_1 VIL Low-Level Input Voltage ILEAK Input Leakage Current (if not used as pulldown/pullup) IPULLDOWN Unit Notes V 0.3 x VANA_1 V -5 5 µA to VANA_1 and VSS Pulldown Current (if configured as pulldown) 5 50 µA to VSS IPULLUP Pullup Current (if configured as pullup) -200 -20 µA to V5_6 or VANA_1 as configured VOH High-Level Output Voltage Supply VANA_1 0.8 x VANA_1 V at -2mA VOL Low-Level Output Voltage 0.2 x VANA_1 V at 2mA CLOAD Capacitive Load 50 pF GPIO1 - GPIO3 can be used to accommodate the following functionality: Software controlled input and output Input pin for the Watchdog Signal input (GPIO1-GPIO3) Interrupt output with configurable interrupt source Configurable frequency and duty cycle output External clock input for Step Up/Down DC/DC Converters and Charge Pump synchronization (GPIO1 only) Active pullup or pulldown; can be combined with other I/O functions Output open drain (push or pull type) www.austriamicrosystems.com 1.00 36 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 15. General Purpose I/O Block Diagram VANA_1 VANA_1 interface Register GPIO Control en_pup en_pdwn en_pmos en_nmos gpio_invert gpio_out_src gpio Frequency Generator sysclk Interrupt f_out MUX GPIOx int Interrupt Sources 7.5.1 GPIO Registers GPIO1 - GPIO3 are controlled by the registers listed in Table 17. Table 17. GPIO Register Summary Name Addr. b7 b6 b5 b4 b3 b2 b1 b0 Page GPIO1 Control 1Ah gpio1_out_src gpio1_ invert gpio1_pulls gpio1_ low_curr gpio1_mode 38 GPIO2 Control 1Bh gpio2_out_src gpio2_ invert gpio2_pulls gpio2_low _curr gpio2_mode 38 GPIO3 Control 1Ch gpio3_out_src gpio3_ invert gpio3_pulls gpio3_ low_curr gpio3_mode 39 GPIO Signal 21h GPIO Frequency Control High Time 22h gpio_h_time 41 GPIO Frequency Control Low Time 23h gpio_l_time 41 Clock Generation 1Eh - Interrupt Enable 1Fh chgov_in chgrmv_in resume_in t_en t_en t_en chdet_ int_en onkey_ int_en ovtmp_ int_en Interrupt Status 20h chgov_i chdet_i onkey_i ovtmp_i www.austriamicrosystems.com - chgrmv_i resume_i gpio3 1.00 gpio2 gpio1 40 ext_clk 41 vchoff_ int_en wdog _int_en 42 vchoff_i wdog_i 43 37 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n GPIO1 Control Register (Address 1Ah). GPIO1 Control Addr: 1Ah Bit Configures pin GPIO1. Bit Name Default Access Bit Description Sets the direction for pin GPIO1. 1:0 2 gpio1_mode gpio1_low_curr 00 R/W 0 00 Input only 01 Output (push and pull) 10 Output (open drain, only push; only NMOS is active) 11 Output (open drain, only pull; only PMOS is active) 0 Fast output slew rate 1 Slow output slew rate R/W Sets pullup/pulldown to pin GPIO1 (independent of bit gpio1_mode setting). 4:3 5 gpio1_pulls gpio1_invert 00 R/W 0 00 None 01 Pulldown 10 Pullup 11 NA 0 Output signal is not inverted. 1 Inverts any output signal going to GPIO1. This is useful for the Watchdog output source to make the output active high or low. R/W Sets the source of pin GPIO1 output. 7:6 gpio1_out_src 00 R/W x0 Bit gpio1 controlled through the serial interface. 01 Frequency generator defined by bits gpio_h_time and gpio_l_time. 11 Interrupt signal (see Interrupt Function on page 42). GPIO2 Control Register (Address 1Bh). GPIO2 Control Addr: 1Bh Bit Configures pin GPIO2. Bit Name Default Access Bit Description Sets the direction for pin GPIO2. 1:0 2 gpio2_mode gpio2_low_curr www.austriamicrosystems.com 00 0 R/W R/W 00 Input only 01 Output (push and pull) 10 Output (open drain, only push; only NMOS is active) 11 Output (open drain, only pull; only PMOS is active) 0 Fast output slew rate 1 Slow output slew rate 1.00 38 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n GPIO2 Control Addr: 1Bh Bit Configures pin GPIO2. Bit Name Default Access Bit Description Sets pullup/pulldown to pin GPIO2 (independent of bit gpio2_mode setting). 4:3 5 gpio2_pulls gpio2_invert 00 0 R/W R/W 00 None 01 Pulldown 10 Pullup 11 NA 0 Output signal is not inverted. 1 Inverts any output signal going to pin GPIO2. This is useful for the Watchdog output source to make the output active high or low. Sets the source of pin GPIO2 output. 7:6 gpio2_out_src 00 R/W x0 Bit gpio2 (controlled through the serial interface). 01 Frequency generator defined by bits gpio_h_time and gpio_l_time. 11 Interrupt signal (see Interrupt Function on page 42). GPIO3 Control Register (Address 1Ch). GPIO3 Control Addr: 1Ch Bit Configures pin GPIO3. Bit Name Default Access Bit Description Sets the direction for pin GPIO3. 1:0 3:2 gpio3_mode gpio3_low_curr www.austriamicrosystems.com 00 0 R/W R/W 00 Input only. 01 Output (push and pull). 10 Output (open drain, only push; only NMOS is active). 11 Output (open drain, only pull; only PMOS is active). 0 Fast output slew rate 1 Slow output slew rate 1.00 39 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n GPIO3 Control Addr: 1Ch Bit Configures pin GPIO3. Bit Name Default Access Bit Description Sets pullup/pulldown to pin GPIO3 (independent of bit gpio3_mode setting). 4 5 gpio3_pulls gpio3_invert 00 0 R/W R/W 00 None 01 Pulldown 10 Pullup 11 NA 0 Output signal is not inverted. 1 Inverts any output signal going to pin GPIO3. This is useful for the Watchdog output source to make the output active high or low. Sets the source of pin GPIO3. Bit gpio3 (controlled through the serial interface) x0 7:6 gpio3_out_src 00 R/W Frequency generator defined by bits gpio_h_time and 01 gpio_l_time. Interrupt signal (see Interrupt Function on page 42). 11 GPIO Signal Register (Address 21h). Table 18. GPIO Signal Register (Address 33) GPIO Signal Addr: 21h Reads the logic signal of the GPIO pins, independently of any other GPIO bit setting. Bit Bit Name Default Access 0 gpio1 NA R Reads the logic signal from pin GPIO1. If gpio1_out_src = 00, this is the output signal at pin GPIO1. 1 gpio2 NA R Reads the logic signal from pin GPIO2. If gpio2_out_src = 00, this is the output signal at pin GPIO2. 2 gpio3 NA R Reads the logic signal from pin GPIO3. If gpio3_out_src = 00, this is the output signal at pin GPIO3. 7:3 - NA NA www.austriamicrosystems.com Bit Description 1.00 40 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.5.2 Programmable Frequency Generator The Programmable Frequency Generator is controlled by bits gpio_h_time and gpio_l_time. It generates a waveform with 0.9 microseconds times gpio_h_time high-level and 0.9 microseconds times gpio_l_time low-level. The accuracy of these timings is ±10%. The frequency of the Programmable Frequency Generator is: f=1/(tCLK*gpio_h_time + tCLK*gpio_l_time) (EQ 1) Where: tclk = 1/fCLK = 1/1.1MHz (typ) = 0.909µ s (typ) The purpose of the Programmable Frequency Generator is to have a controlled sweepable frequency or duty cycle source for one of the following: General User-Defined Clock 8-Bit DAC (output should be filtered by an RC filter) (High) Positive and Negative Voltage Generation (see Interrupt Function on page 42) 7.5.3 Programmable Frequency Generator Registers Bit definition for programmable frequency generator registers are given below. GPIO Frequency Control High Time Register (Address 22h). GPIO Frequency Control High Time Addr: 22h Bit Configures programmable frequency generator. Bit Name Default Access Bit Description Defines the number of system clock cycles (typ 0.9µ s), that the programmable frequency generator at the GPIO output(s) is high. 7:0 gpio_h_time 00h R/W 00h 0.909µ s FFh 232.7µ s GPIO Frequency Control Low Time Register (Address 23h). GPIO Frequency Control Low Time Addr: 23h Bit Configures programmable frequency generator. Bit Name Default Access Bit Description Defines the number of system clock cycles (typ 0.9µ s), that the programmable frequency generator at the GPIO output(s) is low. 7:0 gpio_l_time www.austriamicrosystems.com 64h R/W 00h 0.909µ s FFh 232.7µ s 1.00 41 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.5.4 Interrupt Function Any of the GPIO pins (GPIO1 - GPIO3) can be configured as interrupt output pins. To enable this function, the corresponding GPIO control bits must be set to 11b. See gpio1_out_src, gpio2_out_src, or gpio3_out_src. Several signals can be configured as interrupt source using the Interrupt Enable (page 42). A rising edge of an enabled interrupt control signal sets the selected GPIO interrupt output pin = 1. The Interrupt Status (page 43) shows the currently active interrupt signals. Reading this register resets the Interrupt Status (page 43) bits and sets the active GPIO pin (GPIO 1 - GPIO3) = 0. 7.5.5 Interrupt Registers Bit definition for Interrupt registers are given below. Interrupt Enable Register (Address 1Fh). Interrupt Enable Addr: 1Fh Enables/disables interrupt sources. Bit Bit Name Default Access 0 wdog_int_en 0 R/W 1 vchoff_int_en 1 R/W 2 ovtmp_int_en 1 R/W 3 onkey_int_en 1 R/W 4 chdet_int_en 1 R/W 5 resume_int_en 1 R/W 6 chgrmv_int_en 1 R/W 7 chgov_int_en 1 R/W www.austriamicrosystems.com Bit Description 0 Disables watchdog alarm as interrupt source signal. 1 Enables watchdog alarm as interrupt source signal. 0 Disables charge termination voltage as interrupt source signal. 1 Enables charge termination voltage as interrupt source signal. 0 Disables ov_temp_110 (device temperature alert at 110ºC). 1 Enables ov_temp_110 (device temperature alert at 110ºC). 0 Disables pin ON (active high). 1 Enables pin ON (active high). 0 Disables charger detection. 1 Enables charger detection. 0 Disables charger-resume interrupt. 1 Enables charger-resume interrupt. 0 Disables charger-removed interrupt. 1 Enables charger-removed interrupt. 0 Disables charger overvoltage interrupt. 1 Enables charger overvoltage interrupt. 1.00 42 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Interrupt Status Register (Address 20h). Interrupt Status Addr: 20h Displays the status of the interrupt inputs. Bit Bit Name Default Access 0 wdog_i 0 R 1 vchoff_i 0 R 2 ovtmp_i 0 R 3 onkey_i 0 R 4 chdet_i 0 R Charger detection interrupt, active if ChDet is falling. 5 resume_i 0 R Active if VRESUME is reached (see Table 5). 6 chgrmv_i 0 R Charger detection interrupt, active if ChDet is falling. 7 chgov_i 0 R Charger over voltage interrupt, active if ChOv is rising. www.austriamicrosystems.com Bit Description 0 Software or hardware watchdog is OFF or has not rolled over. 1 Software or hardware watchdog is rollover. 0 Battery voltage is below VCHOFF (see page 12) threshold. 1 Battery voltage has reached VCHOFF threshold. 0 Device temperature is below 110ºC. 1 110ºC temperature threshold ov_temp_110 has been reached. 0 ON key has not been pressed. 1 ON key has been pressed (rising edge). 1.00 43 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.6 Current Sinks The AS3605 contains 5 general purpose current sinks intended to control backlights, buzzers, and vibrators. All current sinks have an integrated protection (VPROTECT) against overvoltage and can therefore also drive inductive loads. The current sinks can also be used as switches to VSS with configurable impedance as indicated in Table 19. Table 19. Current Source Characteristics Symbol Parameter Min ICURRx curr1_current = 01h - FFh curr2_current = 01h - FFh ICURRx curr3_current = 01h - FFh curr4_current = 01h - FFh curr5_current = 01h - FFh VPROTECT Maximum voltage at pin CURRx to protect driver transistor Typ Max Unit Notes 0.63 160 mA resolution = 0.6275mA 0.16 40 mA resolution = 0.1569mA VBAT + 2.0V V ISINK ≥ 20mA, guaranteed by design Note: If a voltage higher than VPROTECT is applied to pins CURR1 - CURR5, a current of more than 20mA will flow into the AS3605. This protects the device from voltage rises caused by inductive loads. 7.6.1 Current Sink Registers The current sinks are controlled by the registers listed in Table 20. Table 20. Current Sink Register Summary Name Addr. b7 b6 b5 b4 b3 b2 b1 b0 Page CURR5 Control GPIO Map 19h CURR1 Value 24h curr1_current 45 CURR2 Value 25h curr2_current 45 CURR3 Value 26h curr3_current 46 CURR4 Value 27h curr4_current 46 CURR Control 28h CURR5 Value 29h CURR GPIO Map 2Ah - curr4_ctrl curr5_gpio curr3_ctrl curr2_ctrl curr5_ctrl curr1_ctrl curr5_current curr4_gpio curr3_gpio curr2_gpio 45 46 47 curr1_gpio 47 Note: For all current sinks, the currx_on signal is controlled with the currx_ctrl bits. www.austriamicrosystems.com 1.00 44 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CURR5 Control GPIO Map Register (Address 19h). CURR5 Control GPIO Map Addr: 19h Bit 1:0 Bit Name curr5_ctrl Default 00b Access R/W Bit Description 00 Pin CURR5 is turned OFF 01 Pin CURR5 is active 1x GPIO control; pin is active when curr5_gpio = 1 If the bits curr5_ctrl = 1x, the following pin is assigned for turning the CURR5 pin ON and OFF. 3:2 7:4 curr5_gpio - 00b NA R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA NA CURR1 Value Register (Address 24h). CURR1 Value Addr: 24h Bit 7:0 Sets the current / resistance of current source CURR1. Bit Name curr1_current Default 00h Access R/W Bit Description 00h Power Down 01h 0.6275mA … FFh 160mA CURR2 Value Register (Address 25h). CURR2 Value Addr: 25h Bit 7:0 Sets the current / resistance of current source CURR2. Bit Name curr2_current Default 00h Access R/W Bit Description 00h Power Down 01h 0.6275mA … FFh www.austriamicrosystems.com 1.00 160mA 45 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CURR3 Value Register (Address 26h). CURR3 Value Addr: 26h Bit 7:0 Sets the current / resistance of current source CURR3. Bit Name curr3_current Default 00h Access R/W Bit Description 00h Power Down 01h 0.1569mA … FFh 40mA CURR4 Value Register (Address 27h). CURR4 Value Addr: 27h Bit 7:0 Sets the current / resistance of current source CURR4. Bit Name curr4_current Default 00h Access R/W Bit Description 00h Power Down 01h 0.1569mA … FFh 40mA CURR Control Register (Address 28h). CURR Control Addr: 28h Bit 1:0 3:2 5:4 7:6 Selects software/ hardware control of current sources. Bit Name curr1_ctrl curr2_ctrl curr3_ctrl curr4_ctrl www.austriamicrosystems.com Default 00b 00b 00b 00b Access R/W R/W R/W R/W Bit Description 00 Pin CURR1 is turned OFF. 01 Pin CURR1 is active. 1x GPIO control; pin is active when curr1_gpio =1. 00 Pin CURR2 is turned OFF. 01 Pin CURR2 is active. 1x GPIO control; pin is active when curr2_gpio =1. 00 Pin CURR3 is turned OFF. 01 Pin CURR3 is active. 1x GPIO control; pin is active when curr3_gpio = 1. 00 Pin CURR4 is turned OFF. 01 Pin CURR4 is active. 1x GPIO control; pin is active when curr4_gpio = 1. 1.00 46 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CURR5 Value Register (Address 29h). CURR5 Value Addr: 29h Bit 7:0 Sets the current. Bit Name curr5_current Default 00h Access R/W Bit Description 00h Power Down 01h 0.1569mA … FFh 40mA CURR GPIO Map Register (Address 2Ah). CURR GPIO Map Addr: 2Ah Bit Selects GPIO pin to control current sources. Bit Name Default Access Bit Description If bits curr1_ctrl = 1x, the following pin is assigned for turning the CURR1 pin ON and OFF. 1:0 curr1_gpio 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA If bits curr2_ctrl = 1x, the following pin is assigned for turning the CURR2 pin ON and OFF. 3:2 curr2_gpio 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA If bits curr3_ctrl = 1x, the following pin is assigned for turning the CURR3 pin ON and OFF. 5:4 curr3_gpio 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA If bits curr4_ctrl = 1x, the following pin is assigned for turning the CURR4 pin ON and OFF. 7:6 curr4_gpio www.austriamicrosystems.com 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA 1.00 47 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.7 Audio Amplifier The integrated Audio Amplifier provides real CD-quality audio and can be used as a headphone amplifier for portable devices. It is designed to meet the operational and power requirements of portable devices by delivering: 1WRMS continuous power into 8Ω differential at 5V supply 2 x 50mWRMS into 32Ω single-ended at 5V supply The Audio Amplifier provides the following operational features: Total harmonic distortion is less than 0.1% at 1kHz and the quiescent current does not exceed 8mA. Power supply rejection is always better than 50dB and allows direct connection to noisy batteries, e.g. in TDMA systems. The internal programmable gain can be used for volume and balance control. Only a few external components are required for AC-coupling and reference bypass. An internal smooth-rampup circuit ensures pop- and click-less startup without expensive and bulky external relays. Device stability even with high capacitive loads of 1nF and does not require external snubber networks. Inputs are high-impedance in power-down. Figure 16. Audio Amplifier Block Diagram – Stereo Mode 330kΩ AIN_L Audio In Left 100nF aud_gain Startup, Biasing, Control Logic Gain Control – AOUT_L ≥100µF + ≥4Ω AGND ≥4Ω 100nF aud_on ≥100µF + aud_lpo – AOUT_R 100nF Audio In Right AIN_R 330kΩ Bit aud_stereo (see page 51) = 1 Note: The value of the audio output decoupling capacitors depends on the speaker impedance and the desired minimum output frequency: C = 1/(2xPxfxR) (EQ 2) Where: f = minimum output cutoff frequency, -3dB point. R = speaker impedance in Ω. C = decoupling capacitance in F. www.austriamicrosystems.com 1.00 48 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 17. Audio Amplifier Block Diagram – Differential Mode AIN_L 330kΩ Audio In 100nF aud_gain Startup, Biasing, Control Logic Gain Control – AOUT_L + AGND ≥8Ω 100nF aud_on + aud_lpo AOUT_R – 100nF AIN_R 165kΩ 165kΩ Bit aud_stereo (see page 51) = 0 Table 21. Audio Amplifier Characteristics Symbol Parameter Min Typ VDDH Supply Voltage Range (VBAT_3) 3 PSRR Power Supply Rejection Ratio, Differential 70 PSRR Power Supply Rejection Ratio, SingleEnded 50 IOFF Shut Down Current Max Unit 5.5 V f = 1kHz dB 50 40 100 Supply Current (Differential Mode) 4 Supply Current (Stereo Mode) IVDDH THD+N Output Load aud_lpo = 0 and aud_ib_red = 00 mA aud_lpo = 1 and aud_ib_red = 11 8 aud_lpo = 0 and aud_ib_red = 00 3 8 mA 4 aud_lpo = 1 and aud_ib_red = 00 aud_lpo = 1 and aud_ib_red = 11 Ω 1.00 aud_lpo = 1 and aud_ib_red = 00 2.7 Differential mode Stereo mode 0.1 % POUT = 1W, RLOAD = 8Ω, f = 1kHz, VBAT = 5.5V; Differential 0.5 % POUT = 1W, RLOAD = 8Ω, f = 20kHz, VBAT = 5.5V; Differential 0.05 % POUT = 50mW, RLOAD =32Ω, f = 1kHz, VBAT = 4V; Single-Ended 0.2 % POUT = 50mW, RLOAD =32Ω, f = 20kHz, VBAT = 4V; Single-Ended Total Harmonic Distortion www.austriamicrosystems.com f = 20kHz nA 1.7 RLOAD f = 20kHz f = 1kHz dB 9 IVDDH Notes 49 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 21. Audio Amplifier Characteristics (Continued) Symbol Parameter Min Typ Max Unit Notes dB VBAT=3.7V, not tested, guaranteed per design dB Programmable gain: AOUT/AIN SNR Signal to Noise Ratio 84 91 A0 Gain -22 0 ΔAx Programmable Gain Step-Size lOV_ON Overcurrent On_limit 591 650 744 mA Current rising into PMOS driver; when aud_lpo = 0 and aud_ib_red = 00, and aud_overcur = 1. lov_off Overcurrent Off_limit 397 550 650 mA Current decreasing in PMOS driver; when aud_lpo = 0 and aud_ib_red = 00, and aud_overcur is cleared. lov_hyst Overcurrent Hysteresis 7.7.1 20 3 dB 100 mA Audio Amplifier Registers Bit definition for Audio amplifier registers are given below. Audio Control Register (Address 2Bh). Audio Control Addr: 2Bh Bit Configures the Audio Amplifier. Bit Name Default Access Bit Description Activates the Audio Amplifier. 0 aud_on 0 R/W 0 Audio amplifier off; inputs AIN_L and AIN_R are highimpedance. 1 Audio amplifier on. Select Low-Power Operation; reduced output power. 1 aud_lpo 0 R/W 0 Use for speakers < 32Ω (nominal impedance) in stereo mode; < 64Ω differential. 1 Use for speakers ≥ 32Ω (nominal impedance) in stereo mode; ≥ 64Ω differential. Reduced bias current into Audio Amplifier circuit. 3:2 aud_ib_red 00b R/W 00 Use for speakers < 8Ω (nominal impedance) in stereo mode; < 16Ω differential. 01 NA 10 NA 11 Use for speakers ≥ 8Ω (nominal impedance) in stereo mode; ≥ 16Ω differential. Audio Amplifier gain adjust. 7:4 aud_gain www.austriamicrosystems.com 0000b R/W 0000 Output off 1000 0dB 0001 -22dB 1001 +2dB 0010 -19dB 1010 +5dB 0011 -16dB 1011 +8dB 0100 -13dB 1100 +11dB 0101 -10dB 1101 +14dB 0110 -7dB 1110 +17dB 0111 -4dB 1111 +20dB 1.00 50 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Audio Control 2 Register (Address 41h). Audio Control 2 Addr: 41h Bit Configures the Audio Amplifier. Bit Name Default Access Bit Description Selects audio mode. 0 1 aud_stereo aud_overcur 1 0 R/W R 0 Differential mono mode (connect pin AIN_R to pin AOUT_L) 1 Stereo mode. 0 Normal operation; audio output current below limit of lOV_ON. 1 Audio output current exceeds limit (lOV_ON). Audio amplifier output pulldown control; active if aud_on=0. 3:2 7:4 aud_pulldwn - www.austriamicrosystems.com 00b NA R/W 00 30µ A 01 0.6mA 10 1.2mA 11 2.5mA Na 1.00 51 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8 System Supervisory Functions 8.1 Reset XRES is an active low bi-directional pin; an external pullup to LDO VANA_1 has to be added (see Digital Input/Output DC/AC Characteristics on page 61). During each reset cycle the following states are controlled by the AS3605: Pin XRES is Forced to GND Programmable Power-off Function Programmable Power-on Sequence and Regulator Voltages Programmable Reset Timer All Register bits Set to Default Values after Power-On (except the Audio Control 2 (page 51), the Interrupt Status (page 43). Note: Programming is controlled by the internal OTP-ROM. 8.1.1 Reset Conditions Reset can be activated from 7 different sources: Power On (Battery or Charger Insertion) Low Battery Power Off Mode Software Forced Reset Externally Triggered through the XRES Pin Overtemperature Watchdog Momentary Power Loss Detection Power On (Battery or Charger Insertion). There are two types of voltage dependent resets: VPOR – Monitors the voltage on pin V2_5. LDO V2_5 uses the voltage VCHARGER or VBAT as its source. VRESET – Monitors the voltage on VBAT pins. Pin XRES is only released if V2_5 > VPOR and VBAT > VRESETRISE. Low Battery. A reset is automatically generated if VBAT drops below VRESETFALLING for a minimum period (VRESETMASk). Table 22. Reset Levels Symbol Parameter Min Typ Max Unit VPOR Overall power on reset 1.5 2.0 2.3 V Monitor voltage on pin V2_5; power on reset for all internal functions. Pin RESET stays low until V2_5 > VPOR VRESETRISE Reset level for VBAT rising 3.1 V Monitor voltage on pin VBAT; rising level. VRESETFALLING Reset level for VBAT falling 2.8 V Monitor voltage on pin VBAT; falling level. VRESETMASK Mask time for VRESETFALLING 40 µs TPOWERLOSS Interval for recovery of power loss on VBAT 1 100 250 500 ms Notes Duration for VBAT < VRESETFALLING until a reset 2 cycle is started . If the duration of a power loss on VBAT is below this duration, the system will restart 1. VRESETFALLING is only accepted if the reset condition is longer than VRESETMASK. This guard time is used to avoid a complete reset of the system in case of short drops of VBAT. 2. VRESET signal is debounced with the specified mask time for rising- and falling-slope of VBAT. The default time is 40µ s and it can be programmed from 0µ s to 200µ s with the register reset-mask timer. www.austriamicrosystems.com 1.00 52 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Power Off. Setting bit power_off = 1 puts the AS3605 into ultra low-power mode. To start a complete reset cycle, the AS3605 waits until the external pin ON is pulled high, the Battery Charger is inserted, or level VPOR is reached. Bit power_off is automatically cleared by this reset cycle. During power off state, all circuits are turned off except LDO V2_5, thus the current consumption of the AS3605 is reduced to less than 10µ A. The digital part is supplied by LDO V2_5, all other circuits are turned off in this mode, including internal references and oscillator. Note: All registers except the Reset Control on page 53 are set to their default value after power-on. Software Forced Reset. Setting bit force_reset = 1 immediately initiates a reset cycle, and is automatically cleared during a reset. External Triggered Reset. If the pin XRES is pulled from high to low by an external source (microprocessor or button) a reset cycle is initiated. Overtemperature Reset. The reset cycle can be started by overtemperature conditions (see page 55). Watchdog Reset. If the Watchdog is armed (bit wtdg_on = 1 and bit wtdg_res_on = 1) and the timer expires, a reset is initiated. Refer to page 57 for information about the Watchdog block. 8.1.2 Reset Registers Bit definition for Reset registers are given below. Reset Control Register (Address 3Ah). Reset Control Addr: 3Ah Controls reset and power off. Bit Bit Name Default Access 0 force_reset 0 R/W 1 power_off 0 R/W Bit Description 0 Normal operation. 1 Initiates a complete reset cycle. 0 Normal operation. 1 Initiates power-off mode where all LDOs are turned off except LDO V2_5. The AS3605 waits for a rising edge on pin ON or until the battery charger is detected. Static indication of ON input pin. 2 on_input 0 R 0 ON input pin is low. 1 ON input pin is high (external ON key depressed). Indicates to the software the reason for the most recent reset. 5:3 reset_reason 0h R 6 tmp_ pwr_loss 0 R 7 - NA NA www.austriamicrosystems.com 000 VPOR was reached (initial battery or charger insertion) 001 VRESETFALLING was reached (VBAT < 2.75V) 010 Software forced by bit force_reset 011 Software forced by bit power_off and a Battery Charger detected 100 Software forced by bit power_off and ON was pulled high 101 Externally triggered through pin XRES 110 Reset caused by overtemperature T140 111 Reset caused by Watchdog 0 Normal startup. 1 A momentary power loss condition was detected. 1.00 53 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Reset Timer Register (Address 13h). Reset Timer Addr: 13h Bit Sets the RESET timer value. Bit Name Default Access Bit Description Set RESTIME 2:0 res_timer OTP R/W 000 RESTIME = 0ms 001 RESTIME = 10ms 010 RESTIME = 20ms 011 RESTIME = 30ms 100 RESTIME = 40ms 101 RESTIME = 50ms 110 RESTIME = 60ms 111 RESTIME = 70ms Set MASKTIME 5:3 7:6 8.1.3 reset_mask_timer - OTP NA R/W 000 MASKTIME = 0µ s 001 MASKTIME = 5µ s 010 MASKTIME = 10µ s 011 MASKTIME = 40µ s 100 MASKTIME = 80µ s 101 MASKTIME = 120µ s 110 MASKTIME = 160µ s 111 MASKTIME = 200µ s NA Reset Cycle During a reset cycle, pin XRES is forced low for at least the time specified by bits res_timer and then all register bits are set to their default values except bit ov_temp_140. During the reset time, a normal startup is initiated (refer to Startup on page 55) and the reset is active until the reset timer (set by bits res_timer) expires. The voltage on pin XRES is then pulled high by the external resistor and the whole system is leaving the reset state. 8.1.4 res_con: Reset Control Reset is internally generated from a power on detection circuit (see page 52) and provided to the internal logic as well as externally through the open-drain pin XRES. This pin can also be forced externally by pulling it low. Additionally Reset can be forced by software by setting bit force_reset = 1. www.austriamicrosystems.com 1.00 54 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.2 Startup 8.2.1 Normal Startup During a normal reset cycle (see page 52), after V2_5 is above VPOR and VBAT is above VRESETRISE, a normal startup is initiated as follows: 1. The external capacitor on pin CREF is charged to 1.8V. 2. The DC/DC converters and LDOs are sequentially powered up according to the Boot OTP configuration. 3. Depending on the Boot OTP setting (Auto-Shutdown): a) The AS3605 enters shutdown mode if no momentary power loss is detected (only valid through initial start-up, not during a reset cycle). -orb) The Reset-Timer is set by the Boot OTP and the reset is released when the Reset-Timer expires (pin XRES is pulled high). 8.2.2 Programmable Startup Sequences The start-up sequnece is factory programmed. For more details please contact austriamicrosystems AG. 8.2.3 Startup from Battery Charger If the voltage on pin VCHARGER is within VSTARTCHARGER, the Battery Charger is started in all cases, even with VBAT = 0V. This allows the battery to be charged (even from deep discharge) and a normal startup to proceed. Table 23. Battery Charger Startup Conditions Symbol Parameter Min Typ Max Unit VSTARTCHARGER Voltage on pin VCHARGER for the AS3605 to start 4.35 5.0 15 V Notes On pin VCHARGER. 8.3 Protection Functions The Step Down DC/DC Converter, and all LDOs have integrated overcurrent protection. Overtemperature protection of the AS3605 is also builtin and can be activated with the serial interface bit temp_pmc_on. The AS3605 has two temperature indicators: ov_temp_110 – Automatically reset if the overtemperature condition is removed. ov_temp_140 – Must be reset via the serial interface with bit rst_ov_temp_140. If ov_temp_140 is set, an automatic reset of the complete AS3605 is initiated. Bit ov_temp_140 is not cleared by this reset cycle to indicate the reason for this (unexpected) shutdown. It must be cleared intentionally by bit rst_ov_temp_140. The cause of this reset is stored in the Reset Control (page 53). This allows a detection of the reset cause, after the device has restarted. 8.3.1 TMP_SV: Temperature Supervision The AS3605 includes an integrated temperature sensor, implemented to provide overtemperature protection of the device. It generates flags linked to the two temperature thresholds: T110 – 110º threshold. Sets ov_temp_110, signalling the 110º overtemperature condition. Thus software can react and shut down powerconsuming functions in order to decrease the device’s temperature. T140 – 140º threshold. Reaching this temperature level generates a Reset, when temp_pmc_on is enabled. This sets all regulators into power-down mode and stops battery charging. www.austriamicrosystems.com 1.00 55 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.3.2 Overtemperature Detection Table 24. Overtemperature Detection Parameters 8.3.3 Symbol Parameter T110 ov_temp_110 Rising Threshold T140 ov_temp_140 Rising Threshold Thyst ov_temp_110 and ov_temp_140 Hysteresis Min Typ Max Unit 95 110 125 ºC 203 230 257 ºF 125 140 155 ºC 257 284 311 ºF 5 ºC Overtemperature Detection Register Overtemperature Control Register (Address 3Bh). Overtemperature Control Addr: 3Bh Bit Device temperature supervision. Bit Name Default Access Bit Description Activates/deactivates temperature supervision. Default: Off - all other bits are only valid if set to 1. 0 1 temp_pmc_on ov_temp_110 0 0 R/W R 0 Temperature supervision is disabled. No reset will be generated when the device temperature exceeds 140ºC. 1 Temperature supervision is enabled. 1 Warning flag indicating that the device temperature has exceeded 110ºC. 1 Indicates that the device overtemperature has exceeded 140ºC. This bit is not cleared by the automatic reset caused by this flag. It must be cleared using bit rst_ov_temp_140. 2 ov_temp_140 0 R 3 rst_ov_temp_140 0 R/W Used to clear bit ov_temp_140; first set this bit = 1 and then set it =0. 4 temp_test0 0 R/W Only used for production; must always be set to 00. 5 temp_test1 0 R/W 6 tco_110_a 0 R Only used for production – direct output of T110 comparator. 7 tco_140_a 0 R Only used for production – direct output of T140 comparator. www.austriamicrosystems.com 1.00 56 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.4 Watchdog Block The AS3605 includes a Watchdog block to detect a deadlock of the connected controller. If the Watchdog block is active (wtdg_on = 1), it must get a continuous trigger signal within a programmable timer window. If there is no signal for a certain time period from a defined GPIO pin or bit wtdg_sw_sig, the Watchdog block starts either a complete reset – bit wtdg_res_on must be set to 1 – or sets interrupt flag wdog_i. The Watchdog timer window is defined by bits: wtdg_min_timer wtdg_max_timer The trigger signal can be configured using bits: wtdg_trigger wtdg_sw_sig – Watchdog is reset by software wtdg_gpio_input – Watchdog is reset by hardware (GPIO) Any of the general purpose input/outputs can be configured as inputs using bit wtdg_gpio_input, and outputs using bits gpio1_out_src, gpio2_out_src, or gpio3_out_src = 11, for the Watchdog. While the GPIO input must be continuously re-triggered in order to avoid a Watchdog interrupt, the GPIO output will generate in interrupt when the Watchdog runs over – wdog_int_en. 8.4.1 Watchdog Registers The Watchdog is controlled by the registers listed in Table 25. Table 25. Low Dropout Regulators Register Summary Name Addr b7 b6 b5 b4 wtdg_ trigger b3 Watchdog Control 2Eh Watchdog_min Timer 2Fh wtdg_min_timer Watchdog_max Timer 30h wtdg_max_timer Watchdog Software Signal - 31h b2 wtdg_gpio_input b1 b0 Page wtdg_ res_on wtdg_on 57 - 58 58 wtdg_ sw_sig 58 Watchdog Control Register (Address 2Eh). Watchdog Control Addr: 2Eh Controls the Watchdog block. Bit Bit Name Default Access 0 wtdg_on 0 R/W Bit Description 0 Disables the Watchdog block. 1 Enables the Watchdog block. If the Watchdog expires and this bit = 1, a reset cycle will be started. Refer to page 52 for information about reset cycles. 1 wtdg_res_on www.austriamicrosystems.com 1 R/W 0 A watchdog overflow does not generate a reset. 1 A watchdog overflow generates a reset. 1.00 57 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Watchdog Control Addr: 2Eh Bit Controls the Watchdog block. Bit Name Default Access Bit Description Specifies the input pin of the Watchdog if bit wtdg_trigger = 1. 3:2 wtdg_gpio_input 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting. Select type of trigger (software or hardware). 4 7:5 wtdg_trigger - 0 NA R/W 0 Use bit wtdg_sw_sig as trigger signal for the Watchdog. 1 Use the pin defined by bit wtdg_gpio_input as trigger signal for the Watchdog. NA Watchdog_min Timer Register (Address 2Fh). Watchdog_min Timer Addr: 2Fh Bit 7:0 Sets the minimum Watchdog trigger time. Bit Name wtdg_min_timer Default 00h Access R/W Bit Description 00h 0s 01h 16ms … FFh 4.08s Watchdog_max Timer Register (Address 30h). Watchdog_max Timer Addr: 30h Bit Sets the maximum Watchdog trigger time. Bit Name Default Access Bit Description 01h 7:0 wtdg_max_timer FFh R/W 16ms … FFh 4.08s Caution: Do not set these bits = 00h Watchdog Software Signal Register (Address 31h). Watchdog Software Signal Addr: 31h Bit Resets the Watchdog block by software. Bit Name Default Access Bit Description Trigger input by the serial interface if wtdg_trigger = 0 0 7:1 wtdg_sw_sig - www.austriamicrosystems.com 0 NA R/W 0 Force watchdog trigger = low (see Figure 18) 1 Force watchdog trigger = high (see Figure 18) NA 1.00 58 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Figure 18. Watchdog Timing Diagram tMAX tMIN wtdg_trigger tMIN tMAX 8.5 Internal Reference Circuits The internal reference circuits (V, I, fCLK) require the external components listed in Table 26. Table 26. Reference External Components Symbol CEXT Parameter External filter capacitor Min Typ Max Unit Notes -20% 100 +20% nF Ceramic low-ESR capacitor between pins CREF and VSS Table 27. References Characteristics Symbol Parameter Min Typ Max Unit Notes VCEXT Reference voltage -1% 1.8 +1% V Low noise trimmed voltage reference - connected to pin CREF; do not load. fCLK Internal reference clock 1.0 1.1 1.2 MHz Trimmed clock reference To reduce the current consumption of the AS3605, internal references circuits can be set into a special low-power mode with bit low_power_on. www.austriamicrosystems.com 1.00 59 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.5.1 Internal Reference Registers References Control Register (Address 2Dh). References Control Addr: 2Dh Bit 0 Configures low-power mode. Bit Name low_power_on Default 0 Access Bit Description 0 Standard mode or controlled by GPIO, if low_power_gpio_on = 1. 1 Low-power mode; all parameters except noise (see LDO parameters, section 7.3) are still valid. R/W If set and low_power_on = 0 then the low-power mode is controlled by a GPIO pin. 1 low_power_gpio_on 0 R/W 0 Low-power mode disabled for GPIO control. 1 Low-power mode is activated by GPIO pin (low_power_gpio). low_power_on must be enabled. Specifies the pin to be used as GPIO control. 3:2 4 7:5 low_power_gpio low_power_gpio_pol - 00 0 NA R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 GPIO3 0 Low-power mode is activated. If the selected GPIO input, bit low_power_gpio = 1. 1 Low-power mode is activated. If the selected GPIO input, bit low_power_gpio = 0. R/W NA 8.6 Low Power Mode Bit low_power_on controls low-power mode. In low-power mode the integrated voltage reference and the temperature supervision comparators operate in pulsed mode. This reduces the quiescent current of the AS3605 by 45µ A (typical). Because of the pulsed function, the LDO output noise parameters do not meet the specification in low-power mode but the full functionality is still available. Note: Low-power mode can be activated by hardware using one of the GPIO pins, or by software by setting bit low_power_on = 1. www.austriamicrosystems.com 1.00 60 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.7 Serial Interface 8.7.1 Digital Input/Output DC/AC Characteristics VBAT_1 is used as supply voltage of the pins. Table 28. DC Characteristics Input Pin SCK Symbol Parameter Min Max Unit VIH High-Level Input Voltage 1.5 VBAT V VIL Low-Level Input Voltage 0.4 V ILEAK Input Leakage Current -5 5 µA Max Unit Notes to VBAT_1 and GND_PAD Table 29. DC Characteristics Open Drain Pin SDA Symbol Parameter Min VIH High-Level Input Voltage 1.5 VIL Low-Level Input Voltage ILEAK Input Leakage Current VOL CLOAD Notes V 0.4 V 5 µA to VBAT_1 and GND_PAD Low-Level Output Voltage 0.2 V at 4.0mA Capacitive Load 50 pF Max Unit -5 Table 30. DC Characteristics Input/Output Open Drain Pin XRES Symbol Parameter Min VIH High-Level Input Voltage 1.5 VIL Low-Level Input Voltage ILEAK Input Leakage Current VOL Notes V 0.4 V 5 µA to VANA_1 and GND_PAD Low-Level Output Voltage 0.2 V at 4mA CLOAD Capacitive Load 50 pF RPULLUP External Pullup Resistor 100k Ω www.austriamicrosystems.com -5 1.00 Connect to