AGB64LV01-QC-E

General Description Amulet Easy GUI Browser Chip is a special purpose micro controller that is optimized to execute Amulet’s GUI kernel and component based GUI firmware, The chip is a combination LCD controller chip and a user interface chip. This chip eliminates the need for complex code to draw each pixel on a LCD. The chip renders GUI pages containing graphic images, Amulet Widgets, and other UI objects directly to the LCD. This lets your embedded micro do it’s job more efficiently. Thus, the main application can run on a smaller processor with less RAM and ROM, and code development and maintenance time is Significantly reduced. Features Requirements Dedicated GUI Chip - Manages the GUI, Interacts with the user, and controls the LCD – Frees up your Micro! HTML-Based GUI Creation – Create and edit Quickly using drag-and-drop HTML tools Compiler Included – Converts from HTML, JPEG, and GIF into small, quickly-executable Amulet HTML pages Processor Independent – Easily interfaces to Most micro controllers (8/16/32-bit and DSPs) Replaces Traditional GUI Library – No Library porting, complex GUI programming, or RTOS required RS232 Interface – Up to 115,200 bps 3.3V Power Supply Serial Flash (Atmel 4 Megabit recommended) Asynchronous SRAM (128Kx8 Minimum) Clock/Crystal (up to 20 MHz.) Typical Circuit Block Diagram SRAM Crystal ICLK XTAL Display CP Pixel D0-D7 Xsync DISP M Ysync ADDR0-16 DATA0-7 /WE /OE /FSS SCLK MOSI /RESET /PEN /TSS MISO /Reset Flash /CS SCK SI SO Touch Screen DCLK /CS DIN DOUT /PENIRQ Pin Configurations Overview The Amulet is a powerful 8-bit microcontroller featuring task specific opcodes, registers, and memory segments allowing for optimization of graphics rendering, I/O processing, and general purpose computing. The Amulet is equipped with the following built-in peripherals: LCD Controller Microprocessor UART Timers SPI Master The Easy GUI Browser chip has 13 dedicated output lines for LCD control of various sized sub-VGA displays. The chip is able to drive different size displays because the bias voltage, which determines the LCD driving voltage, is supplied from an external source. Supply voltage: 3.3V +/- 10% Applicable LCD duty: up to 1/640 (adjustable in single increments) RAMTSTO STATUS RAMTSTI /PEN TPC FFBS CFS2 CFS1 PROG MODE Block Diagram ADDR[16:0] DATA[7:0] Microprocessor /WE /OE /RESET Timers XTAL ICLK /IRQ RXD SPI PIXEL[7:0] CP XSYNC YSYNC M LCD Controller DISP TXD UART SCLK MOSI MISO /FSS /TSS /CSS /BSS /SS4 /SS5 /SS6 Pin Descriptions I O I/O P 1 = = = = 1 CMOS CMOS 1 CMOS Power 1 Input Output Input & Output Supply The I/O pins are only VCC tolerant and must adhere to the voltage levels depicted in the DC CHARACTERISTICS section. All input pins have an internal pull-up resistor. VCC Pin Name Type P ICLK I Pin Number 8, 26, 44, 62, 80 2, 14, 20, 32, 38, 50, 56, 68, 74 1 GND P Description Supply voltage. 3.3V XTAL O 3 1 /RESET I 4 1,5,6 /IRQ I 5 1 PIXELD0 - PIXELD7 O 6-7, 9-13, 15 DISP O 16 Ground. 1 1 1 1 Xsync O 17 M O 18 1 1 CP O 19 Ysync O 21 1 O 22-25, 34-37, 39-42, 49, 51-54 1 ADDR0 - ADDR16 System clock. Reference Recommended XTAL Connections section. System clock. Reference Recommended XTAL Connections section. System reset. A low level of 10us or longer will generate a system reset. System interrupt. This pin should be left unconnected. LCD pixel data. The LCD pixel data bus width can be set to 1, 2, 4, or 8 data bits via the HTMLCompiler software. LCD control signal (High = LCD on, Low = LCD off). LCD data latch. Xsync goes active for one clock period after all the LCD pixel data for the current line has been shifted out. The Xsync polarity can be set via the HTMLCompiler software. LCD crystal polarization clock. LCD pixel clock. The CP’s active edge can be set to a rising or falling edge via the HTMLCompiler software. LCD first frame synchronization. System address bus. DATA0 - DATA7 I/O 28-31, 45-48 1 /WE O 27 1 /OE O 43 1 STATUS O 33 1 TXD O 55 1 RXD I 57 1,5 System data bus. Memory write enable to data bus (Low = write). Memory output enable from data bus (Low = read). Internal operational status. This pin should be left unconnected. UART data output. UART data input. 1,2,5 System power up mode. A low level boots Amulet in run mode. A high level boots Amulet in program mode. 1 Crystal frequency selection 1. Reference Recommended XTAL Component Selections section. 1 Crystal frequency selection 2. Reference Recommended XTAL Component Selections section. 1,3,5 Flash programming baud rate. A low level sets the flash programming rate to 19,200 bps. A high level sets the flash programming rate to 115,200 bps. 1,4,5 Touch panel calibration mode. A low level does not perform a calibration session. A high level performs a calibration session. 1,5 Touch panel status if a touch panel is used. A low level indicates touch panel is pressed. A high level indicates touch panel is not pressed. This pin should be left unconnected if no touch panel is used. 1,4 External SRAM test. A low level instructs Amulet to perform an external SRAM test. A high level instructs Amulet to not perform an external SRAM test. When applicable, results of external SRAM test are output on pin 79 (RAMTSTO). PROG MODE I 58 CFS1 I 59 CFS2 I 60 FFBS I 61 TPC I 63 /PEN I 64 RAMTSTI I 65 FT I 66 1 SCLK O 67 1 MOSI O 69 1 MISO I 70 1,5 Factory test. This pin should be left unconnected. SPI clock. SPI data out. SPI data in. /FSS O 71 1 /TSS O 72 1 /CSS O 73 1 /BSS O 75 1 /SS4 O 76 1 /SS5 O 77 1 /SS6 O 78 1 O 79 Touch panel slave select. Contrast slave select. Backlight slave select. SPI slave select 4. This pin is for future use and should be left unconnected. SPI slave select 5. This pin is for future use and should be left unconnected. SPI slave select 6. This pin is for future use and should be left unconnected. 1 RAMTSTO Flash slave select. External SRAM test results. A low level indicates external SRAM test failed. A high level indicates external SRAM test passed. Results are only valid if external SRAM test was performed. See input pin RAMTSTI description above. 1 The I/O pins are only VCC tolerant and must adhere to the voltage levels depicted in the DC CHARACTERISTICS section. 2 Input pin is read upon power up, a system reset, or when writing to flash. 3 Input pin is only read when a flash programming session has been initiated. 4 Input pin is read upon power up or a system reset. 5 Internally pulled high. If pin is externally connected, interface it to an open collector output. 6 The /RESET pin should be held low for a minimum of 140ms after applying VCC. DC Characteristics Absolute Maximum Ratings Voltage on Vcc with respect to ground…………………………..….... Operating temperature………………………………………….…...…. Storage temperature……………………………………………...…….. Soldering lead temperature………………………………………...….. Soldering 10 Sec. - 0.3 to + 6.5V -20 to +75ºC -60 to +150ºC 210ºC DC Characteristics For Vcc = 3.3V Item CMOS INPUT Input "High" Voltage Input "Low" Voltage Input Leakage current CMOS OUTPUT Output "High" Voltage Output "Low" Voltage Operating Frequency Pull-up Resistor Symbol Minimum VIH VIH IL 2.0 VOH VOL Fopr RI 2.8 - - 10 37K Typical Maximum (VCC tolerant only) 0.8 5 (VCC tolerant only) 0.2 16 20 202K Unit V V uA V V MHz Ω Current VCC = 3.3V +/-10%, Ground = 0, Temperature = -20ºC to +75ºC Item Operating Current Operating Current Operating Current Operating Current Symbol Condition ICC 10MHz ICC 10MHz Reset ICC 16MHz ICC 16MHz Reset Minimum - Typical 10 7 16 10 Maximum - Unit mA mA mA mA CPU Memory Access Timing The CPU performs both Read and Write accesses to memory. In either case, all timing parameters for CPU accesses are relative to the falling edge of CLK. All input signals are sampled at the falling edge of CLK and all output signals transition after some delay relative to the falling edge of CLK. Input Hold times are the amount of time after the falling edge of CLK that a signal must remain stable. Output Hold times are the minimum delay that the signal will remain stable after the falling edge of CLK. Label tcyc tad tah tds0 tdh0 tws twh Description Clock Cycle Period Address Delay Address Hold Write Data Delay Write Data Hold Write Enable Delay Write Enable Hold Label tad tah tdsl tdhl Description Address Delay Address Hold Read Data Setup Read Data Hold Value 10 5 10 5 8 3 Units nS nS nS nS nS nS nS Value 10 5 5 0 Units nS nS nS nS 1/Crystal Line Buffer Memory Access Timing The Line buffer only performs Read accesses to memory. Timing parameters for Line buffer reads are relative to both edges of CLK. All input signals are sampled at the rising edge of CLK and all output signals transition after some delay relative to the falling edge of CLK. Input Hold times are the amount of time after the rising of CLK that a signal must remain stable. Output Hold times are the minimum delay that the signal will remain stable after the falling edge of CLK. Label tad tah tds2 tdh2 Description Address Delay Address Hold Read Data Setup Read Data Hold Value 10 5 5 5 Units nS nS nS nS Recommended XTAL Connections Recommended Crystal Component Selections 1 CFS1 = Amulet Pin 59 1 CFS2 = Amulet Pin 60 R1, R2 = Resistor (+/- 10%) C1, C2 = Capacitor (+/- 10%) Z1 CFS1 10 MHz. 12 MHz. 16 MHz. 20 MHz. High Low High Low CFS2 R1 R2 High 1 MΩ 1.8 kΩ High 1 MΩ 1.0 kΩ Low 1 MΩ 560 Ω Low 1 MΩ 560 Ω 1 By default, CFS1 and CFS2 are internally pulled high. C1 C2 18 pF 18 pF 15 pF 12 pF 18 pF 18 pF 15 pF 12 pF LCD Timing Chart of Signals The following signal timing assumes: CP = Negative Edge (Adjustable in HTMLCompiler Software). # of Data Bits = 4 (Adjustable in HTMLCompiler Software). Xsync = Positive Polarity (Adjustable in HTMLCompiler Software). MAXBYTE = 4 bytes of data per line and with the following data in the line buffer: 20, 21, 22, 23… CP PIXEL0-PIXEL3 Xsync Ysync M Display Data Pattern The LCD Characteristics settings within the HTMLCompiler software let you specify a display either by manufacturer or by size (up to full VGA resolution). External Asynchronous SRAM Size and speed are the two most important factors to consider when selecting an external SRAM device. The minimum size of the SRAM must be at least 128K x 8. The minimum speed of the SRAM will be a function of the system clock. Use the following formula to calculate the minimum speed: 1 / (2 * system clock) For example, a design utilizing a system clock of 16 MHz. would require an SRAM device with a speed grade of at least 31 nS. ADDR0-ADDR16 SRAM DATA0-DATA7 /WE /OE Flash SPI Interface The Amulet supports Atmel DataFlash for storage of uHTML pages. The DataFlash must be organized with a minimum of 512 pages of 264 bytes each, plus one SRAM data buffer of 264 bytes like the AT45DB011B-SC device from Atmel. The DataFlash is enabled through a chip select pin (/CS) and accessed via a three wire serial interface consisting of a serial input (SI), serial output (SO), and a serial clock (SCK). The DataFlash is controlled by instructions from the Amulet. The list of instructions Amulet uses to interface to the DataFlash is as follows: Main Memory Page Read (52H) Main Memory Page to Buffer Transfer (53H) Buffer Write (84H) Buffer to Main Memory Page Program (83H) Status Register (57H) If you decide to use a flash device other than the recommended Atmel DataFlash, then the device must support the DataFlash organization as well as the five instructions above. Please check the Atmel DataFlash datasheet for more information on the device. Touch-Screen SPI Interface Amulet’s Easy GUI Browser Chip supports Burr-Brown touch-screen controllers (ADS7843 and ADS7846) for decoding 4-wire resistive touch panels. The touch-screen controller is enabled through a chip select pin (/CS) and accessed via a three-wire serial interface consisting of a serial input (DIN), serial output (DOUT), and a serial clock (DCLK). The firmware to decode a Burr-Brown touch-screen controller is included with the Amulet OS. Below is a sample schematic on how a Burr-Brown touch-screen controller should be interfaced in a typical application requiring the use of a 4-wire resistive touch panel for user input. The 4 noise filtering capacitors between the TP HEADER and Burr-Brown device may or may not be needed, but it is recommended you design them in because you can always leave them unpopulated. Whether or not you need the noise filtering capacitors will depend on the size of the touch panel, as well as the environment in which the product will be used. For applications requiring the use of the noise filtering capacitors, .01uF (+/- 10%) capacitors will normally address the problem. 1 2 3 4 5 3.3V 1 2 3 4 5 6 7 8 1 2 3 4 CON4 AMT 9502 Touch Panel C27 .01uF C26 .01uF C25 .01uF C24 .01uF C13 .1uF U2 J2 D VCC DCLK X+ /CS Y+ DIN XBUSY YDOUT GND /PEN VBAT VCC IN VREF U4 16 15 14 13 12 11 10 9 1 2 3 4 /RESET SI SCK /RESET /CS R2 100K 2 SW1 C3 R1 R7 3 SW-PB 1M See Table1 4 3.3V See Table 1 C7 4.7uF 3.3V /RESET NC RESET /PFO /MR VCC PFI GND 8 PROG MODE 6 /BSS /CSS SCLK RAMTSTI MAX708S 20MHZ 0 0 560 16MHZ 1 0 560 12MHZ 0 1 1.0K 1.8K 10MHZ 1 1 CFSlines a re pulled high by default U5 C 12pF 15pF 18pF 18pF 11 12 13 14 15 16 17 18 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 9 8 7 6 5 4 3 2 D8 D7 D6 D5 D4 D3 D2 D1 74HCT541 +5V VEE VADJ 3.3V ICLK GND XTAL /RESET /IRQ PIXEL_D7 PIXEL_D6 VCC PIXEL_D5 PIXEL_D4 PIXEL_D3 PIXEL_D2 PIXEL_D1 GND PIXEL_D0 DISP Xsync M CP GND Ysync ADDR7 ADDR6 ADDR5 Displaytech - 240320A FFBS SW2 1 2 3 4 Okaya - RG320240-F 8 7 6 5 Opt rex - DMF50840NB Shelly - SGM32024031 Tianma - TM320240DFG Winstar - WG320240A DB9 SW-DIP4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 /PEN C 3.3V C8 .22uF See Table 1 U10 C20 VADJ D1 1 5 VEE .22uF VIN /SHDN GND 4 /RESET C5 4.7uF SW U8 MBR0540 D2 MBR0540 8 7 6 5 +5V U6 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C10 .22uF LT1617 U12 Contrast Adj. A 3 /CSS MOSI 4 5 H GND W GND VDD /CS /SHDN SDI 10 9 A16 A15 A14 A13 OE I/O 7 I/O 6 GND VCC I/O 5 I/O 4 A12 A11 A10 A9 A8 VOUT ADJ GND BYP 1 2 3 4 B R5 14.3K LT1763 U14 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 L 2 3 4 /BSS MOSI H GND W GND VDD /CS /SHDN 5 SDI SCLK AD5200 10 9 R6 C28 22uF Tant 7.68K 8 3.3V 7 6 SCLK Backlight Adj. A C11 .22uF 7 6 SCLK 3.3V A0 A1 A2 A3 CE I/O 0 I/O 1 VCC GND I/O 2 I/O 3 WE A4 A5 A6 A7 VLED VIN GND GND SHDN IS63 LV1024 3.3V 8 Title Size SCLK 320x240 Number Revision B AD5200 1 Date: File: 2 3 C19 .22uF 3.3V C6 22uF L 3.3V C23 22uF U13 + 2 3 .22uF R4 33K 1 OUT C12 R3 560K 3 NFB IN LM2937ES3.3 L1 22uH 1 +5V AGB64 LV01-QC +5V D NanYa - LMAGA_032_27 J8 1 6 2 7 3 8 4 9 5 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CON14 EDT - EW32F10 / EW32F62 Microtips - MTG-S322240 Lines a re pulled high by default TPC /PEN TPC VCC FFBS CFS2 CFS1 PROG MODE RXD GND TXD ADDR8 ADDR9 ADDR10 ADDR11 GND ADDR12 DATA4 DATA5 DATA6 DATA7 VCC /OE ADDR13 ADDR14 C15 .22uF 2 Appendix: Sample Reference Design 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 19 1 E2 E1 J1 B C4 .22uF VCC RAMTSTO /SS6 /SS5 /SS4 /BSS GND /CSS /TSS /FSS MISO MOSI GND SCLK FT RAMTST C2 / C3 ADDR4 VCC /WE DATA3 DATA2 DATA1 DATA0 GND STATUS ADDR3 ADDR2 ADDR1 ADDR0 GND ADDR16 ADDR15 R7 14 C18 .1uF U1 CFS1 CFS2 AllShore - ASI -A-32024A / ASI -C-32024A C17 .1uF 7 5 List of Manufactures and Displ ays Schematic Supports 3.3V Tabel 1 Crystall Selection Freq. 3 7 13 8 10 16 Hantronix - HDM3224-1 MOSI MISO 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 C16 .1uF MAX3221 3.3V /RESET Z1 CRYSTAL C1+ V+ C1VC2+ T1OUT C2R1IN /INVALID T1IN R1OUT /FORCEOFF /EN GND FORCEON C9 .22uF /PEN U3 See Table 1 C14 .1uF 8 7 6 5 SO GND VCC /WP 2 4 5 6 11 9 1 12 AT45DB041B ADS7846 C2 6 U7 C1 .22uF 4 5 XA 3-May-2006 Sheet of 1 OF 1 Drawn By: Fred Power 6 REFERENCE LOCATIONS ITEM QTY PACKAGE DESCRIPTION MANUFACTURER 1 1 R1 805 RES, 1M, 1/10W, 5% 2 1 R2 805 RES, 100K, 1/10W, 5% 3 1 R3 805 RES, 560K, 1/10W, 5% 4 1 R4 805 RES, 33K, 1/10W, 5% 5 6 7 8 1 1 1 10 R5 R6 R7 C1,C4,C8-C12, C19, C20, C15 805 805 805 1206 RES, 14.3K, 1/10W, 1% RES, 7.68K, 1/10W, 1% See Table on Schematic CAP, .22uF, 16V, Z5U, 20% 9 10 2 1 C6, C23 C5, C7 C 4X5.5CAN 11 2 C2,C3 1206 12 5 1206 13 4 C13, C14, C16 C17, C18 C24 - C27 1206 CAP, 22uF, 50V, Elect Nippon CAP, 4.7uF, 25V, Electrolitic, 20% NIC NICHICON See Table on Schematic AVX CAP,.1uF,50V,5% PANASONIC VITRAMON CAP, .01uF, 50V VITRAMON 14 15 1 2 C28 D1, D2 1206 SOD-123 CAP, 22uF, 10V, 10%, Tant Diode, Schottky, .5A, 40V 16 17 1 1 L1 Z1 SMD CSM-7 22 uH CRYSTAL, 16MHz, 20pF 18 1 SW1 6X3.7 Momentary Push Button 19 1 SW2 SMD 4-Pos Dip Switch 20 21 22 1 1 1 J1 J2 J8 SMD SMD Con, 14pin ZIF Con, 4pin Header DB-9 Female Connector 23 24 25 1 1 1 U8 U2 U4 SOT-23 SSOP-16 SOIC-8 26 27 28 1 1 1 29 30 31 32 33 1 1 1 2 1 U1 U6 U7 U3 U13 U10 U12, U14 U5 MANUFACTURER PART # AVX VISHAY / DALE KOA AVX VISHAY / DALE KOA AVX VISHAY / DALE KOA AVX VISHAY / DALE KOA VISHAY / DALE VISHAY / DALE CR21-105J-T CRCW0805-105JRT1 RM73B2AT105J CR21-104J-T CRCW0805-104JRT1 RM73B2AT104J CR21-564J-T CRCW0805-564JRT1 RM73B2AT564J CR21-333J-T CRCW0805-333JRT1 RM73B2AT333J CRCW0805-1432FRT1 CRCW0805-7681FRT1 PANASONIC SAMSUNG VITRAMON AVX ECP-U1C224MA5 CL31F224ZAAD VJ12066224MXAMT 12065E224MAT2A NACE220M50V6.3x6.3TR13 NACE4R7M35V 4X5.5 TR13 UWX1E4R7MCR1GB 12065A200JAT2A ECU-V1H104KBW VJ1206Y10JXAMT VJ1206Y103KXAMT Vishay ON SPECIALTY ELECT. JW MILLER ECS FOX PANASONIC C&K CTS C&K JST 293D226X9010C2T MBR0540LT1 FPCHB04TT PM43-220M ECS-160-20-5P FOXSD/160-20/TR-1K EVG-PPBA25 PTS635SL25SM 219-4LPST SDA04H0SK 14FE-ST-VK-N LCD Power Supply Touch Panel A/D DATA FLASH, 4MB, 2.7V SMP ADAM TECH LINEAR BURR-BROWN ATMEL PQFP-80 SOJ-32 SSOP-16 Amulet Controller SRAM, 128K X 8, 15ns RS-232 Transceiver AMULET ISSI INTERSIL 3170-09-F DE09-SL-24 LT1617ES5 ADS7846E AT45DB041B-SC AT45DB041B-SI AGB64LV01-QC SOIC-8 8-MSOP SOT-223 Under Voltage Detector Linear Regulator 3.3V Regulator ON-SEMI LINEAR NATIONAL MAX708SESA-T LT1763CS8 LM2937IMP-3.3 8-MSOP SOIC-20 SPI, 10K POT 74HCT541, Buffer Driver ANALOG DEVICES ST AD5200BRM10 74HCT541M1R IS63LV1024-15K ICL3221CA Recommended Chip Pad Dimensions 90.945mil 31.496mil 90.945mil 31.496mil 15mil 80mil Chip Mechanicals 80 PQFP (14x20x2.7mm) Symbol A A1 A2 b c D E e D1 E1 L L1 Y inch 134mil MAX 10.0mil MIN 106mil NOM 15.0mil NOM 7.0mil NOM 913mil NOM 677mil NOM 31.496mil NOM 787mil NOM 551mil NOM 35.0mil NOM 63.0mil NOM 4.0mil NOM Rev. F October 2007