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WIZ812MJ

WIZ812MJ

  • 厂商:

    WIZNET

  • 封装:

    模块

  • 描述:

    IC MODULE W5100 + MAG JACK

  • 数据手册
  • 价格&库存
WIZ812MJ 数据手册
WIZ812MJ Datasheet (Ver. 1.2) © 2013 WIZnet Co., Ltd. All Rights Reserved. For more information, visit our website at www.wiznet.co.kr WIZ812MJ Datasheet Document History Information Revision Ver. 1.0 Ver. 1.1 Data September 17, 2008 January 28, 2009 Ver. 1.2 January 28, 2013 Description Release with WIZ812MJ Launching Added temperature specification Hardware revision(Rev1.1) Changed operation temperature range, partlist and schematic 2 TOP WIZ8 10M J Data shee t © Copyright 2013 WIZnet Co., Ltd. All rights reserved WIZ812MJ Datasheet WIZnet’s Online Technical Support If you have something to ask about WIZnet Products, Write down your question on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an answer as soon as possible. 3 TOP WIZ8 10M J Data shee t © Copyright 2013 WIZnet Co., Ltd. All rights reserved WIZ812MJ Datasheet Table of Contents 1. Introduction .............................................................................. 5 4 1.1. 1.2. 1.3. 2. Pin Assignments & descriptions ................................................... 7 2.1. 2.2. 2.3. 2.4. 3. Features ............................................................................. 5 Block Diagram ...................................................................... 5 Difference between WIZ811MJ and WIZ812MJ .............................. 6 Pin Assignments ................................................................... 7 Power & Ground ................................................................... 8 MCU Interfaces ..................................................................... 8 Miscellaneous Signals ............................................................ 9 Timing Diagrams ..................................................................... 10 3.1. 3.2. 3.3. 3.4. Reset Timing .................................................................... 10 Register/Memory READ Timing ............................................... 10 Register/Memory WRITE Timing .............................................. 11 SPI Timing......................................................................... 11 4. Dimensions ............................................................................. 12 5. Schematic .............................................................................. 13 6. Partlist ................................................................................... 14 © Copyright 2013 WIZnet Co., Ltd. All rights reserved TOP WIZ8 10M J Data shee t WIZ812MJ Datasheet 1. Introduction WIZ812MJ is the network module that includes W5100 (TCP/IP hardwired chip, include PHY), MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and no effort is required to interface W5100 and Transformer. The WIZ812MJ is an ideal option for users who want to develop their Internet enabling systems rapidly. For the detailed information on implementation of Hardware TCP/IP, refer to the W5100 Datasheet. WIZ812MJ consists of W5100 and MAG-JACK.  TCP/IP, MAC protocol layer: W5100  Physical layer: Included in W5100  Connector: MAG-JACK(RJ45 with Transformer) 1.1. Features               Supports 10/100 Base TX Supports half/full duplex operation Supports auto-negotiation and auto cross-over detection IEEE 802.3/802.3u Compliance Operates 3.3V with 5V I/O signal tolerance Supports network status indicator LEDs Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP Includes Hardware Ethernet protocols: DLC, MAC Supports 4 independent connections simultaneously Supports MCU bus Interface and SPI Interface Supports Direct/Indirect mode bus access Supports Socket API for easy application programming Interfaces with two 2.54mm pitch 2 x 10 header pin Temperature : [PCB rev1.0] : 0 ~ 70℃ (Operation), -40 ~ 85℃ (Storage) [PCB rev1.1] : -40 ~ 85℃ (Operation), -40 ~ 85℃ (Storage) 1.2. Block Diagram © Copyright 2013 WIZnet Co., Ltd. All rights reserved 5 TOP WIZ8 10M J Data shee t WIZ812MJ Datasheet 1.3. Difference between WIZ811MJ and WIZ812MJ WIZ811MJ WIZ812MJ 6 TOP Two 2.54mm pitch 10x2 header The same pin-header is mounted but pin description is different J2:9 GND -> RX_LED J2:10 GND -> TX_LED J2:19 GND -> /LINKLED Two PCB Through Hole(Ø 3.00mm) Four PCB Through Hole(Ø 3.00mm) 55.5 x 25 x 23.5mm (W x H x D) The same size LINKLED : Active low in link state indicates a good status for 10/100M. It is always ON when the link is OK and it flashes while in a TX or RX state. /LINKLED : Active low in link state indicates a good status for 10/100M. It is always ON when the link is OK. It does not flashes while in a TX or RX state. ACT_LED : Active low in active state indicates a good status for 10/100M. It is always ON when the link is OK and it flashes while in a TX or RX state. © Copyright 2013 WIZnet Co., Ltd. All rights reserved WIZ8 10M J Data shee t WIZ812MJ Datasheet 2. Pin Assignments & descriptions 2.1. Pin Assignments 7 TOP WIZ8 10M J Data shee t © Copyright 2013 WIZnet Co., Ltd. All rights reserved WIZ812MJ Datasheet I : Input I/O : Bi-directional Input and output O : Output P : Power 2.2. Power & Ground Symbol Type Pin No. Description 3V3D P J1:12 , J2:1 Power : 3.3 V power supply GND P J1:11, J2:20 Ground 8 TOP 2.3. MCU Interfaces Symbol SCLK Type I Pin No. Description J2:3 SCLK(Serial Clock) This pin is used to SPI Clock Signal pin. /SCS I J2:4 /SCS (Slave Select) * This pin is used to SPI Slave Select signal Pin. This pin controls SPI_EN signal of W5100. When /SCS signal assert low, W5100 drive SPI mode by SPI_EN signal toggled high. MOSI I J1:1 MOSI (Master Out Slave In) * This pin is used to SPI MOSI signal pin. MISO I/O J1:2 MISO (Master In Slave Out) * This pin is used to SPI MISO signal pin. J1:13 ~ J1:19 Address Used as Address[14-8] pin A14~A8 I A7~A0 I J2:11 ~ J2:18 Address Used as Address[7-0] pin D7~D0 I/O J1:3 ~ J1:10 Data 8 bit-wide data bus /CS I J2:7 Module Select : Active low. /CS of W5100 /RD I J2:6 Read Enable : Active low. /RD of W5100 /WR I J2:5 Write Enable : Active low /WR of W5100 J2:8 Interrupt : Active low After reception or transmission it indicates that the W5100 requires MCU attention. By writing values to the Interrupt Status Register of W5100 the interrupt will be cleared. All interrupts can be masked by writing values to the IMR of W5100 (Interrupt Mask Register). For more details refer to the W5100 Datasheet /INT O © Copyright 2013 WIZnet Co., Ltd. All rights reserved WIZ8 10M J Data shee t WIZ812MJ Datasheet 2.4. Miscellaneous Signals Symbol Type Pin No. Description /RESET I J2:2 Reset : This pin is active low input to initialize or re-initialize W5100. By asserting this pin low for at least 2us, all internal registers will be re-initialized to their default states. RX_LED O J2:9 RX_LED : Receive activity LED Active low indicates the presence of receiving activity. TX_LED O J2:10 TX_LED : Transmit activity LED Active low indicates the presence of transmitting activity. /LINKLED O J2:19 LINKLED : Active low in link state indicates a good status for 10/100M. It is always ON when the link is OK. It does not flashes while in a TX or RX state. NC - J1 : 20 Not Connect © Copyright 2013 WIZnet Co., Ltd. All rights reserved 9 TOP WIZ8 10M J Data shee t WIZ812MJ Datasheet 3. Timing Diagrams WIZ812MJ provides following interfaces of W5100. -. Direct/Indirect mode bus access -. SPI access Reset Timing 3.1. 10 TOP 1 2 3.2. Description Reset Cycle Time /RESET to internal PLOCK Min 2 us - Max 10 ms Register/Memory READ Timing 1 2 3 4 5 6 Description Read Cycle Time Valid Address to /CS low time /CS low to /RD low time /RD high to /CS high time /RD low to Valid Data Output time /RD high to Data High-Z Output time © Copyright 2013 WIZnet Co., Ltd. All rights reserved Min 80 ns 8 ns - Max 1 ns 1 ns 80 ns 1 ns WIZ8 10M J Data shee t WIZ812MJ Datasheet 3.3. Register/Memory WRITE Timing 11 TOP 1 2 3 4 5 6 3.4. 1 2 3 4 5 6 Description Write Cycle Time Valid Address to /CS low time /CS low to /WR high time /CS low to /WR low time /WR high to /CS high time /WR low to Valid Data time Min 70 ns 7 ns 70 ns - Max 1 ns 1 ns 14 ns Min 21 ns 7 ns 28 ns 7 ns 21 ns 70 ns Max 14 ns - SPI Timing Description /SS low to SCLK Input setup time Input hold time Output setup time Output hold time SCLK time © Copyright 2013 WIZnet Co., Ltd. All rights reserved Mode Slave Slave Slave Slave Slave Slave WIZ8 10M J Data shee t WIZ812MJ Datasheet 4. Dimensions 12 TOP WIZ8 10M J Data shee t Symbols Dimensions (mm) A B C D E F G H I J K L M N 25.00 22.86 17.00 3.00 4.00 52.00 3.20 33.02 9.00 2.54 2.54 15.90 13.50 6.00 © Copyright 2013 WIZnet Co., Ltd. All rights reserved WIZ812MJ Datasheet 5. Schematic C12 0.1uF C13 0.1uF C14 3V3D C11 0.1uF 3V3A Y1 25MHz (SMD) 10uF/16V 15pF 15pF RSET_BG RXIP RXIN 1V8A TXOP TXON R1 1M XTLP XTLN A9 A11 A13 MISO D0 D2 D4 D6 3V3D 3V3D 1V8_OUT 1V8D 1V8D D7 D6 2 4 6 8 10 12 14 16 18 20 FB1 RSET_BG VCC3V3A NC GNDA RXIP RXIN VCC1V8A TXOP TXON GNDA 1V8_OUT VCC3V3D GNDD GNDD VCC1V8D VCC1V8D GNDD VCC3V3D DATA7 DATA6 U1 3V3D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 W5100 1uH C7 0.01uF C9 3V3A 10uF/16V 3V3D SCLK /WR /CS RX_LED A0 A2 A4 A6 /LINKLED 1 3 5 7 9 11 13 15 17 19 J2 2 4 6 8 10 12 14 16 18 20 A14 A13 A12 HEADER 10X2 2.54 Pitch NC /RESET /RD /WR /INT /CS ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 VCC3V3D GNDD ADDR10 ADDR11 /RESET /SCS /RD /INT TX_LED A1 A3 A5 A7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 A10 A11 /RESET /RD /WR /INT /CS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1V8_OUT 3V3D R11 4.7K C21 3.3uF/16V 1V8D 1uH 1V8A C28 0.1uF 0.1uF VCC 1Y 2Y GND C29 0.1uF C23 10uF/16V U7 1A 1B 2A 2B VCC 1Y 2Y GND 5 6 4 2 8 7 3 4 3V3D SN74LVC2G08DCT 1 2 5 6 0.1uF 1A U4 2A SN74LVC2G14DCK 3 1 1V8A C6 CHGND C10 CHGND C27 0.1uF ACT_LED RX_LED TX_LED C22 10uF/16V FB2 1V8D C26 0.1uF 3V3D LINK_LED /SCS C24 0.1uF 3V3D C17 0.1uF C18 U5 C25 0.1uF 0.1uF 1 D TXOP TXON RXIP RXIN VCC Q GND 3V3D CLK 5 4 3 SN74LVC1G79DCK 2 SPI_EN VCC 3V3D C3 R3 0.1uF R2 3V3A C4 49.9 R9 49.9 R8 0.1uF C5 0.1uF B A U6 49.9 1 R5 3V3D R4 9 10 1 2 3 4 5 6 7 8 /LINKLED 11 12 13 14 ACT_LED CHGND C20 CH_GND1 CH_GND2 L2L1+ L4L3+ TD+ TDTCT NC1 NC2 NC3 RD+ RD- U2 GH5 1 GH3 CON1 BS-RB10005 1 2 3 4 5 6 7 8 of /LINKLED GH4 CON8 0.1uF GH2 1 2 3 4 5 6 7 8 3V3D 200 5 4 3 200 VCC Y GND GH1 1 2 3 4 5 6 7 8 1 CHGND 1 2 3 4 5 6 7 8 CHGND CON8 CHGND CON8 CHGND CON8 SN74LVC1G32DCK 2 49.9 C19 0.1uF Title Sheet WIZ812MJ Thursday , October 04, 2012 Document Number Rev 1.1 © Copyright 2013 WIZnet Co., Ltd. All rights reserved 1V8D 1V8D R6 12K (1%) J1 R7 300 (1%) 1 3 5 7 9 11 13 15 17 19 D5 D4 D3 D2 D1 D0 MISO MOSI /SCS SCLK SPI_EN C1 C2 MOSI D1 D3 D5 D7 A8 A10 A12 A14 HEADER 10X2 2.54 Pitch Size A3 Date: 1 LINK_LED WIZ8 10M J Data shee t XTLP XTLN 1V8A TX_LED RX_LED TOP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NC NC NC GNDA XTLP XTLN VCC1V8A TXLED RXLED COLLED FDXLED VCC1V8D GNDD SPDLED LINKLED OPMODE2 OPMODE1 OPMODE0 NC NC 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 MISO MOSI /SCS SCLK SEN GNDD VCC1V8D TEST_MODE3 TEST_MODE2 TEST_MODE1 TEST_MODE0 ADDR14 ADDR13 ADDR12 13 WIZ812MJ Datasheet 6. Partlist Item 1 Q.ty 2 2 18 3 4 5 6 4 1 1 2 Reference C1,C2 C3,C4,C5,C6,C10, C12,C13,C14,C17, C18,C19,C20,C24, C25,C26,C27,C28, C29 C7,C11,C22,C23 C21 C9 FB1,FB2 7 2 J1,J2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 1 4 2 1 1 1 1 1 1 1 1 1 1 1 R1 R2,R3,R8,R9 R4,R5 R6 R7 R11 U1 U2 U4 U5 U6 U7 Y1 Part 15pF Tech. Characteristics 50V-20% Ceramic Package CASE 0603 0.1uF 50V-20% Ceramic CASE 0603 10uF/16V 3.3uF/16V 0.01uF 1uH Ferrite Inductor 2X10 2.54mm DIP STRAIGHT Header 1M 49.9 (1%) 200 12K (1%) 300 (1%) 4.7K W5100 BS-RB10005 SN74LVC2G14DCK SN74LVC1G79DCK SN74LVC1G32DCK SN74LVC2G08DCT 25MHz (SMD) PCB REV1.1 16Vmin 10% 16Vmin 10% 50V-20% Ceramic EIA/IECQ 3216 EIA/IECQ 3216 CASE 0603 CASE 0805 © Copyright 2013 WIZnet Co., Ltd. All rights reserved 2 X 10 2.54mm pitch 1/10W-5% SMD 1/10W-1% SMD 1/10W-5% SMD 1/10W-1% SMD 1/10W-1% SMD 1/10W-5% SMD WIZnet Hardware TCP/IP Transformer + RJ45 Dual Inverting Buffer D-type Flip Flop (vendor : TI) OR-Gate (vendor : TI) Dual AND-Gate (vendor : TI) SMD Type, Industrial FR4, 1.6T, 4Layer CASE 0603 CASE 0603 CASE 0603 CASE 0603 CASE 0603 CASE 0603 LQFP80 SC70-6 SC70-5 SC70-5 SM8 SX-1 14 TOP WIZ8 10M J Data shee t
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