WIZ810MJ Datasheet
(Ver. 1.3)
© 2013 WIZnet Co., Ltd. All Rights Reserved.
For more information, visit our website at www.wiznet.co.kr
WIZ810MJ Datasheet
Document History Information
Revision
Ver. 1.0
Data
September , 2007
Ver. 1.1
February, 2008
Ver. 1.2
January, 2009
Ver. 1.3
January, 2013
Description
Release with WIZ810MJ Launching
Hardware revision(ver.1.1).
Modified the SPI_EN signal description (P.8)
Modified the Schematic & Partlist : R10 is mounted
as SPI_EN pull-down resistor. (P.15~16)
Added temperature specification
Hardware revision(ver.1.2)
Changed operation temperature range(P.5)
Changed Partlist and schematic
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WIZ810MJ Datasheet
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© Copyright 2013 WIZnet Co., Ltd. All rights reserved
WIZ810MJ Datasheet
Table of Contents
1.
2.
3.
Introduction .............................................................................. 5
1.1.
Features ............................................................................. 5
1.2.
Block Diagram ...................................................................... 5
Pin Assignments & descriptions ................................................... 6
2.1.
Pin Assignments ................................................................... 6
2.2.
Power & Ground ................................................................... 6
2.3.
MCU Interfaces ..................................................................... 7
2.4.
Network status & LEDs ........................................................... 8
2.5.
Miscellaneous Signals ............................................................ 8
Timing Diagrams ....................................................................... 9
3.1.
Reset Timing ...................................................................... 9
3.2.
Register/Memory READ Timing ............................................... 10
3.3.
Register/Memory WRITE Timing .............................................. 11
3.4.
SPI Timing......................................................................... 12
4.
Dimensions ............................................................................. 13
5.
Connector Specification ............................................................ 14
6.
Schematic .............................................................................. 15
7.
Partlists .................................................................................. 16
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WIZ810MJ Datasheet
1. Introduction
WIZ810MJ is the network module that includes W5100 (TCP/IP hardwired chip, include PHY),
MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and no
effort is required to interface W5100 and Transformer. The WIZ810MJ is an ideal option for users
who want to develop their Internet enabling systems rapidly.
For the detailed information on implementation of Hardware TCP/IP, refer to the W5100
Datasheet.
WIZ810MJ consists of W5100 and MAG-JACK.
TCP/IP, MAC protocol layer: W5100
Physical layer: Included in W5100
Connector: MAG-JACK(RJ45 with Transformer)
1.1. Features
Supports 10/100 Base TX
Supports half/full duplex operation
Supports auto-negotiation and auto crossover detection
IEEE 802.3/802.3u Complaints
Operates 3.3V with 5V I/O signal tolerance
Supports network status indicator LEDs
Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP
Includes Hardware Ethernet protocols: DLC, MAC
Supports 4 independent connections simultaneously
Supports MCU bus Interface and SPI Interface
Supports Direct/Indirect mode bus access
Supports Socket API for easy application programming
Interfaces with Two 2.0mm pitch 2 * 14 header pin
Temperature :
[PCB rev1.0] : 0 ~ 70℃ (Operation), -40 ~ 85℃ (Storage)
[PCB rev1.1] : 0 ~ 70℃ (Operation), -40 ~ 85℃ (Storage)
[PCB rev1.2] : -40 ~ 85℃ (Operation), -40 ~ 85℃ (Storage)
1.2. Block Diagram
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2. Pin Assignments & descriptions
2.1.
Pin Assignments
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I : Input
I/O : Bi-directional Input and output
O : Output
P : Power
2.2. Power & Ground
Symbol
Type
VCC
GND
P
P
Pin No.
JP1:1 ,
JP1:8,
JP2:1,
JP2:13,
JP2:24
JP1:13, JP1:24,
JP2:4, JP2:7
JP2:14, JP2:23
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
Description
Power : 3.3 V power supply
Ground
WIZ810MJ Datasheet
2.3. MCU Interfaces
Symbol
Type
A14_SCLK
I
Pin No.
JP1:7
Description
ADDRESS PIN OR SCLK(Serial Clock)
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI Clock signal Pin.
A13_/SCS
I
JP1:10
ADDRESS PIN or /SCS (Slave Select) *
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI Slave Select signal Pin. In only SPI Mode,
this pin is active low
A12_MOSI
I
JP1:9
ADDRESS PIN or MOSI (Master Out Slave In) *
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI MOSI signal pin.
A11_MISO
I/O
JP1:12
ADDRESS PIN or MISO (Master In Slave Out) *
This pin is used to select a register or memory.
When asserting SPI_EN pin high, this pin is used
to SPI MISO signal pin.
A10~A8
I
JP1:11,
JP1:15
A7~A0
I
JP1:16 ~ JP1:23
Address
Used as Address[7-0] pin
D7~D0
I/O
JP2:21,
JP2:19,
JP2:17,
JP2:15,
Data
8 bit-wide data bus
/CS
I
JP1:5
Module Select : Active low.
/CS of W5100
/RD
I
JP1:4
Read Enable : Active low.
/RD of W5100
/WR
I
JP1:3
Write Enable : Active low
/WR of W5100
JP1:14
JP2:22
JP2:20
JP2:18
JP2:16
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Address
Used as Address[10-8] pin
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/INT
O
Interrupt : Active low
After reception or transmission it indicates that
the W5100 requires MCU attention.
By writing values to the Interrupt Status Register
of W5100 the interrupt will be cleared.
All interrupts can be masked by writing values to
the IMR of W5100 (Interrupt Mask Register).
For more details refer to the W5100 Datasheet
JP1:2
8
2.4. Network status & LEDs
You can observe the network status using MAG-JACK LEDs. LED interface can be extended to
the LED of the main board.
Symbol
Type
Pin No.
COL_LED
O
JP2:6
TX_LED
O
JP2:8
RX_LED
O
JP2:10
FDX_LED
O
JP2:11
LINK_LED
O
JP2:12
Description
Collision LED : Active low when collisions occur.
Transmit activity LED : Active low indicates the
presence of transmitting activity.
Receive activity LED : Active low indicates the
presence of receiving activity.
Full Duplex LED : Active low when in full duplex
operation. Active high when in half duplex
operation.
Link LED : Active low in link state indicates a
good status for 10/100M.
It is always ON when the link is OK and it flashes
while in a TX or RX state.
2.5. Miscellaneous Signals
Symbol
Type
Pin No.
/RESET
I
JP2:2
SPI_EN
I
JP2:9
NC
-
JP1 : 6, 25, 26, 27, 28
JP2 : 3, 5, 25, 26, 27, 28
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
Description
Reset : This pin is active low input to
initialize or re-initialize W5100.
By asserting this pin low for at least 2us,
all internal registers will be re-initialized
to their default states.
SPI Enable : This pin selects
Enable/Disable W5100 SPI Mode.
Low = SPI Mode Disable
High = SPI Mode Enable
A pull-down resistor(R10) sets to the
default of SPI Mode Disable.
H/W ver.1.0 : R10 is not mounted
H/W ver.1.1 : R10 is mounted
Not Connect
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3. Timing Diagrams
WIZ810MJ provides following interfaces of W5100.
-. Direct/Indirect mode bus access
-. SPI access
Reset Timing
3.1.
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1
2
Description
Reset Cycle Time
/RESET to internal PLOCK
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Min
2 us
-
Max
10 ms
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3.2.
Register/Memory READ Timing
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1
2
3
4
5
6
Description
Read Cycle Time
Valid Address to /CS low time
/CS low to /RD low time
/RD high to /CS high time
/RD low to Valid Data Output time
/RD high to Data High-Z Output time
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
Min
80 ns
8 ns
-
Max
1 ns
1 ns
80 ns
1 ns
WIZ810MJ Datasheet
3.3.
Register/Memory WRITE Timing
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1
2
3
4
5
6
Description
Write Cycle Time
Valid Address to /CS low time
/CS low to /WR high time
/CS low to /WR low time
/WR high to /CS high time
/WR low to Valid Data time
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
Min
70 ns
7 ns
70 ns
-
Max
1 ns
1 ns
14 ns
WIZ810MJ Datasheet
3.4.
SPI Timing
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1
2
3
4
5
6
Description
/SS low to SCLK
Input setup time
Input hold time
Output setup time
Output hold time
SCLK time
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Min
21 ns
7 ns
28 ns
7 ns
21 ns
70 ns
Max
14 ns
-
WIZ810MJ Datasheet
4. Dimensions
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Symbols
Dimensions (mm)
A
48.0
B
3.5
C
25.0
D
22.4
E
18.4
F
1.0
G
2.0
H
2.0
I
16.0
J
13.5
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
WIZ810MJ Datasheet
5. Connector Specification
UNIT:mm
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© Copyright 2013 WIZnet Co., Ltd. All rights reserved
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
3V3D
A8
A6
A4
A2
A0
D7
D6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
HEADER 14X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
JP1
1V8D
1V8D
1V8_OUT
RXIP
RXIN
1V8A
TXOP
TXON
3V3D
3V3A
XTLN
R1
1M
RSET_BG
/WR
/CS
A14_SCLK
A12_MOSI
A10
R7
300 (1%)
R6
12K (1%)
C2 15pF
Y1
RSET_BG
VCC3V3A
NC
GNDA
RXIP
RXIN
VCC1V8A
TXOP
TXON
GNDA
1V8_OUT
VCC3V3D
GNDD
GNDD
VCC1V8D
VCC1V8D
GNDD
VCC3V3D
DATA7
DATA6
A13_/SCS
A11_MISO
A9
A7
A5
A3
A1
/INT
/RD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
U1
D1
D3
D5
D7
SPI_EN
FDX_LED
C11
10uF/16V
D5
D4
D3
D2
D1
D0
MISO
MOSI
/SCS
SCLK
SPI_EN
25MHz (SMD)
XTLP
XTLN
1V8A
TX_LED
RX_LED
COL_LED
FDX_LED
1V8D
1V8D
XTLP
LINK_LED
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
NC
NC
NC
GNDA
XTLP
XTLN
VCC1V8A
TXLED
RXLED
COLLED
FDXLED
VCC1V8D
GNDD
SPDLED
LINKLED
OPMODE2
OPMODE1
OPMODE0
NC
NC
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
MISO
MOSI
/SCS
SCLK
SEN
GNDD
VCC1V8D
TEST_MODE3
TEST_MODE2
TEST_MODE1
TEST_MODE0
ADDR14
ADDR13
ADDR12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
3V3D
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D0
D2
D4
D6
COL_LED
TX_LED
RX_LED
LINK_LED
/RESET
0.1uF
C14
W5100
NC
/RESET
/RD
/WR
/INT
/CS
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
VCC3V3D
GNDD
ADDR10
ADDR11
3V3D
0.1uF
C13
HEADER 14X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
JP2
0.1uF
C12
3V3D
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A14
A13
A12
C1 15pF
FB1
3V3D
1uH
11
10
14
13
A12
MOSI
A11
MISO
4B1
4B2
3B1
3B2
2B1
2B2
1B1
1B2
U3
/OE
S
GND
1A
2A
3A
4A
VCC
15
1
8
4
7
9
12
16
4.7K
R10
FB2
RXIP
RXIN
TXOP
TXON
C22
0.1uF
C18
10uF/16V
1V8D
1V8D
SPI_EN
C17
3.3uF/16V
A14_SCLK
A13_/SCS
A12_MOSI
A11_MISO
3V3D
1V8_OUT
SN74CB3Q3257
5
6
2
3
C9
0.01uF
A13
/SCS
A14
SCLK
C7
10uF/16V
3V3A
A10
A11
/RESET
/RD
/WR
/INT
/CS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
49.9
R9
C23
0.1uF
1uH 1V8A
0.1uF
C5
49.9
R8
49.9
R2
0.1uF
C3
Date:
B
Size
Title
200
200
C20
0.1uF
9
10
1
2
3
4
5
6
7
8
1
U2
CON1
LOGO
0.1uF
C10
0.1uF
C6
Sheet
CHGND
CHGND
BS-RB10005
CH_GND1
CH_GND2
L2L1+
L4L3+
TD+
TDTCT
NC1
NC2
NC3
RD+
RD-
Friday, January 25, 2013
Document Number
WIZ810MJ
C21
0.1uF
CHGND
13
14
LINK_LED 11
12
FDX_LED
R5
R4
C25
0.1uF
C19
10uF/16V
0.1uF
C4
3V3A
C24
0.1uF
1V8A
49.9
R3
3V3A
1
3V3D
of
1
VCC
Rev
1.2
WIZ810MJ Datasheet
6. Schematic
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7. Partlists
Item
1
Q.ty
2
Part
15pF
Tech. Characteristics
50V-20% Ceramic
Package
CASE 0603
0.1uF
50V-20% Ceramic
CASE 0603
4
Reference
C1,C2
C3,C4,C5,C6,C10,
C12,C13,C14,C20,
C21,C22,C23,C24,C25
C7,C11,C18,C19
2
14
3
10uF/16V
16Vmin 10%
EIA/IECQ 3216
4
5
1
2
C9
FB1,FB2
50V-20% Ceramic
CASE 0603
CASE 0805
6
2
JP1,JP2
7
8
9
10
11
12
13
14
15
1
4
2
1
1
1
1
1
1
R1
R2,R3,R8,R9
R5,R4
R6
R7
R10
U1
U2
U3
0.01uF
1uH Chip Ferrite Inductor
2X14 28PIN 2mm DIP
STRAIGHT Header
1M
49.9
200
12K
300
16
1
Y1
25MHz (SMD)
17
1
PCB
WIZ810MJ REV1.2 1.6T
4LAYER
4.7K
W5100
BS-RB10005
SN74CB3Q3257
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
2 X 14 2mm pitch
1/10W-5% SMD
1/10W-1% SMD
1/10W-5% SMD
1/10W-1% SMD
1/10W-1% SMD
1/10W-5% SMD
WIZnet Hardware TCP/IP
Transformer + RJ45
Bus Switch(vendor : TI)
SMD Type, CL=18pF,
Industrial.
FR4, OSP
CASE 0603
CASE 0603
CASE 0603
CASE 0603
CASE 0603
CASE 0603
LQFP80
TSSOP
SX-1
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