DA7212
Company confidential
Datasheet/Ultra-low power stereo codec
General description
DA7212 is an ultra-low power audio codec targeting portable audio devices. The input paths support
stereo FM line input and up to four analogue (or two analogue and two digital) microphones with two
independent microphone biases. Comprehensive analogue mixing and bypass paths to the output
drivers are available.
The headphone output is true-ground Class G with integrated charge pump. There is also a
differential Class AB speaker driver that can serve as a mono lineout.
Digital audio transfer to/from the external processor is via a bidirectional digital audio interface that
supports all common sample rates and formats. The device may be operated in slave or master
modes using the internal PLL which may be bypassed if not required.
To fully optimise each customer application, a range of built in filtering, equalisation and audio
enhancements are available. These are accessible by the processor over the I2C serial interface.
Key features
■ 100 dB SNR stereo audio playback into
■ Built-in 5-band equaliser, ALC and noise-gate
16 - 32 Ω headphones
functions
■ 3.1 mW power consumption for stereo DAC to ■
headphone playback
■
■ 1.2 W mono speaker driver
■ 650 µW mono voice record
■
■ Stereo digital microphone support
■
■ Supports up to four analogue microphones
■
■ Two low-noise microphone-bias outputs
■ Low-power PLL provides system clocking and
Built-in beep generator
Integrated system controller to eliminate pops
and clicks
Minimised external component count
34-ball WLCSP (4.54 mm x 1.66 mm) package
Staggered 0.5 mm pitch for easy PCB routing
audio sample rate flexibility
Applications
■ Personal Media Players
■ Audio headphone/headsets
■ Wearables
■ Embedded applications
■ Arduino-compatible development systems
Figure 1: The DA7212 chip
Datasheet
CFR0011-120-00 Rev 4
Revision 3a
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Datasheet/Ultra-low power stereo codec
Contents
General description .................................................................................................................... 1
Key features ............................................................................................................................... 1
Applications ............................................................................................................................... 1
Contents .................................................................................................................................... 2
Figures ....................................................................................................................................... 6
Tables ........................................................................................................................................ 7
1
Terms and definitions ........................................................................................................... 9
2
Block diagram ......................................................................................................................10
3
Pinout .................................................................................................................................11
4
Absolute maximum ratings ..................................................................................................14
5
Recommended operating conditions ....................................................................................15
6
Electrical characteristics .......................................................................................................16
7
Parametric specifications .....................................................................................................17
8
Digital signal processing .......................................................................................................20
9
Audio outputs......................................................................................................................23
11 Clock generation ..................................................................................................................27
12 Phase Locked Loop (PLL) ......................................................................................................27
13 Digital interfaces..................................................................................................................28
13.1 Codec Start-Up Time ........................................................................................................... 31
14 Functional description .........................................................................................................32
14.1 General description............................................................................................................. 32
14.2 Input Signal Chain ............................................................................................................... 32
14.3 Microphone Inputs ............................................................................................................. 33
14.4 Digital microphones ............................................................................................................ 34
14.5 Auxiliary inputs ................................................................................................................... 35
14.6 Input mixers ........................................................................................................................ 35
14.7 Stereo audio ADC ................................................................................................................ 36
14.8 Automatic Level Control (ALC) ............................................................................................ 36
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14.9 Beep Generator and Controller .......................................................................................... 38
14.10 Output Signal Chain ............................................................................................................ 39
14.11 Stereo Audio DAC................................................................................................................ 40
14.12 Output Mixer ...................................................................................................................... 40
14.13 Headphone Amplifier .......................................................................................................... 41
14.14 Speaker Amplifier................................................................................................................ 41
14.15 Charge Pump Control .......................................................................................................... 42
14.16 Charge pump clock control ................................................................................................. 44
14.17 Boosting the charge pump using demand feedback control .............................................. 44
14.17.1 Tracking the demands on the charge pump output ............................................. 44
14.17.1.1 CP_MCHANGE = 00 (manual mode) .................................................. 44
14.17.1.2 CP_MCHANGE = 01 (tracking the PGA gain setting) .......................... 44
14.17.1.3 CP_MCHANGE = 10 (tracking the DAC signal setting)........................ 44
14.17.1.4 CP_MCHANGE = 11 (tracking the output signal magnitude) ............. 44
14.17.2 Specifying clock frequencies when tracking the charge pump output
demand................................................................................................................. 45
14.17.3 Controlling the boost of the charge pump clock-frequency ................................ 45
14.17.3.1 CP_ANALOGUE_LVL = 01 ................................................................... 45
14.17.3.2 CP_ANALOGUE_LVL = 10 ................................................................... 45
14.18 Other Charge Pump Controls .............................................................................................. 46
14.19 Digital Signal Processing Engine .......................................................................................... 46
14.20 Variable High Pass Audio Filter (DC Cut) ............................................................................. 47
14.21 Variable High Pass Filter (Wind Noise Filtering) ................................................................. 48
14.22 DAC 5-Band Equaliser ......................................................................................................... 49
14.23 Soft Mute ............................................................................................................................ 52
14.24 Playback Noise-Gate ........................................................................................................... 53
14.25 Clock Modes ........................................................................................................................ 53
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14.26 PLL Bypass Mode ................................................................................................................ 54
14.26.1 Normal PLL Mode (DAI Master)............................................................................ 55
14.26.2 Example calculation of the Feedback Divider setting: ......................................... 55
14.27 SRM PLL Mode (DAI Slave) .................................................................................................. 56
14.28 32 kHz PLL Mode (DAI Master) ........................................................................................... 56
14.28.1 Operating with a 2 MHz to 5 MHz MCLK .............................................................. 57
14.29 Mixed Sample Rates............................................................................................................ 57
14.30 I2C Control Interface ........................................................................................................... 57
14.31 Details of the I2C Control interface protocol ...................................................................... 58
14.32 Digital Audio Interface (DAI) ............................................................................................... 61
14.33 I2S Mode ............................................................................................................................. 63
14.34 Left Justified Mode ............................................................................................................. 63
14.35 Right Justified Mode ........................................................................................................... 63
14.36 DSP Mode............................................................................................................................ 64
14.37 Time Division Multiplexing (TDM) Mode ............................................................................ 65
14.37.1 Configuration of the Digital Audio Interface ........................................................ 66
14.38 Pop-Free and Click-Free Start-up using the System Controllers ......................................... 66
14.38.1 Level 1 System Controller (SCL1) .......................................................................... 66
14.38.2 Level 2 System Controller (SCL2) .......................................................................... 67
14.39 Power Supply – Standby Mode ........................................................................................... 67
14.39.1 Entering Standby Mode ........................................................................................ 67
14.39.2 Exiting Standby Mode........................................................................................... 67
15 Register definitions ..............................................................................................................69
15.1 Register map ....................................................................................................................... 69
15.2 Status registers ................................................................................................................... 76
15.3 System initialisation registers ............................................................................................. 84
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Datasheet/Ultra-low power stereo codec
15.4 Input gain/select filter registers.......................................................................................... 92
15.4.1
Output Gain-Filter Registers ................................................................................. 98
15.4.2
System Controller Registers ............................................................................... 108
15.4.3
Control Registers ................................................................................................ 110
15.4.4
Mixed Sample Mode Registers ........................................................................... 121
15.4.5
Configuration Registers ...................................................................................... 122
16 Package information .......................................................................................................... 140
17 Ordering information ......................................................................................................... 141
Appendix A Applications information ....................................................................................... 142
A.1
Codec initialisation ............................................................................................................ 142
A.2
Automatic ALC calibration ................................................................................................ 142
Appendix B Components ......................................................................................................... 143
B.1
Audio inputs ...................................................................................................................... 143
B.2
Microphone Bias ............................................................................................................... 144
B.3
Digital Microphone ........................................................................................................... 144
B.4
Audio Outputs ................................................................................................................... 145
B.5
Headphone Charge pump ................................................................................................. 146
B.6
Digital Interfaces ............................................................................................................... 147
B.7
Capacitor Selection ........................................................................................................... 147
Appendix C Calibration Routine ............................................................................................... 149
C.1
Troubleshooting ................................................................................................................ 149
C.2
References ........................................................................................................................ 150
C.3
Supplies ............................................................................................................................. 151
C.4
Ground .............................................................................................................................. 151
Appendix D PCB Layout Guidelines .......................................................................................... 152
D.1
Layout and Schematic support ......................................................................................... 152
D.2
General Recommendations .............................................................................................. 152
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Datasheet/Ultra-low power stereo codec
Figures
Figure 1: The DA7212 chip .................................................................................................................... 1
Figure 2: Block diagram showing component values for a typical application ................................... 10
Figure 3: DA7212 Ball layout ............................................................................................................... 11
Figure 4: I2C Bus Timing ...................................................................................................................... 29
Figure 5 Digital audio interface timing diagram .................................................................................. 30
Figure 6: Audio input routing and gain ranges .................................................................................... 33
Figure 7: Typical microphone application for MIC1 (MIC2 is similar) ................................................. 34
Figure 8: Digital microphone timing example ..................................................................................... 35
Figure 9: Principle of Operation of the ALC......................................................................................... 37
Figure 10: Attack, Delay and Hold parameters ................................................................................... 38
Figure 11: Analogue output signal paths and gain ranges .................................................................. 40
Figure 12: Input (clk) and Output Clocks (cp_clk and cp_clk2) at CP_FCONTROL = 010 ..................... 44
Figure 13: ADC and DAC DC blocking (Cut-off frequency setting ‘00’ to ‘11’, 16 kHz)........................ 48
Figure 14: Wind noise high-pass filter (cut-off frequency setting ‘000’ to ‘111’, 16 kHz) .................. 49
Figure 15: Equaliser filter Band 1 frequency response at FS = 48 kHz ................................................ 50
Figure 16: Equaliser filter Band 2 frequency response at FS = 48 kHz ................................................ 51
Figure 17: Equaliser filter Band 3 frequency response at FS = 48 kHz ................................................ 51
Figure 18: Equaliser filter Band 4 frequency response at FS = 48 kHz ................................................ 52
Figure 19: Equaliser filter Band 5 frequency response at FS = 48 kHz ................................................ 52
Figure 20: Schematic of the I2C control interface bus ........................................................................ 58
Figure 21 Timing of I2C START and STOP Conditions .......................................................................... 58
Figure 22: I2C Byte write (SDA signal) ................................................................................................. 59
Figure 23: Examples of the I2C Byte Read (SDA line) .......................................................................... 59
Figure 24: Examples of I2C Page Read (SDA line) ................................................................................ 59
Figure 25: I2C Page Write (SDA Line) .................................................................................................. 60
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Figure 26: I2C Repeated Write (SDA Line) ........................................................................................... 61
Figure 27: Master Mode (DAI_CLK_EN = 1) ........................................................................................ 61
Figure 28: Slave Mode (DAI_CLK_EN = 0) ............................................................................................ 62
Figure 29: I2S Mode ............................................................................................................................ 63
Figure 30: Left Justified Mode ............................................................................................................. 63
Figure 31: Right Justified Mode ........................................................................................................... 63
Figure 32: DSP Mode ........................................................................................................................... 64
Figure 33: TDM Example (slave mode)................................................................................................ 65
Figure 34: TDM Mode (left justified mode)......................................................................................... 65
Figure 35: DA7212 package outline drawing .................................................................................... 140
Figure 36 Micbias decoupling ............................................................................................................ 144
Figure 37 Recommended Headphone layout.................................................................................... 145
Figure 38 Charge Pump Decoupling .................................................................................................. 146
Figure 39 Charge Pump Flying Capacitor .......................................................................................... 146
Figure 40 I2C pull ups ........................................................................................................................ 147
Figure 41 Reference Capacitors ........................................................................................................ 150
Figure 42 Power Supply Decoupling .................................................................................................. 151
Figure 43 DA7212 Example Layout.................................................................................................... 152
Tables
Table 1: Pin descriptions ..................................................................................................................... 12
Table 2: Pin type definition ................................................................................................................. 13
Table 3: Absolute maximum ratings.................................................................................................... 14
Table 4: Recommended operating conditions .................................................................................... 15
Table 5: Power consumption............................................................................................................... 16
Table 6: Reference voltage generation ............................................................................................... 16
Table 7: Analogue to Digital Converter (ADC) ..................................................................................... 17
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Table 8: Microphone bias .................................................................................................................... 18
Table 9: Input mixing units .................................................................................................................. 19
Table 10: ADC/DAC Digital high-pass filter cut-off frequencies in music mode ................................. 20
Table 11: ADC/DAC Digital high-pass filter cut-off frequencies in voice mode .................................. 20
Table 12: DAC 5-Band equaliser frequencies ...................................................................................... 21
Table 13: Beep generator .................................................................................................................... 22
Table 14: Digital to Analogue Converter (DAC) ................................................................................... 23
Table 15: Class AB lineout amplifier / speaker .................................................................................... 24
Table 16: True Ground charge pump .................................................................................................. 25
Table 17: True Ground headphone amplifier ...................................................................................... 26
Table 18: MCLK Input .......................................................................................................................... 27
Table 19: PLL Mode ............................................................................................................................. 27
Table 20: Bypass Mode ....................................................................................................................... 28
Table 21: I/O Characteristics ............................................................................................................... 28
Table 22: I2C Control bus .................................................................................................................... 29
Table 23: Digital Audio Interface Timing (I2S/DSP in Master/Slave Mode) ........................................ 30
Table 24 Codec start-up times ............................................................................................................ 31
Table 25: DTMF Keypad frequencies ................................................................................................... 39
Table 26: Charge pump output voltage control .................................................................................. 42
Table 27: CP_THRESH_VDD2 Settings in DAC_VOL mode (CP_MCHANGE = 10) ................................ 43
Table 28: CP_THRESH_VDD2 Settings in Signal Size mode (CP_MCHANGE = 11)............................... 43
Table 29: Charge pump current load control ...................................................................................... 46
Table 30: ADC/DAC Digital High Pass Filter specifications in Audio Mode ......................................... 47
Table 31: Wind noise high-pass filter specifications ........................................................................... 48
Table 32: DAC 5-Band Equaliser Turnover/Centre Frequencies ......................................................... 50
Table 33: Sample rate control register and corresponding system clock frequency .......................... 54
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Datasheet/Ultra-low power stereo codec
Table 34: PLL Input Divider .................................................................................................................. 55
Table 35: Example PLL configurations ................................................................................................. 56
Table 36: Ordering information......................................................................................................... 141
Table 37: Audio inputs....................................................................................................................... 143
Table 38: Microphone bias ................................................................................................................ 144
Table 39: Digital microphones ........................................................................................................... 144
Table 40: Headphone outputs ........................................................................................................... 145
Table 41: Speaker outputs................................................................................................................. 145
Table 42: Headphone charge pump .................................................................................................. 146
Table 43: Digital interfaces – I2C ....................................................................................................... 147
Table 44: Offset calibration, MIC1_P and MIC2_P single ended, slave mode .................................. 149
Table 45: Digital interfaces - I2S ........................................................................................................ 150
Table 46: References ......................................................................................................................... 150
Table 47: Power supplies................................................................................................................... 151
Table 48: Ground ............................................................................................................................... 151
1
Terms and definitions
ADC
ALC
DAC
DAI
DTMF
I2C
I2S
PLL
PSSR
SNR
TDM
THD+N
Datasheet
CFR0011-120-00 Rev 4
Analogue Digital Converter
Automatic Level Control
Digital Audio Converter
Digital Audio Interface
Dual Tone Multi-Frequency
Inter-Integrated Circuit interface
Inter-IC Sound
Phase Locked Loop
Power Supply Rejection Ratio
Signal to Noise Ratio
Time Division multiplexing
Total Harmonic Distortion plus Noise
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2
Block diagram
AUX_L
MICBIAS1
1µF
AUX_L
_AMP
+
MIC
BIAS1
MIC1_P/
DMICCLK
GND_SENSE
DAC_L
HP_L_
AMP
MIC1_N/
DMICIN
AUX
Input
MIC_1
_AMP
+
MIXIN_L
Headphones
ADC
DIGITAL
FILTERS
DAC
DIGITAL
FILTERS
Wind Noise
Filtering,
Automatic
Level Control
(ALC)
Digital Mixer,
Digital
Volume,
5 Band
Equaliser,
Noise Gate
VDD_MIC
MIC2_P
MIC_2
_AMP
+
MIXIN_R
HP_L
ADC_L
HP_R_
AMP
HP_R
HPCSP
DA7212
HPCFP
1uF
HPCFN
Charge
Pump
ADC_R
1uF
GND_CP
HPCSN
1uF
MIC2_N
+
DAC_R
VDD_SP
MICBIAS2
SP_P
MIC
BIAS2
LINE_
AMP
+
SP_N
1µF
AUX_R_
AMP
VMID
VREF
DACREF
VDIG
BIAS
VDD_IO
VDD_A
LDO
GND_A
WCLK
DATIN
DIGITAL AUDIO
INTERFACE (DAI)
BCLK
BEEP
GENERATOR
DATOUT
CONTROL
INTERFACE
SCL
MCLK
PLL
SDA
AUX_R
Figure 2: Block diagram showing component values for a typical application
ADC Digital Filter
Control (ALC)
Analogue filter block incorporating wind noise filtering and Automatic Level
DAC Digital Filter
Digital filter block incorporating digital mixing, digital volume control, a 5-band
equaliser and a noise gate
Beep Generator
The Beep Generator block has two sine wave generators, each of which can
be independently controlled. Output frequency is controllable in 10 Hz step sizes, and output gain is
controllable in 3 dB steps from 0 dB to 45 dB. The Beep Generator block can also output standard
DTMF keypad frequencies (see Table 25).
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3
Pinout
1
A
HPCSP
B
C
2
3
HP_L
HPCSN
2
9
VMID
DATOUT
6
10
GND_A
SDA
9
10
13
14
SP_N
VDD_MIC
AUX_L
12
16
MIC1_N
AUX_R
13
14
17
MICBIAS2
MIC2_N
VDIG
11
15
MICBIAS1
SP_P
VDD_IO
8
12
MCLK
SCL
7
11
VDD_SP
VREF
WCLK
5
8
DACREF
DATIN
4
7
VDD_A
BCLK
3
6
HP_R
HPCFN
HPCFP
1
5
GND_
SENSE
GND_CP
D
4
MIC1_P
MIC2_P
15
16
17
KEY
Sensitive
Analogue
Low Power
(up to 100mA)
Quiet Ground
Noisy Digital
Medium Power
(up to 500mA)
Noisy Ground
View from above
“Live Bug”
Figure 3: DA7212 Ball layout
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Datasheet/Ultra-low power stereo codec
Table 1: Pin descriptions
Pin Name
Bump/Pin
Function
Alternate Function
Class
Audio Inputs
MIC1_P
C17
Differential mic. input 1 (pos) / Single-ended mic.
input 1 (left)
Digital mic. clock
(DMICCLK)
AI/DO
MIC1_N
B16
Differential mic. input 1 (neg) / Single-ended mic.
input 2 (left)
Digital Mic. data
(DMICIN)
AI/DI
MIC2_P
D16
Differential mic. input 2 (pos) / Single-ended mic.
input 1 (right)
AI
MIC2_N
C15
Differential mic. input 2 (neg) / Single-ended mic.
input 2 (right)
AI
AUX_L
C13
Single-ended auxiliary input left
AI
AUX_R
D14
Single-ended auxiliary input right
AI
MICBIAS1
A15
Microphone bias output 1
AO
MICBIAS2
A17
Microphone bias output 2
AO
Audio Outputs
HP_L
A3
True-ground headphone output left
AO
HP_R
A5
True-ground headphone output right
AO
SP_P
B12
Differential speaker output (pos)
AO
SP_N
A13
Differential speaker output (neg)
AO
Audio Charge pump
HPCSP
A1
Charge pump reservoir capacitor (pos)
AIO
HPCSN
C1
Charge pump reservoir capacitor (neg)
AIO
HPCFP
D2
Charge pump flyback capacitor (pos)
AIO
HPCFN
C3
Charge pump flyback capacitor (neg)
AIO
Digital Interfaces
SDA
C9
I2C bidirectional data
DIO
SCL
D8
I2C clock input
DI
DATIN
C5
DAI data input
DIO
DATOUT
C7
DAI data output
DIO
BCLK
D4
DAI bit clock
DIO
WCLK
D6
DAI word clock (L/R select)
DIO
MCLK
C11
Master clock
DI
References
DACREF
A7
Audio DAC reference capacitor
AIO
VMID
A9
Audio mid-rail reference capacitor
AIO
GND_SENSE
B4
Ground reference for headphone output
VREF
B8
Bandgap reference capacitor
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Datasheet/Ultra-low power stereo codec
Pin Name
Bump/Pin
Function
Alternate Function
Class
Supplies
VDD_A
B6
Supply for analogue circuits
PS
VDD_IO
D10
Supply for digital interfaces
PS
VDD_SP
A11
Supply for speaker driver
PS
VDD_MIC
B14
Supply for microphone bias circuits
PS
VDIG
D12
Supply for digital circuits (LDO Output)
PS
Grounds
GND_A
B10
Analogue ground
PG
GND_CP
B2
Charge pump/digital ground
PG
Table 2: Pin type definition
Pin type
Description
Pin type
Description
DI
Digital Input
AI
Analogue Input
DO
Digital Output
AO
Analogue Output
DIO
Digital Input/Output
AIO
Analogue Input/Output
DIOD
Digital Input/Output open drain
PU
Fixed pull-up resistor
SPU
Switchable pull-up resistor
PD
Fixed pull-down resistor
SPD
Switchable pull-down resistor
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4
Absolute maximum ratings
Table 3: Absolute maximum ratings
Symbol
Ta
Parameter
Test Conditions
Unit
+165
°C
Operating
Temperature
-40
+85
°C
-0.3
6.0
V
-0.3
2.75
V
-0.3
5.5
V
-0.3
VDD_IO +
0.3
Supply Voltages
Digital Interface
Signals
Package Thermal
Resistance
ESD Susceptibility
Note 1
Max
-65
VDD_IO
VDD_MIC
SDA
SCL
BCLK
WCLK
DATIN
DATOUT
Typ
Storage Temperature
VDD_SP
VDD_A
Min
60
Human body model
°C/W
2
kV
Stresses beyond those listed under ‘Absolute maximum ratings’ may cause permanent damage to the
device. These are stress ratings only, so functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specification are not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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Recommended operating conditions
Table 4: Recommended operating conditions
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Operating
temperature
-40
+85
°C
Supply Voltages
1.6
2.65
V
VDD_IO
1.5
3.6
V
VDD_MIC
1.8
3.6
V
VDD_SP
0.95
5.25
V
Ta
VDD_A
Note 2
Within the specified limits, a life time of 10 years is guaranteed
Note 3
All Voltages are referenced to VSS unless otherwise stated
Note 4
Currents flowing into DA7212 are deemed positive. Currents flowing out are deemed negative
Note 5
All parameters are valid over the recommended temperature range and power supply range unless
otherwise noted.
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6
Electrical characteristics
Table 5: Power consumption
Power
Consumption
Unit
5
µA
DAC_L/R to LINE, 10 kΩ load
2.2
mW
Digital playback to Headphone,
no load
DAC_L/R to HP_L/R, quiescent
3.1
mW
Digital playback to Headphone,
with load
DAC_L/R to HP_L/R, 16 Ω load, 0.1 mW at
0 dBFS
6.9
mW
AUX_L/R to LINE, 10 kΩ load
2.0
mW
AUX_L/R to HP_L/R, quiescent
2.6
mW
AUX_L/R to HP_L/R, 16 Ω load, 0.1 mW at
0 dBFS
6.7
mW
MIC_1/2 to ADC_L/R
2.1
mW
Microphone stereo record and
digital playback to Headphone,
no load
MIC_1/2 to ADC_L/R and
DAC_L/R to HP_L/R, quiescent
4.8
mW
Microphone stereo record and
digital playback to Headphone,
with load
MIC_1/2 to ADC_L/R and
DAC_L/R to HP_L/R, 16 Ω load,
0.1 mW at 0 dBFS
8.9
mW
MIC_1 to ADC_R, 8 kHz, quiescent,
optimised clocking and bias
0.65
mW
Operating Mode
Conditions (Note 6)
Powerdown mode
Digital playback to Lineout
Analogue bypass to Lineout
Analogue bypass to
Headphone, no load
Analogue bypass to
Headphone, with load
Microphone stereo record
Ultra-low power microphone
mono record
Note 6
VDD_A=VDD_SP=VDD_IO=1.8 V, Ta=25°C, Fs=48 kHz, Charge pump signal-size mode, 0x95 =
0x06
Table 6: Reference voltage generation
Symbol
Parameter
VMID
Audio mid-rail voltage
CVMID
VMID decoupling capacitor
Test Conditions
Min
Typ
Max
Unit
0.45 × VDD_A
V
1.0
µF
0.9 × VDD_A
V
DACREF decoupling capacitor
1.0
µF
VBG
Bandgap voltage
1.2
V
CVBG
Bandgap decoupling capacitor
1.0
µF
DACREF
CDACREF
Audio DAC/ADC reference voltage
Datasheet
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7
Parametric specifications
Table 7: Analogue to Digital Converter (ADC)
Symbol
VMAX
SNR
(Note 7)
THD+N (Note 8)
Parameter
Test Conditions
Full-scale input
signal
Digital output level
= 0 dBFS
1.6 ×
VDD_A
VPP
Signal to Noise
Ratio
A-weighted
no input selected
90
dB
-1 dBFS
44.1 kHz slave
mode
-85
dB
-1 dBFS
32 kHz PLL mode
-80
dB
Analog input level =
0 dBFS
-85
dB
90
dB
Total Harmonic
Distortion plus
Noise
In-band Spurious
Min
Channel separation
BPASS
Pass band
BSTOP
Stop band
PSRR (Note 9)
with respect to
VDD_A
Fs 48 kHz
Fs = 88.2/96 kHz
Pass band Ripple
Voice mode
Music mode
Stop band
Attenuation
Voice mode
Music mode
Group delay
Voice mode
Music mode
Fs = 88.2/96 kHz
Group delay
mismatch
Between left and
right channels
Power Supply
Rejection Ratio
20Hz – 2 kHz
20 kHz
Typ
0.56*Fs
Max
Unit
0.45*Fs
Hz
7*Fs
3.5*Fs
Hz
±0.3
±0.1
dB
70
55
dB
4.3/Fs
18/Fs
9/Fs
600
µs
2
µs
70
50
dB
Note 7
SNR (Signal-to-Noise Ratio) is a ratio of the full-scale output signal level to the noise level with no
signal applied
Note 8
THD+N (Total Harmonic Distortion plus Noise) is a ratio of the level of the harmonics and noise to the
output signal
Note 9
PSRR (Power Supply Rejection Ratio) is a measure of the attenuation of a signal on the supply to the
signal at the output
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Table 8: Microphone bias
MICBIAS1 and MICBIAS2
Symbol
VMICBIAS
IBIAS
PSRR with
respect to
VDD_MIC
VNOISE
Parameter
Bias Voltage
Maximum Current
Power Supply
Rejection Ratio
Output Noise Voltage
Capacitive Load
Datasheet
CFR0011-120-00 Rev 4
Test Conditions
No load, VDD_MIC >
VMICBIAS + 200 mV
Min
Typ
Max
1.52
1.57
1.62
2.18
2.25
2.32
2.41
2.48
2.56
2.91
3.00
3.10
V
Voltage drop < 50 mV
20Hz – 200 Hz
>2 kHz
Unit
2
70
50
mA
dB
VMICBIAS ≤ 2.2 V
5
µVRMS
IBIAS < 100 µA
100 µA < IBIAS < 2 mA
100
200
pF
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Table 9: Input mixing units
(MIC1_P/MIC1_N/MIC2_P/MIC2_N/AUX_L/AUX_R ) to ADC_L/ADC_R
Symbol
VMAX
Parameter
Test Conditions
Full-scale input signal
Single-ended
Differential
MIC_1/2_AMP =
AUX_L/R_AMP = MIXIN_L/R =
0dB
RIN
Input resistance
CIN
Input capacitance
Amplitude ripple
PSRR with
respect to
VDD_A
MIC, single-ended
AUX
Min
Typ
Max
Unit
0.8 × VDD_A
1.6 × VDD_A
VPP
12
6
15
18
40
1
kΩ
pF
20Hz to 20 kHz
-0.5
+0.5
dB
Programmable gain
MIC_1_AMP and MIC_2_AMP
AUX_L_AMP and AUX_R_AMP
MIXIN_L and MIXIN_R
-6
-54
-4.5
36
15
18
dB
Programmable gain
step size
MIC_1_AMP and MIC_2_AMP
AUX_L_AMP and AUX_R_AMP
MIXIN_L and MIXIN_R
6
1.5
1.5
dB
Absolute gain
accuracy
0 dB @ 1 kHz
-1.0
+1.0
dB
Left/Right gain
mismatch
20 Hz to 20 kHz
-0.1
+0.1
dB
Gain step error
20 Hz to 20 kHz
-0.1
+0.1
dB
Input noise level
Inputs connected to GND,
A-weighted, input-referred,
measured @ ADC output
MIC_1/2_AMP = 24 dB
AUX_L/R_AMP = 15 dB
Power supply
rejection ratio
Datasheet
CFR0011-120-00 Rev 4
µVRMS
5
6.5
Single-ended input
20Hz to 2 kHz
20 kHz
70
50
dB
Differential input
20Hz to 2 kHz
20 kHz
90
70
dB
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8
Digital signal processing
Table 10: ADC/DAC Digital high-pass filter cut-off frequencies in music mode
Sampling
Frequency (kHz)
Music Mode – Cut-Off Frequency (-3 dB) in Hz at
ADC_AUDIO_HPF_CORNER / DAC_AUDIO_HPF_CORNER Register Settings
00
01
10
11
8
0.3
0.7
1.3
2.7
11.025
0.4
0.9
1.8
3.7
12
0.5
1
2
4
16
0.7
1.3
2.7
5.3
24
1
2
4
8
32
1.3
2.7
5.3
10.7
44.1
1.8
3.7
7.3
14.7
48
2
4
8
16
88.2
3.6
7.4
14.6
29.4
96
4
8
16
32
Table 11: ADC/DAC Digital high-pass filter cut-off frequencies in voice mode
Sampling
Frequency (kHz)
Voice Mode – Cut-Off Frequency (-3 dB) in Hz at
ADC_VOICE_HPF_CORNER / DAC_VOICE_HPF_CORNER Register Settings
000
001
010
011
100
101
110
111
8
2.66
25
50
100
150
200
300
400
11.025
3.5
35
69
138
207
275
415
553
12
4
37.5
75
150
225
300
450
600
16
5
50
100
200
300
400
600
800
Datasheet
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Table 12: DAC 5-Band equaliser frequencies
Centre/Cutoff frequency of 5-Band Equaliser (Hz)
Sampling
Frequency (kHz)
Band 1
Cutoff (Note 10)
Band 2
Centre
Band 3
Centre
Band 4
Centre
Band 5
Cutoff (Note 10)
8
21
85
563
1151
2909
11.025
29
117
776
2137
4009
12
31
128
845
2326
4364
16
41
90
441
2128
5840
22.05
56
124
607
2933
8048
24
61
135
664
3192
8759
32
58
95
418
1731
6374
44.1
80
132
577
2385
8784
48
87
143
628
2596
9560
88.2
N/A
N/A
N/A
N/A
N/A
96
N/A
N/A
N/A
N/A
N/A
Note 10 For equaliser bands 1 and 5 the cut-off frequency depends on the gain setting. The figures quoted in
this table refer to the –1 dB point with the band gain set to –3 dB
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Table 13: Beep generator
Symbol
Parameter
Test Conditions
Single-tone frequency
Min
10
Max
Unit
12000
Hz
Single-tone frequency step
10
Hz
Dual-tone modulation
frequency A
697
770
852
941
Hz
Dual-tone modulation
frequency B
1209
1336
1477
1633
Hz
Output signal level
-45
Output signal step size
TON,TOFF
Typ
3
On/off pulse duration
On/off pulse step size
On/off pulse repeat
Datasheet
CFR0011-120-00 Rev 4
0
10
dBFS
dB
2000
ms
TON/OFF=10 – 200ms
TON/OFF=200 – 2000ms
10
50
ms
continuous mode
1,2,4,8,16,32
∞
cycles
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9
Audio outputs
Table 14: Digital to Analogue Converter (DAC)
Symbol
Parameter
VMAX
Full-scale output signal
SNR
Signal to Noise Ratio
THD+N
Total Harmonic
Distortion Plus Noise
Test Conditions
Min
Pass band
BSTOP
Stop band
PSRR with
respect to
VDD_A
Datasheet
CFR0011-120-00 Rev 4
Unit
1.6×VDD_A
VPP
A-weighted
100
dB
-1 dBFS
44.1 kHz slave
mode
-90
dB
-1 dBFS
32 kHz PLL mode
-80
dB
90
dB
Fs 48 kHz
Fs = 88.2/96 kHz
Pass band Ripple
Voice mode
Music mode
Stop band Attenuation
Voice mode
Music mode
Group delay
Max
Digital input level =
0 dBFS
Channel separation
BPASS
Typ
0.56×Fs
0.45×Fs
kHz
7×Fs
3.5×Fs
kHz
±0.15
±0.1
dB
70
55
Voice mode
Music mode
Fs = 88.2/96 kHz
dB
4.8/Fs
18.5/Fs
9/Fs
650
µs
Group delay variation
20Hz to 20 kHz
1
µs
Group delay mismatch
Between left and
right channels
2
µs
Power Supply Rejection
Ratio
20Hz to 2 kHz
20 kHz
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50
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Table 15: Class AB lineout amplifier / speaker
From DAC_L/DAC_R to (SP_P, SP_N)
Symbol
Parameter
Test Conditions
VMAX
Full-scale output signal
No load
1.8×VD
D_SP
VPP
VDD_SP = 1.2 V
THD < 10 %
RLOAD = 8 Ω, 1 kHz
65
mW RMS
VDD_SP = 1.5 V
THD < 10 %
RLOAD = 8 Ω, 1 kHz
115
mW RMS
VDD_SP = 3.7 V
THD < 10 %
RLOAD = 8 Ω, 1 kHz
745
mW RMS
VDD_SP = 5.0 V
THD < 10 %
RLOAD = 8 Ω, 1 kHz
1200
mW RMS
PMAX
Maximum output power
Min
6.4
RLOAD
Typ
Amplitude ripple
Ω
µH
pF
±0.5 dB
20
20k
Hz
20Hz to 20 kHz
-0.5
0.5
dB
-48
+15
dB
Programmable gain
Mute attenuation
Programmable gain
step size
Absolute gain accuracy
Unit
1
200
8
Load impedance
Frequency response
Max
100
dB
1
dB
0 dB @ 1 kHz
-0.8
+0.8
dB
Gain step error
20 Hz to 20 kHz
-0.1
+0.1
dB
SNR
Signal to noise ratio
A-weighted
gain = 0 dB
VDD_SP = 1.6 V
96.5
dB
VNOISE
Output Noise Level
Non A-weighted
Gain ≤ -15 dB
20Hz to 20 kHz
6
µV
VDD_SP = 1.6 V
-1 dBFS
44.1 kHz slave mode
RLOAD > 2 kΩ
-86
dB
VDD_SP = 1.6 V
-1 dBFS
32 kHz PLL mode
RLOAD > 2 kΩ
-80
dB
THD+N
PSRR with
respect to
VDD_SP
Total Harmonic
Distortion Plus Noise
Power Supply
Rejection Ratio
Datasheet
CFR0011-120-00 Rev 4
20 Hz to 2 kHz
20 kHz
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70
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Table 16: True Ground charge pump
HPCSP and HPCSN
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VDDCSP
Positive rail output
CP_MOD = 11
CP_MOD = 10
VDD_A
VDD_A / 2
V
VDDCSN
Negative rail output
CP_MOD = 11
CP_MOD = 10
-VDD_A
-(VDD_A /
2)
V
Flyback capacitor
One capacitor
1.0
µF
Reservoir capacitors
Two capacitors
1.0
µF
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Table 17: True Ground headphone amplifier
From DAC_L/DAC_R to (HP_L/HP_R)
Symbol
Parameter
Test Conditions
VMAX
Full-scale Output Signal
No load
DC output offset
PMAX
RLOAD
LLOAD
CLOAD
Maximum power per
channel
HP Gain < -30 dB
PSRR with
respect to
VDD_A
Datasheet
CFR0011-120-00 Rev 4
Unit
VPP
µV
VDD_A = 1.6 V
THD < 0.1 %
RLOAD=16 Ω, 1 kHz
L = 23
R = 23
mW RMS
VDD_A = 1.8 V
THD < 0.1 %
RLOAD=16 Ω, 1 kHz
L = 29
R = 29
mW RMS
VDD_A = 2.5 V
THD < 0.1 %
RLOAD=16 Ω, 1 kHz
L = 67
R = 67
mW RMS
400
500
Ω
µH
pF
16
±0.5 dB
20
20k
Hz
20Hz to 20 kHz
-0.5
+0.5
dB
-56
+6
dB
Programmable Gain
THD+N
Max
100
Load Impedance
Amplitude Ripple
VNOISE
Typ
1.6×VDD_A
13
Frequency Response
SNR
Min
Mute Attenuation
70
dB
Programmable Gain
Step Size
1.0
dB
Absolute Gain Accuracy
0 dB @ 1 kHz
-0.8
+0.8
dB
Input Gain L/R-Mismatch
20Hz to 20 kHz
-0.1
+0.1
dB
Input Gain Step Error
20Hz to 20 kHz
-0.1
+0.1
dB
Signal to Noise Ratio
A-weighted
gain = 0 dB
VDD_A = 2.5 V
VDD_A = 1.8 V
Output Noise Level
20 to 20 kHz,
non A-weighted
gain < -20 dB
Total Harmonic
Distortion Plus Noise
VDD_A = 1.6 V
-5 dBFS
RLOAD=16 Ω
Power Supply Rejection
Ratio
20Hz to 2 kHz
20 kHz
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dB
100
98
2.5
-87
70
50
µVrms
dB
dB
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11 Clock generation
Table 18: MCLK Input
Symbol
Parameter
Test Conditions
Min
Typ
Input Amplitude
MCLK squarer enabled
MCLK squarer disabled
0.3
0.9×VDD_IO
Input Impedance
DC impedance > 10 MΩ
300
0.5
1
Max
Unit
VDD_IO
VDD_IO
V
2
Ω
pF
12 Phase Locked Loop (PLL)
Table 19: PLL Mode
Symbol
JC
JA
Parameter
MCLK Input Jitter
Test Conditions
Min
Typ
Cycle jitter (rms)
Absolute jitter (rms)
Max
Unit
50
100
ps
ps
FIN
Input frequency
Normal mode
32 kHz mode
SRM Tracking Range
DAI slave mode
WCLK frequency
variation
SRM Tracking Rate
DAI slave mode
WCLK drift rate
2 (Note 11)
-4
5 - 50
32.768
50
MHz
kHz
4
%
50
ppm/s
Note 11 See section 32 kHz PLL Mode (DAI Master) on page 56 for further details on using an MCLK
frequency between 2 MHz and 5 MHz
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Table 20: Bypass Mode
Symbol
Parameter
JC
JA
Input Jitter
FIN
Input frequency
Test Conditions
Min
Typ
Cycle jitter (rms)
Absolute jitter (rms)
Sample frequency:
11.025, 22.05, 44.1, 88.2 kHz
8, 12, 16, 24, 32, 48, 96 kHz
Max
Unit
TBD
TBD
ps
11.2896
12.288
ps
MHz
13 Digital interfaces
Table 21: I/O Characteristics
Symbol
Parameter
VIH
SCL, SDA,
Input High Voltage
VIL
SCL, SDA,
Input Low Voltage
VIH
MCLK, BCLK, WCLK, DATIN,
DATOUT
Input High Voltage
VIL
MCLK, BCLK, WCLK, DATIN,
DATOUT
Input Low Voltage
VOL
@3mA
Test
Conditions
CFR0011-120-00 Rev 4
Typ
Max
0.7*VDD_IO
0.7*VDD_IO
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Unit
V
0.3*VDD_IO
SDA Output Low Voltage
Datasheet
Min
V
V
0.3*VDD_IO
V
0.24
V
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CLKL
CLKH
SCL
STH
DST
DHT
TSS
SDA
Figure 4: I2C Bus Timing
Table 22: I2C Control bus
Symbol
Test Conditions
(Note 12)
Parameter
Bus free time STOP to START
Min
Typ
Max
500
Bus line capacitive load
Unit
ns
150
pF
1000
kHz
Standard/Fast Mode
SCL clock frequency
0
Start condition setup time
260
ns
STH
Start condition hold time
260
ns
CLKL
SCL low time
500
ns
CLKH
SCL high time
260
ns
SCL rise/fall time
Input requirement
1000
ns
SDA rise/fall time
Input requirement
300
ns
DST
SDA setup time
50
ns
DHT
SDA hold time
0
ns
TSS
Stop condition setup time
260
ns
High-Speed Mode
SCL clock frequency
0
3400
kHz
Start condition setup time
160
ns
STH
Start condition hold time
160
ns
CLKL
SCL low time
160
ns
CLKH
SCL high time
60
ns
SCL rise/fall time
Datasheet
CFR0011-120-00 Rev 4
Input requirement
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SDA rise/fall time
Input requirement
160
ns
DST
SDA setup time
10
ns
DHT
SDA hold time
0
ns
TSS
Stop condition setup time
160
ns
Note 12 VDD_IO = 1.8 V
T
WCLK
tdCW
tf
tsW
thW
thC
tr
tlC
BCLK
tdWD
tdCD
DATOUT
tsD
thD
DATIN
Figure 5 Digital audio interface timing diagram
Note 13 Diagram shown is valid for all modes except DSP. For DSP mode the BCLK signal is inverted
Table 23: Digital Audio Interface Timing (I2S/DSP in Master/Slave Mode)
Symbol
Parameter
Input impedance
Test
Conditions
(Note 14)
Min
DC impedance
> 10MΩ
300
1.0
Typ
Max
Unit
2.5
Ω
pF
T
BCLK period
75
ns
tr
BCLK rise time
8
ns
tf
BLCK fall time
8
ns
thC
BCLK high period
40 %
60 %
T
tlC
BCLK low period
40 %
60 %
T
tdCW
BCLK to WCLK
delay
-30 %
+30 %
T
tdCD
BCLK to DATOUT
delay
-30 %
+30 %
T
thW
WCLK high time
Datasheet
CFR0011-120-00 Rev 4
DSP mode
100 %
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tlW
WCLK low time
Non-DSP
mode
Word
length
(Note 15)
T
DSP mode
100 %
T
Non-DSP
mode
Word
length
(Note 16)
T
tsW
WCLK setup time
Slave mode
7
ns
thW
WCLK hold time
Slave mode
2
ns
tsD
DATIN setup time
7
ns
thD
DATIN hold time
2
ns
tdWD
DATOUT to WCLK
delay
DATOUT is synchronised to BCLK
Note 14 VDD_IO = 1.8 V
Note 15 WCLK must be high for at least the word length number of BCLK periods
Note 16 WCLK must be low for at least the word length number of BCLK periods
13.1 Codec Start-Up Time
After the audio system controller has been enabled using SYSTEM_MODES_INPUT and
SYSTEM_MODES_OUTPUT, the startup times for the various codec paths are as specified below:
Table 24 Codec start-up times
Source
Output
Comment
VMID
VMID > 90 % of final
value
1µF capacitor
Any analogue input or
DAC_L/R
HP_L
HP_R
PLL bypass or PLL
normal mode
Any analogue input or
DAC_L/R
HP_L
HP_R
Any analogue input or
DAC_L/R
Min
Typ
Max
Unit
25
ms
200
ms
PLL SRM or PLL 32 kHz
mode
500
ms
SP_P
SP_N
PLL bypass or PLL
normal mode
250
ms
Any analogue input
ADC_L
ADC_R
PLL bypass or PLL
normal mode
200
ms
Any analogue input
ADC_L
ADC_R
PLL SRM or PLL 32 kHz
mode
600
ms
Datasheet
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14 Functional description
14.1 General description
DA7212 is an ultra-low-power audio CODEC with true ground headphone drivers, mixing capability,
and digital audio enhancement. It offers HiFi audio quality with class-leading power consumption for
portable media and embedded applications.
Featuring a high efficiency headphone amplifier and minimum supply voltage of 1.6 V, the ultra-low
3.1 mW quiescent power consumption extends music playback time for battery-operated equipment.
Control and data interfaces are supplied from a dedicated VDD_IO rail. For compatibility with higher
I/O levels, an extended voltage range up to 3.6 V can be selected.
The integrated PLL uses a fractional-N architecture that supports frequencies from 2 MHz to 50 MHz.
Standard mobile phone/USB system clock frequencies are supported, and audio data
synchronisation is supported even when no master clock is available.
The DA7212 has a stereo pair of single-ended line inputs as well as two microphone inputs, each of
which can be configured as single-ended or differential. Both line and microphone signals can be
routed to the ADC or directly to the output mixers via a bypass path. In addition, the DA7212
supports both single and dual-channel digital microphone inputs by routing the digital signals directly
to the ADC digital filters.
Input and output mixers with stereo-to-mono conversion also support mono configurations such as
single speaker outputs.
Three output drivers are available in the output stage of the DA7212. A stereo true-ground amplifier
directly drives standard 3-wire 16 ohm headphones while a differential mono speaker amplifer is
capable of driving 1.2W into 8 ohms.
Audio enhancement functions are performed digitally including programmable high-pass filtering, 5band EQ, noise-gate and an AGC with configurable attack and decay parameters.
The multislot I2S/PCM Digital Audio Interface (DAI) supports all common sample rates between
8 kHz and 96 kHz in master or slave modes.
The CODEC register space can be accessed via the I2C interface of DA7212 on the default 7-bit
address 0x1A.
DA7212 implements a unique Smart Controller that enables easy configuration of the Codec for
different application scenarios, thereby reducing the number of register writes needed for each case.
The Smart Controller runs automatically once enabled, and is optimised to allow pop-free and
click-free power-up and power-down operation.
14.2 Input Signal Chain
The DA7212 has a stereo pair of single-ended line inputs as well as two microphone inputs that can
each be configured as single-ended or differential. Both line and microphone signals can be routed to
the ADC or directly to the output mixers via a bypass path. In addition, the DA7212 supports both
single and dual channel digital microphone inputs by routing the digital signals directly to the ADC
digital filters. The input routing paths and input amplifier gain ranges are illustrated in Figure 5.
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-54dB to +15dB
in 1.5dB steps
AUX_L_AMP
AUX_L
MIC1_P /
-6dB to +36dB
in 6dB steps
MIC_1_AMP
DMICCLK
to ADC_L
MIXIN_L
-4.5dB to +18dB
in 1.5dB steps
MIC1_N /
DMICIN
to ADC filters
MICBIAS1
MICBIAS2
MIC2_P
MIC2_N
MIC_2_AMP
-6dB to +36dB
in 6dB steps
to ADC_R
MIXIN_R
-4.5dB to +18dB
in 1.5dB steps
AUX_R
AUX_R_AMP
-54dB to +15dB
in 1.5dB steps
from PLL
Figure 6: Audio input routing and gain ranges
14.3 Microphone Inputs
The DA7212 includes two pairs of analogue microphone inputs that can be connected in three ways:
● fully differential mode for improved common mode noise rejection
● single ended or pseudo-differential mode by connecting MIC1_N or MIC2_N to GND (see Figure
7). The microphone source is specified using MIC_1_AMP_IN_SEL and MIC_2_AMP_IN_SEL
● single ended or pseudo-differential mode by connecting MIC1_P or MIC2_P to GND (see Figure
7). The microphone source is specified using MIC_1_AMP_IN_SEL and MIC_2_AMP_IN_SEL
The microphone PGAs are enabled by the MIC_1_AMP_EN / MIC_2_AMP_EN controls and can be
muted via MIC_1_AMP_MUTE_EN / MIC_2_AMP_MUTE_EN. For maximum flexibility, each
microphone channel includes an individual gain setting (MIC_1_AMP_GAIN / MIC_2_AMP_GAIN
controls) that has a range of -6 dB to +36 dB in 6 dB steps. The currently active gain setting of each
microphone is stored in MIC_1_GAIN_STATUS and MIC_2_GAIN_STATUS.
A maximum analogue gain from microphone to ADC input of +54 dB with a resolution of 1.5 dB can
be selected.
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MICBIAS1
MICBIAS1
MICBIAS1
MICBIAS2
MIC1_P
MIC1_P
MIC1_P
MIC1_N
MIC1_N
MIC1_N
(a) Differential
(b) Pseudo-differential
(c) Single-ended
(c) Single-ended
Figure 7: Typical microphone application for MIC1 (MIC2 is similar)
Standard electret microphones can be supplied from an embedded microphone bias regulator,
enabled using the MICBIAS2_EN control bit. Two separate outputs are available on either the
MICBIAS1 pin or the MICBIAS2 pin. These are enabled using the MICBIAS2_EN and MICBIAS1_EN
controls. The voltage on the MICBIAS pins is set to 1.6 V, 2.2 V, 2.5 V or 3.0 V by the
MICBIAS2_LEVEL and MICBIAS1_LEVEL controls. The microphone bias generates an ultralow-noise voltage to feed several electret microphones with up to 2mA.
14.4 Digital microphones
DA7212 implements a digital microphone interface via a clock output (shared pin with MIC1_P) and a
serial data input (shared pin with MIC1_N). The serial data is a sigma delta sampled bitstream.
Modulators up to 3rd Order are supported.
MICBIAS1 can be used to power the digital microphone, but it must be enabled because it is
MICBIAS1 that supplies the digital microphone pins.
The clock and data pins are shared with two analogue microphone inputs. This allows DA7212 to
record from single or dual channel digital microphones, or from conventional mono/stereo analogue
microphones.
The clock frequency can be selected to be either 1.5 MHz or 3 MHz by using DMIC_CLK_RATE
control.
Single channel and dual channel digital microphone modules are supported. The dual channel
modules change the output data on both the rising and the falling edges of the clock, as illustrated in
Figure 7. In this case DMIC_SAMPLEPHASE must be set to zero in order to enable the sample
detection at the edges of the clock. Each DMIC input is enabled via DMIC_L_EN / DMIC_R_EN and
is associated with a clock edge via DMIC_DATA_SEL control.
A digital microphone requires a decimation filter to reconstruct the signal at the required sampling
rate. The ADC decimation filters are re-used for this purpose, so either digital microphones or
analogue sources may be used for recording at any one time.
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Falling edge to
valid data on 1
Rising edge to
valid data on 2
Falling edge to high
impedance on 2
Rising edge to high
impedance on 1
DMICCLK
Output 1
to DMIC1
DATA
VALID
DATA
HIGH Z
DATA
VALID
Output 2
to DMIC1
DATA
HIGH Z
DATA
VALID
DATA
HIGH Z
Figure 8: Digital microphone timing example
14.5 Auxiliary inputs
Standard analogue sources (for example FM radio) are supported via the AUX stereo line inputs.
Auxiliary inputs are enabled by AUX_L_AMP_EN / AUX_R_AMP_EN. They can be summed with
each other, and with the microphone paths, which enables flexible audio mixing.
Each channel includes individual gain settings in 1.5 dB steps from -54 dB to +15 dB using
AUX_L_AMP_GAIN and AUX_R_AMP_GAIN. The auxiliary amplifiers can be muted by asserting
AUX_L_AMP_MUTE_EN and AUX_R_AMP_MUTE_EN.
Changes in gain can be synchronised with zero-crossing by asserting the AUX_L_AMP_ZC_EN and
AUX_R_AMP_ZC_EN bits. If no zero-crossing is detected within approximately 85ms, the gain
change is applied unconditionally. The sensitivity of the zero-cross detector is maximised by
automatic selection of whether the zero-cross detection is performed at the input to the AUX
amplifier, or the output from it. This is configured using the AUX_L_AMP_ZC_SEL and
AUX_R_AMP_ZC_SEL controls.
Smooth changes in gain are enabled by asserting the AUX_L_AMP_RAMP_EN and
AUX_R_AMP_RAMP_EN controls. If the ramp controls are asserted, the rate of ramping is specified
by the GAIN_RAMP_RATE control. Any zero-cross activation is over-ridden if gain ramping is set.
The currently active AUX_L_GAIN and AUX_R_GAIN settings are stored in the
AUX_L_GAIN_STATUS and AUX_R_GAIN_STATUS controls.
NOTE: When implementing fade-in and fade-out effects on the record path, it is recommended that
this is done through ADC L and ADC_R. When implementing fade-in and fade-out effects on the
output path, this should be done using the HP L, HP R and LINE amplifiers.
14.6 Input mixers
The DA7212 has two second level input amplifiers (MIXIN_L and MIXIN_R) that mix the analogue
inputs as well as providing up to 18 dB extra gain. They are enabled by asserting the controls
MIXIN_L_AMP_EN and MIXIN_R_AMP_EN. Gain can be controlled in 1.5 dB steps from 4.5 dB to
+18 dB using the MIXIN_L_GAIN and MIXIN_R_GAIN register bits.
Zero-crossing can be enabled by asserting MIXIN_L_AMP_ZC_EN or MIXIN_R_AMP_ZC_EN. If no
zero crossing is detected within approximately 85ms, the gain change is applied unconditionally.
Smooth changes in gain are performed by asserting the MIXIN_L_AMP_RAMP_EN and
MIXIN_R_AMP_RAMP_EN controls. If the ramp controls are asserted, the rate of ramping is
specified by the GAIN_RAMP_RATE control. Any zero-cross activation is over-ridden if gain ramping
is set.
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The left mixer accepts inputs from AUX_L_AMP and from either or both of the microphone PGAs
(MIC_1_AMP and MIC_2_AMP), as well as from the right mixer MIXIN_R for stereo-to-mono
conversion. Similarly the right mxer accepts inputs from AUX_R_AMP and from either or both of the
microphone PGAs (MIC_1_AMP and MIC_2_AMP), as well as from the left mixer MIXIN_L for
stereo-to-mono conversion. Input channel selection is determined by MIXIN_L_MIX_SELECT and
MIXIN_R_MIX_SELECT.
The mixers can be muted using the MIXIN_L_AMP_MUTE_EN and MIXIN_R_AMP_MUTE_EN
controls. The currently active gain settings are stored in MIXIN_L_AMP_GAIN_STATUS and
MIXIN_R_AMP_GAIN_STATUS registers.
14.7 Stereo audio ADC
DA7212 includes a low power 24-bit high quality stereo audio ADC that supports sampling rates from
8 kHz to 96 kHz. The sample rate is specified using the SR register.
The stereo ADC can be enabled and disabled on either channel using ADC_L_EN and ADC_R_EN,
thereby providing the opportunity to save power during mono operation.
The ADC channels offer a configurable digital gain from 83.25 dB to +12 dB in 0.75 dB steps after
the digital conversion. Individual gain settings can be programmed via controls
ADC_L_DIGITAL_GAIN and ADC_R_DIGITAL_GAIN. The currently active gain settings are stored in
ADC_L_GAIN_STATUS and ADC_R_GAIN_STATUS registers.
Muting, and the ramping of digital gain changes, can be controlled using the dedicated
ADC_L_CTRL and ADC_R_CTRL registers. If the ramping is enabled using the control bits
ADC_L_RAMP_EN and ADC_R_RAMP EN, the rate of the ramping is controlled using
GAIN_RAMP_RATE.
To enable saturation-free signals with maximum signal to noise ratios, the input levels of the ADC are
adjusted with second level PGAs that are enabled with controls MIXIN_L_AMP_EN and
MIXIN_R_AMP_EN. The signal routing and mix are configured using the MIXIN_L_SELECT and
MIXIN_R_SELECT registers.
On the dedicated MIXIN_L_CTRL and MIXIN_R_CTRL registers, settings such as gain changes at
zero-cross (for smooth volume changes), ramping of gain changes at signal zero cross ramping of
gain changes, and mute can be configured. If the ramping is enabled using the control bits
MIXIN_L_AMP_RAMP_EN and MIXIN_R_AMP_RAMP_EN, the speed of the ramp can be
configured on GAIN_RAMP_RATE.
14.8 Automatic Level Control (ALC)
For improved sound recordings of signals with a large volume range, the DA7212 offers a fullyconfigurable automatic recording level control (ALC) for microphone inputs. This is enabled via the
ALC_L_EN and ALC_R_EN controls, and can be enabled independently on either left or right
channel. It is recommended that the ALC is only enabled in stereo as this applies the same gain to
both channels and so protects the pan of stereo signals.
The ALC monitors the digital signal after the ADC and adjusts the microphones’ analogue and digital
gain to maintain a constant recording level, whatever the analogue input signal level.
Operation of ALC is illustrated in Figure 9. When the input signal volume is high, the ALC system will
reduce the overall gain until the output volume is below the specified maximum value. When the
input signal volume is low, the ALC will increase the gain until the output volume increases above the
specified minimum value. If the output signal is within the desired signal level (between the specified
minimum and maximum levels), the ALC does nothing.
The maximum and the minimum thresholds that trigger a gain change of the ALC are programmed
by the ALC_THRESHOLD_MAX and ALC_THRESHOLD_MIN controls.
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ALC Input
ALC MAX
level
ALC Gain
ALC MIN
level
Release time
ALC Output
Attack time
Figure 9: Principle of Operation of the ALC
The total gain is made up of an analogue gain, which is applied to the microphone PGAs, and a
digital gain, which is implemented in the filtering stage. The ALC block monitors and controls the gain
of the microphone PGAs and the ADC. Note that although the ALC is controlling the gain, it does not
modify any of the registers MIC_1_AMP_GAIN, MIC_2_AMP_GAIN, ADC_L_DIGITAL_GAIN and
ADC_R_DIGITAL_GAIN. These registers are ignored while the ALC is in operation.
The minimum and maximum levels of digital gain that can be applied by the ALC are controlled using
ALC_ATTEN_MAX and ALC_GAIN_MAX.
Similarly the minimum and maximum levels of analogue gain are controlled by ALC_ANA_GAIN_MIN
and ALC_ANA_GAIN_MAX.The rates at which the gain is changed are defined by the attack and
decay rates in register ALC_CTRL2. When attacking, the gain decreases with ALC_ATTACK rate.
When decaying, the gain increases with ALC_RELEASE rate.
The hold-time is defined by ALC_HOLD in the ALC_CTRL3 register. This controls the length of time
that the system maintains the current gain level before starting to decay. This prevents unwanted
changes in the recording level when there is a short-lived ‘spike’ in input volume, for example when
recording speech.
Typically the attack rate should be much faster than the decay rate, as it is necessary to reduce
rapidly increasing waveforms as quickly as possible, whereas fast release times will result in the
signal appearing to ‘pump’. The ALC also has an anti-clipping function that applies a very fast attack
rate when the input signal is close to full-range. This prevents clipping of the signal by reducing the
signal gain at a faster rate than would normally be applied. The anti-clip function is enabled using
ALC_ANTICLIP_EN, and the threshold above which it is activated is set in the range 1/128 full-scale
to full-scale using ALC_ANTICLIP_LEVEL.
A recording Noise-Gate feature is provided to avoid increasing the gain of the channel when there is
no signal, or when only a noise signal is present. Boosting a signal on which only noise is present is
known as ‘noise pumping’. The Noise-Gate prevents this. Whenever the level of the input signal
drops below the noise threshold configured in ALC_NOISE, the channel gain remains constant.
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max
input signal
min
time
gain level
atk rate
dcy rate
atk
hld
dcy
time
Figure 10: Attack, Delay and Hold parameters
14.9 Beep Generator and Controller
The DA7212 has two sine wave generators (SWG). Each SWG can generate an audio frequency
from 10Hz to 12 kHz with a 12.288 MHz system clock (or from 10Hz to 11.02 kHz with a 11.288 MHz
system clock). The output frequency of each SWG can be specified with a 10Hz step size using the
FREQ1_L and FREQ1_U registers for SWG 1, and FREQ2_L and FREQ2_U for SWG 2.
For all Output Frequency calculations,
FREQ[15:8] = FREQn_U
FREQ[7:0] = FREQn_L
For sample rates (SR) = 8/12/16/24/32/48/96 kHz,
FREQ = (2^16 * (fHz/12)) -1
For sample rates (SR) = 11.025/22.05/44.4/88.2 kHz,
FREQ = (2^16 * (fHz/11.025)) -1
The SWGs have a programmable gain that can be set in 3 dB steps from 0 dB to 45 dB using the
GAIN register field. The gain setting applies equally to both SWGs.
The beep generator generates beeps that can be a single tone from either SWG (register SWG_SEL
= 1 or SWG_SEL = 2), or a mix of two tones from the two SWGs (register SWG_SEL = 0 or
SWG_SEL = 3). The beep generator can also output standard DTMF keypad values (listed in Table
4) by asserting the DTMF_EN register bit.
Note that output from the beep generator is mixed into the DAI to DAC path. This means that if the
source path for DAC_L or DAC_R is selected to be ADC_L or ADC_R (registers 0x2A[5:4] and
0x2A[1:0]), the beep generator is omitted from the signal path.
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Table 25: DTMF Keypad frequencies
Frequency 1
(Hz)
1209
1336
1477
1633
Frequency 2 (Hz)
697
770
852
941
1
2
3
A
4
5
6
B
7
8
9
C
*
0
#
D
The beep tone On and Off periods are specified using the BEEP_ON_PER and BEEP_OFF_PER
register fields. Beep-On and Beep-Off periods can be configured in 10ms steps from 10ms to 200ms,
and in 50ms steps from 250ms to 2000ms. The Beep-On period can also be configured as
continuous. The number of beep cycles is configured using the BEEP_CYCLES register field.
The tone generator is started by asserting the START_STOPN register bit, and is halted by clearing
it. If START_STOPN is cleared, beep generation terminates on completion of the current beep-cycle,
or at the next zero-cross if in continuous mode.
The START_STOPN register bit is cleared automatically once the programmed number of beeps has
completed. In continuous-beep mode (BEEP_CYCLES = 6 or 7, or BEEP_ON_PER = 63), the tone
generator is switched off by clearing START_STOPN.
14.10 Output Signal Chain
The DA7212 has two audio outputs. These are a stereo Class-G headphone driver, and a mono
Class-AB speaker driver. Two output mixers allow mixing of signals from the DACs and the analogue
bypass paths, with output going to any or all of the three output PGAs. These output paths are
illustrated in Figure 11.
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from AUX_L_AMP
-57dB to +6dB
in 1dB steps
HP_L_AMP
from MIXIN_L
HP_L
from DAC_L
HP_R
HP_R_AMP
-57dB to +6dB
in 1dB steps
LINE_AMP
SP_P
from DAC_R
SP_N
-48dB to +15dB
in 1dB steps
from MIXIN_R
from AUX_R_AMP
Figure 11: Analogue output signal paths and gain ranges
14.11 Stereo Audio DAC
The integrated stereo DAC is suitable for high quality audio playback by MP3 players and by portable
multi media players of all kinds.
The left and right channels of the DAC can be individually enabled using controls DAC_L_EN and
DAC_R_EN.
Each channel includes individual gain settings that are controllable in 0.75 dB steps from 78 dB to
12 dB using DAC_L_DIGITAL_GAIN and DAC_R_DIGITAL_GAIN. The currently active gain settings
are stored in DAC_L_GAIN_STATUS and DAC_R_GAIN_STATUS registers.
On the dedicated DAC_L_CTRL and DAC_R_CTRL registers, settings such as mute and ramping of
gain changes can be configured. If ramping is enabled using the control bits DAC_L_RAMP_EN or
DAC_R_RAMP_EN, the rate of the ramping can be controlled using GAIN_RAMP_RATE.
A digital high-pass filter for each DAC channel is implemented with a 3 dB cut-off frequency
controlled by DAC_AUDIO_HPF_CORNER. The high-pass filter is enabled by control
DAC_HPF_EN. After Reset, the high pass filters for both channels are enabled by default.
14.12 Output Mixer
For playback, the output mixer amplifier is enabled using MIXOUT_L_AMP_EN and
MIXOUT_R_AMP_EN. The audio signal can be mixed from all sources, and can be output
simultaneously to both headphones and speakers. The mixing takes place only after asserting the
control MIXOUT_L_MIX_EN and MIXOUT_R_MIX_EN.
The output mixer is configured using register MIXOUT_L_SELECT and MIXOUT_R_SELECT. This
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output-mixer control is independent of the input path, so recording of one audio signal while listening
to another signal such as FM Radio or an MP3 file is possible. The playback sound can be mixed
with background signals or with inverted background microphone signals (side tone) to enable a
basic headphone environmental noise reduction, or to compensate for unwanted damping of
environmental sound while listening with sealed headphones. Playback signals coming from the AUX
or microphone input channels can be individually inverted before being mixed out to the left and right
channel (see MIXOUT_L_SELECT and MIXOUT_R_SELECT registers).
A stereo to mono conversion can be implemented by using either the input or the output mixer. This
allows direct feeding of high power speaker amplifiers and other mono devices with the complete
audio content.
14.13 Headphone Amplifier
The headphone Class G amplifiers offer 'true ground' technology, which allows cost and space
optimisation by removing the need for bulky headphone-coupling capacitors. This also enhances the
bass performance, which is typically reduced by conventional AC-coupling. In comparison to
alternative approaches like ‘phantom ground’, ‘true ground’ technology generates real
ground-centred output signals, which provide common GND as required for Mini-USB connectors
and CEA 936 A-compliant interfaces. An embedded offset compensation circuit suppresses click and
pop noise during start-up and dynamic supply voltage adjustments.
Integrated short circuit protection enables a ‘resistors free’ connection to a standard audio jack, to
achieve a maximum output power of up to 67 mW per channel (referenced to VDD_A). Headphone
load impedance is typically 16 Ω, but the paths can also be used as volume controlled lineout signals
for external speaker amplifiers and audio devices. The headphone Class G amplifiers are supplied
from the positive VDD_A rail via a capacitive charge pump that generates the negative rail required
for ‘true ground’ mode. For improved power efficiency, the headphone headphone supply voltage
levels are dynamically adjusted between ±VDD_A and ±VDD_A/2 to match the levels of the left and
right headphone signals.
The headphone amplifiers are enabled with controls HP_L_AMP_EN and HP_R_AMP_EN. For
optimum pop and click performance when switching the amplifier On and Off, the headphone
amplifier provides a high impedance mode that can be enabled via HP_L_AMP_OE /
HP_R_AMP_OE.
Balance is controlled by programming the left and right gains separately. The gain of each
headphone channel can be programmed independently in steps of 1.0 dB from +6 dB down to –
57 dB using controls HP_L_AMP_GAIN / HP_R_AMP_GAIN.
Settings such as mute, gain changes at signal zero cross (for smooth volume changes), and the
ramping of gain changes are controlled using the dedicated HP_L_CTRL and HP_R_CTRL registers.
If the ramping is enabled using the control bits HP_L_AMP_RAMP_EN and HP_R_AMP_RAMP_EN,
the rate of the ramping is controlled using GAIN_RAMP_RATE.
For smooth volume changes, the gain update can be synchronised to audio signal zero-crossings
using HP_L_AMP_ZC_EN and HP_R_AMP_ZC_EN. If no zero crossing is detected within
approximately 85ms, the gain change is applied unconditionally. The left and right channels are
synchronised independently.
14.14 Speaker Amplifier
The differential lineout channel can be used to directly drive mini speakers with a nominal impedance
≥ 8 Ω. For highest efficiency and speaker output power, a direct supply from the battery is supported
via a separate supply pin. This amplifier offers individually programmable volume control in 1.0 dB
steps from +15 dB to 48 dB using LINE_AMP_GAIN.
On the dedicated LINE_CTRL register, settings such as mute, tri-state output mode and ramping of
gain changes can be configured. If ramping is enabled via control bit LINE_AMP_RAMP_EN, the rate
of the ramping can be configured on GAIN_RAMP_RATE.
The differential speaker amplifier can be used to drive mini-speakers with an impedance of 8 Ω or
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higher. A direct supply from the battery is provided by the VDD_SP pin. This allows maximum
speaker power, and a wide operating range from 5.0 V down to 1.0 V.
The mono lineout/speaker amplifier is enabled by asserting LINE_AMP_EN. Gain can be set in the
range -48 dB to +15 dB in 1 dB steps using the LINE_AMP_GAIN control. The speaker amplifier can
be muted by asserting LINE_AMP_MUTE_EN.
Smooth updates to line/speaker amplifer gain can be made by asserting LINE_AMP_RAMP_EN.
When LINE_AMP_RAMP_EN is asserted, gain updates are made by ramping sequentially through
all intermediate gain values.
14.15 Charge Pump Control
The charge pump is enabled by asserting CP_EN in the CP_CTRL (0x47) register. Once enabled,
the charge pump can be controlled manually or automatically. When under manual control
(CP_MCHANGE = 00), the output voltage level is directly determined by CP_MOD.
The amount of charge stored, and therefore the voltage generated, by the charge pump is controlled
by the charge pump controller (CP_CTRL register). As the power consumed by devices such as
amplifiers is proportional to Voltage2, significant power savings are available by matching the charge
pump’s output with the system’s power requirement.
Under automatic control, there are three modes of operation that are determined by the
CP_MCHANGE setting. All four modes (one manual and three automatic) are described in Table 5.
Table 26: Charge pump output voltage control
Charge Pump
Tracking Mode
Charge Pump Output
Voltage
Details
00
Manual
The charge pump’s output voltage is determined by
the settings of CP_MOD.
01
Voltage level depends on the
programmed gain setting
10
Voltage level depends on the DAC
signal envelope
CP_MCHANGE
11
Voltage level depends on the
signal magnitude and the
programmed gain setting
The charge pump controller monitors the PGA
volume settings, and generates the minimum
voltage that is high enough to drive a full-scale
signal at the current gain level.
The charge pump controller monitors the DAC
signal, and generates a voltage that is high enough
to drive a full-scale output at the current DAC signal
volume level
The charge pump monitors both the programmed
volume settings and the actual signal size, and
generates the appropriate output voltage.
This is the most power-efficient mode of operation.
When CP_MCHANGE is set to 10 (tracking DAC signal size, described in Table 26) or
CP_MCHANGE is set to 11 (tracking the output signal size), the charge pump switches its supply
between the VDD_A rail and the VDD_A/2 rail depending on its power requirements. When low
output voltages are needed, the charge pump saves power by using the the lower-voltage VDD_A/2
rail.
The switching point between using the VDD_A rail and the VDD_A/2 rail is determined by the
CP_THRESH_VDD2 register setting. The switching points determined by CP_THRESH_VDD2 vary
between the two CP_MCHANGE modes, and are summarised in Table 27 and Table 28.
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Note 17 When the charge pump output voltage is controlled manually (CP_MCHANGE = 00) or when
it is tracking the PGA gain settings (CP_MCHANGE = 01), the charge pump always takes its
supply from VDD_A
Table 27: CP_THRESH_VDD2 Settings in DAC_VOL mode (CP_MCHANGE = 10)
CP_THRESH_VDD2 Setting
Approximate Switching
Point
0x01
-30 dBFS
Do not use. Very power-inefficient as nearly
always VDD/1
0x03
-24 dBFS
Not recommended. Very power-inefficient as
nearly always VDD/1
0x07
-18 dBFS
Good to use but not power efficient
0x0E
-12 dBFS
Good to use
0x10
-10 dBFS
Recommended setting
0x3F – 0x13
Notes
Not recommended
Note 18 Full Scale (FS) = 1.6 * VDD_A
Table 28: CP_THRESH_VDD2 Settings in Signal Size mode (CP_MCHANGE = 11)
CP_THRESH_VDD2 Setting
Approximate Switching Point
Notes
0x00
Never
Not recommended. Always VDD/1 mode
0x01
Never
Not recommended. Always VDD/1 mode
0x02
-32 dBFS
Not recommended. Very power-inefficient as
nearly always VDD/1
0x03
-24 dBFS
Good to use
0x04
-20 dBFS
Good to use
0x05
-17 dBFS
Good to use
0x06
-15 dBFS
Recommended setting
0x07
-13 dBFS
Good to use
0x08
-12 dBFS
Good to use
0x09
-11 dBFS
Good to use
0x0A
-10 dBFS
Good to use
0x0B
-9 dBFS
Not recommended. VDD/2 begins to clip
0x0C
Never
Not recommended. Always VDD/2 mode
0x0D
Never
Not recommended. Always VDD/2 mode
0x0E
Never
Not recommended. Always VDD/2 mode
0x0F
Never
Not recommended. Always VDD/2 mode
Note 19 Full Scale (FS) = 1.6 * VDD_A
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14.16 Charge pump clock control
The charge pump on DA7212 requires two clocks (cp_clk and cp_clk2). The cp_clk2 clock runs at a
slower frequency than cp_clk. It is cp_clk that actually clocks the charge pump.
To prevent the clocks stopping in an unknown state, there are always two pulses on cp_clk for every
one pulse of cp_clk2. This is illustrated in Figure 12.
clk
cp_clk
cp_clk2
Figure 12: Input (clk) and Output Clocks (cp_clk and cp_clk2) at CP_FCONTROL = 010
When CP_ANALOGUE_LVL = 00 (‘No feedback’ – see Section 14.17 for more details), the charge
pump’s nominal clock rate cp_clk is controlled by CP_FCONTROL, providing a range from 1 MHz
(CP_FCONTROL = 000) down to 63 kHz (CP_FCONTROL = 100). With the slower clock rates,
quiescent power consumption is lower but the trade-off is a reduced load current, and slower
changes to the voltage.
Section 14.17 describes how quiescent power and load current can be varied according to demand.
14.17 Boosting the charge pump using demand feedback control
When CP_ANALOGUE_LVL = 00, the clock frequency for the charge pump is under direct control of
the registers as described in Section 0.
When CP_ANALOGUE_LVL = 01 or 10 (11 is reserved and is not used), the demands on the charge
pump output are tracked, and the clock frequency is boosted when necessary to give the required
output current.
This gives the benefit of a very low (or even zero) quiescent current when the charge pump is not
required combined with a maximum output when that is required.
14.17.1 Tracking the demands on the charge pump output
There are three points at which the demands on the charge pump can be tracked. These tracking
points are determined by CP_MCHANGE.
14.17.1.1
CP_MCHANGE = 00 (manual mode)
If CP_MCHANGE = 00, the voltage level is controlled by the CP_MOD setting.
14.17.1.2
CP_MCHANGE = 01 (tracking the PGA gain setting)
If CP_MCHANGE = 01, it is the PGA gain setting that is tracked, and which provides the feedback to
boost the clock frequency when necessary.
14.17.1.3
CP_MCHANGE = 10 (tracking the DAC signal setting)
If CP_MCHANGE = 01, it is the size of the DAC signal that is tracked, and which provides the
feedback to boost the clock frequency when necessary.
14.17.1.4
CP_MCHANGE = 11 (tracking the output signal magnitude)
If CP_MCHANGE = 01, it is the magnitude of the output signal that is tracked, and which provides
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the feedback to boost the clock frequency when necessary.
14.17.2 Specifying clock frequencies when tracking the charge pump output
demand
CP_FCONTROL specifies the frequency of the charge pump clock. The frequency is fixed and is set
manually if CP_MCHANGE = 00 (see section 14.17.1.1). The available frequency settings are 1 MHz
(the absolute maximum), and 500, 250, 125 and 63 kHz.
If CP_MCHANGE not = 00, the charge pump load is monitored and the clock frequency adjusted
accordingly to allow the charge pump to supply the required current. Clock frequency varies
depending on the charge pump requirements, and the CP_FCONTROL settings specify the minimum
frequency at which the clock will run. The maximum frequency is always 1 MHz.
In addition to the CP_FCONTROL settings outlined above, and which specify the minimum clock
frequency, there is an extra setting of CP_FCLOCK = 101 which has no minimum frequency. The
clock frequency is under the complete control of the tracking and feedback mechanism. The
frequency can vary from 0 Hz when there is no load on the charge pump and no component leakage,
up to the maximum of 1 MHz.
These settings are all summarised in Table 29.
14.17.3 Controlling the boost of the charge pump clock-frequency
The manner in which the charge pump clock-frequency is boosted is controlled by
CP_ANALOGUE_LVL. If CP_ANALOGUE_LVL = 00, there is no feedback to the clock generator,
and the frequency remains fixed at the frequency specified by CP_FCONTROL.
14.17.3.1
CP_ANALOGUE_LVL = 01
If CP_ANALOGUE_LVL = 01, the clock frequency is boosted from the base frequency specified in
CP_FCONTROL by the insertion of extra clock pulses in to the clock signal as and when required.
When no extra pulses are being inserted, the clock frequency remains fixed at the value specified by
CP_FCONTROL. The extra clock pulses are inserted in to the clock signal as needed as long as the
clock frequency does not exceed its maximum of 1 MHz. These settings are all summarised in Table
29.
.
14.17.3.2
CP_ANALOGUE_LVL = 10
If CP_ANALOGUE_LVL = 10, instead of boosting the clock frequency by inserting extra clock pulses
as described in section 14.17.3.1, the clock is restarted. By restarting the clock before the next pulse
is due, the frequency is effectively increased. The clock frequency can be increased from the
minimum frequency specified in CP_FCONTROL, up to the maximum frequency of 1 MHz. These
settings are all summarised in Table 29.
.
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Table 29: Charge pump current load control
CP_ANALOGUE_LVL (0x47[1:0])
000
001
010
CP_FCONTROL
(0x96[2:0])
011
100
101
110
111
00
No current boost
01
Variable current
boost
10
Variable current
boost
11
1 MHz
1 MHz
1 MHz
Reserved
500 kHz
From 500 kHz
to1MHz depending
on demand Note 20
From 500 kHz
to1MHz depending
on demand Note 20
Reserved
250 kHz
From 250 kHz
to1MHz depending
on demand Note 20
From 250 kHz
to1MHz depending
on demand Note 20
Reserved
125 kHz
From 125 kHz
to1MHz depending
on demand Note 20
From 125 kHz
to1MHz depending
on demand Note 20
Reserved
63 kHz
From 63 kHz
to1MHz depending
on demand Note 20
From 63 kHz
to1MHz depending
on demand Note 20
Reserved
Reserved
0 Hz to 1MHz
depending on
demand Note 20
0 Hz to 1MHz
depending on
demand Note 20
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note 20 Power demand is determined bythe PGA gain level if CP_MCHANGE = 01, by the DAC signal level if
CP_MCHANGE = 10 , or by the output signal level If CP_MCHANGE = 11
14.18 Other Charge Pump Controls
When a higher charge pump output voltage is needed, the charge pump increases its output as the
fastest rate possible given the controls and settings in that currently in place. Once the higher output
voltage is no longer needed, the charge pump controller waits for a period determined by the
CP_TAU_DELAY setting before reducing the output voltage. For best performance Dialog
recommend setting CP_TAU_DELAY to 16ms or greater.
The charge pump limiter is controlled by CP_ON_OFF. The limiter restricts the current flow to the
charge pump’s capacitors at start-up.
CP_SMALL_SWITCH_FREQ_EN enables a low-load, low-power switching mode. If
CP_SMALL_SWITCH_FREQ_EN is enabled and CP_FCONTROL is set to a value between 000 and
100, any feedback from the analogue level detector results in a switch from low-power to full-power.
Full-power is maintained for one CP_TAU_DELAY period after the pulse. Any subsequent pulses
restart the CP_TAU_DELAY period.
If CP_FCONTROL = 101, the first feedback from the analogue level detector primes the change to
full-power mode. If another pulse occurs within 32 clock cycles of the first feedback from the
analogue level detector, full power is enabled for one CP_TAU_DELAY period.
14.19 Digital Signal Processing Engine
The digital signal processing engine includes a configurable audio processor that offers flexible
routing and extensive audio enhancement and effects. Linear phase FIR filters perform the DAC
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interpolation and decimation for the required sample rates. Configurable high-pass filtering (optionally
enabled on both ADC and DAC) removes any signal DC offset and can help to filter out wind noise. A
5-band playback equaliser can be configured to suit the users listening preferences.
14.20 Variable High Pass Audio Filter (DC Cut)
Any DC offset from the input path is removed via IIR filters (typically 5 MHz, you must follow the procedure
below.
Write F0 = 8b
Write F1 = 01
Write F0 = 00
Setup PLL and clocking
14.29 Mixed Sample Rates
In DA7212 there is only one Sample Rate register and therefore, by default, this controls the sample
rate of both the ADC and the DAC
Some applications require the ADC and the DAC to run at different sample rates. A special mode
(24-48 Mode) is available by asserting 24_48_MODE at register address 0x84[0]. Asserting this bit
sets the ADC to run at 24kHz and the DAC to run at 48kHz. In this mode all the functionality of the
ADC and the DAC is available. The DAI will continue to run at 48kHz, and every ADC sample will be
repeated across two WCLK frames.
14.30 I2C Control Interface
The DA7212 is completely software-controlled from the host by registers. The DA7212 provides an
I2C compliant serial control interface to access these registers. Data is shifted into or out of the
DA7212 under the control of the host processor, which also provides the serial clock.
The 7-bit I2C slave address is 0x1A so that the 8-bit address for writing is 0x34 and for reading is
0x35.
The I2C clock is supplied by the SCL line and the bi directional I2C data is carried by the SDA line.
The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be
pulled HIGH by external pull-up resistors (1 kΩ to 20 kΩ range). The attached devices only drive the
bus lines LOW by connecting them to ground. This means that two devices cannot conflict if they
drive the bus simultaneously.
In standard/fast mode the highest frequency of the bus is 1 MHz. The exact frequency can be
determined by the application and does not have any relation to the DA7212 internal clock signals.
DA7212 will follow the host clock speed within the described limitations and does not initiate any
clock arbitration or slow down.
In high-speed mode the maximum frequency of the bus can be increased up to 3.4 MHz. This mode
is supported if the SCL line is driven with a push-pull stage from the host and if the host enables an
external 3mA pull-up at the SDA pin to decrease the rise time of the data. In this mode the SDA line
on DA7212 is able to sink up to 12mA. In all other respects the high speed mode behaves as the
standard/fast mode. Communication on the I2C bus always takes place between two devices, one
acting as the master and the other as the slave. The DA7212 will only operate as a SLAVE. The I2C
interface has direct access to the whole register map of the DA7212.
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VDD_IO
Host
Processor
SCL
SDA
VDD_IO
SCL
SDA Codec
SCL
SDA Peripheral
Device
Figure 20: Schematic of the I2C control interface bus
14.31 Details of the I2C Control interface protocol
All data is transmitted across the I2C bus in groups of 8 bits. To send a bit the SDA line is driven to
the intended state while the SDA is LOW (a LOW on SDA indicates a zero bit). Once the SDA has
settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the
receiver’s shift register.
A two byte serial protocol is used containing one byte for address and one byte for data. Data and
address transfer is transmitted MSB first for both read and write operations. All transmission begins
with the START condition from the master while the bus is in the IDLE state (the bus is free). It is
initiated by a high to low transition on the SDA line while the SCL is in the high state (a STOP
condition is indicated by a low to high transition on the SDA line while the SCL line is in the high
state).
SCL
SDA
Figure 21 Timing of I2C START and STOP Conditions
The I2C bus is monitored by DA7212 for a valid SLAVE address whenever the interface is enabled. It
responds with an Acknowledge immediately when it receives its own slave address. The
Acknowledge is done by pulling the SDA line low during the following clock cycle (white blocks
marked with ‘A’ in Figure 22 to Figure 25).
The protocol for a register write from master to slave consists of a start condition, a slave address
with read/write bit and the 8-bit register address followed by 8 bits of data terminated by a STOP
condition (the DA7212 responds to all bytes with Acknowledge). This is illustrated in Figure 22.
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S
SLAVE addr
7-bits
W
A
REG addr
1-bit
A
8-bits
Master to Slave
DATA
P
A
8-bits
Slave to Master
S = START condition
P = STOP condition
A = Acknowledge (low)
W = Write (low)
Figure 22: I2C Byte write (SDA signal)
When the host reads data from a register it first has to write-access DA7212 with the target register
address and then read access DA7212 with a repeated START, or alternatively a second START
condition. After receiving the data the host sends a Not Acknowledge (NAK) and terminates the
transmission with a STOP condition:
S SLAVEaddr W A
7-bits
1-bit
S SLAVEaddr W A
7-bits
1-bit
REG addr
A Sr SLAVEaddr R
8-bits
7-bits
REG addr
A
P
7-bits
*
DATA
A
P
8-bits
S SLAVEaddr R
8-bits
Master to Slave
A
1-bit
A
1-bit
*
DATA
A
P
8-bits
Slave to Master
S = START condition
Sr = Repeated START condition
P = STOP condition
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 23: Examples of the I2C Byte Read (SDA line)
Consecutive (Page Mode) read-out mode (CIF_I2C_WRITE_MODE (0x1D [0]) = 0) is initiated from
the master by sending an Acknowledge instead of Not Acknowledge (NAK) after receipt of the data
word. The I2C control block then increments the address pointer to the next I2C address and sends
the data to the master. This enables an unlimited read of data bytes until the master sends a NAK
directly after the receipt of data, followed by a subsequent STOP condition. If a non-existent I2C
address is read out, the DA7212 will return code zero.
S SLAVEaddr W A
7-bits
1 bit
S SLAVEaddr W A
7-bits
REG addr
A Sr SLAVEaddr R A
8-bits
REG addr
7-bits
Master to Slave
S = START condition
Sr = Repeat START condition
P = STOP condition
8-bits
S SLAVEaddr R A
A P
7-bits
8-bits
1-bit
1-bit
DATA
1-bit
A
DATA
A
8-bits
DATA
*
DATA
A
P
8-bits
A
8-bits
DATA
*
A
P
8-bits
Slave to Master
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 24: Examples of I2C Page Read (SDA line)
Note 1
The slave address after the Repeated START condition must be the same as the previous
slave address
Consecutive write-mode (CIF_I2C_WRITE_MODE (0x1D [0]) = 0) is supported if the Master sends
several data bytes following a slave register address. The I2C control block then increments the
address pointer to the next I2C address, stores the received data and sends an Acknowledge until
the master sends the STOP condition.
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S SLAVEaddr W A
7-bits
1 bit
REGadr
8-bits
A
DATA
8-bits
Master to Slave
A
DATA
1-bit
8-bits
A
DATA
8-bits
A
……….
A
P
Repeated writes
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 25: I2C Page Write (SDA Line)
An alternative repeated-write mode that uses non-consecutive slave register addresses is available
using the CIF_I2C_WRITE_MODE register. In this Repeat Mode (CIF_I2C_WRITE_MODE (0x1D
[0]) = 1), the slave can be configured to support a host’s repeated write operations into several nonconsecutive registers. Data is stored at the previously received register address. If a new START or
STOP condition occurs within a message, the bus returns to IDLE mode. This is illustrated in Figure
26
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S SLAVEaddr W A
7-bits
1 bit
REG addr
A
8-bits
Master to Slave
DATA
8-bits
A
REG addr
1-bit
8-bits
A
DATA
8-bits
A
……….
A
P
Repeated writes
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
*
A = Not Acknowledge (NAK)
W = Write (low)
R = Read (high)
Figure 26: I2C Repeated Write (SDA Line)
Note 2
Note that in Page Mode (CIF_I2C_WRITE_MODE = 0), both Page Mode reads and writes using
auto-incremented addresses, and Repeat Mode reads and writes using non auto-incremented
addresses, are supported. In Repeat Mode (CIF_I2C_WRITE_MODE = 1) however, only Repeat
Mode reads and writes are supported.
14.32 Digital Audio Interface (DAI)
DA7212 provides one Digital Audio Interface (DAI) to input DAC data or to output ADC data. It is
enabled by asserting DAI_EN. The DSP provides flexible routing options allowing each interface to
be connected to different signal paths as desired in each application.
The DAI consists of a four-wire serial interface, with bit clock (BCLK), word clock (WCLK), data-in
(DATIN) and data-out (DATOUT) pins. Both master and slave clock modes are supported by the
DA7212. Master mode is enabled setting register DAI_CLK_EN (0x28[7]) = 1. In master mode, the bit
clock and word clock signals are outputs from the codec. In slave mode these are inputs to the
codec.
BCLK
WCLK
DA7212
Codec
DATIN
Processor
DATOUT
Figure 27: Master Mode (DAI_CLK_EN = 1)
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BCLK
WCLK
DA7212
Codec
DATIN
Processor
DATOUT
Figure 28: Slave Mode (DAI_CLK_EN = 0)
The internal serialized DAI data is 24 bits wide. Serial data that is not 24 bits wide is either shortened
or zero-filled at input to, or at output from, the DAI’s internal 24-bit data width. The serial data word
length can be configured to be 16, 20, 24 or 32 bits wide using the DAI_WORD_LENGTH register
bits.
Four different data formats are supported by the digital audio interface. The data format is
determined by the setting of the DAI_FORMAT register bits.
●
●
●
●
I2S mode
Left Justified mode
Right Justified mode
DSP mode
Time division multiplexing (TDM) is available in any of these modes to support the case where
multiple devices are communicating simultaneously on the same bus. TDM is enabled by asserting
the DAI_TDM_MODE_EN bit.
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14.33 I2S Mode
In I2S mode (DAI_FORMAT = 0), the MSB of the left channel is valid on the second rising edge of
the bit clock after the falling edge of the word clock. The MSB of the right channel is valid on the
second rising edge of the bit clock after the rising edge of the word clock, and the MSB of the left
channel is valid on the second rising edge of the bit clock after the falling edge of the word clock.
WCLK
WCLK 1 = RIGHT CHANNEL DATA
WCLK 0 = LEFT CHANNEL DATA
BCLK
DATIN/DATOUT
msb
Right Channel
lsb
msb
Left Channel
lsb
msb
Figure 29: I2S Mode
14.34 Left Justified Mode
In left-justified mode (DAI_FORMAT = 1), the MSB of the right channel is valid on the rising edge of
the bit clock following the falling edge of the word clock. The MSB of the left channel is valid on the
rising edge of the bit clock following the rising edge of the word clock.
WCLK
WCLK 1 = LEFT CHANNEL DATA
WCLK 0 = RIGHT CHANNEL DATA
BCLK
DATIN/DATOUT
msb
Left Channel
lsb
msb
Right Channel
lsb
msb
Figure 30: Left Justified Mode
14.35 Right Justified Mode
In right-justified mode (DAI_FORMAT = 2), the LSB of the left channel is valid on the rising edge of
the bit clock preceding the falling edge of word clock. The LSB of the right channel is valid on the
rising edge of the bit clock preceding the rising edge of the word clock.
WCLK
WCLK 1 = LEFT CHANNEL DATA
WCLK 0 = RIGHT CHANNEL DATA
BCLK
DATIN/DATOUT
lsb
msb
Left Channel
lsb
msb
Right Channel
lsb
Figure 31: Right Justified Mode
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14.36 DSP Mode
In DSP mode (DAI_FORMAT = 3), the rising edge of the word clock starts the data transfer with the
left channel data first and immediately followed by the right channel data. Each data bit is valid on the
falling edge of the bit clock.
WCLK
The falling edge of WCLK can occur anywhere in this area
BCLK
DATIN/DATOUT
msb
Left Channel
lsb msb
WCLK
Right Channel
lsb
msb
The falling edge of WCLK can occur anywhere in this area
BCLK
DATIN/DATOUT
msb
Left Channel
lsb msb
Right Channel
lsb
msb
Offset
Figure 32: DSP Mode
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14.37 Time Division Multiplexing (TDM) Mode
Time Division Multiplexing (TDM) allows multiple devices to communicate on the same bus without
conflicting. TDM mode (DAI_TDM_MODE_EN = 1) is an extension of the DSP and the Left Justified
formats (see page 63).
DA7212
Codec
ADC Data Out
DAC Data In
Word Clock
Bit Clock
Processor
DA7212
Codec
Figure 33: TDM Example (slave mode)
WCLK
WCLK 1 = LEFT CHANNEL DATA
WCLK 0 = RIGHT CHANNEL DATA
BCLK
DATIN/DATOUT
msb
Left Channel
WCLK
lsb
msb
Right Channel
WCLK 1 = LEFT CHANNEL DATA
lsb
msb
WCLK 0 = RIGHT CHANNEL DATA
BCLK
DATIN/DATOUT
msb
Left Channel
lsb
msb
Right Channel
lsb
msb
Offset
Figure 34: TDM Mode (left justified mode)
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A time offset is specified from the normal ‘start of frame’ condition using register bit DAI_OFFSET.
Since a different offset may be defined for each device on the bus, they may both communicate
without collisions.
In the Left-Justified TDM example illustrated in Figure 34, the left channel data is valid DAI_OFFSET
clock cycles after the rising edge of the word clock, and the right channel data is valid the same
DAI_OFFSET number of clock cycles after the falling edge of the word clock.
In DSP TDM mode (not illustrated), the left channel data is valid after the same DAI_OFFSET clock
cycles from the rising edge of the word clock, but the right channel data is valid immediately after the
left channel data.
The serial data pin must be tri-stated whenever the output is not valid.
Mono mode is supported in the TDM mode by asserting DAI_MONO_MODE_EN. If
DAI_MONO_MODE_EN is asserted, only the data from the Digital Audio Interface left channel is
transmitted.
14.37.1 Configuration of the Digital Audio Interface
The data format is configured using register DAI_FORMAT. The offset applied in TDM mode is
configured using register DAI_OFFSET. The word length is configured using register
DAI_WORD_LENGTH.
The digital audio interface is enabled using register DAI_EN and the frame length is configured using
DAI_BCLKS_PER_WCLK.
When using the digital audio interface in slave mode (DAI_CLK_EN = 0), if the WCLK input is not
from the same clock source as the MCLK input, then the SRM PLL mode must be enabled to
maintain synchronization.
14.38 Pop-Free and Click-Free Start-up using the System Controllers
DA7212 has two System Controllers that provide pop-free and click-free start-up under most
conditions.
14.38.1 Level 1 System Controller (SCL1)
The Level 1 System Controller (SCL1) is automatically activated whenever a sub-system’s enable bit
is asserted. SCL1 ensures that the desired component parts are sequenced in the correct order to
provide click-free and pop-free start-up.
The following example using the left DAC illustrates SCL1 in operation.
1. When the left DAC is enabled by assertion of the DAC_L_EN register bit (register 0x69[7] )
a. SCL1 first activates the DAC clocks
b. SCL1 then activates the DSP logic
c. Next, SCL1 activates the analogue DAC
d. Finally, SCL1 ramps up the digital gain
In this way, SCL1 helps ensure that the DAC_L start-up is free of pops and clicks.
Note 34 Note, however, that if any dependent functions for a sub-system’s activation have not been enabled,
SCL1 will not automatically enable them. This allows you greater control over the sequencing of the
sub-system, but it also means that any sub-system can potentially be brought up in such a way that
audible artefacts such as pops and clicks are introduced.
Datasheet
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14.38.2 Level 2 System Controller (SCL2)
Level 2 System Controller (SCL2) is a higher level controller that provides one-touch activation of
standard operating modes. Input or output sub-systems can be activated either singly or in
combination. All selected sub-systems will start up in the correct order and without pops or clicks
when SCL2 is activated.
First, the desired input sub-systems must be selected by asserting the relevant fields (bits 1 to 7) of
the SYSTEM_MODES_INPUT (0x50) register. Similarly, the desired output sub-systems must be
selected by asserting the relevant fields (bits 1 to 7) of the SYSTEM_MODES_OUTPUT (0x51)
register.
Once the desired sub-systems have been selected, the SCL2 controller is activated by writing ‘1’ to
the MODE_SUBMIT register field in either the SYSTEM_MODES_INPUT (0x50) or the
SYSTEM_MODES_OUTPUT (0x51) register. It does not matter which of the two MODE_SUBMIT
fields is asserted. Both work in the same way, and each will start up both the input and the output
sub-systems.
When SCL2 is activated by asserting MODE_SUBMIT, all of the register-writes that are required by
the selected sub-systems are performed automatically. Each sub-system is brought up in the correct
order to avoid pops and clicks, and within each sub-system, the component parts are brought up in
the correct pop-free and click-free sequence.
Note 35 Note that the MODE_SUBMIT field used to start SCL2 is self-clearing, and is automatically reset to ‘0’
once SCL2 has started
SCL1 and SCL2 activity can be monitored using the SCL1_BUSY and SCL2_BUSY bits on the
SYSTEM_STATUS (0xE0) register.
Note 36 If the DA7212 device is changed from one playback mode to another, or if it is changed from one
record mode to another, the initial mode is closed down first before the second mode is activated. This
happens automatically.
14.39 Power Supply – Standby Mode
DA7212 has an ultra-low power standby mode that can be enabled to save power when the device is
not in use. Standby Mode is controlled using the SYSTEM_ACTIVE register.
14.39.1 Entering Standby Mode
Standby Mode is activated by writing a ‘0’ to the SYSTEM_ACTIVE register bit. This
SYSTEM_ACTIVE register cannot be read when in Standby Mode because the act of reading the bit
causes it to be asserted, which causes the Standby Mode to be exited.
When entering Standby Mode, it is important that all audio paths are shut down first because the shut
down is abrupt and audio artifacts such as pops and click may be heard. No audio functions are
possible during Standby Mode, as the reference oscillator and the reference voltages are both shut
down.
14.39.2 Exiting Standby Mode
Standby Mode can be exited by writing a ‘1’ to the SYSTEM_ACTIVE register bit.
Any read or write access to the DA7212 will also cause the SYSTEM_ACTIVE bit to be asserted, but
note that the first read or write access may fail because of the time taken to restart the reference
Datasheet
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Datasheet/Ultra-low power stereo codec
oscillator. It is recommended that Standby Mode is exited by writing to the the SYSTEM_ACTIVE
register rather than relying on the automatic assertion of the register by a read or write access.
Read or write accesses to I2C slave addresses other than those used by the DA7212 will not cause
Standby Mode to be exited.
Datasheet
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Datasheet/Ultra-low power stereo codec
15 Register definitions
15.1 Register map
Addr
Function
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
PLL_SRM_LOCK
PLL_LOCK
Status Registers
0x02
STATUS1
Reserved
Reserved
Reserved
Reserved
0x03
PLL_STATUS
Reserved
Reserved
Reserved
Reserved
0x04
AUX_L_GAIN_STAT
US
Reserved
Reserved
AUX_L_AMP_GAIN_STATUS
0x05
AUX_R_GAIN_STAT
US
Reserved
Reserved
AUX_R_AMP_GAIN_STATUS
0x06
MIC_1_GAIN_STAT
US
Reserved
Reserved
Reserved
Reserved
Reserved
MIC_1_AMP_GAIN_STATUS
0x07
MIC_2_GAIN_STAT
US
Reserved
Reserved
Reserved
Reserved
Reserved
MIC_2_AMP_GAIN_STATUS
0x08
MIXIN_L_GAIN_STA
TUS
Reserved
Reserved
Reserved
Reserved
MIXIN_L_AMP_GAIN_STATUS
0x09
MIXIN_R_GAIN_STA
TUS
Reserved
Reserved
Reserved
Reserved
MIXIN_R_AMP_GAIN_STATUS
0x0A
ADC_L_GAIN_STAT
US
Reserved
ADC_L_DIGITAL_GAIN_STATUS
0x0B
ADC_R_GAIN_STAT
US
Reserved
ADC_R_DIGITAL_GAIN_STATUS
0x0C
DAC_L_GAIN_STAT
US
Reserved
DAC_L_DIGITAL_GAIN_STATUS
0x0D
DAC_R_GAIN_STAT
US
Reserved
DAC_R_DIGITAL_GAIN_STATUS
0x0E
HP_L_GAIN_STATU
S
Reserved
Datasheet
CFR0011-120-00 Rev 4
Reserved
PLL_BYPASS_ACTIV
PLL_MCLK_STATUS
E
HP_L_AMP_GAIN_STATUS
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5
4
3
2
Addr
Function
7
6
0x0F
HP_R_GAIN_STATU
S
Reserved
Reserved
HP_R_AMP_GAIN_STATUS
0x10
LINE_GAIN_STATU
S
Reserved
Reserved
LINE_AMP_GAIN_STATUS
1
0
Reserved
CIF_I2C_WRITE_MOD
E
System Initialisation Registers
0x1D
CIF_CTRL
CIF_REG_SOFT_
RESET
Reserved
0x21
DIG_ROUTING_DAI
Reserved
Reserved
0x22
SR
Reserved
Reserved
0x23
REFERENCES
Reserved
Reserved
0x24
PLL_FRAC_TOP
Reserved
Reserved
0x25
PLL_FRAC_BOT
0x26
PLL_INTEGER
Reserved
0x27
PLL_CTRL
PLL_EN
PLL_SRM_EN
PLL_32K_MODE
PLL_MCLK_SQR_EN
0x28
DAI_CLK_MODE
DAI_CLK_EN
Reserved
Reserved
Reserved
Reserved
Reserved
DAI_R_SRC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VMID_FAST_DISCH VMID_FAST_CHARG
ARGE
E
DAI_L_SRC
SR
BIAS_EN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PLL_FBDIV_FRAC_TOP
PLL_FBDIV_FRAC_BOT
PLL_FBDIV_INTEGER
PLL_INDIV
DAI_WCLK_POL
DAI_CLK_POL
0x29
DAI_CTRL
DAI_EN
DAI_OE
DAI_MONO_MODE_
DAI_TDM_MODE_EN
EN
0x2A
DIG_ROUTING_DAC
DAC_R_MONO
Reserved
DAC_R_SRC
DAC_L_MONO
Reserved
0x2B
ALC_CTRL1
ALC_R_EN
Reserved
ALC_CALIB_OVERF ALC_AUTO_CALIB_
LOW
EN
ALC_L_EN
ALC_CALIB_MODE
DAI_BCLKS_PER_WCLK
DAI_WORD_LENGTH
DAI_FORMAT
DAC_L_SRC
ALC_SYNC_MODE
ALC_OFFSET_EN
Input Gain / Select Filter Registers
0x30
AUX_L_GAIN
Reserved
Reserved
AUX_L_AMP_GAIN
0x31
AUX_R_GAIN
Reserved
Reserved
0x32
MIXIN_L_SELECT
DMIC_L_EN
Reserved
Reserved
MIXIN_L_SEL
MIC2_SEL
MIC1_SEL
AUX_L_SEL
0x33
MIXIN_R_SELECT
DMIC_R_EN
Reserved
Reserved
MIXIN_L_SEL
MIC1_SEL
MIC2_SEL
AUX_R_SEL
0x34
MIXIN_L_GAIN
Reserved
Reserved
Datasheet
CFR0011-120-00 Rev 4
AUX_R_AMP_GAIN
Reserved
Reserved
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Addr
Function
7
6
5
4
0x35
MIXIN_R_GAIN
Reserved
Reserved
Reserved
Reserved
0x36
ADC_L_GAIN
Reserved
ADC_L_DIGITAL_GAIN
0x37
ADC_R_GAIN
Reserved
ADC_R_DIGITAL_GAIN
0x38
ADC_FILTERS1
ADC_HPF_EN
Reserved
0x39
MIC_1_GAIN
Reserved
Reserved
Reserved
0x3A
MIC_2_GAIN
Reserved
Reserved
Reserved
ADC_AUDIO_HPF_CORNER
3
2
1
0
MIXIN_R_AMP_GAIN
ADC_VOICE_EN
ADC_VOICE_HPF_CORNER
Reserved
Reserved
MIC_1_AMP_GAIN
Reserved
Reserved
MIC_2_AMP_GAIN
Output Gain / Select Filter Registers
DAC_SOFTMUTE
_EN
0x40
DAC_FILTERS5
DAC_SOFTMUTE_RATE
0x41
DAC_FILTERS2
DAC_EQ_BAND2
DAC_EQ_BAND1
0x42
DAC_FILTERS3
DAC_EQ_BAND4
DAC_EQ_BAND3
0x43
DAC_FILTERS4
DAC_EQ_EN
Reserved
0x44
DAC_FILTERS1
DAC_HPF_EN
Reserved
0x45
DAC_L_GAIN
Reserved
DAC_L_DIGITAL_GAIN
0x46
DAC_R_GAIN
Reserved
DAC_R_DIGITAL_GAIN
0x47
CP_CTRL
CP_EN
CP_SMALL_SWIT
CH_FREQ_EN
0x48
HP_L_GAIN
Reserved
Reserved
HP_L_AMP_GAIN
0x49
HP_R_GAIN
Reserved
Reserved
HP_R_AMP_GAIN
0x4A
LINE_GAIN
Reserved
Reserved
LINE_AMP_GAIN
0x4B
MIXOUT_L_SELECT
Reserved
MIXIN_R_INV
MIXIN_L_INV
AUX_L_INV
DAC_L
MIXIN_R
MIXIN_L
AUX_L
0x4C
MIXOUT_R_SELECT
Reserved
MIXIN_L_INV
MIXIN_R_INV
AUX_R_INV
DAC_R
MIXIN_L
MIXIN_R
AUX_R
Reserved
Reserved
Reserved
Reserved
DAC_AUDIO_HPF_CORNER
Reserved
Reserved
DAC_EQ_BAND5
DAC_VOICE_EN
CP_MCHANGE
DAC_VOICE_HPF_CORNER
CP_MOD
CP_ANALOGUE_LVL
System Controller Registers (1)
0x50
SYSTEM_MODES_I
NPUT
ADC_R
ADC_L
MIXIN_R
MIXIN_L
MIC_2
MIC_1
Reserved
MODE_SUBMIT
0x51
SYSTEM_MODES_O
DAC_R
DAC_L
HP_R
HP_L
LINE
AUX_R
AUX_L
MODE_SUBMIT
Datasheet
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Addr
Function
7
6
5
4
3
2
1
0
UTPUT
Control Registers (2)
0x60
AUX_L_CTRL
AUX_L_AMP_EN
AUX_L_AMP_MUT AUX_L_AMP_RAMP_
AUX_L_AMP_ZC_EN
E_EN
EN
AUX_L_AMP_ZC_SEL
Reserved
Reserved
0x61
AUX_R_CTRL
AUX_R_AMP_EN
AUX_R_AMP_MUT AUX_R_AMP_RAMP
AUX_R_AMP_ZC_EN
E_EN
_EN
AUX_R_AMP_ZC_SEL
Reserved
Reserved
0x62
MICBIAS_CTRL
MICBIAS2_EN
Reserved
0x63
MIC_1_CTRL
MIC_1_AMP_EN
MIC_1_AMP_MUT
E_EN
Reserved
Reserved
MIC_1_AMP_IN_SEL
Reserved
Reserved
0x64
MIC_2_CTRL
MIC_2_AMP_EN
MIC_2_AMP_MUT
E_EN
Reserved
Reserved
MIC_2_AMP_IN_SEL
Reserved
Reserved
0x65
MIXIN_L_CTRL
MIXIN_L_AMP_E
N
MIXIN_L_AMP_MU
MIXIN_L_AMP_RAM MIXIN_L_AMP_ZC_E
TE_EN
P_EN
N
MIXIN_L_MIX_EN
Reserved
Reserved
Reserved
0x66
MIXIN_R_CTRL
MIXIN_R_AMP_E MIXIN_R_AMP_M MIXIN_R_AMP_RAM MIXIN_R_AMP_ZC_E
N
UTE_EN
P_EN
N
MIXIN_R_MIX_EN
Reserved
Reserved
Reserved
0x67
ADC_L_CTRL
ADC_L_EN
ADC_L_MUTE_EN
ADC_L_RAMP_EN
Reserved
Reserved
Reserved
Reserved
Reserved
0x68
ADC_R_CTRL
ADC_R_EN
ADC_R_MUTE_EN
ADC_R_RAMP_EN
Reserved
Reserved
Reserved
Reserved
Reserved
MICBIAS2_LEVEL
MICBIAS1_EN
Reserved
MICBIAS1_LVL
0x69
DAC_L_CTRL
DAC_L_EN
DAC_L_MUTE_EN
DAC_L_RAMP_EN
Reserved
Reserved
Reserved
Reserved
Reserved
0x6A
DAC_R_CTRL
DAC_R_EN
DAC_R_MUTE_EN
DAC_R_RAMP_EN
Reserved
Reserved
Reserved
Reserved
Reserved
0x6B
HP_L_CTRL
HP_L_AMP_EN
HP_L_AMP_MUTE HP_L_AMP_RAMP_E
HP_L_AMP_ZC_EN
_EN
N
HP_L_AMP_OE
HP_L_AMP_MIN_GAI
N_EN
Reserved
Reserved
0x6C
HP_R_CTRL
HP_R_AMP_EN
HP_R_AMP_MUTE HP_R_AMP_RAMP_
_EN
EN
HP_R_AMP_ZC_EN
HP_R_AMP_OE
HP_R_AMP_MIN_GAI
N_EN
Reserved
Reserved
0x6D
LINE_CTRL
LINE_AMP_EN
LINE_AMP_MUTE LINE_AMP_RAMP_E
_EN
N
Reserved
LINE_AMP_OE
LINE_AMP_MIN_GAI
N_EN
Reserved
Reserved
0x6E
MIXOUT_L_CTRL
MIXOUT_L_AMP_
EN
Reserved
Reserved
MIXOUT_L_SOFTMI
X_EN
MIXOUT_L_MIX_EN
Reserved
Reserved
Reserved
0x6F
MIXOUT_R_CTRL
MIXOUT_R_AMP
_EN
Reserved
Reserved
MIXOUT_R_SOFTMI
MIXOUT_R_MIX_EN
X_EN
Reserved
Reserved
Reserved
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Addr
Function
7
6
5
4
MIXED_SAMPLE_M
ODE
Reserved
Reserved
Reserved
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DMIC_CLK_RATE
DMIC_SAMPLEPHA
SE
DMIC_DATA_SEL
Reserved
Reserved
PC_RESYNC_AUTO
PC_FREERUN
Mixed Sample Mode Register
0x84
Reserved
24_48_MODE
Configuration Registers
0x90
LDO_CTRL
LDO_EN
Reserved
0x92
GAIN_RAMP_CTRL
Reserved
Reserved
0x93
MIC_CONFIG
Reserved
Reserved
0x94
PC_COUNT
Reserved
Reserved
0x95
CP_VOL_THRESHO
LD1
Reserved
Reserved
0x96
CP_DELAY
0x97
CP_DETECTOR
0x98
DAI_OFFSET
0x99
DIG_CTRL
0x9A
ALC_CTRL2
LDO_LEVEL_SELECT
Reserved
Reserved
Reserved
Reserved
Reserved
CP_THRESH_VDD2
CP_ON_OFF
CP_TAU_DELAY
Reserved
Reserved
Reserved
Reserved
DAC_R_INV
Reserved
Reserved
Reserved
CP_FCONTROL
Reserved
Reserved
DAC_L_INV
Reserved
ALC_RELEASE
ALC_CTRL3
ALC_NOISE
Reserved
Reserved
ALC_NOISE
0x9D
ALC_TARGET_MIN
Reserved
Reserved
ALC_THRESHOLD_MIN
0x9E
ALC_TARGET_MAX
Reserved
Reserved
ALC_THRESHOLD_MAX
ALC_GAIN_LIMITS
0XA0
ALC_INTEG_RELEASE
ALC_ANTICLIP_CTR ALC_ANTICLIP_E
L
N
0xA2
ALC_ANTICLIP_LEV
EL
Reserved
0xA3
ALC_OFFSET_AUT
Reserved
CFR0011-120-00 Rev 4
ALC_ATTEN_MAX
ALC_ANA_GAIN_MAX
Reserved
Reserved
ALC_HOLD
ALC_GAIN_MAX
0xA1
Datasheet
ALC_INTEG_ATTACK
Reserved
Reserved
ALC_ATTACK
0x9B
ALC_ANA_GAIN_LI
MITS
CPDET_DROP
DAI_OFFSET
0x9C
0x9F
Reserved
GAIN_RAMP_RATE
Reserved
Reserved
Reserved
Reserved
ALC_ANA_GAIN_MIN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ALC_ANTICLIP_LEVEL
Reserved
Reserved
Reserved
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Addr
Function
7
6
5
4
3
2
1
0
O_M_L
0xA4
ALC_OFFSET_AUT
O_U_L
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xA6
ALC_OFFSET_MAN
_M_L
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xA7
ALC_OFFSET_MAN
_U_L
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xA8
ALC_OFFSET_AUT
O_M_R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xA9
ALC_OFFSET_AUT
O_U_R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xAB
ALC_OFFSET_MAN
_M_R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xAC
ALC_OFFSET_MAN
_U_R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xAD
ALC_CIC_OP_LVL_
CTRL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xAE
ALC_CIC_OP_LVL_
DATA
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xAF
DAC_NG_SETUP_TI
ME
Reserved
Reserved
Reserved
Reserved
0xB0
DAC_NG_OFF_THR
ESHOLD
Reserved
Reserved
Reserved
Reserved
Reserved
DAC_NG_OFF_THRESHOLD
0xB1
DAC_NG_ON_THRE
SHOLD
Reserved
Reserved
Reserved
Reserved
Reserved
DAC_NG_ON_THRESHOLD
0xB2
DAC_NG_CTRL
DAC_NG_EN
Reserved
Reserved
Reserved
Reserved
DAC_NG_RAMPDN_ DAC_NG_RAMPUP_
RATE
RATE
DAC_NG_SETUP_TIME
Reserved
Reserved
Reserved
Tone Generation & Beep Registers
0xB4
TONE_GEN_CFG1
0xB5
TONE_GEN_CFG2
0xB6
TONE_GEN_CYCLE
S
Datasheet
CFR0011-120-00 Rev 4
START_STOPN
Reserved
Reserved
DTMF_EN
GAIN
Reserved
Reserved
DTMF_REG
Reserved
Reserved
Reserved
Revision 3a
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Reserved
Reserved
SWG_SEL
BEEP_CYCLES
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7
6
5
4
3
Addr
Function
0xB7
TONE_GEN_FREQ1
_L
FREQ1_L
0xB8
TONE_GEN_FREQ1
_U
FREQ1_U
0xB9
TONE_GEN_FREQ2
_L
FREQ2_L
0xBA
TONE_GEN_FREQ2
_U
FREQ2_U
0xBB
TONE_GEN_ON_PE
R
Reserved
Reserved
BEEP_ON_PER
0xBC
TONE_GEN_OFF_P
ER
Reserved
Reserved
BEEP_OFF_PER
2
1
0
System Controller Registers (2)
0xE0
SYSTEM_STATUS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SC2_BUSY
SC1_BUSY
0xFD
SYSTEM_ACTIVE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SYSTEM_ACTIVE
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15.2 Status registers
Register
address
Bit
Type
Label
Default
0x02
STATUS1
7:0
R
(reserved)
00000000
Register
address
Bit
Type
Label
Default
7:4
R
(reserved)
0000
R
PLL_BYPASS_A
CTIVE
3
2
R
0x03
PLL_STATU
S
1
0
Datasheet
CFR0011-120-00 Rev 4
R
R
PLL_MCLK_STA
TUS
PLL_SRM_LOCK
PLL_LOCK
Description
Description
0
Indicates whether the PLL is in bypass mode
0 = not in bypass mode
1 = bypass mode
0
Indicates if the frequency on MCLK is greater
than 1 MHz
0 = MCLK frequency 1 MHz or less
1 = MCLK frequency greater than 1 MHz
0
Asserted if the SRM is locked to the reference
signal
0 = SRM not locked to reference signal
1 = SRM locked to reference signal
0
Asserted if the PLL is locked to the reference
clock
0 = PLL not locked to reference clock
1 = PLL locked to reference clock
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Register
address
0x04
AUX_L_GAI
N_STATUS
Bit
Type
Label
Default
7:6
R
(reserved)
00
5:0
R
AUX_L_AMP_G
AIN_STATUS
Description
Actual AUX_L amplifier gain
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