NAU8820YG

NAU8820 Low Power 24-bit Stereo Audio Codec with High Current Outputs emPowerAudio™ Description The NAU8820 is a low power, high quality CODEC for portable applications. In addition to precision 24-bit stereo ADCs and DACs, this device integrates a broad range of additional functions to simplify implementation of complete audio system solutions. The NAU8820 includes drivers for headphones, and differential or stereo line outputs, and integrates preamps for stereo differential microphones, significantly reducing external components. Advanced on-chip digital signal processing includes a 5-band equalizer, a 3-D audio enhancer, a mixed-signal automatic level control for the microphone or line input through the ADC, and a digital limiter function for the playback path. Additional digital filtering options are available in the ADC path, to simplify implementation of specific application requirements such as ‘wind noise reduction’. The digital interface can operate as either a master or a slave. Additionally, an internal fractional PLL is available to generate accurately any desired audio sample rate clock for the CODEC, using any commonly available system clock from 8MHz to 33MHz and no external parts. The NAU8820 operates with analog supply voltages from 2.5V to 3.6V, while the digital core can operate as low as 1.65V to conserve power. The two high current auxiliary line outputs can operate using separate supply rails for increased output capability and design flexibility, and may be used for cap-less headphone drive. Internal register controls enable flexible power saving modes by powering down sub-sections of the chip under software control. The NAU8820 is specified for operation from -40°C to +85°C. AEC-Q100 & TS16949 compliant device is available upon request. Key Features  DAC: 94dB SNR and -84dB THD (“A” weighted)  ADC: 90dB SNR and -80dB THD (“A” weighted)  Integrated head-phone driver: 40mW into 16Ω  Integrated programmable microphone amplifier  Integrated line input and high current line output  On-chip PLL  Integrated DSP with specific functions: • 5-band equalizer • 3-D audio enhancement • Automatic level control • Audio level limiter • Multiple filtering options  Standard audio interfaces: PCM and I2S  Serial control interfaces with read/write capability  Supports audio sample rates from 8kHz to 48kHz Applications  Personal Media Players  Smartphones  Personal Navigation Devices  Portable Game Players  Camcorders  Digital Still Cameras  Portable TVs  Stereo Bluetooth Headsets NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 1 of 23 June 28, 2016 LAUXIN RAUXIN ADC Filter LLIN LADC RLIN LMICN LMICP Stereo Microphone Interface Input Mixer DAC Filter Volume Control AUXOUT2 Volume Control High Pass & Notch Filters RADC Headphones/ Line drivers LDAC Limiter RDAC AUXOUT1 Output Mixer LHP 5-band EQ RHP 3D RMICN RMICP Digital Audio Interface Microphone Bias GPIO PLL LMICP 1 LMICN 2 LLIN/GPIO2 3 RMICP 4 RMICN 5 RLIN/GPIO3 6 FS 7 BCLK 8 I2S Serial Control Interface PCM NAU8820YG MICBIAS VDDA LHP RHP VSSA VREF VDDSPK NC 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 Pinout Top View WAU8820YG 32-lead QFN RoHS 15 16 14 VDDB SCLK 13 CSB/GPIO1 12 MCLK VSSD 11 DACIN VDDC 9 10 ADCOUT Bulk Ground Pad 24 24 VSSSPK 23 23 NC 22 22 AUXOUT2 21 21 AUXOUT1 20 20 RAUXIN 19 19 LAUXIN 18 18 MODE 17 17 SDIO Part Number Dimension Package Package Material NAU8820YG 5 x 5 mm 32-QFN Pb-Free NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 2 of 23 June 28, 2016 Pin Descriptions Pin # Name Type Functionality 1 2 3 LMICP LMICN LLIN/GPIO2 4 5 6 RMICP RMICN RLIN/GPIO3 Analog Input Analog Input Analog Input / Digital I/O Analog Input Analog Input Analog Input / Digital I/O 7 8 9 10 11 12 13 14 15 FS BCLK ADCOUT DACIN MCLK VSSD VDDC VDDB CSB/GPIO1 Digital I/O Digital I/O Digital Output Digital Input Digital Input Supply Supply Supply Digital I/O 16 17 18 19 20 21 22 23 24 25 26 SCLK SDIO MODE LAUXIN RAUXIN AUXOUT1 AUXOUT2 NC VSSSPK NC VDDSPK Digital Input Digital I/O Digital Input Analog Input Analog Input Analog Output Analog Output 27 28 29 30 31 32 VREF VSSA RHP LHP VDDA MICBIAS Reference Supply Analog Output Analog Output Supply Analog Output Supply Supply Left MICP Input (common mode) Left MICN Input Left Line Input / alternate Left MICP Input / GPIO2 Right MICP Input (common mode) Right MICN Input Right Line Input/ alternate Right MICP Input / Digital Output In 4-wire mode: Must be used for GPIO3 Digital Audio DAC and ADC Frame Sync Digital Audio Bit Clock Digital Audio ADC Data Output Digital Audio DAC Data Input Master Clock Input Digital Ground Digital Core Supply Digital Buffer (Input/Output) Supply 3-Wire MPU Chip Select or GPIO1 multifunction input/output 3-Wire MPU Clock Input / 2-Wire MPU Clock Input 3-Wire MPU Data Input / 2-Wire MPU Data I/O Control Interface Mode Selection Pin Left Auxiliary Input Right Auxiliary Input Headphone Ground / Mono Mixed Output / Line Output Headphone Ground / Line Output Not Internally Connected AUXOUT Line/Speaker Pre-amp Driver Analog Ground Not Internally Connected AUXOUT Line/Speaker Pre-amp Driver Analog Power Supply Decoupling for Midrail Reference Voltage Analog Ground Headphone Positive Output / Line Output Right Headphone Negative Output / Line Output Left Analog Power Supply Microphone Bias Notes 1. The 32-QFN package includes a bulk ground connection pad on the underside of the chip. This bulk ground should be thermally tied to the PCB as much as possible, and electrically tied to the analog ground (VSSA, pin 28). 2. Unused analog input pins should be left as no-connection. 3. Unused digital input pins should be tied to ground. 4. Pins designated as NC (Not Internally Connected) should be left as no-connection NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 3 of 23 June 28, 2016 Figure 1: NAU8820 Block Diagram NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 4 of 23 June 28, 2016 MICBIAS VREF RAUXIN RLIN RMICP RMICN LLIN LMICP LMICN LAUXIN 32 27 20 6 4 5 3 1 2 19 MICROPHONE BIAS R R VDDA + - + Σ LADC MIX/BOOST 12 VSSD PLL RADC MIX/BOOST Σ ALC Control 13 14 - VDDC VDDB 31 VDDA RADC 8 7 9 LDAC DACIN 10 RDAC Limiter AUDIO INTERFACE (PCM/IIS) RINMIX 24 VSSSPK 5 Band EQ 3D LINMIX 26 VDDSPK BCLK FS ADCOUT Notch Filter ALC HPF RADC 28 VSSA 11 Σ Σ 16 17 18 AUX2 MIXER AUX1 MIXER CSB/ MODE GPIO1 15 CONTROL INTERFACE (2-, 3- and 4-wire) LMIX LDAC LINMIX RMIX LMIX MCLK SCLK SDIO Σ RMAIN MIXER LMAIN MIXER Σ RDAC LDAC RINMIX -6dB Normal -1.0X +1.5X -1.0X +1.5X 23 25 29 30 22 21 NC NC RHP LHP AUXOUT2 AUXOUT1 Electrical Characteristics Conditions: VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V, MCLK = 12.288MHz, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, 64X oversampling rate, unless otherwise stated. Parameter Analog to Digital Converter (ADC) Full scale input signal 1 Symbol Comments/Conditions PGABST = 0dB PGAGAIN = 0dB Signal-to-noise ratio SNR Gain = 0dB, A-weighted Total harmonic distortion 2 THD+N Input = -3dB FS input Channel separation 1kHz input signal Digital to Analog Converter (DAC) driving RHP / LHP with 10kΩ / 50pF load Full-scale output 4 Output boost disabled PGA gains = 0dB AUX1BST = 1 AUX2BST = 1 Output boost enabled PGA gains = 0dB AUX1BST = 0 AUX2BST = 0 Signal-to-noise ratio SNR A-weighted Total harmonic distortion 2 THD+N RL = 10kΩ; full-scale signal Channel separation 1kHz input signal Output Mixers Maximum PGA gain into mixer Minimum PGA gain into mixer PGA gain step into mixer Guaranteed monotonic Analog Outputs (RHP / LHP) Maximum programmable gain Minimum programmable gain Programmable gain step size Guaranteed monotonic Mute attenuation 1kHz full scale signal Headphone Output (RHP / LHP with 32Ω load) 0dB full scale output voltage Signal-to-noise ratio SNR A-weighted THD+N RL = 16Ω, Po = 20mW, Total harmonic distortion 2 VDDA = 3.3V RL = 32Ω, Po = 20mW, VDDA = 3.3V AUXOUT1 / AUXOUT2 with 10kΩ / 50pF load AUX1BST = 0 Full scale output 3 AUX2BST = 0 Typ VINFS AUX1BST = 1 AUX2BST = 1 Signal-to-noise ratio Total harmonic distortion 2 Channel separation Power supply rejection ratio (50Hz - 22kHz) Min SNR THD+N 1kHz signal PSRR NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 5 of 23 tbd Max 1.0 0 90 -80 103 tbd VDDA / 3.3 Units Vrms dBV dB dB dB Vrms Vrms 1.5 * (VDDA / 3.3) 88 94 -84 96 tbd dB dB dB +6 -15 3 dB dB dB +6 -57 1 85 dB dB dB dB AVDD / 3.3 92 80 Vrms dB dB 85 dB VDDSPK / 3.3 Vrms (VDDSPK / 3.3) * 1.5 Vrms 87 -83 99 53 dB dB dB dB June 28, 2016 Electrical Characteristics, cont’d. Conditions: VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V, MCLK = 12.288MHz, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, unless otherwise stated. Parameter Symbol Comments/Conditions Min Typ Max Microphone Inputs (LMICP, LMICN, RMICP, RMICN, LLIN, RLIN) and Programmable Gain Amplifier (PGA) PGABST = 0dB 1.0 Full scale input signal 1 PGAGAIN = 0dB 0 Programmable gain -12 35.25 Programmable gain step size Guaranteed Monotonic 0.75 Mute Attenuation 120 Input resistance Inverting Input PGA Gain = 35.25dB 1.6 PGA Gain = 0dB 47 PGA Gain = -12dB 75 Non-inverting Input 94 Input capacitance 10 PGA equivalent input noise 0 to 20kHz, Gain set to 120 35.25dB Input Boost Mixer Gain boost Boost disabled 0 Boost enabled 20 Gain range LLIN / RLIN or -12 6 LAUXIN / RAUXIN to boost/mixer Gain step size to boost/mixer 3 Auxiliary Analog Inputs (LAUXIN, RAUXIN) Gain = 0dB 1.0 Full scale input signal 1 0 Input resistance Aux direct-to-out path, only Input gain = +6.0dB 20 Input gain = 0.0dB 40 Input gain = -12dB 159 Input capacitance 10 NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 6 of 23 June 28, 2016 Units Vrms dBV dB dB dB kΩ kΩ kΩ kΩ pF µV dB dB dB dB Vrms dBV kΩ kΩ kΩ pF Electrical Characteristics, cont’d. Conditions: VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V, MCLK = 12.288MHz, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, unless otherwise stated. Parameter Symbol Comments/Conditions Automatic Level Control (ALC) & Limiter: ADC path only Target record level Programmable gain tHOLD Doubles every gain step, Gain hold time 4 with 16 steps total tDCY ALC Mode Gain ramp-up (decay) 4 ALC = 0 Limiter Mode ALC = 1 tATK ALC Mode Gain ramp-down (attack) 4 ALC = 0 Limiter Mode ALC = 1 Mute Attenuation Microphone Bias Bias voltage VMICBIAS See Figure 4 Bias current source Output noise voltage Digital Input/Output Input HIGH level IMICBIAS Vn 1kHz to 20kHz VIL Min Typ Max -22.5 -1.5 -12 35.25 0 / 2.67 / 5.33 / … / 43691 dBFS dB ms 4 / 8 / 16 / … / 4096 ms 1 / 2 / 4 / … / 1024 ms 1 / 2 / 4 / … / 1024 ms 0.25 / 0.5 / 1 / … / 128 ms 120 dB 0.50, 0.60,0.65, 0.70, 0.75, 0.85, or 0.90 3 14 VDDA VDDA mA nV/√Hz 0.7 * VDDC Input LOW level VIH Output HIGH level VOH ILoad = 1mA Output LOW level VOL ILoad = -1mA V 0.3 * VDDC Input capacitance Units 0.9 * VDDC V V 0.1 * VDDC 10 V pF Notes 1. Full Scale is relative to the magnitude of VDDA and can be calculated as FS = VDDA/3.3. 2. Distortion is measured in the standard way as the combined quantity of distortion products plus noise. The signal level for distortion measurements is at 3dB below full scale, unless otherwise noted. 3. With default register settings, SPKVDD should be 1.5xVDDA (but not exceeding maximum recommended operating voltage) to optimize available dynamic range in the AUXOUT1 and AUXOUT2 line output stages. Output DC bias level is optimized for SPKVDD = 5.0Vdc (boost mode) and VDDA = 3.3Vdc. 4. Time values scale proportionally with MCLK. Complete descriptions and definitions for these values are contained in the detailed descriptions of the ALC functionality. NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 7 of 23 June 28, 2016 Absolute Maximum Ratings Condition Min Max Units VDDB, VDDC, VDDA supply voltages -0.3 +3.61 V VDDSPK supply voltage (default register configuration) -0.3 +5.80 V VDDSPK supply voltage (optional low voltage configuration) -0.3 +3.61 V Core Digital Input Voltage range VSSD – 0.3 VDDC + 0.30 V Buffer Digital Input Voltage range VSSD – 0.3 VDDB + 0.30 V Analog Input Voltage range VSSA – 0.3 VDDA + 0.30 V Industrial operating temperature -40 +85 °C Storage temperature range -65 +150 °C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. Operating Conditions Condition Symbol Min Digital supply range (Core) VDDC Digital supply range (Buffer) Analog supply range Typical Max Units 1.65 3.60 V VDDB 1.65 3.60 V VDDA 2.50 3.60 V Speaker supply (SPKBST=0) VDDSPK 2.50 5.50 V Speaker supply (SPKBST=1) VDDSPK 2.50 5.50 V Ground VSSD VSSA VSSSPK 0 V 1. VDDA must be ≥ VDDC. 2. VDDB must be ≥ VDDC. NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 8 of 23 June 28, 2016 1 General Description The NAU8820 is a stereo device with identical left and right channels that share common support elements. The left and right channels are identical, except for the mixing options and gain options available for each of the two auxiliary outputs. 1.1 Analog Inputs All inputs, except for the wide range programmable amplifier (PGA), have available analog input gain conditioning of -15dB through +6dB in 3dB steps. All inputs also have individual muting functions with excellent channel isolation and off-isolation from all outputs. All inputs are suitable for full quality, high bandwidth signals. Each of the left-right stereo channels includes a low noise differential PGA amplifier, programmable for highgain input. This may be used for a microphone level through line level source. Gain may be set from +35.25db through -12dB at the analog difference-amplifier type programmable amplifier input stage. A separate additional 20dB analog gain is available on this input path, between the PGA output and ADC mixer input. The output of the ADC mixer may be routed to the ADC and/or analog bypass to the analog output sections. Each channel also has a line level input. This input may be routed to the input PGA, and/or directly to the ADC input mixer. Each channel has a separate additional auxiliary input. This is a line level input which may be routed the ADC input mixer and/or directly to the analog output mixers. 1.2 Analog Outputs There are four high current analog audio outputs. These are very flexible outputs that can be used individually or in stereo pairs for a wide range of end uses. However, these outputs are optimized for specific functions and are described in this section using the functional names that are applicable to those optimized functions. Each output receives its signal source from built-in analog output mixers. These mixers enable a wide range of signal combinations, including muting of all sources. Additionally, each output has a programmable gain function, output mute function, and output disable function. The RHP and LHP headphone outputs are optimized for driving a stereo pair of headphones, and are powered from the main analog voltage supply rail, VDDA. These outputs may be coupled using traditional DC blocking series capacitors. Alternatively, these may be configured in a no-capacitor DC coupled design using a virtual ground at ½ VDDA provided by an AUXOUT analog output. Gain of each headphone output can be separately varied in 1dB steps from +6dB through -57dB. The AUXOUT1 and AUXOUT2 analog outputs can be coupled to a wide range of input signal mixing options, and support two gain choices. Gain may either be unity for 3.3V operation, or 1.5x for 5V operation. The auxiliary outputs are powered from the VDDSPK supply rail and VSSSPK ground return path. The supply rail may be the same as VDDA, or may be a separate voltage up to 5.0Vdc. These separate supply rails enable these outputs to have increased output range and power capabilities, and facilitate system design through enabling power supply and routing separate from VDDA. Important: For analog outputs depopping purpose, when powering up speakers, headphone, AUXOUTs, certain delays are generated after enabling sequence. However, the delays are created by MCLK and sample rate register. For correct operation, sending I2S signal no earlier than 250ms after speaker or headphone enabled and MCLK appearing. NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 9 of 23 June 28, 2016 ADC, DAC, and Digital Signal Processing Each left and right channel has an independent high quality ADC and DAC associated with it. These are high performance, 24-bit delta-sigma converters that are suitable for a very wide range of applications. The ADC and DAC functions are each individually supported by powerful analog mixing and routing. The ADC output may be routed to the digital output path and/or to the input of the DAC in a digital passthrough mode. The ADC and DAC blocks are also supported by advanced digital signal processing subsystems that enable a very wide range of programmable signal conditioning and signal optimizing functions. All digital processing is with 24-bit precision, as to minimize processing artifacts and maximize the audio dynamic range supported by the NAU8820. The ADCs are supported by a wide range, mixed-mode Automatic Level Control (ALC), a high pass filter, and a notch filter. All of these features are optional and highly programmable. The high pass filter function is intended for DC-blocking or low frequency noise reduction, such as to reduce unwanted ambient noise or “wind noise” on a microphone input. The notch filter may be programmed to greatly reduce a specific frequency band or frequency, such as a 50Hz, 60Hz, or 217Hz unwanted noise. The DACs are supported by a programmable limiter/DRC (Dynamic Range Compressor). This is useful to optimize the output level for various applications and for use with small loudspeakers. This is an optional feature that may be programmed to limit the maximum output level and/or boost an output level that is too small. Digital signal processing is also provided for a 3D Audio Enhancement function, and for a 5-Band Equalizer. These features are optional, and are programmable over wide ranges. This pair of digital processing features may be applied jointly to either the ADC audio path or to the DAC audio path, but not to both paths simultaneously. 1.3 Voltage Reference and Microphone Bias Built-in power management includes a high stability voltage reference. This is used as an internal reference, and to generate a high quality, programmable microphone bias supply voltage that is well isolated from the supply rails. This microphone bias supply is suitable for both conventional electret (ECM) type microphone, and to power the newer MEMS all-silicon type microphones. 1.4 Digital Interfaces Command and control of the device is accomplished using a 2-wire/3-wire/4-wire serial control interface. This is a simple, but highly flexible interface that is compatible with many commonly used command and control serial data protocols and host drivers. Digital audio input/output data streams are transferred to and from the device separately from command and control. The digital audio data interface supports either I2S or PCM audio data protocols, and is compatible with commonly used industry standard devices that follow either of these two serial data formats. 1.5 Clock Requirements The clocking signals required for the audio signal processing, audio data I/O, and control logic may be provided externally, or by optional operation of a built-in PLL (Phase Locked Loop). An external master clock (MCLK) signal must be active for analog audio logic paths to align with control register updates, and is required as the reference clock input for the PLL, if the PLL is used. The PLL is provided as a low cost, zero external component count optional method to generate required clocks in almost any system. The PLL is a fractional-N divider type design, which enables generating accurate desired audio sample rates derived from a very wide range of commonly available system clocks. The frequency of the system clock provided as the PLL reference frequency may be any stable frequency in the range between 8MHz and 33MHz. Because the fractional-N multiplication factor is a very high precision 24-bit value, any desired sample rate supported by the NAU8820 can be generated with very high accuracy, typically limited by the accuracy of the external reference frequency. Reference clocks and sample rates outside of these ranges are also possible, but may involve performance tradeoffs and increased design verification. NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 10 of 23 June 28, 2016 2 Application Information NAU8820 11 8 7 10 9 16 17 15 18 VDDB VDDC VDDA MCLK BCLK FS DACIN ADCOUT VDDSPK VSSA VSSSPK VSSD SCLK SDIO CSB/GPIO1 MODE VDDA VDDSPK VDDC VDDB 14 13 31 26 C1 4.7uF 28 C2 4.7uF C3 4.7uF C4 4.7uF 24 12 VSS R5 220K ohm VDDB VSS Jack Switch Detection Example Analog Inputs: No Connection if LLIN/GPIO2 6 RLIN/GPIO3 19 C16 1uF C15 1uF R4 0 ohm C14 1uF ECM lectret? type Mic R3 0 ohm 3 R2 2200 ohm R1 2200 ohm 2 1 C13 1uF 5 C12 1uF ECM lectret? type Mic 20 4 C11 1uF 32 AUXOUT1 21 C5 1uF ot used? R9 vss LAUXIN AUXOUT2 optional R8 22 C6 1uF RAUXIN LMICN Left Headphone ip? on 3.5mm Stereo connector C7 220uF LMICP LHP 30 + RMICN R7 vss RHP RMICP MICBIAS 29 optional + C8 220uF VREF R6 VSS leeve? on 3.5mm Audio connector Right Headphone ing? on 3.5mm Stereo connector 27 C10 4.7uF C9 4.7uF VSS 2.1 Typical Application Schematic Figure 2: Schematic with recommended external components for typical application with AC-coupled headphones and stereo electret (ECM) style microphones. Note 1: All non-polar capacitors are assumed to be low ESR type parts, such as with MLC construction or similar. If capacitors are not low ESR, additional 0.1ufd and/or 0.01ufd capacitors may be necessary in parallel with the bulk 4.7ufd capacitors on the supply rails. Note 2: Load resistors to ground on outputs may be helpful in some applications to insure a DC path for the output capacitors to charge/discharge to the desired levels. If the output load is always present and the output load provides a suitable DC path to ground, then the additional load resistors may not be necessary. If needed, such load resistors are typically a high value, but a value dependent upon the application requirements. Note 3: To minimize pops and clicks, large polarized output capacitors should be a low leakage type. Note 4: Depending on the microphone device and PGA gain settings, common mode rejection can be improved by choosing the resistors on each node of the microphone such that the impedance presented to any noise on either microphone wire is equal. Note 5: Unused analog input pins should be left as no-connection. Note 6: Unused digital input pins should be tied to ground. NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 11 of 23 June 28, 2016 2.2 Power Consumption The NAU8820 has flexible power management capability which allows sections not being used to be powered down, to draw minimum current in battery-powered applications. The following table shows typical power consumption in different operating conditions. The “off” condition is the initial power-on state with all subsystems powered down, and with no applied clocks. Mode OFF Sleep Stereo Record Stereo Playback Conditions VREF maintained @ 300kΩ, no clocks, VREF maintained @ 75kΩ, no clocks, VREF maintained @ 5kΩ, no clocks, 8kHz, 0.9Vrms input signal 8kHz, 0.9Vrms input signal, PLL on 16Ω HP, 44.1kHz, quiescent 16Ω HP, 44.1kHz, quiescent, PLL on 16Ω HP, 44.1kHz, 0.6 Vrms sine wave 16Ω HP, 44.1kHz, 0.6Vrms sine, PLL on VDDA = 3V mA 0.008 0.008 0.014 0.259 6.44 7.42 7.25 9.77 21.3 23.8 VDDC = 1.8V mA 0.001 0.001 0.001 0.001 1.07 1.33 6.10 7.53 6.28 7.72 VDDB = 3V mA 0.0003 0.0003 0.0003 0.0003 0.10 0.10 0.03 0.025 0.015 0.015 Total Power mW 0.025 0.025 0.045 0.781 21.5 24.9 32.8 42.9 75.2 85.3 Table 1: Typical Power Consumption in Various Application Modes. NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 12 of 23 June 28, 2016 2.3 Supply Currents of Specific Blocks The NAU8820 can be programmed to enable/disable various analog blocks individually, and the current to some of the major blocks can be reduced with minimum impact on performance. The table below shows the change in current consumed with different register settings. Sample rate settings affect current consumption of VDDC supply. Lower sampling rates draw lower current. Register Dec Hex Function Bit REFIMP[1:0] 1 01 Power Management 1 IOBUFEN[2] ABIASEN[3] MICBIASEN[4] PLLEN[5] AUX2MXEN[6] AUX1MXEN[7] DCBUFEN[8] LADCEN[0] RADCEN[1] 2 02 Power Management 2 LPGAEN[2] RPGAEN[3] LBSTEN[4] RBSTEN[5] SLEEP[6] LHPEN[7] RHPEN[8] LDACEN[0] 3 03 Power Management 3 58 3A Power Management 4 RDACEN[1] LMIXEN[2] RMIXEN[3] AUXOUT2EN[7] AUXOUT1EN[8] IBIADJ[1:0] REGVOLT[2:3] MICBIASM[4] LPADC[6] LPIPBST[7] LPDAC[8] VDDA current increase/ Decrease when enabled +100μA for 80kΩ and 300kΩ +260μA for 3kΩ +100μA +600μA +540μA +2.5 mA +1/5mA from VDDC with clocks applied +200μA +200μA +140μA +2.3 mA with 64X OSR +3.3 mA with 128X OSR +2.3 mA with 64X OSR +3.3 mA with 128X OSR +300μA +300μA +650μA +650μA Same as PLLEN (R1[5]) +800μA +800μA +1.6 mA with 64X OSR +1.7 mA with 128X OSR +1.6 mA with 64X OSR +1.7 mA with 128X OSR +250μA +250μA +225μA +225μA -1.2mA with IBIADJ at 11 -1.1mA with no SNR decrease @ 8kHz -600μA with no SNR decrease @ 8kHz -1.1mA with 1.4dB SNR decrease @ 44.1kHz Table 2: VDDA 3.3V Supply Current in Various Modes NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 13 of 23 June 28, 2016 3 Appendix A: Digital Filter Characteristics Parameter Conditions Min +/- 0.015dB 0 Typ Max Units 0.454 fs ADC Filter Passband -6dB 0.5 Passband Ripple +/-0.015 Stopband Stopband Attenuation fs f > 0.546*fs dB 0.546 fs -60 dB Group Delay 28.25 1/fs -3dB 3.7 Hz -0.5dB 10.4 Hz -0.1dB 21.6 Hz ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband +/- 0.035dB 0 -6dB 0.454 0.5 Passband Ripple +/-0.035 Stopband Stopband Attenuation f > 0.546*fs fs fs dB 0.546 fs -55 dB Group Delay 28 1/fs Table 3: Digital Filter Characteristics TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region 3. Note that this delay applies only to the filters and does not include other latencies, such as from the serial data interface NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 14 of 23 June 28, 2016 Figure 3: DAC Filter Frequency Response Figure 4: DAC Filter Ripple Figure 5: ADC Filter Frequency Response NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 15 of 23 June 28, 2016 Figure 6: ADC Filter Ripple NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 16 of 23 June 28, 2016 0 -2 d B r -4 -6 10 20 30 Hz Figure 7: ADC Highpass Filter Response, Audio Mode 0 -20 d B -40 r -60 -80 100 300 500 700 900 Hz Figure 8: ADC Highpass Filter Response, HPF enabled, FS = 48kHz 0 -20 d B -40 r -60 -80 100 300 500 700 900 Hz Figure 9: ADC Highpass Filter Response, HPF enabled, FS = 24kHz 0 -20 d B -40 r -60 -80 100 300 500 700 900 Hz Figure 10: ADC Highpass Filter Response, HPF enabled, FS = 12kHz NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 17 of 23 June 28, 2016 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 11: EQ Band 1 Gains for Lowest Cut-Off Frequency +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 12: EQ Band 2 Peak Filter Gains for Lowest Cut-Off Frequency with EQ2BW = 0 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 13: EQ Band 2, EQ2BW = 0 versus EQ2BW = 1 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k Hz Figure 14: EQ Band 3 Peak Filter Gains for Lowest Cut-Off Frequency with EQ3BW = 0 NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 18 of 23 June 28, 2016 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15: EQ Band 3, EQ3BW = 0 versus EQ3BW = 1 +15 T +10 +5 d B r 0 -5 -10 -15 Figure 16: EQ Band 4 Peak Filter Gains for Lowest Cut-Off Frequencies with EQ4BW = 0 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 17: EQ Band 4, EQ4BW = 0 versus EQ4BW =1 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k Hz Figure 18: EQ Band 5 Gains for Lowest Cut-Off Frequency NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 19 of 23 June 28, 2016 4 Appendix D: Register Overview DEC HEX NAME Bit 8 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 00 Software Reset RESET (SOFTWARE) 1 01 Power Management 1 DCBUFEN AUX1MXEN AUX2MXEN PLLEN MICBIASEN ABIASEN IOBUFEN REFIMP 2 02 Power Management 2 RHPEN NHPEN SLEEP RBSTEN LBSTEN RPGAEN LPGAEN RADCEN LADCEN 3 03 Power Management 3 AUXOUT1EN AUXOUT2EN Reserved Reserved BIASGEN RMIXEN LMIXEN RDACEN LDACEN General Audio Controls 4 04 Audio Interface BCLKP LRP WLEN AIFMT DACPHS ADCPHS MONO 5 05 Companding Reserved CMB8 DACCM ADCCM ADDAP 6 06 Clock Control 1 CLKM MCLKSEL BCLKSEL Reserved CLKIOEN 7 07 Clock Control 2 4WSPIEN Reserved SMPLR SCLKEN 8 08 GPIO Reserved GPIO1PLL GPIO1PL GPIO1SEL 9 09 Jack Detect 1 JCKMIDEN JCKDEN JCKDIO Reserved 10 0A DAC Control Reserved SOFTMT Reserved DACOS AUTOMT RDACPL LDACPL 11 0B Left DAC Volume LDACVU LDACGAIN 12 0C Right DAC Volume RDACVU RDACGAIN 13 0D Jack Detect 2 Reserved JCKDOEN1 JCKDOEN0 14 0E ADC Control HPFEN HPFAM HPF ADCOS Reserved RADCPL LADCPL 15 F Left ADC Volume LADCVU LADCGAIN 16 10 Right ADC Volume RADCVU RADCGAIN 17 11 Reserved Equalizer 18 12 EQ1-low cutoff EQM Reserved EQ1CF EQ1GC 19 13 EQ2-peak 1 EQ2BW Reserved EQ2CF EQ2GC 20 14 EQ3-peak 2 EQ3BW Reserved EQ3CF EQ3GC 21 15 EQ4-peak3 EQ4BW Reserved EQ4CF EQ4GC 22 16 EQ5-high cutoff Reserved EQ5CF EQ5GC 23 17 Reserved DAC Limiter 24 18 DAC Limiter 1 DACLIMEN DACLIMDCY DACLIMATK 25 19 DAC Limiter 2 Reserved DACLIMTHL DACLIMBST 26 1A Reserved Notch Filter 27 1B Notch Filter 1 NFCU1 NFCEN NFCA0[13:7] 28 1C Notch Filter 2 NFCU2 Reserved NFCA0[6:0] 29 1D Notch Filter 3 NFCU3 Reserved NFCA1[13:7] 30 1E Notch Filter 4 NFCU4 Reserved NFCA1[6:0] 31 1F Reserved ALC and Noise Gate Control 32 20 ALC Control 1 ALCEN Reserved ALCMXGAIN ALCMNGAIN 33 21 ALC Control 2 Reserved ALCHT ALCSL 34 22 ALC Control 3 ALCM ALCDCY ALCATK 35 23 Noise Gate Reserved ALCTBLSEL ALCNEN ALCNTH Phase Locked Loop 36 24 PLL N Reserved PLLMCLK PLLN 37 25 PLL K 1 Reserved PLLK[23:18] 38 26 PLL K 2 PLLK[17:9] 39 27 PLL K 3 PLLK[8:0] 40 28 Mic Bias Mode Reserved MICBIASM Miscellaneous 41 29 3D control Reserved 3DDEPTH 42 2A Reserved 43 2B Reserved 44 2C Input Control MICBIASV RLINRPGA RMICNRPGA RMICPRPGA Reserved LLINLPGA LMICNLPGA LMICPLPGA 45 2D Left Input PGA Gain LPGAU LPGAZC LPGAMT LPGAGAIN 46 2E Right Input PGA Gain RPGAU RPGAZC RPGAMT RPGAGAIN 47 2F Left ADC Boost LPGABST Reserved LPGABSTGAIN Reserved LAUXBSTGAIN 48 30 Right ADC Boost RPGABST Reserved RPGABSTGAIN SPKSTAGE RAUXBSTGAIN 49 31 Output Control Reserved LDACRMX RDACLMX AUX1BST AUX2BST SPKBST TSEN AOUTIMP 50 32 Left Mixer LAUXMXGAIN LAUXLMX LBYPMXGAIN LBYPLMX LDACLMX 51 33 Right Mixer RAUXMXGAIN RAUXRMX RBYPMXGAIN RBYPRMX RDACRMX 52 34 LHP Volume LHPVU LHPZC LHPMUTE LHPGAIN 53 35 RHP Volume RHPVU RHPZC RHPMUTE RHPGAIN 54 36 Reserved 55 37 Reserved 56 38 AUX2 Mixer Reserved AUXOUT2MT Reserved AUX1MIX>2 LADCAUX2 LMIXAUX2 LDACAUX2 57 39 AUX1 Mixer Reserved AUXOUT1MT AUX1HALF LMIXAUX1 LDACAUX1 RADCAUX1 RMIXAUX1 RDACAUX1 58 3A Power Management 4 LPDAC LPIPBST LPADC Reserved MICBIASM REGVOLT IBADJ PCM Time Slot and ADCOUT Impedance Option Control 59 3B Left Time Slot LTSLOT[8:0] 60 3C Misc PCMTSEN TRI PCM8BIT PUDEN PUDPE PUDPS Reserved RTSLOT[9] LTSLOT[9] 61 3D Right Time Slot RTSLOT[8:0] Silicon Revision and Device ID 62 3E Device Revision # Reserved REV 63 3F Device ID ID NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 20 of 23 June 28, 2016 Default 000 000 000 050 000 140 000 000 000 000 0FF 0FF 000 100 0FF 0FF 12C 02C 02C 02C 02C 032 000 000 000 000 000 038 00B 032 010 008 00C 093 0E9 000 000 033 010 010 100 100 002 001 001 039 039 001 001 000 000 020 000 xxx 01A Package Dimensions 32-lead Plastic QFN; 5X5mm2, 1.0mm thickness, 0.5mm lead pitch 32 25 1 24 8 17 9 16 25 32 24 1 17 8 16 NAU8820 Design Guide Rev 1.3 emPowerAudio™ 9 Page 21 of 23 June 28, 2016 5 Ordering Information Nuvoton Part Number Description NAU8820YG Package Material: G = Pb-free Package Package Type: Y = 32-Pin QFN Package Version History VERSION DATE PAGE DESCRIPTION A0.0 February, 2008 NA Preliminary Revision A0.6 May 2008 NA Preliminary Revision A0.86 September 2008 NA Preliminary Revision Rev1.0 Mar. 05, 2009 NA Correct minor errata; minor text improvements Rev 1.1 Jan.15, 2014 1 Updated AECQ100 description Rev 1.2 March 2016 9 Add Important Notice Rev 1.3 June 28, 2016 20 Update package information Table 4: Version History NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 22 of 23 June 28, 2016 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. NAU8820 Design Guide Rev 1.3 emPowerAudio™ Page 23 of 23 June 28, 2016