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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
Data Sheet, Confidential
AS3514
The AS3514 is a low power stereo audio codec and is
designed for Portable Digital Audio Applications. It allows
playback in CD quality and recording in FM-stereo quality. It
has a variety of audio inputs and outputs to directly connect
electret microphones, 16Ω headset, 4Ω speaker and auxiliary
signal sources via a 10-channel mixer. It only consumes 22mW
in playback mode.
High Power Speaker Amplifier
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 2x500mW @8Ω driver capability
– over-current detection
Power Management
– step up for system supply (3.0V – 3.6V)
– step down for CPU core (0.85V – 1.8V, 200mA)
– step up for backlight (15V, 38.5mA)
– LDO for digital supply (2.9V, 200mA)
– LDO for analogue supply (2.9V, 200mA)
– LDO for peripherals (1.7V-3.3V, 200mA)
– LDO for peripherals (3.1V-3.3V, 200mA)
– LDO for RTC (1.0V-2.5V, 2mA)
– LDO for USB 1.1 transceiver (3.26V, 10mA)
– battery supervision
– 10sec emergency shut-down
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Further the device offers advanced power management
functions. All necessary ICs and peripherals in a flash based
Digital Audio Player are supplied by the AS3514. The power
management block generates 9 different supply voltages out of
the battery supply. CPU, NAND flash, SRAM, memory cards,
LCD back-light, USB RX/TX can be powered. The different
supply voltages are programmable via the serial control
interface. It also contains a charger and is designed for battery
supplies from 1V to 5V.
High Efficiency Headphone Amplifier
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 2x40mW @16Ω driver capability
– headphone and over-current detection
– phantom ground eliminates large capacitors
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1 General Description
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Stereo Audio Codec with System Power Management
The AS3514 has an on-chip, phase locked loop (PLL)
controlled, clock generator. It generates 44.1kHz, 48kHz and
other sample rates defined in MP3, AAC, WMA, OGG VORBIS
etc. No additional external crystal or PLL is needed. Further the
AS3514 has an independent 32kHz real time clock (RTC) on
chip which allows a complete power down of the system CPU.
2 Key Features
Multi-bit Sigma Delta Converters
– DAC: 18bit with 94dB SNR (‘A’ weighted) , 48kHz
– ADC: 14bit with 82dB SNR (‘A’ weighted), 16kHz
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2 Microphone Inputs
– 3 gain pre-setting (28dB/34dB/40dB) with AGC
– 32 gain steps @1.5dB and MUTE
– supply for electret microphone
– microphone detection
– remote control by switch
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2 Line Inputs
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– stereo or 2x mono or mono differential
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Line Outputs
– volume control via serial interface
– 32 steps @1.5dB and MUTE
– 1Vp @10kΩ
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Audio Mixer
– 10 channel input/output mixer with AGC
– mixes line inputs and microphones with DAC
– left and right channels independent
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Battery Charger
– automatic trickle charge (50mA)
– prog. constant current charging (100-400mA)
– prog. constant voltage charging (3.9V-4.25V)
Real Time Clock
– ultra low power 32kHz oscillator
– 32bit RTC sec counter
– selectable alarm (seconds or minutes)
General Purpose ADC
– 10bit resolution
– 16 inputs analogue multiplexer
Interfaces
– I²S digital audio interface
– 2 wire serial control interface
– watchdog via serial interface
– power good pin
– 128bit unique ID (OTP)
– 17 different interrupts
Package CTBGA64 [7.0x7.0x1.1mm] 0.8mm pitch
3 Application
Portable Digital Audio Player and Recorder
PDA, Smartphone
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
4 Block Diagram
AS3514 Block Diagram
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Figure 1
VSSC1
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LOUT_L
CVDD
LX_C1
LOUT_R
VDDC1
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VTRM
CPVDD
UVDD
RVDD
CHG_OUT
XIN
CHG_IN
XOUT
BATTEMP
CSDA
CSCL
ISINK
IRQ
VSS15
SW15
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ZAPOE
ZAPEN
PROG
AGND
P_CVDD
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P_PVDD
to I2C
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VREF
MCLK
DVSS
LRCK
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DVDD
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
Contents
General Description ......................................................................................................................................... 1
Key Features.................................................................................................................................................... 1
Application ....................................................................................................................................................... 1
Block Diagram.................................................................................................................................................. 2
Absolute Maximum Ratings (Non-Operating)................................................................................................... 6
5.1
Operating Conditions ................................................................................................................................ 7
6 Detailed Functional Block Description.............................................................................................................. 8
6.1
Line Output ............................................................................................................................................... 8
6.1.1
General.............................................................................................................................................. 8
6.1.2
Register Description .......................................................................................................................... 8
6.1.3
Parameter .......................................................................................................................................... 9
6.2
Headphone Output ................................................................................................................................. 10
6.2.1
General............................................................................................................................................ 10
6.2.2
Phantom Ground ............................................................................................................................. 10
6.2.3
No-Pop Function.............................................................................................................................. 10
6.2.4
Over-current Protection ................................................................................................................... 10
6.2.5
Headphone Detection ...................................................................................................................... 10
6.2.6
Power Save Options ........................................................................................................................ 10
6.2.7
Parameter ........................................................................................................................................ 11
6.2.8
Register Description ........................................................................................................................ 11
6.3
Speaker Output....................................................................................................................................... 13
6.3.1
General............................................................................................................................................ 13
6.3.2
No-Pop Function.............................................................................................................................. 13
6.3.3
Over-current Protection ................................................................................................................... 13
6.3.4
Power Save Options ........................................................................................................................ 13
6.3.5
Parameter ........................................................................................................................................ 14
6.3.6
Register Description ........................................................................................................................ 14
6.4
Microphone Inputs (2x) ........................................................................................................................... 15
6.4.1
General............................................................................................................................................ 15
6.4.2
AGC................................................................................................................................................. 15
6.4.3
Supply & Detection .......................................................................................................................... 15
6.4.4
Remote Control................................................................................................................................ 15
6.4.5
Parameter ........................................................................................................................................ 16
6.4.6
Register Description ........................................................................................................................ 16
6.5
Line Inputs (2x) ....................................................................................................................................... 18
6.5.1
General............................................................................................................................................ 18
6.5.2
Parameter ........................................................................................................................................ 18
6.5.3
Register Description ........................................................................................................................ 18
6.6
Digital Audio Interface............................................................................................................................. 20
6.6.1
Input................................................................................................................................................. 20
6.6.2
Output.............................................................................................................................................. 20
6.6.3
Signal Description............................................................................................................................ 20
6.6.4
Power Save Options ........................................................................................................................ 20
6.6.5
Clock Supervision ............................................................................................................................ 20
6.6.6
Parameter ........................................................................................................................................ 21
6.6.7
Register Description ........................................................................................................................ 21
6.7
Audio Output Mixer ................................................................................................................................. 23
6.7.1
General............................................................................................................................................ 23
6.7.2
Register Description ........................................................................................................................ 23
6.8
Audio Settings......................................................................................................................................... 24
6.8.1
Register Description ........................................................................................................................ 24
6.9
3V Step-Up Converter............................................................................................................................. 26
6.9.1
General............................................................................................................................................ 26
6.9.2
Parameter ........................................................................................................................................ 27
6.10
Low Drop Out Regulators.................................................................................................................... 28
6.10.1
General ........................................................................................................................................ 28
6.10.2
LDO1............................................................................................................................................ 28
6.10.3
LDO2............................................................................................................................................ 28
6.10.4
LDO3............................................................................................................................................ 28
6.10.5
LDO4............................................................................................................................................ 29
6.10.6
Parameter .................................................................................................................................... 29
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1
2
3
4
5
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AS3514 V12
Data Sheet, Confidential
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6.11
DCDC Step-Down Converter .............................................................................................................. 30
6.11.1
General ........................................................................................................................................ 31
6.11.2
Parameter .................................................................................................................................... 33
6.12
SYSTEM ............................................................................................................................................. 35
6.12.1
General ........................................................................................................................................ 35
6.12.2
Power Up ..................................................................................................................................... 35
6.12.3
Power Down................................................................................................................................. 35
6.12.4
Parameter .................................................................................................................................... 35
6.12.5
Register Description..................................................................................................................... 36
6.13
Charger ............................................................................................................................................... 38
6.13.1
General ........................................................................................................................................ 38
6.13.2
Trickle Charge.............................................................................................................................. 38
6.13.3
Temperature Supervision............................................................................................................. 38
6.13.4
Parameter .................................................................................................................................... 38
6.13.5
Register Description..................................................................................................................... 39
6.14
15V Step-Up Converter ....................................................................................................................... 40
6.14.1
General ........................................................................................................................................ 40
6.14.2
Parameter .................................................................................................................................... 40
6.14.3
Register Description..................................................................................................................... 41
6.15
Supervisor ........................................................................................................................................... 42
6.15.1
General ........................................................................................................................................ 42
6.15.2
BVDD Supervision ....................................................................................................................... 42
6.15.3
Junction Temperature Supervision............................................................................................... 42
6.15.4
Register Description..................................................................................................................... 42
6.16
Interrupt Generation ............................................................................................................................ 43
6.16.1
General ........................................................................................................................................ 43
6.16.2
IRQ Source Interpretation ............................................................................................................ 43
6.16.3
De-bouncer .................................................................................................................................. 43
6.17
Real Time Clock .................................................................................................................................. 45
6.17.1
General ........................................................................................................................................ 45
6.17.2
RTC supply .................................................................................................................................. 45
6.17.3
Register Description..................................................................................................................... 45
6.18
10-Bit ADC .......................................................................................................................................... 47
6.18.1
General ........................................................................................................................................ 47
6.18.2
Input Sources ............................................................................................................................... 47
6.18.3
Reference .................................................................................................................................... 47
6.18.4
Parameter .................................................................................................................................... 48
6.18.5
Register Description..................................................................................................................... 48
6.19
128 bit Fuse Array ............................................................................................................................... 50
6.19.1
General ........................................................................................................................................ 50
6.19.2
Register Description..................................................................................................................... 50
6.20
VTRM-LDO ......................................................................................................................................... 51
6.20.1
General ........................................................................................................................................ 51
6.21
I2C Control Interface ........................................................................................................................... 52
6.21.1
General ........................................................................................................................................ 52
6.21.2
Parameter .................................................................................................................................... 52
6.21.3
Register Description..................................................................................................................... 53
7 Electrical Specification ................................................................................................................................... 56
8 Pinout and Packaging .................................................................................................................................... 58
8.1
Pin Description........................................................................................................................................ 58
8.2
Ball & Pin Assignment............................................................................................................................. 60
8.2.1
CTBGA64 ........................................................................................................................................ 60
8.2.2
LQFP64 ........................................................................................................................................... 61
8.3
Package Drawings .................................................................................................................................. 62
8.3.1
CTBGA64 ........................................................................................................................................ 62
8.3.2
LQFP64 ........................................................................................................................................... 63
9 Ordering Information ...................................................................................................................................... 64
10
Copyright .................................................................................................................................................... 65
11
Disclaimer................................................................................................................................................... 65
12
Contact Information .................................................................................................................................... 65
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
Revision History
Revision
Date
Owner
Description
17.1.2005
pkm
first public release
0.2
15.4.2005
pkm
new LQFP pinning (chapter 8.2.2)
0.2
18.4.2005
pkm
0.2
19.4.2005
pkm
added P_CVDD description as pin is missing now in the LQFP package (chapter
8.1)
new PLL description, audio in/out chapters combined (chapter 6.6)
0.2
20.4.2005
pkm
new ordering information (chapter 9)
0.2
22.4.2005
pkm
added additional audio and performance parameter (chapter 6, 7)
0.2
3.5.2005
pkm
new DCDC buck description (chapter 0, 6.12)
0.21
5.5.2005
pkm
updated audio and performance parameter (chapter 6, 7)
0.21
5.5.2005
pkm
added AGC information for audio mixer (chapter 6.7)
0.21
5.5.2005
pkm
updated power up timing (chapter 6.12)
0.21
5.5.2005
pkm
updated absolute maximum ratings and operating conditions (chapter 5)
0.3
19.5.2005
0.3
20.5.2005
0.3
20.5.2005
0.31
9.6.2005
0.31
9.6.2005
0.9
15.3.2006
0.91
12.5.2006
0.92
20.11.2006 pkm
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0.1
changed power up sequence for chip version V12 (chapter 6.12)
pkm
updated audio performance parameter (chapter 7)
pkm
updated 15 DCDC description (chapter 6.14)
pkm
updated soldering conditions (chapter 5)
pkm
added ESD note to pin description (chapter 8.1)
pkm
bug fix in left line in register (chapter 6.5)
pkm
updated PMU block diagrams (chapter 6.x)
updated BGA ball list and assignment (chapter 8.x)
updated absolute maximum ratings (chapter 5)
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pkm
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
5 Absolute Maximum Ratings (Non-Operating)
Stresses beyond the absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or beyond those listed is not implied.
Caution: Exposure to absolute maximum rating conditions may affect device reliability.
Table 1
Absolute Maximum Ratings
Min
-0.5
Max
5.0
Unit
V
5V pins
-0.5
7.0
V
V IN_SW15
15V pin
-0.5
17
V
V IN_VSS
-0.5
0.5
V
V IN_DVDD
Voltage difference at VSS
terminals
3.3V pins with diode to DVDD
-0.5
5.0
DVDD+0.5
V
V IN_xDVDD
pins with no diode to DVDD
-0.5
7.0V
V
V IN_AVDD
3.3V pins with diode to AVDD
-0.5
5.0
AVDD+0.5
V
V IN_REG
voltage regulator pins with
diodes to BVDD
voltage regulator pin with
diode to BVDD
pins with diode to BVDD
-0.5
5.0
BVDD+0.5
3.6
BVDD+0.5
7.0
BVDD+0.5
100
V
mA
Applicable for pins LSP_R/L, HPH_R/L,
CHGOUT, SW3
Norm: JEDEC JESD78 A
+/-1
kV
Norm: MIL 883 E method 3015
1000
mW
CTBGA64, T amb =70°C
-55
125
°C
5
85
%
Min
Max
260
Unit
°C
235
245
°C
30
45
s
V IN_RTC
V IN_BVDD
I scr
Input Current (latchup
immunity)
Electrostatic Discharge HBM
ESD
Pt
T strg
Total Power Dissipation (all
supplies and outputs)
Storage Temperature
H
Humidity non-condensing
Symbol
Parameter
-0.5
-100
V
V
Solder Profile*
Note
Norm IPC/JEDEC J-STD-020C, reflects
moisture sensitivity level only
above 217 °C
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D well
-0.5
Package Body Temperature
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T body
T peak
Applicable for pins VSS3, VSS15,
BVSS, BVSS2, AVSS, DVSS, VSSC1
Applicable for pins MCLK, LRCK, SCLK,
SDI, P_PVDD, P_CVDD, BATTEMP,
ISINK, IRQ, PWGOOD
Applicable for pins
CSCL, CSDA, PWR_UP
Applicable for pins BGND, HPH_CM,
HPGND, LOUT_L/R, VREF, AGND,
LIN1L/R, LIN2L/R, MIC1P/N,
MIC2P/N, MIC1SUP, MIC2SUP
Applicable for pins AVDD, DVDD, PVDD,
CPVDD, CVDD, UVDD
Applicable for pins RVDD, XIN, XOUT
Soldering Conditions
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Table 2
Applicable for pins BVDD, CHGIN,
VBUS, BVDDC1
Applicable for pins SW15
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V IN_5V
Note
Applicable for pin VB1V
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Parameter
single cell supply voltage
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Symbol
V IN_VB1V
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* austriamicrosystems AG strongly recommends to use underfill.
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5.1
Operating Conditions
Table 3
Operating Conditions
PARAMETER
Battery Supply Voltage
SYMBOL
BVDD
3.0
MIN
5.5
MAX
UNIT
V
DCDC 3V Supply Voltage
VB1V
1.0
4.5
V
USB Supply Voltage
UVDD
-
5.5
V
Digital Supply Voltage
DVDD
2.8
3.6
V
Analoge Supply Voltage
AVDD
2.8
3.6
V
Charger Supply Voltage
CHG_IN
4.5
5.5
V
Difference of Positive Supplies
AVDD-DVDD -0.25
0.25
V
NOTE
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AS3514 V12
Data Sheet, Confidential
-0.1
0.1
V
To achieve good performance,
the negative supply terminals
should be connected to low
ohmic ground plane.
Ambient Temperature
T amb
-20
85
°C
Supply Current
BVDD
6.8
20
mA
In Audio Loop Mode
LRCLK
8
48
kHz
According to 8-48kSps
Audio Data
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Difference of Negative Supplies
Any
DVSS, AVSS, VSS3, VSS15, VSSC1, Combination
BVSS
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System Clock Frequency
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AS3514 V12
Data Sheet, Confidential
6 Detailed Functional Block Description
6.1
Line Output
6.1.1
General
The line output is designed to provide the audio signal with typical 1Vp at a load of minimum 10kΩ, which is a minimum value for line
inputs. Additional this output amplifier is capable to drive a 32Ω load (e.g. an earpiece of a mobile phone. To achieve this the operation
mode can be switched from single ended stereo to mono differential.
6.1.2
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This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB.
Register Description
Enabling the output stage is done via a control bit in the audio settings register (AudioSet1 register 0x14h). The line out driver itself is
controlled by the following two registers.
LINE_OUT_R Register
Bit
Name
7,6
5
4..0
reserved
LOR_VOL
Description
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Table 4
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Right Line Out Register (00h)
For testing purpose only, must be set to 0h
not used
volume settings for right line output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
The register is R/W; default value is 00h
Left Line Out Register (01h)
Table 5
LINE_OUT_L Register
Name
7,6
LO_SES_DM
Description
5
4..0
LOL_VOL
Single ended stereo or differential mono selection
11: tbd.
10: output switched to single ended stereo
01: output switched to differential mono
00: output switched to mute
not used
volume settings for left line output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
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Bit
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The register is R/W; default value is 00h
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austriamicrosystems
6.1.3
Parameter
Table 6
Line Output Characteristics
Symbol Parameter
Notes
Min
RL
Output Load
A0
Ax
SNR
Gain
Gain Step-Size
Signal to Noise Ratio
Mute Attenuation
stereo mode
differential mode
programmable gain
10k
32
-40.5
stereo mode
Max
6
1.5
100
100
Unit
Ohm
Ohm
dB
dB
dB
dB
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BVDD = 3.3V, TA= 25oC unless otherwise mentioned
Typ
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AS3514 V12
Data Sheet, Confidential
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Revision 0.92
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AS3514 V12
Data Sheet, Confidential
6.2
Headphone Output
6.2.1
General
The headphone output is designed to provide the audio signal with 2x40mW @ 16Ω or 2x20mW @32Ω, which are typical values for
headphones.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
43.43dB to +1.07dB. The maximum output power of 40mW @ 16Ω is achieved, by setting the mixer output to 1Vp and using the gain of
1.07dB.
6.2.2
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Figure 2 Headphone-Output
Phantom Ground
HPCM pin is the buffered HPGND output. It can be used to drive the loads without external blocking capacitors between HPL / HPR and
HPCM. If the load is between HPR / HPL and BVSS, 100uF of de-coupling capacitors are needed. The phantom ground can be switched
off to save power if not needed.
6.2.3
No-Pop Function
To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output stage is disabled.
HPGND pin, which needs a 100nF capacitor outside, gets charged on power-up with 2uA to AGND=1.45V. After start-up the DC level of
the following pins are the same: HPR=HPL=HPCM=HPGND=AGND=1.45V. The Start-up time before releasing mute is about 90ms. To
avoid pop-noise 150ms discharging time of HPGND after a shutdown, have to be waited before starting up again.
6.2.4
Over-current Protection
6.2.5
ca
This output stage has an over-current protection, which disables the output for 256ms or 512ms. This value can be set in the headphone
registers. The over-current protection limit of HPR and HPL pin is typical 145mA while HPCM pin has a 210mA threshold. If needed, the
over-current condition can also be signalled via an interrupt to the controlling microprocessor.
Headphone Detection
6.2.6
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With a control bit the headphone detection can be enabled. The detection is only working as long as the headphone stage is in power
down mode and the load is applied between HPR / HPL and HPCM. the headphone detection can also trigger a corresponding interrupt.
Power Save Options
ch
To save power, especially when driving 32 Ohm loads, a reduction of the bias current can be selected. Together with switching off the
phantom ground this gives 4 possible operating modes.
Table 7
Headphone Power-Save Options
Te
HPCM_OFF IBR_HPH IDD_HPH (typ.) Load
0
0
2.2mA
16 Ohm
1
0
1
0
1
1
1.5mA
1.5mA
1.0mA
16 Ohm
32 Ohm
32 Ohm
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
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Revision 0.92
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austriamicrosystems
6.2.7
Parameter
Table 8
Power Amplifier Block Characteristics
Symbol Parameter
Notes
RL
Pout
Output Load
Maximum Output Power
stereo mode
A0
Ax
PSRR
Gain
Gain Step-Size
Power Supply Rejection Ratio 200Hz-20kHz, 720mVpp, R L = 16Ω
Short Current Protection Level
I OUT power down
HPGND is forced high
I OUT_pd
T power_up
SNR
Min
R L = 32Ω
R L = 16Ω
programmable gain
Signal to Noise Ratio
Mute Attenuation
Max
16
20
40
-43.43
0.8
1.5
90
145
-20
1.07
2.2
20
90
100
100
Unit
Ohm
mW
mW
dB
dB
dB
mA
uA
ms
dB
dB
lv
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
6.2.8
Typ
al
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AS3514 V12
Data Sheet, Confidential
Register Description
am
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st
il
To get an interrupt on an over-current event, the corresponding bit in the IRQ_ENRD1 register (0x26h) has to be set. Also the interrupt
request for HP detection has to be set in this register. The power-save options are controlled via AudioSet3 register (0x16h). All other
headphone driver settings are controlled by the following two registers.
Right Headphone Register (02h)
Table 9
HPH_OUT_R Register
Name
7,6
HP_OVC_TO
Description
5
4..0
HPR_VOL
speaker over current time out:
11: 0 ms
10: 512 ms
01: 128 ms
00: 256 ms
volume settings for right headphone output, adjustable in 32 steps @ 1.5dB
11111: 1.07 dB gain
11110: -0.43 dB gain
..
00001: -43.93dB gain
00000: -45.43 dB gain
ca
Bit
Te
ch
ni
The register is R/W; default value is 00h
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Left Headphone Register (03h)
Bit
Name
Description
7
HP_Mute
6
HP_ON
5
HPdetON
4..0
HPL_VOL
0: normal operation
1: headphone output set to mute (mute is on during power-up)
0: speaker stage not powered
1: power up headphone stage
0: no headphone detection
1: enable headphone detection
volume settings for left headphone output, adjustable in 32 steps @ 1.5dB
11111: 1.07 dB gain
11110: -0.43 dB gain
..
00001: -43.93dB gain
00000: -45.43 dB gain
Te
ch
ni
ca
am
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lv
The register is R/W; default value is 00h
al
id
Table 10 HPH_OUT_L Register
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6.3
Speaker Output
6.3.1
General
The speaker output is designed to provide the stereo audio signal with 2x500mW @ 4Ω.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from
−40.5dB to +6dB. The maximum output power of 500mW @ 4Ω is achieved, by setting the mixer output to 1Vp and using the gain of
+6dB.
6.3.2
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Figure 3 Speaker Output
No-Pop Function
BGND pin, which needs a 100nF capacitor outside, gets charged on power-up to BVDD/2.To avoiding click and pop noise during powerup and shutdown, the output is automatically set to mute when the output stage is disabled.
The Start-up time before releasing mute is about 100ms. To avoid pop-noise the 150ms discharging time of SPR / SPL after a shutdown
(220µF capacitor in stereo single ended mode assumed), have to be waited before starting up again.
6.3.3
Over-current Protection
This output stage has an over-current protection, which disables the output for 0 to 512ms. This value can be set in the speaker registers.
The over-current protection limit of SPR and SPL pin is typical 700mA. To get an interrupt on an over-current event, the corresponding bit
in the IRQ_ENRD1 register (0x26h) has to be set.
6.3.4
Power Save Options
When driving > 4Ω, two power save options can be chosen.
ca
The output driver stage can be set to only 25% drive capacity, which will reduce the maximum output power. Additionally the bias currents
can be reduced to 50% in 3 steps.
Table 11 Speaker Power-Save Options
0
00
8mA
4 Ohm
00
01
10
11
2.8mA
2.4mA
1.9mA
1.5mA
16-32 Ohm
16-32 Ohm
16-32 Ohm
16-32 Ohm
ch
1
1
1
1
IBR_LSP IDD_HPH (typ.) Load
ni
LSP_LP
Te
BVDD = 3.3V, TA= 25oC unless otherwise mentioned
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6.3.5
Parameter
Table 12 Speaker Amplifier Parameter
Notes
RL
Output Load
stereo mode
mono differential mode
Pout
A0
Ax
PSRR
Maximum Output Power
Gain
Gain Step-Size
Power Supply Rejection Ratio
Short Current Protection Level
I OUT power down
R L = 8Ω
programmable gain
BGND is forced high
Max
1
-40.5
0.8
200Hz-20kHz, 720mVpp, no load
1.5
75
700
-20
6
2.2
20
100
100
100
Signal to Noise Ratio
Mute Attenuation
BVDD = 5V, TA= 25oC unless otherwise mentioned
Unit
Ohm
Ohm
W
dB
dB
dB
mA
uA
ms
dB
dB
Register Description
am
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6.3.6
Typ
4
8
lv
I OUT_pd
T power_up
SNR
Min
al
id
Symbol Parameter
To get an interrupt on an over-current event, the corresponding bit in the IRQ_ENRD1 register (0x25h) has to be set. Changing the bias
current or the output driver strength is done via AudioSet2 register (0x15h). All other speaker driver settings are controlled by the following
two registers.
Right Speaker Register (04h)
Table 13 LSP_OUT_R Register
Name
Description
7,6
SP_OVC_TO
5
4..0
SPR_VOL
speaker over current time out:
11: 0 ms
10: 512 ms
01: 128 ms
00: 256 ms
not used
volume settings for right speaker output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
ca
Bit
The register is R/W; default value is 00h
ni
Left Speaker Register (05h)
Table 14 LSP_OUT_L Register
Name
ch
Bit
SP_Mute
6
SP_ON
Te
7
5
4..0
SPR_VOL
Description
0: normal operation
1: speaker output set to mute (mute is on during power-up)
0: speaker stage not powered
1: power up speaker stage
not used
volume settings for left speaker output, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
The register is R/W; default value is 00h
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6.4
Microphone Inputs (2x)
6.4.1
General
AS3514 includes two identical microphone inputs. The blocks have differential inputs to a microphone amplifier with adjustable gain. This
stage also includes an AGC.
The following volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be
set from –40.5dB to +6dB. The stage is set to mute by default. If the microphone input is not enabled, the volume settings are set to their
default values. Changing of volume and mute control can only be done after enabling the input.
6.4.2
AGC
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Figure 4 Microphone Input
The microphone amplifier includes an AGC, which is limiting the signal to 1Vp. The AGC has 15 steps with a dynamic range of about
29dB. The AGC is ON by default but can be disabled by a microphone register bit.
6.4.3
Supply & Detection
6.4.4
ni
ca
Each microphone input generates a supply voltage of 1.5V above HPHCM. The supply is designed for ≤2mA and has a 10mA current
limit. In OFF mode the MICSUP terminal is pulled to AVDD with 30kohm. A current of typically 50uA generates an interrupt to inform the
CPU, that a circuit is connected. When using HPHCM as headset ground the HPH–stage gives the interrupt. After enabling the HPH-stage
through the CPU the microphone detection interrupt will follow.
Remote Control
Te
ch
Fast changes of the supply current of typically 500uA are detected as a remote button press, and an interrupt is generated. Then the CPU
can start the measurement of the microphone supply current with the internal 10-bit ADC to distinguish which button was pressed. As the
current measurement is done via an internal resistor, only two buttons generating a current of about 0.5mA and 1mA can be detected.
With this 1mA as microphone bias is still available.
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6.4.5
Parameter
Table 15 Microphone Inputs Parameter
Min
programmable gain
-40.5
BVDD = 3.3V, TA=
6.4.6
25oC
differential
MicInGain = 0dB, MicAmp_Gain0
MicInGain = 0dB, MicAmp_Gain1
MicInGain = 0dB, MicAmp_Gain2
Typ
1.5
15
28
34
40
15*2.0
60
120
40
20
10
100
100
Max
Unit
6
dB
dB
kOhm
dB
dB
dB
dB
us
ms
mVp
mVp
mVp
dB
dB
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Gain
Gain Step-Size
Input Resistance
MicAmp_Gain0
MicAmp_Gain1
MicAmp_Gain2
SoftClip_AGC_Range
Attack_Time
Release_Time
V Innom 0
Nominal_Input_Voltage0
V Innom 1
Nominal_Input_Voltage1
V Innom 2
Nominal_Input_Voltage2
SNR
Signal to Noise Ratio
Mute Attenuation
Microphone Supply
V MICsup
Microphone Supply Voltage
I MIClim
Mic. Supply Current Limit
I MICdet
Mic. Detection Current
I REMdet
Remote Detection Current
V noise
Voltage Noise
al
id
Notes
A0
Ax
R inMIC
A MIC 0
A MIC 1
A MIC 2
lv
Symbol Parameter
0-2mA
2.95
10
50
500
5.7
V
mA
uA
uA
uV
unless otherwise mentioned
Register Description
Enabling a microphone input is done via a control bit in the audio settings register (AudioSet1 register 0x14h). To get an interrupt on an
microphone detection event, the corresponding bit in the IRQ_ENRD1 register (0x26h) has to be set, while a remote detection interrupt is
controlled via IRQ_ENRD2 register (0x27h). All other microphone input settings are controlled by the following registers.
Right Microphone Registers (06h & 08h)
Table 16 MIC1_R & MIC2_R Register
Name
7
M1_AGC_off
M2_AGC_off
M1_Gain
M2_Gain
M1R_VOL
M2R_VOL
Te
ch
4..0
0: automatic gain control enabled
1: automatic gain control disabled
00: gain set to 28 dB
01: gain set to 34 dB
10: gain set to 40 dB
11: gain set to tbd.
volume settings for right microphone input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
ni
6,5
Description
ca
Bit
The registers are R/W; default value is 00h
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Left Microphone Register (07h & 09h)
Bit
Name
Description
7
M1_Sup_off
M2_Sup_off
M1_Mute_off
M2_Mute_off
M1L_VOL
M2L_VOL
0: microphone supply enabled
1: microphone supply disabled
0: microphone input set to mute
1: normal operation
Not used
Volume settings for left microphone input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
6
5
4..0
Te
ch
ni
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am
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The registers are R/W; default value is 00h
al
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Table 17 MIC1_L & MIC2_L Register
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6.5
Line Inputs (2x)
6.5.1
General
AS3514 includes two identical line inputs. The blocks can work in mono differential, 2x mono single ended or in stereo single ended mode.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
34.5dB to +12dB. The stage is set to mute by default. If the line input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
If using the inputs as mono differential, the volume setting for the right channel should be set to 0dB.
6.5.2
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Figure 5 Line Input
Parameter
Figure 6 Line Input Parameter
Symbol Parameter
Notes
Min
A0
Ax
R inLINE
Gain
Gain Step-Size
Input Resistance
programmable gain
-34.5
SNR
Signal to Noise Ratio
Mute Attenuation
Mute
Min Gain, single ended stereo
Typ
1.5
49
100
100
100
Max
Unit
12
dB
dB
kOhm
kOhm
dB
dB
BVDD = 3.3V, TA= 25oC, fs=48kHz unless otherwise mentioned
Register Description
ca
6.5.3
Enabling a line-input is done via a control bit in the audio settings register (AudioSet1 register 0x14h). All other line input settings are
controlled by the following registers.
ni
Right Line In Registers (0Ah & 0Ch)
ch
Table 18 LINE_IN1_R & LINE_IN2_R Register
Name
7,6
5
LI1R_Mute_off
LI2R_Mute_off
LI1R_VOL
LI2R_VOL
Te
Bit
4..0
Description
0: right line input is set to mute
1: normal operation
volume settings for right line input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
The registers are R/W; default value is 00h
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Left Line In Register (0Bh & 0Dh)
Name
Description
7,6
LI1_Mode
LI2_Mode
5
LI1L_Mute_off
LI2L_Mute_off
LI1L_VOL
LI2L_VOL
Single ended stereo or differential mono selection
00: inputs switched to single ended stereo
01: inputs switched to differential mono
10: inputs switched to single ended mono
11: tbd.
0: left line input is set to mute
1: normal operation
Volume settings for left line input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
4..0
Te
ch
ni
ca
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The registers are R/W; default value is 00h
lv
Bit
al
id
Table 19 LINE_IN1_L & LINE_IN2_L Register
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6.6
Digital Audio Interface
6.6.1
Input
Digital audio data can be fed into the AS3514 via the I2S interface These input data are then used by the 18-bit DAC to generate the
analog audio signal.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
40.5dB to +6dB. The stage is set to mute by default. If the DAC input is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
6.6.2
Output
al
id
This block consists of an audio multiplexer where the signal, which should be recorded, can be selected. The output is then fed through a
volume control to the 14 bit ADC. The digital output is done via an I2S interface.
The volume control has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be set from –
34.5dB to +12dB. The stage is set to mute by default. If the ADC output is not enabled, the volume settings are set to their default values.
Changing the volume and mute control can only be done after enabling the input.
6.6.3
lv
The I2S output uses the same clocks as the I2S input. The sampling rate therefore depends also on the input sampling rate.
Signal Description
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The digital audio interface uses the standard I2S format:
•
•
left justified
MSB first
•
one additional leading bit
The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than
18 bits sampled, the data sample is completed with “0”s. The ADC output is always 16 bit. If more SCLK pulses are provided, only the first
16 will be significant. All following bit will be “0”.
SCLK has not to be necessarily synchronous to LRCK but the high going edge has to be separate from LRCK edges. The LRCK signal
has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always
in correct phase lock condition to the external LRCK.
Figure 7 I2S_Timing
Error! Not a valid link.
6.6.4
Power Save Options
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.
6.6.5
Clock Supervision
Te
ch
ni
ca
The digital audio interface automatically checks the LRCK. An interrupt can be generated when the state of the LRCK input changes. A bit
in the interrupt register represents the actual state (present or not present) of the LRCK.
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6.6.6
Parameter
Table 20 DAC Block Parameter
Symbol Parameter
Notes
A0
programmable gain DAC input
programmable gain ADC output
Gain Step-Size
Mute Attenuation
I2S inputs / outputs
V IL
V IH
V OL
V OH
t su
Set-up Time
t hd
Hold Time
t s1, t s2
Separation Time
Min
Typ
-43.43
-34.5
SCLK, LRCK, SDI (30%DVDD/2)
SCLK, LRCK, SDI (70%DVDD/2)
SDO @ 2mA
SDO @ 2mA
SDI versus high going edge of SCLK
SDI versus high going edge of SCLK
SCLK high going edges separation from
LRCK edges
LRCK
1.02
2.6
80
80
80
-20
-
0.42
DVDD
0.3
-
V
V
V
V
ns
ns
ns
20
ns
am
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BVDD = 3.3V, DVDD = 2.9V, TA= 25oC unless otherwise mentioned
6.6.7
dB
dB
dB
dB
lv
clock Jitter
Unit
1.07
12
1.5
100
Ax
t jitter
Max
al
id
Gain
Register Description
Enabling the DAC or ADC is done via a control bit in the audio settings register (AudioSet1 register 0x14h). To get an interrupt on a LRCK
state change, the corresponding bit in the IRQ_ENRD1 register (0x25h) has to be set. Changing the bias current and adding a dither
signal is done via AudioSet2 register (0x15h). All other DAC or ADC settings are controlled by the following two registers.
Right DAC Register (0Eh)
Table 21 DAC_R Register
Bit
Name
7..5
4..0
DAR_VOL
Description
volume settings for right DAC input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
ca
The register is R/W; default value is 00h
Left DAC Register (0Fh)
ni
Table 22 DAC_R Register
Name
7
6
DAC_Mute_off
5
4..0
DAL_VOL
Te
ch
Bit
Description
0: DAC input is set to mute
1: normal operation
volume settings for left DAC input, adjustable in 32 steps @ 1.5dB
11111: 6 dB gain
11110: 4.5 dB gain
..
00001: -39 dB gain
00000: -40.5 dB gain
The register is R/W; default value is 00h
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Right ADC Register (10h)
Bit
Name
Description
7,6
ADCmux
00: Stereo Microphone
01: Line_IN1
10: Line_IN2
11: Audio SUM
5
4..0
ADR_VOL
volume settings for right ADC input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
lv
The register is R/W; default value is 00h
al
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Table 23 ADC_R Register
Left ADC Register (11h)
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Table 24 ADC_L Register
Bit
Name
Description
7
AD_FS2
6
ADC_Mute_off
5
4..0
ADL_VOL
Divider selection for ADC clock
0: ADC sample clock is I2S LRCK / 2
1: ADC sample clock is I2S LRCK / 4
0: ADC input is set to mute
1: normal operation
Volume settings for left ADC input, adjustable in 32 steps @ 1.5dB
11111: 12 dB gain
11110: 10.5 dB gain
..
00001: -33 dB gain
00000: -34.5 dB gain
The register is R/W; default value is 00h
PLL Mode Register (1Dh)
Table 25 PLLMode Register
Name
7..3
2,1
Not used
PLLmode Sets the MCLK generation for different LRCK speeds:
00: LRCK: 24-48kHz
01: reserved
10: LRCK: 8-23kHz
11: reserved
Not used
ni
ch
0
Description
ca
Bit
Te
The register is R/W; default value is 00h
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6.7
Audio Output Mixer
6.7.1
General
The mixer stage sums up the audio signals of the following stages
•
•
Microphone Input 1
Microphone Input 2
•
•
•
Line Input 1
Line Input 2
Digital Audio Input (DAC)
al
id
The mixing ratios have to be with the volume registers of the corresponding input stages. Please be sure that the input signals of the
mixer stage are not higher than 1Vp. If summing up several signals, each has of course to be lower.
This shall insure that the output signal is also not higher than 1Vp to get a proper signal for the output amplifier. This stage has an
automatic gain control, which automatically avoids clipping.
AGC
lv
6.7.2
The audio mixer includes an AGC, which is limiting the signal to 1Vp. The AGC has 12 steps with a dynamic range of about 18dB. The
AGC is ON by default but can be disabled by a register bit.
Register Description
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6.7.3
The mixer stage has no direct associated registers.
Te
ch
ni
ca
Enabling the Summing / Mixer stage is done via a control bit in the audio settings register (AudioSet1 register 0x14h). Disabling the AGC
is done via AudioSet2 register (0x15h).
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6.8
Audio Settings
6.8.1
Register Description
First AudioSet Register (14h)
Name
Description
7
ADC_on
6
SUM_on
5
DAC_on
4
LOUT_on
3
LIN2_on
2
LIN1_on
1
MIC2_on
0
MIC1_on
1: ADC for recording is enables
0: ADC disabled
1: Summing / Mixing stage is enabled
0: Summing / Mixing stage is disabled (no audio output possible)
1: DAC enabled
0: DAC disabled
1: Line output enabled
0: Line output disabled
1: Line input 2 enabled
0: Line input 2 disabled
1: Line input 1 enabled
0: Line input 1 disabled
1: Microphone input 2 enabled
0: Microphone input 2 disabled
1: Microphone input 1 enabled
0: Microphone input 1 disabled
am
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Bit
al
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Table 26 AudioSet1 Register
The register is R/W; default value is 00h
Second AudioSet Register (15h)
Table 27 AudioSet2 Register
Bit
Name
7
BIAS_off
4,3
2
ch
1,0
ca
5
ni
6
Description
1: Bias disabled
0: Bias enabled
DITH_off
1: no dither added
0: add dither to the audio stream
AGC_off
1: Automatic gain control for summing stage disabled
0: Automatic gain control for summing stage enabled
IBR_DAC Bias current reduction settings for DAC:
00: 0%
01: 25%
10: 40%
11: 50%
LSP_LP
Low power mode for speaker output:
1: speaker output driver set for 16Ohm load or more (25%)
0: speaker output driver set for 4Ohm to 16Ohm load (100%)
IBR_LSP Bias current reduction settings for speaker output:
00: 0%
01: 17%
10: 34%
11: 50%
Te
The register is R/W; default value is 00h
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Third AudioSet Register (16h)
Bit
Name
Description
7..3
2
ZCU_off
1
IBR_HPH
0
HPCM_off
Not used
Zero cross gain update of audio outputs
1: zero cross update disabled
0: zero cross update enabled
Bias current reduction settings for headphone output:
1: headphone output driver set for 32Ohm load or more (68%)
0: headphone output driver set for 16Ohm load (100%)
Headphone common mode buffer settings:
1: headphone CM buffer is switched off
0: headphone CM buffer is switched on
Te
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The register is R/W; default value is 00h
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Table 28 AudioSet3 Register
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6.9
6.9.1
3V Step-Up Converter
General
Output voltage 3V to 3.6V (BVDD) programmable in 4 steps via DCDC3p bit to save power
Input voltage 1V (1.2V) to 3V, voltages higher than that can be connected to BVDD directly
Maximum output current to BVDD: 150mA
•
•
•
Current mode operation
On-chip compensation and feedback network
On chip 300mΩ NMOS switch
•
•
•
•
PWM mode with 1.2MHz switching frequency
Inductor current limitation 850mA
Pulse skipping capability
Low quiescent current: 40μA in PFM-mode, 300μA in PWM mode
•
•
≤1μA shutdown current
uses external coil (6.8uH) and Schottky diode (500mA)
lv
Te
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Figure 8 DCDC Block Diagram
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•
•
•
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6.9.2
Parameter
Table 29 DCDC Boost Parameter
Notes
I VDD2.9
Power down mode
PFM mode operation
PWM mode (low output load)
R Load >220Ω
I OUT =1mA, VBAT falling from 1.5 to 0V
Minimum Startup Voltage
Hold-on Voltage
Internal Switch R DS_ON
Switching Frequency
t ON_min
t OFF_min
η eff
Minimum On-time
Minimum Off-time
Efficiency
I SW_LIM
I OUT
ΔV OUT
Current Limit
Maximum Load Current
Output Voltage Ripple
Start-up, X3VOK=1
PWM mode operation, X3VOK=0
100
0.9
I OUT =20mA, Vin=1.35
I OUT =50mA, Vin=1.5
1.0V ≤ VB1V ≤ 3.0V
VB1V=1.0V
ΔI OUT =100mA in 100μs
Typ
40
300
1.0
0.5
300
250
1.2
100
100
85
87
0.85
150
Max
Unit
5
μA
μA
μA
V
V
mΩ
kHz
MHz
ns
ns
%
%
A
mA
mV
500
1.42
tbd.
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V STARTUP
V HOLD
R SW_on
f SW
Min
lv
Supply Current
al
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Symbol Parameter
Vin=1.0..2.0V, C(Vbat) = 2.2μF ceramic || 2000μF elko, C(Vreg) = 3 x 2.2μF ceramic, L=DS1608 4.7μH, Temp = 25deg
Figure 9 DCDC Boost Typical Performance Characteristics
90,0
85,0
Eff. [%]
80,0
1,5V
1,35V
1,25V
1,1V
0,9V
75,0
70,0
65,0
ca
60,0
1
10
100
1000
Iout [mA]
Te
ch
ni
BVDD=3.1V, L=DS1608 4.7μH, Temp = 25deg
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6.10 Low Drop Out Regulators
6.10.1 General
These LDO’s are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, micro-controller and other
peripheral devices.
The design is optimised to deliver the best compromise between quiescent current and regulator performance for battery powered
devices.
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id
Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps
ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the
power transistor has to operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output.
The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of
the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.
6.10.2 LDO1
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Figure 10 LDO Block Diagram
This LDO generates the analog supply voltage used for the AS3514 itself.
•
•
Input voltage is BVDD
Output voltage is AVDD (typ. 2.9V)
6.10.3 LDO2
This LDO generates the digital supply voltage used for the AS3514 itself, microprocessor peripheral supply and external components like
SD-Cards, Nand-Flashes, FM-Radio…
ca
Input Voltage is BVDD
Output Voltage is DVDD (typ. 2.9V)
Driver strength: 200mA
ni
•
•
•
6.10.4 LDO3
This LDO will be used to supply the periphery voltage for a microprocessor.
ch
•
Input Voltage BVDD
Output Voltage is PVDD 1.7 to 3.3V
Driver strength: 200mA
Programmable via P_PVDD pin and PVDDp bit in 8 steps
Te
•
•
•
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Table 30 PVDD programming
P_PVDD
VSS
150k to VSS
Open
150k to DVDD
DVDD
PVDDp=0 PVDDp=1
OFF
2.50V
3.33V
2.90V
1.80V
OFF
2.36V
3.15V
2.74V
1.70V
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6.10.5 LDO4
This LDO will be used to supply peripheral circuits. Default value is 3.3V, but it can be manually programmed to 3.1V if needed.
Input Voltage BVDD
Output Voltage is CPVDD (3.1 or 3.3)
Programmable via CPVDDp bit.
Driver strength: 200mA
lv
•
•
•
•
6.10.6 Parameter
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Table 31 LDOs Block Characteristics
Symbol Parameter
R ON
Notes
Min
Typ
On resistance
PSRR
Power supply rejection ratio
I OFF
I VDD
Noise
t start
V out_tol
Shut down current
Supply current
Output noise
Startup time
Output voltage tolerance
V LineReg
Line regulation
V LoadReg
Load regulation
I LIMIT
Current limitation
f=1kHz
f=100kHz
-50
Static
Transient;Slope: t r =10μs
Static
Transient;Slope: t r =10μs
LDO2, LDO3, LDO4
Unit
1
Ω
dB
100
50
50
200
50
nA
μA
μV rms
μs
mV
70
40
without load
10Hz < f < 100kHz
LDO1,
LDO1,
LDO1,
LDO1,
LDO1,
Max
3V, UVDD>4.5V)
•
•
Input voltage on the CHG_IN pin (charger plug in: >80ms, BVDD>3V, CHG_IN>4.0V)
Input voltage on RTCSUP pin (battery change: >1.35V)
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The AS3514 powers up when on of the following condition is true:
To hold the chip in power up mode the PwrUpHld bit in the SYSTEM register (0x20h)is set.
The chip automatically shuts off if one of the following conditions arises:
lv
6.12.3 Power Down
Clearing the PwrUpHld bit in SYSTEM register (0x20h)
I2C watchdog power down if enabled
•
•
•
BVDD drops below the minimum threshold voltage (2.6V)
Junction temperature reaches maximum threshold, set in SUPERVISOR register (0x24h)
High signal on the PWR_UP pin for more than 11s.
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•
•
Figure 16 Power Up Timing
Te
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Error! Not a valid link.
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6.12.4 Parameter
Table 36 Supply Regulator Block Characteristics
Notes
Min
DVDD_POR_OFF
DVDD_POR_ON
POR_ON/OFF_HYST
LRCK WATCHDOG
F(LRCK)_WD_OFF
ON_Delay
Digital Outputs
IRQ, PWGOOD @ 8 mA
IRQ @ 8 mA, push/pull mode
only
IRQ, PWGOOD
Typ
Max
2.15
2.0
100
2
2.6
4.1
50
-
8
kHz
us
V
V
uA
lv
10
0.3
-
Unit
V
V
mV
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Symbol Parameter
DVDD=2.9V; Tamb=25ºC; unless otherwise specified
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6.12.5 Register Description
SYSTEM Register (20h)
Table 37 System Register
Bit
Name
Description
7..4
Version
3
PVDDp
2
CPVDDp
1
EnWDogPwdn
0
PwrUpHld
Unique number to identify the design version
0010: revision 2
PVDD trimming:
0: Vnom
1: Vnom *17/18
CPVDD trimming:
0: Vnom 3.3
1: 3.1V
0: forced power down through watchdog is disabled
1: forced power down through watchdog is enabled
0: power up hold is cleared and supply is switched off
1: set to on after power on
Te
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The register is R/W (bits 7 to 4 are read only); default value is 21h
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CVDD / DCDC3 Register (21h)
Description
cfm_off
6
pmos_mode
5
4,3
Reserved
DCDC3p
2
0,1
Reserved
CVDDp1
CVDD DCDC current force mode
0: force current mode is enabled (higher efficency)
1: force current mode is disabled (lower noise)
CVDD DCDC PMOS 100% on mode
0: PMOS can operate at 100% duty cycle (LDO mode possible)
1: PMOS 100% duty cycle disabled
For testing purpose only, must be set to 0h
DCDC3 Vout programminig
00: 3.6V
01: 3.2V
10: 3.1V
11: 3.0V
For testing purpose only, must be set to 0h
CVDD trimming:
00: Vnom
01: Vnom –50mV
10: Vnom –100mV
11: Vnom – 150mV
lv
Name
7
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Bit
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Table 38 CVDD / DCDC3 Register
Te
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The register is R/W; default value is 00h
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6.13 Charger
6.13.1 General
This block can be used to charge a 4V Li-Io accumulator. It supports constant current and constant voltage charging modes with
adjustable charging currents (50 to 400mA) and maximum charging voltage (3.9 to 4.25V).
6.13.2 Trickle Charge
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If the battery voltage is below 3V, the charger goes automatically in trickle charge mode with 50mA charging current and 3.9V endpoint
voltage. In this mode charging current and voltage are not precise, but provide a charger function also for deep discharged batteries. Also
the temperature supervision
6.13.3 Temperature Supervision
This charger block also features a supply for an external 100k NTC resistor to measure the battery temperature while charging. If the
temperature is too high, an interrupt can be generated.
Table 39 Charger Parameter
I CHG_trick
V CHG_trick
I CHG (0-7)
Parameter
Notes
Charging Current
(trickle charge)
Charger Endpoint Voltage
(trickle charge)
Charging Current
BVDD 3V, end of charge is true
V ON_ABS
V ON_REL
V OFF_REL
V BATEMP_ON
V BATEMP_OFF
I CHG_OFF
Charger On Voltage IRQ
Charger On Voltage IRQ
Charger Off Voltage IRQ
Battery Temp. high level
Battery Temp. low level
End Of Charge current level
BVDD = 3V
CHG_IN-CHG_OUT
CHG_IN-CHG_OUT
BVDD >3V
BVDD >3V
BVDD >3V
I REV_OFF
Reverse current shut down
CHG_OUT = 5V, CHG_IN = VSS
I NOM
-20%
V NOM
-50mV
40
380
480
5%
I NOM
V NOM
3.1
170
77
400
500
10%
I NOM
20mA
t MIN_ON
MDC
I LOAD < 20mA
Minimum On-Time
Maximum Duty Cycle
Te
ch
F IN
C OUT
L (Inductor)
Ceramic
Use inductors with small C PARASITIC
(0>
Qrtc
Qrtc
Qrtc
second
second
second
second
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Addr
register
register
register
register
Te
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The registers are R/W; default value is 00h
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0
1
2
3
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6.18 10-Bit ADC
6.18.1 General
This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature
supervision, button press detection, etc..
6.18.2 Input Sources
Table 50 ADC10 Input Sources
Source
Range
LSB
Description
0
1
2
3
4
5
6
BVDD
RTCSUP
UVDD
CHG_IN
CVDD
BatTemp
MicSup1
5.120V
5.120V
5.120V
5.120V
2.560V
2.560V
2.560V
5mV
5mV
5mV
5mV
2.5mV
2.5mV
2.5mV
7
MicSup2
2.560V
2.5mV
8
9
10
11
12
13..15
VBE1
VBE2
I_MicSup1
I_MicSup2
VBAT
Reserved
check battery voltage of 4V LiIo accumulator
check RTC backup battery voltage
check USB host voltage
check charger input voltage
check charge pump output voltage
check battery charging temperature
check voltage on MicSup1 for remote control or external voltage
measurement
check voltage on MicSup2 for remote control or external voltage
measurement
measuring junction temperature @ 2uA
measuring junction temperature @ 1uA
check current of MicSup1 for remote control detection
check current of MicSup2 for remote control detection
check single cell battery voltage
for testing purpose only
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Nr.
1.024
1mV
1.024
1mV
2.048mA typ. 2.0uA
2.048mA typ. 2.0uA
2.560V
2.5mV
1.024V
1mV
BVDD, RTCSUP, UVDD, CHG_IN
These sources are fed into a 1/5 voltage divider (180kΩ typ.) and further amplified by 2.5.
CVDD, BatTemp, MicSup1, MicSup2
These sources are fed directly to the ADC input multiplexer.
VBE1, VBE2
These inputs are first amplified by 2.5 and than fed to the ADC input multiplexer.
ca
I_MicSup1, I_MicSup2
VBAT
ni
The measurement of the microphone supply LDOs is not very accurate, as the current-voltage conversion is only done by a single resistor
which shows wide process and temperature variations. These measurements should be only used for remote function detection.
ch
This source is divided by 2.5 with a voltage divider (180kΩ typ.) and than amplified by 2.5. This has to be done, as VBAT can represent
voltages up to 3.6V. Please note, that the maximum measurement rage will be still 2.560V
6.18.3 Reference
Te
AVDD=2.9V is used as reference to the ADC. AVDD is trimmed to +/-20mV with over all precision of +/-29mV. So the absolute accuracy is
+/-1%.
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6.18.4 Parameter
Table 51 ADC10 Parameter
Parameter
Notes
Min
Typ
Max
Unit
BVDD, RTCSUP, UVDD, CHG_IN,
VBAT
138k
180k
234k
Ω
ADC Full Scale Range
Divition Factor 1
BVDD, RTCSUP, UVDD, CHG_IN
Divition Factor 2
VBAT
ADC Gain Stage
Conversion Time
I_MicSup1/2 Full Scale Range
2.534
0.198
0.396
2.475
1.4
2.56
0.2
0.4
2.5
34
2
2.586
0.202
0.404
2.525
50
2.8
V
1
1
V
µs
mA
R DIV
Input Divider Resistance
ADC FS
Ratio1
Ratio2
Gain
T CON
I_MIC FS
BVDD=3.6V; Tamb=25ºC; unless otherwise specified
lv
6.18.5 Register Description
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Symbol
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The conversion gets started by writing to the ADC_0 register (0x2Eh). After finishing the conversion an interrupt request can be generated
if the corresponding bit in the IRQ_ENRD2 register (0x27h) is set. Conversion source and result can be set / read with the following two
registers.
ADC_0 Register (2Eh)
Table 52 ADC_0 Register
Name
7..4
ADC_Source
Description
3,2
1
0
ADC
ADC
0000: BVDD
0001: RTCSUP
0010: UVDD
0011: CHG_IN
0100: CVDD
0101: BatTemp
0110: MicSup1
0111: MicSup2
1000: VBE_1uA
1001: VBE_2uA
1010: I_MicSup1
1011: I_MicSup2
1100: VBAT
1101: reserved
1110: reserved
1101: reserved
Not used
ADC result bit 10
ADC result bit 9
ni
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Bit
Te
ch
The register is R/W; default value is 000000xxb
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ADC_1 Register (2Fh)
Table 53 ADC_1 Register
Name
Description
7
6
5
4
3
2
1
0
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
result
result
result
result
result
result
result
result
bit
bit
bit
bit
bit
bit
bit
bit
8
7
6
5
4
3
2
1
al
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Bit
Te
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The register is R/W; default value is xxh
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6.19 128 bit Fuse Array
6.19.1 General
This fuse array is used to store a unique identification number, which can be used for DRM issues. The number is randomly generated
and programmed during the production process.
6.19.2 Register Description
UID Registers (30h to 3Fh)
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Table 54 UID_0 to UDI15_3 Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
UID_0
UID_1
UID_2
UID_3
UID_4
UID_5
UID_6
UID_7
UID_8
UID_9
UID_10
UID_11
UID_12
UID_13
UID_14
UID_15
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
Unique
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
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The register is read only.
Description
lv
Addr
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byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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AS3514 V12
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6.20 VTRM-LDO
6.20.1 General
This LDO is generating a supply voltage for an external USB 1.1 transceiver out of the 5V USB master supply.
Input Voltage is UVDD (4.5 to 5.5V)
Output Voltage is VTRM (typ. 3.2V)
•
Driver strength: ~10mA
Te
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•
•
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6.21 I2C Control Interface
6.21.1 General
There is an I2C slave block implemented to have access to 64 byte of setting information.
The I2C address is: Adr_Group8 - audioprocessors
•
•
8Ch_write
8Dh_read
Error! Not a valid link.
6.21.2 Parameter
Table 55 I2C Operating Conditions
CSCL, CSDA (max 30%DVDD)
CSCL, CSDA (min 70%DVDD)
CSCL, CSDA
CSDA @3mA
Spike insensitivity
Frequency at CSCL
Notes
Min
Typ
0
2.03
200
50
100
450
100
-
Max
Unit
0.87
5.5
800
0.4
1
-
V
V
mV
V
ns
MHz
ns
lv
Parameter
VIL
VIH
HYST
VOL
Tsp
Speed
Tsetup
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Symbol
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Figure 19 I2C timing
CSDA has to change Tsetup before
rising edge of CSCL
No hold time needed for CSDA relative
to rising edge of CSCL
CSDA H hold time relative to CSDA
edge for start/stop/rep_start
CSDA prop delay relative to lowgoing
edge of CSCL
Thold
TS
Tdata
0
-
-
ns
200
-
-
ns
24
50
80
ns
Te
ch
ni
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DVDD =2.9V, Tamb=25ºC; unless otherwise specified
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6.21.3 Register Description
Registers Overview (00h to 3Fh)
Table 56 I2C Register Overview
Addr
Name
00h
LINE_OUT_R reserved
05h
06h
07h
08h
09h
0Ah
0Bh
D
D
D
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ch
0Ch
D
LOR_Vol
Gain from Mixer_Out to Line_Out= (-40.5dB … +6dB)
0
0
0
0
0
0
0
0
LINE_OUT_L LO_SES_DM
LOL_Vol
Gain from Mixer_Out to Line_Out= (-40.5dB … +6dB)
0
0
0
0
0
0
0
0
HPH_OUT_R HP_OVC_TO
HPR_Vol
Gain from Mixer_Out to HPH_Out= (-45.43dB … +1.07dB)
0
0
0
0
0
0
0
0
HPH_OUT_L HP_Mute HP_ON
HPdetON HPL_Vol
Gain from Mixer_Out to HPH_Out= (-45.43dB … +1.07dB)
0
0
0
0
0
0
0
0
LSP_OUT_R SP_OVC_TO
SPR_Vol
Gain from Mixer_Out to LSP_Out= (-40.5dB … +6.0dB)
0
0
0
0
0
0
0
0
LSP_OUT_L SP_Mute SP_ON
SPL_Vol
Gain from Mixer_Out to LSP_Out= (-40.5dB … +6.0dB)
0
0
0
0
0
0
0
0
MIC1_R
M1_AGC M1_Gain
M1R_Vol
_off
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
0
0
0
MIC1_L
M1_Sup M1_Mute M1L_Vol
_off
_off
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
0
0
0
MIC2_R
M2_AGC M2_Gain
M2R_Vol
_off
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
0
0
0
MIC2_L
M2_Sup M2_Mute M2L_Vol
_off
_off
Gain from MicAmp_Out to Mixer_In= (-40.5dB … +6.0dB)
0
0
0
0
0
0
0
0
Line_IN1_R LI1R_Mut LI1R_Vol
e
Gain from LineIn_Pin to Mixer_In=-34.5dB+LI1R_VOL*1.5dB
_off
(-34.5dB … +12dB)
0
0
0
0
0
0
0
0
Line_IN1_L
LI1_Mode
LI1L_Mut LI1L_Vol
e
Gain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB)
_off
0
0
0
0
0
0
0
0
Line_IN2_R LI2R_Mut LI2R_Vol
e_off
Gain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB)
0
0
0
0
0
0
0
0
Line_IN2_L
LI2_Mode
LI2L_Mut LI2L_Vol
e_off
Gain from LineIn_Pin to Mixer_In= (-34.5dB … +12dB)
0
0
0
0
0
0
0
0
DAC_R
DAR_Vol
Gain from DAC_Out to Mixer_In= (-40.5dB … +6dB)
0
0
0
0
0
0
0
0
DAL_Vol
DAC_L
DAC_Mute _off
Gain from DAC_Out to Mixer_In= (-40.5dB … +6dB)
0
0
0
0
0
0
0
0
lv
04h
D
-
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on A
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03h
D
ca
02h
D
ni
01h
D
Te
0Dh
0Eh
0Fh
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
Addr
Name
D
10h
ADC_R
ADCmux
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
D
ch
2Bh
D
al
id
1Dh
D
lv
16h
D
ADR_Vol
Gain from ADCMux_Out to ADC_In= (-34.5dB … +12dB)
0
0
0
0
0
0
0
0
ADC_L
AD_FS2 ADC_Mute ADL_Vol
_off
Gain from ADCMux_Out to ADC_In= (-34.5dB … +12dB)
0
0
0
0
0
0
0
0
AudioSet1
ADC_on SUM_on
DAC_on LOUT_on
LIN2_on
LIN1_on MIC2_on
MIC1_on
0
0
0
0
0
0
0
0
AudioSet2
BIAS_off DITH_off AGC_off IBR_DAC
LSP_LP IBR_LSP
0
0
0
0
0
0
0
0
AudioSet3
ZCU_OFF IBR_HPH
HPCM_off
0
0
0
0
0
0
0
0
PLL_MODE
PLLmode
0
0
0
0
0
0
0
0
SYSTEM
Design_Version
PVDDp
CVDDp
EnWDogPw PwrUPHld
dn
0
0
1
0
0
0
0
1
CVDD/DCDC3 cfm_off
pmos_
For
DCDC3p
For
CVDDp
mode
testing
testing
only
only
0
0
0
0
0
0
0
0
CHARGER
TmpSup_ CHGI
CHGV
CHG_off
off
0
0
0
0
0
0
0
0
DCDC15
For testing purpose only, must
I_V15
be set to 0h
0
0
0
0
0
0
0
0
SUPERVISOR
BVDD_Sup
JT_Sup
0
0
0
0
0
0
0
0
IRQ_ENRD0 CHG
CHG
CHG
CHG
USB
USB
RVDD
BVDD
tmphigh
endofch status
changed
status
changed was low
Is low
0
0
0
0
0
0
0
0
IRQ_ENRD1 JTEMP
LSP
HPH
I2S
I2S
Mic2
Mic1
HeadPh
high
overcurr overcurr status
changed
connect
connect
Connect
0
0
0
0
0
0
0
0
IRQ_ENRD2 T_deb
IRQ_ActH IRQ_PushP Remote_Det Remote_D RTC_Updat ADC_EndCo
igh
ull
2
et1
e
n
0
0
0
0
0
0
0
0
RTCV
VRTC
For testing purpose
RTC_ON
OSC_ON
only, must be set to 0h
0
0
1
0
0
0
1
1
RTCT
IRQ_MIN
TRTC
0
1
0
0
0
0
0
0
RTC_0
Qrtc
0
0
0
0
0
0
0
0
RTC_1
Qrtc
0
0
0
0
0
0
0
0
RTC_2
Qrtc
0
0
0
0
0
0
0
0
RTC_3
Qrtc
0
0
0
0
0
0
0
0
ADC_0
ADC_Source
ADC
0
0
0
0
0
0
X
X
ADC_1
ADC
X
X
X
X
X
X
X
X
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15h
D
-
ca
14h
D
ni
11h
D
Te
2Ch
2Dh
2Eh
2Fh
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
Name
UID_0 .. 15
D
D
ID
…
ID>127:120>
D
D
D
D
D
D
Te
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ni
ca
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Addr
30-3F
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
7 Electrical Specification
Table 57 Audio Parameter
Notes
Min
R L = 16Ω
A-weighted, no load, silence input
A-weighted, no load, -60dB FS 1kHz
input
no load, 1kHz FS input
SNR
DR
Signal to Noise Ratio
Dynamic Range
THD
Total Harmonic Distortion
SINAD
Pout=20mW, R L = 32Ω, f=1kHz FS input
Pout=40mW, R L = 16Ω, f=1kHz FS input
Signal to Noise and Distortion A-weighted, no load, 1kHz FS input
CS
Channel Separation
Signal to Noise Ratio
Dynamic Range
THD
Total Harmonic Distortion
ni
SNR
DR
R L = 32Ω, 1kHz 1V RMS (FS) input
R L = 16Ω, 1kHz 1V RMS (FS) input
A-weighted, no load, silence input
A-weighted, no load, -60dB FS 1kHz
(FS) input
no load, 1kHz 1V RMS input
ch
Pout=20mW, R=32Ω, 1kHz 1V RMS (FS)
input
Pout=40mW, R=16Ω, 1kHz 1V RMS (FS)
input
Signal to Noise and Distortion A-weighted, no load, 1kHz 1V RMS input
Te
CS
A-weighted,Pout=20mW, R L = 32Ω,
f=1kHz FS input
A-weighted,Pout=40mW, R L = 16Ω,
f=1kHz FS input
R L = 32Ω
R L = 16Ω
ca
Line Input to HP Output
FS
Full Scale Output
SINAD
Max
Channel Separation
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A-weighted, Pout=20mW, R=32Ω, 1kHz
1V RMS (FS) input
A-weighted, Pout=40mW, R=16Ω, 1kHz
1V RMS (FS) input
R L = 32Ω
R L = 16Ω
Revision 0.92
Unit
0.985
92
89
V RMS
dB
dB
-90
83
dB
dB
0.95
93
-85
80
89
V RMS
dB
dB
dB
dB
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1kHz FS input
A-weighted, no load, silence input
A-weighted, no load, -60dB FS 1kHz
input
THD
Total Harmonic Distortion
1kHz FS input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz FS input
Line Input to Line Output
FS
Full Scale Output
1kHz 1V RMS (FS) input
SNR
Signal to Noise Ratio
A-weighted, no load, silence input
THD
Total Harmonic Distortion
1kHz 1V RMS (FS) input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz FS input
CS
Channel Separation
DAC Input to HP Output
FS
Full Scale Output
R L = 32Ω
Typ
al
id
Parameter
DAC Input to Line Output
FS
Full Scale Output
SNR
Signal to Noise Ratio
DR
Dynamic Range
lv
Symbol
0.950
0.944
91
90
V RMS
V RMS
dB
dB
-90
-73
-66
84
73
dB
dB
dB
dB
dB
66
-60
dB
73
67
dB
dB
0.930
0.929
95
95
V RMS
V RMS
dB
dB
-85
-73
dB
dB
-68
-60
dB
84
73
dB
dB
68
dB
73
68
dB
dB
56 - 65
austriamicrosystems
SNR
THD
Signal to Noise Ratio
Total Harmonic Distortion
R L = 32Ω, 1kHz 1V RMS (FS) input
R L = 16Ω, 1kHz 1V RMS (FS) input
R L = 4Ω, 1kHz 1V RMS (FS) input
A-weighted, no load, silence input
no load, 1kHz 1V RMS (FS) input
85
77
71
-58
V RMS
V RMS
V RMS
dB
dB
dB
dB
dB
dB
dB
dB
60
dB
60
dB
81
80
dB
dB
-62
61
dB
dB
83
82
dB
dB
-62
61
dB
dB
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st
il
R=32Ω, 1kHz 1V RMS (FS) input
R=16Ω, 1kHz 1V RMS (FS) input
R=4Ω, 1kHz 1V RMS (FS) input,
BVDD=5V
SINAD
Signal to Noise and Distortion A-weighted, no load, 1kHz 1V RMS (FS)
input
A-weighted, R=32Ω, 1kHz 1V RMS (FS)
input
A-weighted, R=16Ω, 1kHz 1V RMS (FS)
input
A-weighted, R=4Ω, 1kHz 1V RMS (FS)
input, BVDD=5V
CS
Channel Separation
R L = 32Ω
MIC Input to ADC Output
SNR
Signal to Noise Ratio
A-weighted, no load, silence input
DR
Dynamic Range
A-weighted, no load, -60dB FS 1kHz
input
THD
Total Harmonic Distortion
1kHz 27mV RMS (-3dB FS) input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz 27mV RMS (-3dB FS)
input
Line Input to ADC Output
SNR
Signal to Noise Ratio
A-weighted, no load, silence input
DR
Dynamic Range
A-weighted, no load, -60dB FS 1kHz
input
THD
Total Harmonic Distortion
1kHz 1V RMS (-3dB FS) input
SINAD
Signal to Noise and Distortion A-weighted, 1kHz 1V RMS (-3dB FS) input
1.036
1.023
0.950
91
-88
-78
-71
-60
al
id
DAC to SP Output
FS
Full Scale Output
lv
AS3514 V12
Data Sheet, Confidential
Te
ch
ni
ca
BVDD = 3.3V, TA= 25oC, fs=48kHz, RL= 10kΩ unless otherwise mentioned
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
8 Pinout and Packaging
8.1
Pin Description
Please observe that pin assignment may change in preliminary data sheet
Type
Function
BVDDC1
Supply
DCDC1V Battery terminal
LXC1
Aout
DCDC1V Coil terminal
VSSC1
Supply
DCDC1V Neg. Supply terminal
CVDD
Ai/o
DCDC1V Output for CPU supply progr. 0.85-1.8V
VB1V
Supply
Battery supply input for single cell application
VSS3
Supply
DCDC3V Neg. Supply terminal
SW3
Aout
DCDC3V Switch terminal
SW15
Aout
DCDC15V Switch terminal
VSS15
Supply
DCDC15V Neg. Supply terminal
ISINK
Aout
DCDC15V Load Current Sink terminal
lv
PinName
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CTBGA64 LQFP64
ball #
pin #
1
A1
2
B1
3
C3
4
C2
5
D2
6
C1
7
D1
8
F1
9
E1
10
D3
11
E2
12
E3
13
D4
14
F2
15
G1
16
H1
17
G2
H2
18
F3
al
id
Table 58 Pinlist CTBGA64 & LQFP64
DVSS
Supply
Digital Circuit Neg. Supply terminal
BATTEMP
Ai/o
Charger Battery Temperature Sensor input (RNTC 100k)
VTRM
Aout
USB1.1 VTRM Regulator output 3.25V
UVDD
Ain
USB1.1 USB supply input
CHGOUT
Aout
Charger Output prog. Ichg 50-400mA Vchg 3.9-4.25V
CHGIN
Ain
Charger Input
P_PVDD
Ain
5 State Prog Input of PVDD regulator
P_CVDD
Ain
5 State Prog Input of CVDD regulator
PWR_UP
Din
Pull_dn
Di/o
pull_up
Din
pull_up
Dout OD
Power Up input
I2S Left/Right Clock
G3
19
G4
20
F5
H3
21
H4
23
E4
24
H5
F4
G5
25
SDO
Din
pull_dn
Din
pull_dn
Din
pull_dn
Dout
26
PWGOOD
Dout
Goes high when power up sequence is completed (XRES)
27
IRQ
Dout OD
Interrupt Request Output, default open drain
28
DVDD
Aout
Analog Circuit Pos. Supply terminal, to be supplied via pin 62 on LQFP
29
XOUT
Ai/o
32kHz RTC Oscillator Crystal terminal
30
RVDD
Aout
RTC Supply Regulator Output prog. to 1.0-2.5V
31
XIN
Ai/o
32kHz RTC Oscillator Crystal terminal
32
RTCSUP
Supply
RTC Pos. Supply terminal 5.5V max
33
MIC1SUP
Ai/o
Microphone Supply 1 (2.95V) / Remote Input 1
34
MIC1N
Ain
Microphone Input 1N
35
MIC1P
Ain
Microphone Input 1P
CSCL
Q32k
LRCK
SCLK
ca
SDI
ni
Te
ch
H6
G6
H7
G7
H8
G8
F6
F7
E7
F8
E8
E5
22
CSDA
Data I/O of two wire interface
Clock Input of two wire interface
32kHz RTC clock output, default open drain
I2S Shift Clock
I2S Data Input to DAC
I2S Data output from ADC
36
MIC2P
Ain
Microphone Input 2P
37
MIC2N
Ain
Microphone Input 2N
38
MIC2SUP
Ai/o
Microphone Supply 2 (2.95V) / Remote Input 2
39
LIN1R
Ain
Line Input 1 Right Channel
40
LIN1L
Ain
Line Input 1 Left Channel
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
CTBGA64 LQFP64
ball #
pin #
41
D8
42
E6
43
D7
44
D6
45
C8
46
C7
Type
Function
LIN2R
Ain
Line Input 2 Right Channel
LIN2L
Ain
Line Input 2 Left Channel
AGND
Ai/o
Analog Reference (AVDD/2) decoupling cap terminal (10uF)
VREF
Ai/o
Analog Reference ( filtered AVDD) decoupling cap terminal (10uF)
AVSS
Supply
Analog Circuit Neg Supply terminal
LOUT_R
Aout
Line Output Right Channel / Ear Piece diff output N
LOUR_L
Aout
Line Output Left Channel / Ear Piece diff output P
48
AVDD
Supply
Analog Circuit Pos. Supply terminal
49
HPGND
Ai/o
Headphone Amplifier Reference decoupling cap terminal (100nF)
50
BVSS2
Supply
Headphone Amplifier Neg. Supply terminal
51
HPH_CM
Aout
Headphone Common GND Output for DC-coupled speakers
52
BVSS
Supply
Loudspeaker Amplifier Neg. Supply terminal
53
HPH_R
Aout
Headphone Output Right Channel
54
BVSS2
Supply
Headphone Amplifier Neg. Supply terminal
55
HPH_L
Aout
Headphone Output Left Channel
56
BGND
Ai/o
Loudspeaker Amplifier Reference decoupling cap terminal (100nF)
57
BVDD
Supply
Pos. Supply Terminal 5.5V max.
58
59
60
61
62
63
64
lv
al
id
47
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B8
B7
A8
A7
C6
B6
B5
A6
A5
D5
A4
C5
B4
C4
A3
B3
A2
B2
PinName
LSP_R
Aout
Loudspeaker Output Right Channel
BVDD
Supply
Pos. Supply Terminal 5.5V max.
LSP_L
Aout
Loudspeaker Output Left Channel
BVDD
Supply
Pos. Supply Terminal 5.5V max.
DVDD
Aout
LDO2 Regulator Output fixed 2.9V to be connected to pin 28 on LQFP
PVDD
Aout
LDO3 Regulator Output prog. to 1.7-3.3V
CPVDD
Aout
LDO4 Regulator Output limiter to 3.56V as ChargePump Input
Please observe that pin assignment may change in preliminary data sheet.
Te
ch
ni
ca
Note: The guarantee ESD robustness pin VSSC1 (double bond of 2 VSSC1 pads) and pin VSS3 (triple bond of 2x VSS3 and 1x SUB pad)
have to be connected together inside the package (e.g. package substrate)
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
8.2
Ball & Pin Assignment
8.2.1
CTBGA64
please observe that pin assignment may change in preliminary data sheet
Figure 20 Ball Assignment CTBGA64
2
3
4
5
6
7
8
A
VDDC1
PVDD
BVDD
BVDD
HPH_L
BVSS2
BVSS2
HPGND
B
LXC1
CPVDD
DVDD
BVDD
HPH_R
BVSS
AVDD
LOUT_L
C
VSS3
CVDD
VSSC1
LSP_L
LSP_R
HPH_CM
LOUT_R
AVSS
D
SW3
VB1V
ISINK
VTRM
BGND
VREF
AGND
E
VSS15
F
SW15
G
H
lv
al
id
1
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nt
st
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LIN2R
DVSS
BATTEMP
SDI
LIN1L
LIN2L
MIC2N
LIN1R
UVDD
PWR_UP
PWGOOD
Q32k
MIC1P
MIC2P
MIC2SUP
CHGOUT
P_PVDD
CSDA
CSCL
IRQ
RVDD
RTCSUP
MIC1N
CHGIN
P_CVDD
LRCK
SCLK
SDO
XOUT
XIN
MIC1SUP
Te
ch
ni
ca
please observe that pin assignment may change in preliminary data sheet
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
8.2.2
LQFP64
please observe that pin assignment may change in preliminary data sheet
1
AVDD
LOUT_L
LOUT_R
AVSS
VREF
AGND
LIN2L
LIN2R
LIN1L
LIN1R
MIC2SUP
MIC2N
MIC2P
MIC1P
MIC1N
MIC1SUP
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lv
VDDC1
LX_C1
VSSC1
CVDD
VB1V
VSS3
SW3
SW15
VSS15
ISINK
DVSS
BATTEMP
VTRM
UVDD
CHGOUT
CHGIN
al
id
Figure 21 Pin Assignment LQFP64
33
please observe that pin
Te
ch
ni
ca
assignment may change in preliminary data sheet
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
8.3
Package Drawings
8.3.1
CTBGA64
Te
ch
ni
ca
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al
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Figure 22 CTBGA64 7x7mm 0.8mm pitch
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
8.3.2
LQFP64
Te
ch
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lv
al
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Figure 23 LQFP 10x10mm 0.5mm pitch
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
9 Ordering Information
Device ID
Number
AS3514[V]-XY[Z]
AS3514-QT
AS3514-BTZ
AS3514-BRZ
AS3514-WD
Package Type
LQFP 64
CTBGA 64
CTBGA 64
8” Wafer
Delivery Form
Tray
Tray
Tape and Reel
Dies on Foil
Description
evaluation only
Package Size = 7x7mm
Pitch = 0.8mm
V = Version
X = Package Type:
Q = LQFP 64 Thin Quad Flat Pack
lv
B = CTBGA 64, Thin ChipArray Ball Grid Array 7x7mm
W = 8” Wafer
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Y = Delivery Form:
T = Tray
al
id
Where
R = Tape and Reel
D = Dies on Foil
Z = Pb-free Status:
Te
ch
ni
ca
Z = Pb-free/ RoHS package type
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Revision 0.92
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austriamicrosystems
AS3514 V12
Data Sheet, Confidential
10 Copyright
Copyright © 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks
Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the
prior written consent of the copyright owner.
All products and companies mentioned are trademarks of their respective companies.
11 Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or
regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change
specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check
with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications
requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each
application.
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG
shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of
profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or
arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall
arise or flow out of austriamicrosystems AG rendering of technical or other services.
12 Contact Information
Headquarters:
austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 5692
info@austriamicrosystems.com
For Sales Offices, Distributors and Representatives, please visit:
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www.austriamicrosystems.com
– a leap ahead
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austriamicrosystems
www.austriamicrosystems.com
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