ISD15D00 DATASHEET
ISD15D00
Digital ChipCorder
with
Digital Audio Interface
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
TABLE OF CONTENTS
1
GENERAL DESCRIPTION .............................................................................................................. 3
2
FEATURES ...................................................................................................................................... 3
3
BLOCK DIAGRAM ........................................................................................................................... 5
4
PINOUT CONFIGURATION ............................................................................................................ 6
4.1
QFN-32 .................................................................................................................................................... 6
5
PIN DESCRIPTION .......................................................................................................................... 7
6
ELECTRICAL CHARACTERISTICS .............................................................................................. 10
6.1
ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 10
6.2
OPERATING CONDITIONS ........................................................................................................................ 10
6.3
DC PARAMETERS ................................................................................................................................... 12
6.4
AC PARAMETERS ................................................................................................................................... 13
6.4.1
Internal Oscillator ......................................................................................................................... 13
6.4.2
Inputs ............................................................................................................................................. 13
6.4.3
Outputs ........................................................................................................................................... 15
6.4.4
SPI Timing ..................................................................................................................................... 18
6.4.5
I2S Timing ...................................................................................................................................... 19
7
APPLICATION DIAGRAM .............................................................................................................. 21
8
PACKAGE SPECIFICATION ......................................................................................................... 23
8.1
9
10
QFN-32 (5X5 MM^2, THICKNESS 0.8MM ,PITCH 0.5 MM) .................................................................. 23
ORDERING INFORMATION .......................................................................................................... 24
REVISION HISTORY.................................................................................................................. 25
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
1
GENERAL DESCRIPTION
®
The ISD15D00 is a digital ChipCorder featuring digital compression, comprehensive memory
management, and integrated analog/digital audio signal paths. The ISD15D00 utilizes serial flash
2
memory to provide non-volatile audio playback for a two-chip solution. The ISD15D00 provides an I S
digital audio interface, faster digital programming, higher sampling frequency, and a signal path with
SNR 80dB.
2
2
The ISD15D00 can take digital audio data via I S or SPI interface. When I S input is selected, it will
replace the analog audio inputs and will support sample rates of 32, 44.1 or 48 kHz depending upon
clock configuration. When SPI interface is chosen, the sample rate of the audio data sent must be one
of the ISD15D00 supported sample rates.
The ISD15D00 has inbuilt analog audio inputs, analog audio line driver, and speaker driver output.
The analog audio input, Aux-in, has a fixed gain configured by SPI command. Aux-in can directly
feed-through to the analog outputs; it can also mix with the DAC output and then feed-through to the
analog outputs.
Analog outputs are available in two forms: (1) Aux-out is an analog single-ended voltage output; (2)
Class-AB BTL (bridge-tied-load) is an analog differential voltage output. Class-AB BTL delivers 0.7watt output power at VCCSPK = 4.5V.
Class-D PWM direct-drive is also available, which delivers 0.9-watt output power at VCCSPK = 4.5V.
2
FEATURES
External Memory:
o The ISD15D00 supports the following flash:
Manufacturer
Family
JEDEC ID
Winbond
25X
25Q
EF 30 1X
EF 40 1X
25P
20 20 1X
Numonyx
25PX
20 71 1X
25PE
20 80 1X
MXIC
25L / 25V
C2 20 1X
o
The addressing ability of ISD15D00 is up to 128Mbit, which is 64-minute playback time based
on 8kHz/4bit ADPCM.
o Inbuilt 3V voltage regulator to provide power source to the external flash memory
Fast Digital Programming
o Programming rate can go up to 1Mbits/second mainly limited by the flash memory write rate.
Memory Management
o Store pre-recorded audio (Voice Prompts) using high quality digital compression
o Use a simple index-based command for playback
o Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration
of the device and play back Voice Prompts sequences.
Sample Rate
o Seven sampling frequencies are available for a given master sample rate. For example, the
sampling frequencies of 4, 5.3, 6.4, 8, 12.8, 16 and 32kHz are available when the device is
clocked at a 32kHz master sample rate.
2
o For I S operation, 32, 44.1 and 48kHz master sample rates are available with playback
sampling frequencies scaling accordingly.
Compression Algorithms
o For Pre-Recorded Voice Prompts
µ-Law: 6, 7 or 8 bits per sample
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Revision 1.2
ISD15D00 DATASHEET
1
2
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample
Enhanced ADPCM: 2, 3, 4 or 5 bits per sample
Variable-bit-rate optimized compression. This allows best possible compression given a
metric of SNR and background noise levels.
Oscillator
o Internal oscillator with internal reference: 2.048 MHz with ±1% deviation
1
o Internal oscillator with external resistor: 2.048 MHz with ±2% deviation
2
o I S bit clock input
Inputs
o Aux-in: Analog input with 2-bit gain control configured by SPI command
Outputs
o PWM: Class-D speaker driver to directly drive an 8Ω speaker or buzzer
Deliver 0.9-watt output power at VCCSPK = 4.5V
o Aux-out: an analog single-ended voltage output
o Class-AB BTL: an analog differential voltage output
Deliver 0.7-watt output power at VCCSPK = 4.5V
Class-AB BTL can directly drive an 8Ω speaker or buzzer
Class-AB BTL can drive an 8Ω speaker or buzzer via an external amplifier
I/Os
o SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data
2
2
2
2
2
o I S interface: I S_CLK, I S_WS, I S_SDI, I S_SDO for digital audio data
o 8 GPIO pins:
2
4 GPIO pins share with I S
4 GPIO pins share with SPI Interface
GPIO pins can trigger Voice Macro for a pushbutton application
8-bit Volume Control set by SPI command for flexible mixing
Talarm temperature threshold: 125°C typical
Operating Voltage: 2.7 ~ 5.5V
Standby Current: 1uA typical
Package:
o Green QFN-32
Automotive grade:
o AEC-Q100 grade 3 operating temperature range -40⁰C to 85⁰C
2
o Tested to a high reliability standard
With ±1% precision 80kohm external resistor.
Contact Nuvoton sale s representatives for details.
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Revision 1.2
ISD15D00 DATASHEET
BLOCK DIAGRAM
AUXIN
Av = 0, 3, 6, 9dB
AUXIN
SUM2
GPIO7 / SDI
GPIO5 / WS
Digital Signal Path:
Digital Filters
Resampling
Volume Control
I2S
Interface
GPIO4 / SDO
DAC
PWM
Control
AUX_MUX
GPIO6 / SCK
+
SPI
Interface
Memory Management
and Command
Interpreter
Flash Memory
Controller
Figure 3-1 ISD15D00 Block Diagram
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Publication Release Date: Aug 5, 2016
Revision 1.2
AUXOUT
SPK+
SPK-_MUX
SCLK
SSB
GPIO1 / MISO
GPIO0 / MOSI
GPIO3 / INTB
GPIO2 / RDY/BSYB
AUXOUT
SPK+_MUX
De-Compression
FCLK
FCSB
FDI
FDO
3
SPK-
ISD15D00 DATASHEET
VMID
VSSA
VCCA
AUXOUT
32
31
30
29
28
27
26
I2S_WS / GPIO5 2
XTALIN
AUXIN
25
24 VCCFS
23 VCCF
22 FCSB
I2S_SDO / GPIO4 3
VSSD 4
21 FDI
ISD15D00
VCCD 5
20 FCLK
19 FDO
VREG 6
18 RESET
MISO / GPIO1 7
12
VCCSPK
SPK+
13
14
15
VCCSPK
11
SPK-
10
VSSSPK
9
MOSI / GPIO0
SCLK 8
17 GPIO2 / RDY/BSYB
16
GPIO3 / INTB
I2S_SCK / GPIO6 1
NC
QFN-32
I2S_SDI / GPIO7
4.1
PINOUT CONFIGURATION
SSB
4
Figure 4-1 ISD15D00 QFN-32 Pin Configuration.
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Revision 1.2
ISD15D00 DATASHEET
5
PIN DESCRIPTION
Pin
Number
QFN-32
Pin Name
I/O
Function
32
GPIO7 /
2
I S_SDI
I/O
A GPIO pin. By default this pin is a pull-high input.
2
Can be configured as Serial Data Input of the I S interface.
1
GPIO6 /
2
I S_SCK
I/O
A GPIO pin. By default this pin is a pull-high input.
Can be configured as Clock input in slave mode or clock output in
master mode. This pin can be configured as an external clock buffer
2
if I S is not used.
2
GPIO5 /
2
I S_WS
I/O
A GPIO pin. By default this pin is a pull-high input.
Can be configured as Word Select (WS) input in slave mode or WS
output in master mode.
3
GPIO4 /
2
I S_SDO
I/O
A GPIO pin. By default this pin is a pull-high input.
2
Can be configured as Serial Data Output of the I S Interface.
4
VSSD
I
Digital Ground.
5
VCCD
I
Digital power supply.
6
VREG
O
A 1.8V regulator to supply the internal logic. A minimum 1uF
capacitor with low ESR 0.2W
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Typ
Max
Units
65
dB
-40
dB
80
%
Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
CLASS-AB BTL OUTPUT
Conditions: VCCD = 3.3V, VCCA = VCCSPK = 5V, MCLK = 16.384MHz, TA = +25°C, 1kHz signal
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Speaker CLASS-AB BTL Output (SPK_PLUS / SPK_MINUS with 8Ω bridge-tied-load)
Full scale output
Gain paths all at 0dB
VCCA / 3.3
gain
Vrms
Signal-to-noise ratio
2
Total harmonic distortion
Efficiency
dB
dB
%
SNR
THD
EAB
A-weighted
A-weighted
8Ω bridge-tied-load
Pout > 0.7W
90
-60
50
Conditions: VCCD = 3.3V, VCCA = VCCSPK = 3.3V, MCLK = 16.384MHz, TA = +25°C, 1kHz signal
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Speaker CLASS-AB BTL Output (SPK_PLUS / SPK_MINUS with 8Ω bridge-tied-load)
Full scale output
Gain paths all at 0dB
VCCA / 3.3
gain
Vrms
Signal-to-noise ratio
2
Total harmonic distortion
Efficiency
dB
dB
%
SNR
THD
EAB
A-weighted
A-weighted
8Ω bridge-tied-load
Pout > 0.4W
84
-60
50
Notes
1.
2.
3.
Full Scale is relative to the magnitude of VCCA and can be calculated as FS = VCCA/3.3.
Distortion is measured in the standard way as the combined quantity of distortion products plus noise. The signal
level for distortion measurements is at 3dB below full scale, unless otherwise noted.
SNR measured with a -100dbFS signal at input.
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Revision 1.2
ISD15D00 DATASHEET
6.4.4
SPI Timing
TSSBHI
SSB
TSSBS
TSSBH
TSCK
TRISE
TFALL
SCLK
TSCKH
TSCKL
MOSI
TMOS
TMOH
TZMID
TMIZD
MISO
TMID
TCRBD
TRBCD
RDY/BSYB
Figure 6-2 SPI Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
TSCK
SCLK Cycle Time
60
---
---
ns
TSCKH
SCLK High Pulse Width
25
---
---
ns
TSCKL
SCLK Low Pulse Width
25
---
---
ns
TRISE
Rise Time for All Digital Signals
---
---
10
ns
TFALL
Fall Time for All Digital Signals
---
---
10
ns
st
TSSBS
SSB Falling Edge to 1 SCLK Falling Edge Setup
Time
30
---
---
ns
TSSBH
Last SCLK Rising Edge to SSB Rising Edge Hold
Time
30ns
---
50us
---
TSSBHI
SSB High Time between SSB Lows
20
---
---
ns
TMOS
MOSI to SCLK Rising Edge Setup Time
15
---
---
ns
TMOH
SCLK Rising Edge to MOSI Hold Time
15
---
---
ns
TZMID
Delay Time from SSB Falling Edge to MISO Active
--
--
12
ns
TMIZD
Delay Time from SSB Rising Edge to MISO Tri-state
--
--
12
ns
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
SYMBOL
MIN
TYP
MAX
Delay Time from SCLK Falling Edge to MISO
---
---
12
ns
TCRBD
Delay Time from SCLK Rising Edge to RDY/BSYB
Falling Edge
--
--
12
ns
TRBCD
Delay Time from RDY/BSYB Rising Edge to SCLK
Falling Edge
0
--
--
ns
TMID
6.4.5
DESCRIPTION
UNIT
2
I S Timing
TSCK
TRISE
TFALL
IS_SCK
TWSH
TSCKH
TWSH
TSCKL
TWSS
TWSS
IS_WS
TSDIS
TSDIH
IS_SDI
MSB
LSB
MSB
TSDOD
IS_SDO
MSB
LSB
MSB
2
Figure 6-3 I S Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
TSCK
IS_SCK Cycle Time
60
---
---
ns
TSCKH
IS_SCK High Pulse Width
25
---
---
ns
TSCKL
IS_SCK Low Pulse Width
25
---
---
ns
TRISE
Rise Time for All Digital Signals
---
---
10
ns
TFALL
Fall Time for All Digital Signals
---
---
10
ns
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
TWSS
WS to IS_SCK Rising Edge Setup Time
20
---
---
ns
TWSH
IS_SCK Rising Edge to IS_WS Hold Time
20
---
---
ns
TSDIS
IS_SDI to IS_SCK Rising Edge Setup Time
15
---
---
ns
TSDIH
IS_SCK Rising Edge to IS_SDI Hold Time
15
---
---
ns
TSDOD
Delay Time from IS_SCLK Falling Edge to IS_SDO
---
---
12
ns
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
7
APPLICATION DIAGRAM
VCCD
CSB
VCC
DO
HOLDB
WPB
CLK
GND
DIO
0.1
uF
Flash
VSSD 4
21
22
20
19
FDI
FCSB
FCLK
FDO
32
1
2
3
I2S_SDI / GPIO7
I2S_SCK / GPIO6
I2S_WS / GPIO5
I2S_SDO / GPIO4
VCCD VCCD
VREG
ISD15D00
10K
10K
VCCD 5
24 V
CCFS
23 V
CCF
1uF
7
8
VCCD
9
10
10K
16
data flow control 17
18
high pulse of 50ms
MISO / GPIO1
SCLK
SSB
MOSI / GPIO0
INTB / GPIO3
RDY/BSYB / GPIO2
RESET
220pF
0.1uF
30
5.6 K
: Ground for SPK;
1uF
VCCSPK
VCCSPK 11
VCCSPK 15
0.1
uF
VSSSPK 13
SPK+ 12
VCCA
VCCD
VCCSPK1uH
0
XTALIN 25
VCCA
VCCA
27
VSSA
28
AUXOUT 26
4.7
uF
0.1
uF
0.1uF 100
4.7K
200
pF
Figure 7-1 ISD15D00 Application Diagram – VCCF is regulated internally from VCCFS
- 21 -
47
uF
1uH
SPK- 14
AUXIN
29 V
MID
: Analog ground;
6
10K
5.6 K
: Digital ground;
0.1
uF
Publication Release Date: Aug 5, 2016
Revision 1.2
0
ISD15D00 DATASHEET
VCCD
VCCFS
CSB
VCC
DO
HOLDB
WPB
0.1
uF
CLK
DIO
GND
Flash
VSSD 4
21
22
20
19
FDI
FCSB
FCLK
FDO
32
1
2
3
I2S_SDI / GPIO7
I2S_SCK / GPIO6
I2S_WS / GPIO5
I2S_SDO / GPIO4
VCCD VCCD
VREG 6
ISD15D00
10K
10K
VCCD 5
24 V
CCFS
23 V
CCF
1uF
7
8
VCCD
9
10
10K
16
data flow control 17
18
high pulse of 50ms
MISO / GPIO1
SCLK
SSB
MOSI / GPIO0
INTB / GPIO3
RDY/BSYB / GPIO2
RESET
220pF
30
5.6 K
VCCA
VCCD
VCCSPK1uH
SPK- 14
1uH
0
47
uF
0
XTALIN 25
VCCA
VCCA
27
AUXIN
29 V
MID
0.1
uF
SPK+ 12
VSSA 28
0.1uF
: Ground for SPK;
1uF
VCCSPK
13
10K
5.6 K
: Analog ground;
VCCSPK 11
VCCSPK 15
VSSSPK
: Digital ground;
0.1
uF
AUXOUT 26
4.7
uF
0.1
uF
0.1uF 100
4.7K
200
pF
Figure 7-2 ISD15D00 Application Diagram – VCCF is tied to VCCFS
The above application examples are for references only. It makes no representation or warranty that such applications shall be suitable for the use specified. Each design has to be optimized in
its own system for the best performance on voice quality, current consumption, functionalities and etc.
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Revision 1.2
ISD15D00 DATASHEET
8
8.1
PACKAGE SPECIFICATION
QFN-32 (5X5 MM^2, THICKNESS 0.8MM ,PITCH 0.5 MM)
32
25
1
24
8
17
9
16
25
32
24
1
17
8
16
9
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
9
ORDERING INFORMATION
I15D00 YYI
Lead-Free Package Type
Y: QFN-32
Y: Green (RoHS Compliant)
I: Industrial -40 C to 85C
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
10
REVISION HISTORY
Version
Date
Description
0.23
Aug 3, 2009
Initially released as the Preliminary Datasheet.
0.26
Aug 17, 2009
Update application diagram.
0.27
Sep 28, 2009
Update the list of supported Flash Memory.
0.29
Nov 18, 2009
Update:
Block Diagram.
Electrical Characteristics.
0.34
Dec 7, 2009
Add QFN-32 Package.
0.35
Feb 8, 2010
Update block diagram.
0.40
July 1, 2010
Update crystal configuration.
0.50
Aug 12, 2010
Update PWM spec.
0.60
Mar 31, 2011
Class-AB output delivers 0.7-watt at 4.5V.
0.63
Apr 13, 2011
Update package information.
0.64
Aug 09,2011
AEC_Q100 standard.
1.0
Aug 23, 2013
Add internal oscillator characteristics.
1.1
Jun 13, 2014
Update current consumption characteristic data
1.2
Aug 3, 2016
Add Absolute Maximum Ratings. Add Talarm temperature
threshold typical value.
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Publication Release Date: Aug 5, 2016
Revision 1.2
ISD15D00 DATASHEET
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment
intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or
sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could
result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Nuvoton for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no
representation or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.
No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this
publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability
whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or
infringement of any Intellectual property.
The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any
express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual
property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for
loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this
documents, even if Nuvoton has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only
and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in
the Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD ® ChipCorder®
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information in
this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is
subject to change without notice.
Copyright© 2005, Nuvoton Technology Corporation. All rights reserved. ChipCorder ® and ISD® are trademarks of
Nuvoton Technology Corporation. All other trademarks are properties of their respective owners.
Headquarters
Nuvoton Technology Corporation America
Nuvoton Technology (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.Nuvoton.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441797
http://www.Nuvoton-usa.com/
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62356998
Taipei Office
Nuvoton Technology Corporation Japan
Nuvoton Technology (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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Publication Release Date: Aug 5, 2016
Revision 1.2
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