ISD15100
ISD ChipCorder®
ISD15100 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of Audio Product Line based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Jun 15, 2021
Page 1 of 21
Rev 1.6
ISD15100
TABLE OF CONTENTS
1
GENERAL DESCRIPTION .............................................................................................................. 3
2
FEATURES ...................................................................................................................................... 3
3
BLOCK DIAGRAM ........................................................................................................................... 5
4
PINOUT CONFIGURATION ............................................................................................................ 7
5
PIN DESCRIPTION .......................................................................................................................... 8
6
ELECTRICAL CHARACTERISTICS .............................................................................................. 11
6.1
ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 11
6.2
OPERATING CONDITIONS ........................................................................................................................ 11
6.3
DC PARAMETERS ................................................................................................................................... 12
6.4
AC PARAMETERS ................................................................................................................................... 12
6.4.1
Internal Oscillator ......................................................................................................................... 12
6.4.2
Inputs ............................................................................................................................................. 12
6.4.3
Outputs ........................................................................................................................................... 13
6.4.4
SPI Timing ..................................................................................................................................... 15
6.4.5
I2S Timing ...................................................................................................................................... 16
7
APPLICATION DIAGRAM .............................................................................................................. 17
8
PACKAGE SPECIFICATION ......................................................................................................... 18
8.1
9
10
48 LEAD LQFP(7X7X1.4MM FOOTPRINT 2.0MM).................................................................................... 18
ORDERING INFORMATION .......................................................................................................... 19
REVISION HISTORY.................................................................................................................. 20
IMPORTANT NOTICE........................................................................................................................... 21
Jun 15, 2021
Page 2 of 21
Rev 1.6
ISD15100
1
GENERAL DESCRIPTION
The ISD15100 series is a multi-message ChipCorder® featuring digital compression, comprehensive
memory management, flash storage, and integrated analog/digital audio signal paths. The message
management feature is designed to make message recording simple and address-free as well as make
code development easier for playback-only applications. This family utilizes flash memory to provide
non-volatile audio record/playback with durations up to 8 minutes for a single-chip solution. Unlike other
ChipCorder series, the ISD15100 series provides an I2S digital audio interface, faster digital recording,
higher sampling frequency, and a signal path with SNR equivalent to 12bit resolution.
The ISD15100 series can take digital audio data via I2S or SPI interface. When I2S input is selected, it
will replace the analog audio inputs and will support sample rates of 32, 44.1 or 48 kHz depending upon
clock configuration. When SPI interface is chosen, the sample rate of the audio data sent must be one
of the ISD15100 supported sample rates.
The ISD15100 series has built-in analog audio inputs, analog audio line driver, and speaker driver
output. The two analog audio inputs to the device are: (1) AUXIN has a fixed gain configured by SPI
command, and (2) ANAIN/ANAOUT has a fixed gain amplifier with the gain set by two external resistors.
ANAIN/ANAOUT can also be used as a microphone differential input (ANAIN/ANAOUT becomes
MIC+/MIC-) in conjunction with an automatic gain control (AGC) circuit configured by SPI command.
Analog outputs are available in three forms: (1) AUXOUT is a single-ended voltage output; (2) AUDOUT
can be configured as either a single-ended voltage output or a single-ended current output; (3) BTL
(bridge-tied-load) is a differential voltage output.
2
•
•
•
•
•
FEATURES
Fast Digital Programming
o Programming rate can go up to 1Mbits/second mainly limited by the flash memory write rate.
Duration
o 2 to 8 minutes based on 8kHz/4bit ADPCM
Message Management
o Perform address-free recording: The ISD15100 allocates memory for new recording requests
and upon completion, returns a start address to the host via SPI interface
o Store pre-recorded audio (Voice Prompts) using high quality digital compression
o Use a simple index based command for playback
o Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration
of the device and play back Voice Prompts sequences and message recordings.
Sample Rate
o Seven record and playback sampling frequencies are available for a given master sample
rate. For example, the record and playback sampling frequencies of 4, 5.3, 6.4, 8, 12.8, 16
and 32kHz* are available when the device is clocked at a 32kHz master sample rate.
o For I2S operation, 32, 44.1 and 48kHz master sample rates are available with record and
playback sampling frequencies scaling accordingly.
Compression Algorithms
o For recording
ADPCM: 2, 3, 4 or 5 bits per sample
µ-Law: 6, 7 or 8 bits per sample
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample. Each sampled value is stored as a code, offering no
compression but preserving maximum resolution
o For Pre-Recorded Voice Prompts
µ-Law: 6, 7 or 8 bits per sample
Differential µ-Law: 6, 7 or 8 bits per sample
PCM: 8, 10 or 12 bits per sample
Enhanced ADPCM: 2, 3, 4 or 5 bits per sample
Variable-bit-rate optimized compression. This allows best possible compression given a
Jun 15, 2021
Page 3 of 21
Rev 1.6
ISD15100
•
•
•
•
•
•
•
•
•
metric of SNR and background noise levels.
Oscillator
o Internal oscillator with internal reference: 2.048 MHz with ±10% deviation
o Internal oscillator with external resistor: 2.048 MHz with ±5% deviation when Rosc is 80k-ohm
o External crystal or clock input
o I2S bit clock input
o Crystals and resonators support standard audio sampling rates of 2.048, 4.096, 8.192, 12.288
and11.2896MHz
Inputs
o AUXIN: Analog input with 2-bit gain control configured by SPI command
o ANAIN/ANAOUT:
Analog input with the gain set by two external resistors from ANAOUT to ANAIN, or
Microphone differential input (ANAIN/ANAOUT becomes MIC+/MIC-)
o Digital AGC:
Automatic gain control of digitized data from the analog input
Outputs
o PWM: Class D speaker driver which can deliver typical output power:
8Ω load: 350mW @3.3v, 420mW @3.6v 8Ω load.
4Ω load: 520mW @3.3v, 620mW @3.6v 8Ω load.
o AUDOUT: configurable as a current or voltage single-ended line driver
o AUXOUT: a single-ended voltage output
o BTL: differential voltage output which can deliver typical output power:
63mW for 8Ω load, 115mW for 4Ω load.
I/Os
o SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data
o I2S interface: I2S_CLK, I2S_WS, I2S_SDI, I2S_SDO for digital audio data
o 8 GPIO pins (4 of the 8 GPIO pins share with I2S).
Three 8-bit Volume Control set by SPI command for flexible mixing
o VOLA: volume control for the digital audio data from I2S or analog inputs
o VOLB: volume control for the digital audio data from decompression block or SPI
o VOLC: master volume control for PWM, AUDOUT, AUXOUT and I2S outputs
Operating Voltage: 2.7-3.6V
Standby Current: 1uA typical
Package: Green 48L-LQFP
Temperature Options:
o Industrial: -40°C to 85°C
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Rev 1.6
ISD15100
3
BLOCK DIAGRAM
Figure 3-1 ISD15100 Block Diagram, ANAIN Selected
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Rev 1.6
ISD15100
Figure 3-2 ISD15100 Block Diagram, MICIN Selected
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Rev 1.6
ISD15100
PINOUT CONFIGURATION
NC
AUXIN
ANAIN/MIC+
ANAOUT/MICVSSA
VCCA
AUXOUT
AUDOUT
NC
NC
GPIO0
NC
4
48 47 46 45 44 43 42 41 40 39 38 37
36
35
2
3
34
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
1
ISD15100
XTALIN
XTALOUT
VCCD
VCCD
GPIO1
GPIO2
GPIO3
NC
NC
RESET
RDY/BSYB
INTB
NC
NC
NC
VSSD_PWM
SPKVCCD_PWM
VCCD_PWM
SPK+
MISO
25
12
13 14 15 16 17 18 19 20 21 22 23 24
SCLK
SSB
MOSI
NC
NC
NC
2
I S_SDI/GPIO7
I2S_SCK/GPIO6
I2S_WS/GPIO5
2
I S_SDO/GPIO4
VCCD
VSSD
VSSD
VCCD
VREG
Figure 4-1 ISD15100 48-Lead LQFP Pin Configuration.
Jun 15, 2021
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Rev 1.6
ISD15100
5
PIN DESCRIPTION
Pin
Number
Pin Name
I/O
Function
1
NC
This pin should be left unconnected.
2
NC
This pin should be left unconnected.
3
NC
This pin should be left unconnected.
4
I2S_SDI/
I
Serial Data Input of the I2S interface (If I2S is not used, this pin should
be grounded).
Or, can be configured as a GPIO pin.
GPIO7
5
I2S_SCK/
GPIO6
I/O
Clock input in slave mode or clock output in master mode. This pin can
be configured as an external clock buffer if I2S is not used (If I2S is not
used, this pin should be grounded).
Or, can be configured as a GPIO pin.
6
I2S_WS/
GPIO5
I/O
Word Select (WS) input in slave mode or WS output in master mode (If
I2S is not used, this pin should be grounded).
Or, can be configured as a GPIO pin.
7
I2S_SDO/
GPIO4
O
Serial Data Output of the I2S Interface (If I2S is not used, this pin
should be left unconnected).
Or, can be configured as a GPIO pin.
8
VCCD
I
Digital power supply.
9
VSSD
I
Digital Ground.
10
VSSD
I
Digital Ground.
11
VCCD
I
Digital power supply.
12
VREG
O
A 1.8V regulator to supply the internal logic. A 0.1uF capacitor should
be connected to this pin for supply decoupling and stability.
13
MISO
O
Master-In-Slave-Out. Serial output from the ISD15100 to the host. This
pin is in tri-state when SSB=1.
14
SCLK
I
Serial Clock input to the ISD15100 from the host.
15
SSB
I
Slave Select input to the ISD15100 from the host. When SSB is low
device is selected and responds to commands on the SPI interface.
16
MOSI
I
Master-Out-Slave-In. Serial input to the ISD15100 from the host.
17
VCCD_PWM
I
Digital Power for the PWM Driver.
18
SPK+
O
PWM driver positive output. This SPK+ output, together with SPK- pin,
provide a differential output to drive 8Ω speaker. During power down
this pin is in tri-state.
Or, can be configured as BTL which, together with SPK- pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
19
VSSD_PWM
I
Digital Ground for the PWM Driver.
20
SPK-
O
PWM driver negative output. This SPK- output, together with SPK+
pin, provides a differential output to drive 8Ω speake. During power
down this pin is tri-state.
Jun 15, 2021
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Rev 1.6
ISD15100
Pin
Number
Pin Name
I/O
Function
Or, can be configured as BTL which, together with SPK+ pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
21
VCCD_PWM
22
NC
This pin should be left unconnected.
23
NC
This pin should be left unconnected.
24
NC
This pin should be left unconnected.
25
INTB
O
Active low interrupt request pin. This pin is an open-drain output.
26
RDY/BSYB
O
An output pin to report the status of data transfer on the SPI interface.
“High” indicates that ISD15100 is ready to accept new SPI commands
or data.
27
RESET
I
Applying power to this pin will reset the chip. (A high pulse of 50ms or
more will reset the chip.)
28
NC
This pin should be left unconnected.
29
NC
This pin should be left unconnected.
30
GPIO3
I/O
GPIO
31
GPIO2
I/O
GPIO
32
GPIO1
I/O
GPIO
33
VCCD
I
Digital power supply pin.
34
VCCD
I
Digital power supply pin.
35
XTALOUT
O
Crystal interface output pin.
36
XTALIN
I
The CLK_CFG register determines one of the following three
configurations: (1) A crystal or resonator connected between the
XTALOUT and XTALIN pins. (2) A resistor connected to GND as a
reference current to the internal oscillator and left the XTALOUT
unconnected. (3) An external clock input to the device and left the
XTALOUT unconnected.
37
NC
38
GPIO0
39
NC
This pin should be left unconnected.
40
NC
This pin should be left unconnected.
41
AUDOUT
O
Audio Out. This pin can be either a voltage output or a current output
configured by the internal registers via SPI command.
If AUDOUT is not used, this pin should be left unconnected.
42
AUXOUT
O
Aux Out. This pin is an analog voltage output.
If AUXOUT is not used, this pin should be left unconnected.
43
VCCA
I
Analog power supply pin.
44
VSSA
I
Analog ground pin.
45
ANAOUT/
O
Variable gain analog output with the gain set by feedback resistance to
Jun 15, 2021
I
Digital Power for the PWM Driver.
This pin should be left unconnected.
I/O
GPIO
Page 9 of 21
Rev 1.6
ISD15100
Pin
Number
Pin Name
I/O
MIC-
Function
ANAIN.
Or, can be configured as MIC- which, together with MIC+, provides a
microphone differential input.
If ANAIN/ANAOUT is not used, this pin should be left unconnected.
46
ANAIN/
MIC+
I
Variable gain analog input.
Or, can be configured as MIC+ which, together with MIC-, provides a
microphone differential input.
If ANAIN/ANAOUT is not used, this pin should be left unconnected.
47
AUXIN
I
Auxiliary input with the gain set by SPI command
If AUXIN is not used, this pin should be left unconnected.
48
NC
Jun 15, 2021
This pin should be left unconnected.
Page 10 of 21
Rev 1.6
ISD15100
6
ELECTRICAL CHARACTERISTICS
6.1
ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) [1]
CONDITIONS
VALUES
Junction temperature
Storage temperature range
Voltage Applied to any pins
Voltage applied to any pin (Input current limited to +/-20 mA)
Power supply voltage to ground potential
[1]
6.2
1300C
-650C to +1500C
(VSS - 0.3V) to (VCC + 0.3V)
(VSS – 1.0V) to (VCC + 1.0V)
-0.3V to +5.0V
Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
OPERATING CONDITIONS
OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS)
CONDITIONS
VALUES
Operating temperature range (Case temperature)
-40°C to +85°C
Supply voltage (VDD) [1]
+2.7V to +3.6V
Ground voltage (VSS) [2]
0V
Input voltage (VDD)
[1]
0V to 3.6V
Voltage applied to any pins
NOTES:
Jun 15, 2021
(VSS –0.3V) to (VDD +0.3V)
[1] V
DD
= VCCA = VCCD = VCCPWM
[2] V
SS
= VSSA = VSSD = VSSPWM
Page 11 of 21
Rev 1.6
ISD15100
6.3
DC PARAMETERS
TYP [1]
PARAMETER
SYMBOL
Supply Voltage
VDD
2.7
3.6
V
Input Low Voltage
VIL
VSS-0.3
0.3xVDD
V
Input High Voltage
VIH
0.7xVDD
VDD
V
Output Low Voltage
VOL
VSS-0.3
0.3xVDD
V
IOL = 1mA
Output High Voltage
VOH
0.7xVDD
VDD
V
IOH = -1mA
INTB Output Low Voltage
VOH1
0.4
V
IDD_Record
40
mA
Playback Current
IDD_Playback
30
mA
Standby Current
ISB
10
µA
VDD= 3.6V
Input Leakage Current
IIL
±1
µA
Force VDD
Record Current
Notes:
[1] Conditions
6.4
AC PARAMETERS
6.4.1
Internal Oscillator
MIN
MAX
1
UNITS
CONDITIONS
VDD= 3.6V, No load,
Sampling freq = 16 kHz
VDD=3V, TA=25°C unless otherwise stated
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Internal Oscillator with internal
reference
FINT
-10%
2.048
MHz
+10
%
MHz
Vdd = 3V.
At room temperature
FExt
-5%
2.048
MHz
+5%
MHz
With 1% precision
resistor, 80k-ohm.
Vdd = 3V.
At room temperature
Internal Oscillator with external
resistor [1]
Notes:
[1] Characterization data shows that frequency deviation is +/- 5% across temperature and voltage
ranges.
6.4.2 Inputs
ANAIN & MICIN
PARAMETER
SYMBOL
ANAIN Input Voltage
VANAIN
ANAIN Feed Back Resistance
RANA(FB)
MICIN Input Voltage
VMICIN
Notes:
TYP [1]
MAX
10-1000
40
100
5-500
UNITS
CONDITIONS
mV
Peak-to-Peak[2]
KΩ
mV
Peak-to-Peak[2]
[1] Conditions
[2] Depends
Jun 15, 2021
MIN
VDD=3V, TAB=25°C unless otherwise stated
on Gain Setting
Page 12 of 21
Rev 1.6
ISD15100
AUXIN
PARAMETER
SYMBOL
AUXIN Input Voltage
VAUXIN
Gain from AUXIN to
AUXOUT/ANAOUT
AAUXIN GAIN
AUXIN Gain Accuracy
AAUXIN (GA)
MIN
UNITS
CONDITIONS
1000
mV
Peak-to-Peak[2]
0 to 9
dB
4 Gain Steps of 3db
each
-0.5
MAX
+0.5
dB
KΩ
20-40
RAUXIN
AUXIN Input Resistance
TYP[1]
Depending on
AUXIN Gain Setting
[1] Conditions
Notes:
[2] With
VDD=3V, TA=25°C unless otherwise stated.
0db Gain setting.
6.4.3 Outputs
AUXOUT
MIN
TYP[1]
PARAMETER
SYMBOL
MAX
SINAD, AUXIN to AUXOUT
SINADAUXIN_AUXOUT
80
dB
Load 5K[2][3]
SINAD, ANAIN to AUXOUT
SINADANAIN_AUXOUT
80
dB
Load 5K[2][3]
PSRR
PSRRAUXOUT
-40
dB
[4]
DC Bias
VBIAS_AUXOUT
Minimum Load Impedance
RL(AUXOUT)
Maximum Load Capacitance
CL(AUXOUT)
1.2
UNITS
CONDITIONS
V
KΩ
5
0.1
nF
[1] Conditions
Notes:
VDD=3V, TA=25°C unless otherwise stated.
Vpp 1KHz signal applied at AUXIN/ANAIN with 0db Gain setting.
[3] All measurements are C-message weighted.
[4] Measured with 1KHz, 100 mVpp sine wave applied to V
CCA pins.
[2] 1
OUT
PARAMETER
SYMBOL
MIN
TYP[1]
MAX
UNITS
CONDITIONS
AUDOUT[5]
SINADAUXIN_AUDOUT
80
dB
Load 5K[2][3]
SINAD, ANAIN to AUDOUT[5]
SINADANAIN_AUDOUT
80
dB
Load 5K[2][3]
PSRR[5]
PSRRAUDOUT
-40
dB
[4]
SINAD, AUXIN to
DC
Bias[5]
Minimum Load
VBIAS_AUDOUT
Impedance[5]
RL(AUDOUT)
Capacitance[5]
CL(AUDOUT)
Maximum Load
Output Current [6]
Notes:
IAUDOUT
1.2
KΩ
5
0
V
3
0.1
nF
6
mA
[2][6]
[1] Conditions
Vcc=3V, TA=25°C unless otherwise stated.
Vpp 1KHz signal applied at AUXIN/ANAIN with 0db Gain setting.
[3] All measurements are C-message weighted.
[4] Measured with 1Khz, 100 mVpp sine wave applied to V
CCA pins.
[5] Configured as AUDOUT(Voltage Output).
[6] Configured as AUDOUT(Current Output).
[2] 1
Jun 15, 2021
Page 13 of 21
Rev 1.6
ISD15100
SPEAKER OUTPUTS
PARAMETER
SYMBOL
SNR, AUXIN to SPK+/SPK-
SNRAUXIN_SPK
SNR, ANAIN to SPK+/SPK-
SNRANAIN_SPK
Output Power
POUT_SPK VCC=3.0
THD, AUXIN to SPK+/SPK-
THD %
Minimum Load Impedance
RL(SPK)
Notes:
MIN
TYP[1]
MAX
UNITS
CONDITIONS
60
dB
Load 150Ω [2][3]
60
dB
Load 150Ω [2][3]
mW
Load 8Ω [2]
360
Load 8Ω [2]
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