NAU8501YG

NAU8501 24-bit Stereo Audio ADC with Differential Microphone Inputs GENERAL DESCRIPTION The NAU8501 is a low power, high quality audio input system for portable applications. In addition to precision 24-bit stereo ADCs, this device integrates a broad range of additional functions to simplify implementation of complete audio systems. The NAU8501 includes low-noise stereo differential high gain microphone inputs with wide range programmable amplifiers, separate line inputs, and an analog bypass/side tone line level stereo output. Advanced on-chip digital signal processing includes a limiter/ALC (Automatic Level Control), 5-band equalizer, notch filter, and a high-pass filter for speech optimization and wind noise reduction. The digital interface can operate as either a master or a slave. Additionally, an internal Fractional-N PLL is available to accurately generate any audio sample rate clock for the ADCs derived using any available system clock from 8MHz through 33MHz. The NAU8501 operates with analog supply voltages from 2.5V to 3.6V, while the digital core can operate as low as 1.7V to conserve power. Internal control registers enable flexible power conserving modes, shutting down or reducing power in sub-sections of the chip under software control. The NAU8501 is specified for operation from -40°C to +85°C. AEC-Q100 & TS16949 compliant device is available upon request. FEATURES        ADC: 90dB SNR and -80dB THD (“A” weighted) Stereo differential input microphone amplifiers Very wide range programmable input amplifier Stereo line inputs with gain options and mixing Stereo line outputs with gain control and mute On-chip high resolution Fractional-N PLL Integrated DSP with specific functions: • 5-band equalizer • High pass filter / wind noise reduction • Automatic level control / limiter • Programmable notch filter NAU8501 Datasheet Rev 1.9     Serial control interfaces with read/write capability Standard audio interfaces: PCM and I2S Supports any sample rate from 8kHz to 48kHz Read/Write control register interface Applications  Audio Recording Devices  Security Systems  Video and Still Cameras  Enhanced Audio Inputs for SOC products  Audio Input Accessory Products  Gaming Systems Page 1 of 80 Jul, 2018 MICBIAS VDDA LLINOUT RLINOUT VSSA VREF VDDA2 n/c 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 Pinout LMICP 1 24 24 VSSA2 LMICN 2 23 23 n/c LLIN/GPIO2 3 22 22 n/c RMICP 4 21 21 n/c RMICN 5 20 20 n/c RLIN/GPIO3 6 19 19 n/c FS 7 18 18 MODE BCLK 8 17 17 SDIO 10 11 12 13 14 15 16 n/c MCLK VSSD VDDC VDDB CSB/GPIO1 SCLK ADCOUT 9 NAU8501YG 32-lead QFN RoHS Part Number Dimension Package Package Material NAU8501YG 5 x 5 mm 32-QFN Pb-Free NAU8501 Datasheet Rev 1.9 Page 2 of 80 Jul, 2018 Pin Descriptions Pin # Name Type 1 2 3 LMICP LMICN LLIN/GPIO2 4 5 6 RMICP RMICN RLIN/GPIO3 Analog Input Analog Input Analog Input / Digital I/O Analog Input Analog Input Analog Input / Digital I/O 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FS BCLK ADCOUT n/c MCLK VSSD VDDC VDDB CSB/GPIO1 SCLK SDIO MODE n/c n/c n/c n/c n/c VSSA2 n/c VDDA2 VREF VSSA RLINOUT LLINOUT VDDA MICBIAS Digital I/O Digital I/O Digital Output Digital Input Supply Supply Supply Digital I/O Digital Input Digital I/O Digital Input Supply Supply Reference Supply Analog Output Analog Output Supply Analog Output Functionality Left MICP Input (common mode) Left MICN Input Left Line Input / alternate Left MICP Input / GPIO2 Right MICP Input (common mode) Right MICN Input Right Line Input/ alternate Right MICP Input / Digital Output In 4-wire mode: Must be used for GPIO3 Digital Audio DAC and ADC Frame Sync Digital Audio Bit Clock Digital Audio ADC Data Output Not internally connected Master Clock Input Digital Ground Digital Core Supply Digital Buffer (Input/Output) Supply 3-Wire MPU Chip Select or General Purpose I/O 3-Wire MPU Clock Input / 2-Wire MPU Clock Input 3-Wire MPU Data Input / 2-Wire MPU Data I/O Control Interface Mode Selection Pin Not internally connected Not internally connected Not internally connected Not internally connected Not internally connected Secondary analog ground connection for minimum noise Not internally connected Secondary analog power connection for minimum noise Decoupling for Midrail Reference Voltage Analog Ground Right Line Level Output Left Line Level Output Analog Power Supply Programmable Low Noise Supply for Microphone Biasing Notes 1. The 32-QFN package includes a bulk ground connection pad on the underside of the chip. This bulk ground should be thermally tied to the PCB as much as possible, and electrically tied to the analog ground (VSSA, pin 28). 2. Unused analog input pins should be left as no-connection. 3. Unused digital input pins should be tied to ground. 4. Pins designated as NC (Not Internally Connected) should be left as no-connection NAU8501 Datasheet Rev 1.9 Page 3 of 80 Jul, 2018 Block Diagram VDDB 14 VDDC VSSD 13 12 VDDA 31 VSSA 28 VDDA2 26 VSSA2 24 Bypass Buffer LADC MIX/BOOST 2 - LMICN 1 LLINOUT 30 S + LMICP Bypass Mute Output paths support -57dB through +6dB gain in 1dB steps, with each path having an independent mute and output disable LADC 3 LLIN HPF ALC ALC Control 5 4 + RMICP RLIN Notch Filter - RMICN 6 S R Outputs are line-level, able to drive 1Vrms into 1k-ohms 5 Band EQ 3D RADC MIX/BOOST VDDA 27 RADC VREF R 32 MICBIAS Bypass Buffer MICROPHONE BIAS AUDIO INTERFACE (PCM/IIS) PLL 8 BCLK 7 9 FS ADCOUT NAU8501 CONTROL INTERFACE (2-, 3- and 4-wire) 11 16 17 MCLK SCLK SDIO 15 Bypass Mute 18 CSB/ MODE GPIO1 Figure 1: NAU8501 Block Diagram NAU8501 Datasheet Rev 1.9 Page 4 of 80 Jul, 2018 29 RLINOUT Electrical Characteristics Conditions: VDDC = 1.8V, VDDA = VDDB = VDDA2 = 3.3V, MCLK = 12.288MHz, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, 64X oversampling rate, unless otherwise stated. Parameter Analog to Digital Converter (ADC) Full scale input signal 1 Symbol Comments/Conditions Min Typ Max PGABST = 0dB 1.0 PGAGAIN = 0dB 0 Signal-to-noise ratio SNR Gain = 0dB, A-weighted tbd 90 Total harmonic distortion 2 THD+N Input = -3dB FS input -80 tbd Channel separation 1kHz input signal 103 Microphone Inputs (LMICP, LMICN, RMICP, RMICN, LLIN, RLIN) and Programmable Gain Amplifier (PGA) Full scale input signal 1 PGABST = 0dB 1.0 PGAGAIN = 0dB 0 Programmable gain -12 35.25 Programmable gain step size Guaranteed Monotonic 0.75 Mute Attenuation 120 Input resistance Inverting Input PGA Gain = 35.25dB 1.6 PGA Gain = 0dB 47 PGA Gain = -12dB 75 Non-inverting Input 94 Line Inputs Line Path Gain = +6dB 20 Line In Gain = 0dB 40 Line In Gain = -12dB 159 Input capacitance 10 PGA equivalent input noise 0 to 20kHz, Gain set to 120 35.25dB Input Boost Mixer Gain boost Boost disabled 0 Boost enabled 20 Line Input to boost/mixer gain -12 6 Line Input step size to boost/mixer 3 Microphone Bias Bias voltage VMICBIAS See Figure 3 0.50, 0.60,0.65, 0.70, 0.75, 0.85, or 0.90 Bias current source IMICBIAS 3 Output noise voltage Vn 1kHz to 20kHz 14 NAU8501 Datasheet Rev 1.9 VINFS Page 5 of 80 Jul, 2018 Units Vrms dBV dB dB dB Vrms dBV dB dB dB kΩ kΩ kΩ kΩ kΩ kΩ kΩ pF µV dB dB dB dB VDDA VDDA mA nV/√Hz Electrical Characteristics, cont’d. Conditions: VDDC = 1.8V, VDDA = VDDB = VDDA2 = 3.3V, MCLK = 12.288MHz, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data, 64X oversampling rate, unless otherwise stated. Parameter Symbol Comments/Conditions Min Typ Line Output (RLINOUT and LLINOUT with 1k-Ω load) 0dB full scale output voltage Signal-to-noise ratio SNR A-weighted Total harmonic distortion 2 THD+N VDDA = 3.3V Channel separation Power supply rejection ratio PSRR (50Hz – 22kHz) Automatic Level Control (ALC) and Limiter Target record level Programmable gain Gain hold time 3 tHOLD Gain ramp-up (decay) 3 Gain ramp-down (attack) 3 tDCY tATK Mute Attenuation Digital Input/Output Input HIGH level VIL Input LOW level VIH Output HIGH level VOH ILoad = 1mA Output LOW level VOL ILoad = -1mA Notes 1. 2. 3. Vrms dB dB 99 53 dB dB -22.5 -1.5 -12 35.25 0 / 2.67 / 5.33 / … / 43691 dBFS dB ms 4 / 8 / 16 / … / 4096 ms 1 / 2 / 4 / … / 1024 ms 1 / 2 / 4 / … / 1024 ms 0.25 / 0.5 / 1 / … / 128 ms 120 dB 0.7 * VDDB V 0.3 * VDDB Input capacitance Units VDDA / 3.3 92 85 1kHz signal Doubles every gain step, with 16 steps total ALC Mode ALC = 0 Limiter Mode ALC = 1 ALC Mode ALC = 0 Limiter Mode ALC = 1 Max 0.9 * VDDB V V 0.1 * VDDB 10 V pF Full Scale is relative to the magnitude of VDDA and can be calculated as FS = VDDA/3.3. Distortion is measured in the standard way as the combined quantity of distortion products plus noise. The signal level for distortion measurements is at 3dB below full scale, unless otherwise noted. Time values scale proportionally with MCLK. Complete descriptions and definitions for these values are contained in the detailed descriptions of the ALC functionality. NAU8501 Datasheet Rev 1.9 Page 6 of 80 Jul, 2018 Absolute Maximum Ratings Condition Min Max Units -0.3 +3.61 V Core Digital Input Voltage range VSSD – 0.3 VDDC + 0.30 V Buffer Digital Input Voltage range VSSD – 0.3 VDDB + 0.30 V Analog Input Voltage range VSSA – 0.3 VDDA + 0.30 V Industrial operating temperature -40 +85 °C Storage temperature range -65 +150 °C VDDB, VDDC, VDDA, VDDA2 supply voltages CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. Operating Conditions Condition Symbol Min Digital supply range (Core) VDDC Digital supply range (Buffer) Analog supply range Ground Max Units 1.65 3.60 V VDDB 1.65 3.60 V VDDA, VDDA2 2.50 3.60 V VSSD VSSA VSSA2 Typical 0 V 1. VDDA must be ≥ VDDB. 2. VDDB must be ≥ VDDC. NAU8501 Datasheet Rev 1.9 Page 7 of 80 Jul, 2018 Table of Contents 1 2 3 GENERAL DESCRIPTION ............................................................................................................................. 10 POWER SUPPLY............................................................................................................................................. 12 INPUT PATH DETAILED DESCRIPTIONS.................................................................................................. 13 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 4 Differential microphone input (MICN & MICP pins) .................................................................................... 13 Programmable Gain Amplifier (PGA) ......................................................................................................... 13 Positive Microphone Input (MICP) .............................................................................................................. 14 Negative Microphone Input (MICN) ............................................................................................................ 15 Microphone biasing .................................................................................................................................... 16 Line Input Impedance and Variable Gain Stage Topology ......................................................................... 16 Left and Right Line Inputs (LLIN and RLIN) ............................................................................................... 18 ADC Mix/Boost Stage................................................................................................................................. 19 Input Limiter / Automatic Level Control (ALC) ............................................................................................ 19 ALC Peak Limiter Function......................................................................................................................... 21 Noise Gate (Normal Mode Only) ................................................................................................................ 22 ALC Example with ALC Min/Max Limits and Noise Gate Operation........................................................... 23 Limiter Mode .............................................................................................................................................. 24 ADC DIGITAL BLOCK .................................................................................................................................. 25 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 5 Sampling / Oversampling Rate, Polarity Control, Digital Passthrough ....................................................... 25 ADC Digital Volume Control and Update Bit Functionality ......................................................................... 26 ADC Programmable High Pass Filter ......................................................................................................... 26 Programmable Notch Filter ........................................................................................................................ 27 5-Band Equalizer ........................................................................................................................................ 28 3D Stereo Enhancement ............................................................................................................................ 29 Companding ............................................................................................................................................... 30 µ-law .......................................................................................................................................................... 30 A-law .......................................................................................................................................................... 30 8-bit Word Length ....................................................................................................................................... 30 ANALOG OUTPUTS....................................................................................................................................... 31 5.1 6 Line Level Outputs (LLINOUT and RLINOUT) ........................................................................................... 31 MISCELLANEOUS FUNCTIONS .................................................................................................................. 32 6.1 6.2 6.3 7 Slow Timer Clock ....................................................................................................................................... 32 General Purpose Inputs and Outputs (GPIO1, GPIO2, GPIO3) and Jack Detection ................................. 33 Automated Features Linked to Jack Detection ........................................................................................... 33 CLOCK SELECTION AND GENERATION .................................................................................................. 34 7.1 7.2 8 Phase Locked Loop (PLL) General Description ......................................................................................... 35 CSB/GPIO1 as PLL output ......................................................................................................................... 36 CONTROL INTERFACES .............................................................................................................................. 37 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Selection of Control Mode .......................................................................................................................... 37 2-Wire-Serial Control Mode (I2C Style Interface) ........................................................................................ 37 2-Wire Protocol Convention ....................................................................................................................... 38 2-Wire Write Operation............................................................................................................................... 39 2-Wire Read Operation .............................................................................................................................. 40 SPI Control Interface Modes ...................................................................................................................... 41 SPI 3-Wire Write Operation ........................................................................................................................ 41 SPI 4-Wire 24-bit Write and 32-bit Read Operation................................................................................... 41 NAU8501 Datasheet Rev 1.9 Page 8 of 80 Jul, 2018 8.9 8.10 8.11 9 PRODUCT FAMILY DIGITAL AUDIO INTERFACES ................................................................................ 44 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 10 Right-Justified Audio Data .......................................................................................................................... 44 Left-Justified Audio Data ............................................................................................................................ 45 I2S Audio Data ............................................................................................................................................ 45 PCM A Audio Data ..................................................................................................................................... 46 PCM B Audio Data ..................................................................................................................................... 46 PCM Time Slot Audio Data ........................................................................................................................ 47 Control Interface Timing ............................................................................................................................. 48 Audio Interface Timing: .............................................................................................................................. 50 APPLICATION INFORMATION ................................................................................................................... 51 10.1 10.2 10.3 10.4 11 12 SPI 4-Wire Write Operation ...................................................................................................................... 42 SPI 4-Wire Read Operation........................................................................................................................ 43 Software Reset........................................................................................................................................... 43 Typical Application Schematic .................................................................................................................... 51 Recommended power up and power down sequences .............................................................................. 52 Power Consumption ................................................................................................................................... 55 Supply Currents of Specific Blocks............................................................................................................. 56 APPENDIX A: DIGITAL FILTER CHARACTERISTICS ............................................................................ 57 APPENDIX B: COMPANDING TABLES ..................................................................................................... 62 12.1 12.2 µ-Law / A-Law Codes for Zero and Full Scale ............................................................................................ 62 µ-Law / A-Law Output Codes (Digital mW)................................................................................................. 62 13 APPENDIX C: DETAILS OF REGISTER OPERATION .............................................................................. 63 14 APPENDIX D: REGISTER OVERVIEW....................................................................................................... 76 15 PACKAGE DIMENSIONS .............................................................................................................................. 77 16 ORDERING INFORMATION ......................................................................................................................... 78 IMPORTANT NOTICE ............................................................................................................................................ 80 NAU8501 Datasheet Rev 1.9 Page 9 of 80 Jul, 2018 1 General Description The NAU8501 is a stereo device with identical left and right channel differential microphone inputs, and also, line level inputs that share common support elements. Additionally, two-line level outputs are included that enable monitoring of the analog signals present at the ADC inputs. A powerful set of integrated programmable signal processing features are included. 1.1.1 Analog Inputs All inputs include individual muting functions with excellent channel isolation and off-isolation from all outputs. All inputs are suitable for full quality, high bandwidth signals. Each of the left-right stereo channels includes a low noise programmable differential PGA amplifier. This may be used for a microphone level through line level source signals. Gain may be set from +35.25db through -12dB at the analog difference-amplifier type programmable amplifier input stage. A separate additional 20dB analog gain is available on this input path, between the PGA output and ADC mixer input. The output of the ADC mixer may be routed to the ADC and/or analog bypass to the analog line level output section. Each channel also has a line level input. This input may be routed to the input PGA non-inverting input, and/or mixed directly to the ADC input mixer. The mixing path into the ADC input mixer includes programmable gain from -12dB through +6dB in 3dB steps. 1.1.2 Analog Outputs There are two-line level analog audio outputs. These outputs are useful for providing “side tone” in telephony applications, or more generally to monitor the analog input signal that is available at the input of the ADCs. Each output has an independently programmable gain function, output mute function, and output disable function. The gain can be programmed from -57dB through +6dB in 1dB steps. A programmable low-noise MICBIAS microphone bias supply output is included. The VREF pin voltage reference is buffered and then scaled to provide a wide range of possible low-noise microphone bias DC voltages. This microphone bias supply is suitable for both conventional electret (ECM) type microphones, and to power the newer MEMS all-silicon type microphones. A small internal series resistance is optionally programmable at the output of the device. This greatly increases the effectiveness of the external output filter capacitor in reducing high frequency noise on the microphone bias output, and is a unique feature not present in most audio codec products. NAU8501 Datasheet Rev 1.9 Page 10 of 80 Jul, 2018 1.1.3 ADC Function and Digital Signal Processing Each left and right channel has an independent high quality ADC associated with it. These are high performance, 24-bit delta-sigma converters that are suitable for a very wide range of applications. Each ADC is supported by an analog input mixer to select/mix the inputs available to that ADC. The output of the ADC is supported by an advanced digital signal processing subsystem (DSP) that enables a very wide range of programmable signal conditioning and signal optimizing functions. All digital processing is with 24-bit precision, as to minimize processing artifacts and maximize the audio dynamic range supported by the NAU8501. The available DSP features include a wide range, mixed-mode Automatic Level Control (ALC), a high pass filter, a notch filter, scaling in decibels, and a digital mute function. All of these features are optional and highly programmable. The high pass filter function includes a very low frequency DC-blocking feature, or optionally, an application mode feature for low frequency audio noise reduction, such as to reduce unwanted ambient noise or “wind noise” on a microphone input. The notch filter may be programmed over a very wide frequency range and notch depth to greatly reduce a specific frequency band or frequency. Typically, this is used to reject a certain frequency such as a 50Hz, 60Hz, or 217Hz unwanted noise, but may also be used to eliminate an unwanted housing resonance or noise such as from camera motors. Digital signal processing is also provided for a 3D Audio Enhancement function, and for a 5-Band Equalizer. These features are optional, and are programmable over wide ranges. 1.1.4 Digital Interfaces Command and control of the device is accomplished using a 2-wire/3-wire/4-wire serial control interface. This is a simple, but highly flexible interface that is compatible with many commonly used command and control serial data protocols and host drivers. Digital audio input/output data streams are transferred to and from the device separately from command and control. The digital audio data interface supports either I2S or PCM audio data protocols, and is compatible with commonly used industry standard devices that follow either of these two serial data formats. 1.1.5 Clock Requirements The clocking signals required for the audio signal processing, audio data I/O, and control logic may be provided externally, or by optional operation of a built-in PLL (Phase Locked Loop). The PLL is provided as a low cost, zero external component count optional method to generate required clocks in almost any system. The PLL is a fractional-N divider type design, which enables generating accurate desired audio sample rates derived from a very wide range of commonly available system clocks. The frequency of the system clock provided as the PLL reference frequency may be any stable frequency in the range between 8MHz and 33MHz. Because the fractional-N multiplication factor is a very high precision 24-bit value, any desired sample rate supported by the NAU8501 can be generated with very high accuracy, typically limited by the accuracy of the external reference frequency. Reference clocks and sample rates outside of these ranges are also possible, but may involve performance tradeoffs and increased design verification. NAU8501 Datasheet Rev 1.9 Page 11 of 80 Jul, 2018 2 Power Supply This device has been designed to operate reliably using a wide range of power supply conditions and poweron/power-off sequences. There are no special requirements for the sequence or rate at which the various power supply pins change. Any supply can rise or fall at any time without harm to the device. However, pops and clicks may result from some sequences. Optimum handling of hardware and software power-on and power-off sequencing is described in more detail in the Applications section of this document. 2.1.1 Power-On Reset The NAU8501 does not have an external reset pin. The device reset function is automatically generated internally when power supplies are too low for reliable operation. The internal reset is generated any time that either VDDA or VDDC is lower than is required for reliable maintenance of internal logic conditions. The reset threshold voltage for VDDA and VDDC is approximately 0.5Vdc. If both VDDA and VDDC are being reduced at the same time, the threshold voltage may be slightly lower. Note that these are much lower voltages than are required for normal operation of the chip. These values are mentioned here as general guidance as to overall system design. If either VDDA or VDDC is below its respective threshold voltage, an internal reset condition is asserted. During this time, all registers and controls are set to the hardware determined initial conditions. Software access during this time will be ignored, and any expected actions from software activity will be invalid. When both VDDA and VDDC reach a value above their respective thresholds, an internal reset pulse is generated which extends the reset condition for an additional time. The duration of this extended reset time is approximately 50 microseconds, but not longer than 100 microseconds. The reset condition remains asserted during this time. If either VDDA or VDDC at any time becomes lower than its respective threshold voltage, a new reset condition will result. The reset condition will continue until both VDDA and VDDC again higher than their respective thresholds. After VDDA and VDDC are again both greater than their respective threshold voltage, a new reset pulse will be generated, which again will extend the reset condition for not longer than an additional 100 microseconds. 2.1.2 Power Related Software Considerations There is no direct way for software to determine that the device is actively held in a reset condition. If there is a possibility that software could be accessing the device sooner than 100 microseconds after the VDDA and VDDC supplies are valid, the reset condition can be determined indirectly. This is accomplished by writing a value to any register other than register 0x00, with that value being different than the power-on reset initial values. The optimum choice of register for this purpose may be dependent on the system design, and it is recommended the system engineer choose the register and register test bit for this purpose. After writing the value, software will then read back the same register. When the register test bit reads back as the new value, instead of the power-on reset initial value, software can reliably determine that the reset condition has ended. Although it is not required, it is strongly recommended that a Software Reset command should be issued after power-on and after the power-on reset condition is ended. This will help insure reliable operation under every power sequencing condition that could occur. If there is any possibility that VDDA or VDDC could be unreliable during system operation, software may be designed to monitor whether a power-on reset condition has happened. This can be accomplished by writing a test bit to a register that is different from the power-on initial conditions. This test bit should be a bit that is never used for any other reason, and does not affect desired operation in any way. Then, software at any time can read this bit to determine if a power-on reset condition has occurred. If this bit ever reads back other than the test value, then software can reliably know that a power-on reset event has occurred. Software can subsequently re-initialize the device and the system as required by the system design. 2.1.3 Software Reset All chip registers can be reset to power-on default conditions by writing any value to register 0, using any of the control modes. Writing valid data to any other register disables the reset, but all registers need to have the correct operating data written. See the applications section on powering NAU8501 up for information on avoiding pops and clicks after a software reset. NAU8501 Datasheet Rev 1.9 Page 12 of 80 Jul, 2018 3 Input Path Detailed Descriptions The NAU8501 provides multiple inputs to acquire and process audio signals from microphones or other sources with high fidelity and flexibility. There are left and right input paths, each with three input pins, which can be used to capture signals from single-ended, differential or dual-differential microphones. These input channels each include a programmable gain amplifier (PGA). The outputs of the PGAs, plus two additional line level inputs, are then connected to the input boost/mix stages for maximum flexibility handling various signal sources. All inputs are maintained at a DC bias at approximately ½ of the VDDA supply voltage. Connections to these inputs should be AC-coupled by means of DC blocking capacitors suitable for the device application. 3.1 Differential microphone input (MICN & MICP pins) The NAU8501 features a low-noise, high common mode rejection ratio (CMRR), differential microphone input pair, MICP and MICN, which are connected to a PGA gain stage. The differential input structure is essential in noisy digital systems where amplification of low-amplitude analog signals is necessary such as in portable digital media devices and cell phones. Differential inputs very useful to reduce ground noise in systems in which there are ground voltage differences between different chips and other components. When properly implemented, the differential input architecture offers an improved power-supply rejection ratio (PSRR) and higher ground noise immunity. 3.2 Programmable Gain Amplifier (PGA) Each PGA supports three possible inputs, MICP, MICN, and LIN. These are the microphone differential pair and a separate line level input. The PGA has a gain range of -12dB through +35.25dB in evenly spaced decibel increments of 0.75dB. Operation of the PGA is subject to control by the following registers: R2 Power management controls for the left and right PGA R2 Power management controls for ADC Mix/Boost (must be “on” for any PGA path to function) R7 Zero crossing timeout control R32 Automatic Level Control (ALC) for the left and right PGA R44 Input selection options for the left and right PGA R45 Volume (gain), mute, update bit, and zero crossing control for the left PGA R46 Volume (gain), mute, update bit, and zero crossing control for the right PGA Important: The R45 and R46 update bits are write-only bits. The primary intended purpose of the update bit is to enable simultaneous changes to both the left and right PGA volume values, even though these values must be written sequentially. When there is a write operation to either R45 or R46 volume settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. When there is a write operation to either R45 or R46 and the update bit is set (value = 1), then the new value in the register being written is immediately put into effect, and any pending value in the other PGA volume register is put into effect at the same time. Note: If the ALC automatic level control is enabled, the function of the ALC is to automatically adjust the R45 or R46 volume setting. If ALC is enabled for the left or right, or both channels, then software should avoid changing the volume setting for the affected channel or channels. The reason for this is to avoid unexpected volume changes caused by competition between the ALC and the direct software control of the volume setting. Zero-Crossing controls are implemented to suppress clicking sounds that may occur when volume setting changes take place while an audio input signal is active. When the zero crossing function is enabled (logic = 1), any volume change for the affected channel will not take place until the audio input signal passes through the zero point in its peak-to-peak swing. This prevents any instantaneous voltage change to the audio signal caused by volume setting changes. If the zero crossing function is disabled (logic = 0), volume changes take place instantly on condition of the Update Bit, but without regard to the instantaneous voltage level of the affected audio input signal. The R7 zero crossing timeout control is an additional feature to limit the amount of time that a volume change to the PGA is delayed pending a zero crossing event. If the input signal is such that there are no zero crossing events, and the timeout control is enabled (level = 1), any new volume setting to either PGA will automatically be put into effect after between 2.5 and 3.5 periods of the Slow Timer Clock (see description under “Miscellaneous Functions”). NAU8501 Datasheet Rev 1.9 Page 13 of 80 Jul, 2018 3.2.1 Zero Crossing Example This drawing shows in a graphical form the problem and benefits of using the zero crossing feature. There is a major audible improvement as a result of using the zero crossing feature. PGA Output with Zero Cross Enabled PGA Output with Zero Cross Disabled PGA Input Gain Change Figure 2: Zero Crossing Gain Update Operation PGA Gain R45, R46 Input Selection R44 R MICN R MICP To ADC Mix/Boost R VREF -12 dB to +35.25 dB LIN R VREF Figure 3: PGA Input Structure Simplified Schematic 3.3 Positive Microphone Input (MICP) The positive (non-inverting) microphone input (MICP) can be used separately, or as part of a differential input configuration. This input pin connects to the positive (non-inverting) terminal of the PGA amplifier under control of register R44. When the R44 associated control bit is set (logic = 1), a switch connects MICP to the PGA input. When the associated control bit is not set (logic = 0), the MICP pin is connected to a resistor of approximately 30kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC level of the MICP pin close to VREF at all times. Note: If the MICP signal is not used differentially with MICN, the PGA gain values will be valid only if the MICN pin is terminated to a low impedance signal point. This termination should normally be an AC coupled path to signal ground. This input impedance is constant regardless of the gain value. The nominal input impedance for this input is given by the following table. Impedance for specific gain values not listed in this table can be estimated through interpolation between listed values. NAU8501 Datasheet Rev 1.9 Page 14 of 80 Jul, 2018 Nominal Input Impedance LMICP & RMICP to non-inverting PGA input or LLIN & RLIN to non-inverting PGA input Gain (dB) -12 -9 -6 -3 0 3 6 9 12 18 30 35.25 Impedance (kΩ) 94 94 94 94 94 94 94 94 94 94 94 94 Table 1: Microphone and Line Non-Inverting Input Impedances 3.4 Negative Microphone Input (MICN) The negative (inverting) microphone input (MICN) can be used separately, or as part of a differential input configuration. This input pin connects to the negative (inverting) terminal of the PGA amplifier under control of register R44. When the R44 associated control bit is set (logic = 1), a switch connects MICP to the PGA input. When the associated control bit is not set (logic = 0), the MICN pin is connected to a resistor of approximately 30kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC level of the MICN pin close to VREF at all times. It is important for a system designer to know that the MICN input impedance varies as a function of the selected PGA gain. This is normal and expected for a difference amplifier type topology. The nominal resistive impedance values for this input over the possible gain range are given by the following table. Impedance for specific gain values not listed in this table can be estimated through interpolation between listed values. Nominal Input Impedance LMICN or RMICN to inverting PGA input Gain (dB) -12 -9 -6 -3 0 3 6 9 12 18 30 35.25 Impedance (kΩ) 75 69 63 55 47 39 31 25 19 11 2.9 1.6 Table 2: Microphone Inverting Input Impedances System designers should also note that at the highest gain values, the input impedance is relatively low. For most inputs, the best strategy if higher gain values are needed is to use the input PGA in combination with the +20dB gain boost available on the PGA Mix/Boost stage that immediately follows the PGA output. A good guideline is to use the PGA gain for up to around 20dB of gain. If more gain than this is required and the lower input impedance of the PGA at high gains is a problem, a combination of the PGA and boost stage should be used. In this type of NAU8501 Datasheet Rev 1.9 Page 15 of 80 Jul, 2018 combined gain configuration, it is preferred to have at least 6dB gain at the PGA input stage to benefit from the PGA low noise characteristics. 3.5 Microphone biasing The MICBIAS pin provides a low-noise microphone DC bias voltage as may be required for operation of an external microphone. This built-in feature can typically provide up to 3mA of microphone bias current. This DC bias voltage is suitable for powering either traditional ECM (electret) type microphones, or for MEMS types microphones with an independent power supply pin. Seven different bias voltages are available for optimum system performance, depending on the specific application. The microphone bias pin normally requires an external filtering capacitor as shown on the schematic in the Application section. The microphone bias function is controlled by the following registers: R1 Power control for MICBIAS feature (enabled when bit 4 = 1) R40 Optional low-noise mode and different bias voltage levels (enabled when bit 0 = 1) R44 Primary MICBIAS voltage selection The low-noise feature results in greatly reduced noise in the external MICBIAS voltage by placing a resistor of approximately 200-ohms in series with the output pin. This creates a low pass filter in conjunction with the external micbias filter capacitor, but without any additional external components. The low noise feature is enabled when the mode control bit 0 in register R40 is set (level = 1) VREF Register 40, bit 0 MICBIASM Register 1, bit 4 MICBIASEN Register 40, Bit 0 0 01 0 0.65 * VDDA 10 0 0.75 * VDDA 11 0 0.50 * VDDA 00 1 0.85 * VDDA 01 1 0.60 * VDDA 10 1 0.70 * VDDA 11 1 0.50 * VDDA MICBIAS R R Microphone Bias Voltage 0.90 * VDDA Register 44, Bits 7-8 00 Register 44, bits 7-8 MICBIASV Figure 4: Microphone Bias Generator 3.6 Line Input Impedance and Variable Gain Stage Topology Except for the input PGAs, other variable gain stages are implemented similarly to the simplified schematic shown here. The gain value changes affect input impedance in the ranges detailed in the description of each type of input path. If a path is in the “not selected” condition, then the input impedance will be in a high impedance condition. If an external input pin is not used anywhere in the system, it will be coupled to a DC tie-off of approximately 30kΩ coupled to VREF. The unused input/output tie-off function is explained in more detail in the Application Information section of this document. NAU8501 Datasheet Rev 1.9 Page 16 of 80 Jul, 2018 Gain Value Adjustment “Not Selected” Switch R Input R To Next Stage VREF -15 dB to +6.0 dB Figure 4: Variable Gain Stage Simplified Schematic NAU8501 Datasheet Rev 1.9 Page 17 of 80 Jul, 2018 The input impedance presented to these inputs depends on the input routing choices and gain values. If an input is routed to more than one internal input node, then the effective input impedance will be the parallel combination of the impedance of the multiple nodes that are used. The impedance looking into the PGA non-inverting input is constant as listed in the section discussing the microphone input PGAs. The nominal resistive input impedances looking into the ADC Mix/Boost input inputs are listed in the following table: Inputs LLIN & RLIN to L/RADC MIX/BOOST amp Gain (dB) Not Selected -12 -9 -6 -3 0 3 6 Impedance (kΩ) High-Z 159 113 80 57 40 28 20 Table 3: MIX/BOOST Amp Impedances 3.7 Left and Right Line Inputs (LLIN and RLIN) A third possible input to the left or right PGA is an optional associated LIN left or right line level input. These inputs may be routed to the PGA non-inverting input, and/or connect directly to the ADC Mixer/Boost stage. If routed to the PGA, this signal is processed as an alternate pin for the MICP signal. LIN may be received differentially in relation to the MICN pin and has available the same gain range as for MICP. As in the operational case of using the MICP input, the MICN input must have a low impedance path to signal ground, so that the gain values chosen in the PGA are valid. Note: It not recommended that both the LIN line input path to the PGA and the MICP path to the PGA be enabled at the same time. This will cause the differential gain to be unbalanced, and result in poor common mode rejection. Also, this will result in the LIN and MICP signals being connected together through internal chip resistors. The line input pins, may alternatively be configured to operate as a GPIO (General Purpose Input/Output) logic input pin. This intended purpose is static logic voltage level sensing to determine if a headset is present or not as part of a physical detection of a possible external headset. Only one GPIO pin at any one time can be assigned for this purpose. Registers that affect operation of the LLIN and RLIN inputs are: R2 ADC Mix/Boost power control (must be “on” for any LIN path to function) R9 GPIO selection for headset detect function R44 PGA input selection control bits If selected, all other PGA control registers (see PGA description) R47 Left line input ADC Mix/Boost volume and mute (bits 4, 5, and 6) R48 Right line input ADC Mix/Boost volume and mute (bits 4, 5, and 6) NAU8501 Datasheet Rev 1.9 Page 18 of 80 Jul, 2018 3.8 ADC Mix/Boost Stage The left and right channels each have an independent ADC Mix/Boost stage. The analog input signals must pass through the ADC Mix/Boost stage before use anywhere else in this device. The ADC mixer stage has the LIN input and PGA output as its two inputs. The PGA input is an internal connection to the associated programmable gain amplifier servicing the microphone and line inputs. Each input to the ADC Mix/Boost stage can be independently muted, and both inputs have independent gain controls. The LIN inputs have an available gain range of -12dB through +6dB in 3dB steps. The PGA input path has a choice of 0dB or 20dB of gain in addition to the gain in the PGA. Registers that affect the ADC Mix/Boot stage are: R2 Power control for left and right channels R45 mute function for left channel PGA (bit 6 = 0 = muted condition) R46 mute function for right channel PGA (bit 6 = 0 = muted condition) R47 gain and mute control for left channel LIN path R48 gain and mute control for right channel LIN path 3.9 Input Limiter / Automatic Level Control (ALC) The input section of the NAU8501 is supported by additional combined digital and analog functionality which implement an Automatic Level Control (ALC) function. This can be very useful to automatically manage the analog input gain to optimize the signal level at the output of the programmable amplifier. The ALC can automatically amplify input signals that are too small, or decrease the amplitude if the signals are too loud. This system also helps to prevent clipping (overdrive) at the input of the ADC while maximizing the full dynamic range of the ADC. The ALC may be operated in the normal mode just described, on in a special limiter mode of operation. The limiter mode is a faster mode of operation, the primary purpose of which is to limit too-loud signals. The limiter mode of operation is described after this section which provides details on the normal mode of operation. The functional block architecture for the ALC is shown below. The ALC monitors the output of the ADC, measured after the digital decimator. The ADC output is fed into a peak detector, which updates the measured peak value whenever the absolute value of the input signal is higher than the current measured peak. The measured peak gradually decays to zero unless a new peak is detected, allowing for an accurate measurement of the signal envelope. The peak value is used by a logic algorithm to determine whether the PGA input gain should be increased, decreased, or remain the same. Rate Convert/ Decimator PGA ADC Filter Digital Decimator ALC Figure 5: ALC Block Diagram NAU8501 Datasheet Rev 1.9 Page 19 of 80 Jul, 2018 3.9.1 Normal Mode Example Operation Immediately following is a simple example of the ALC operation. In the steady state at the beginning of the example time sequence, the PGA gain is at a steady value which results in the desired output level from the ADC. When the input signal suddenly becomes louder, the ALC reduces volume at a register determined rate and step size. This continues until the output level of the ADC is again at the desired target level. When the input signal suddenly becomes quiet, the ALC increases volume at a register determined rate and step size. When the output level from the ADC again reaches the target level, and now the input remains at a constant level, the ALC remains in a steady state. PGA Input PGA Output PGA Gain Figure 6: ALC Normal Mode Operation 3.9.2 ALC Parameter Definitions Automatic level and volume control features are complex and have difficult to understand traditional names for many features and controls. This section defines some terms so that the explanations of this subsystem are more clear. ALC Maximum Gain: Register 32 (ALCMXGAIN) This sets the maximum allowed gain in the PGA during normal mode ALC operation. In the Limiter mode of ALC operation, the ALCMXGAIN value is not used. In the Limiter mode, the maximum gain allowed for the PGA is set equal to the pre-existing PGA gain value that was in effect at the moment in time that the Limiter mode is enabled. ALC Minimum Gain: Register 32 (ALCMNGAIN) This sets the minimum allowed gain in the PGA during all modes of ALC operation. This is useful to keep the AGC operating range close to the desired range for a given application scenario. ALC Target Value: Register 33 (ALCSL) Determines the value used by the ALC logic decisions comparing this fixed value with the output of the ADC. This value is expressed as a fraction of Full Scale (FS) output from the ADC. Depending on the logic conditions, the output value used in the comparison may be either the instantaneous value of the ADC, or otherwise a time weighted average of the ADC peak output level. ALC Attack Time: Register 34 (ALCATK) Attack time refers to how quickly a system responds to an increasing volume level that is greater than some defined threshold. Typically, attack time is much faster than decay time. In the NAU8501, when the absolute value of the ADC output exceeds the ALC Target Value, the PGA gain will be reduced at a step size and rate determined by this parameter. When the peak ADC output is at least 1.5dB lower than the ALC Target Value, the stepped gain reduction will halt. NAU8501 Datasheet Rev 1.9 Page 20 of 80 Jul, 2018 ALC Decay Time: Register 34 (ALCDCY) Decay time refers to how quickly a system responds to a decreasing volume level. Typically, decay time is much slower than attack time. When the ADC output level is below the ALC Target value by at least 1.5dB, the PGA gain will increase at a rate determined by this parameter. The decay time constant is determined by the setting in register 34, bits 4 to 7 (ALCDCY), which sets the delay between increases in gain. In Limiter mode, the time constants are faster than in ALC mode. (See Detailed Register Map.) ALC Hold Time Register 33 (ALCHLD) Hold time refers to a duration of time when no action is taken. This is typically to avoid undesirable sounds that can happen when an ALC responds too quickly to a changing input signal. The use and amount of hold time is very application specific. In the NAU8501, the hold time value is the duration of time that the ADC output peak value must be less than the target value before there is an actual gain increase. 3.10 ALC Peak Limiter Function To reduce clipping and other bad audio effects, all ALC modes include a peak limiter function. This implements an emergency PGA gain reduction when the ADC output level exceeds a built-in maximum value. When the ADC output exceeds 87.5% of full scale, the ALC block ramps down the PGA gain at the maximum ALC Attack Time rate, regardless of the mode and attack rate settings, until the ADC output level has been reduced below the emergency limit threshold. This limits ADC clipping if there is a sudden increase in the input signal level. 3.10.1 ALC Normal Mode Example Using ALC Hold Time Feature Input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter for optimum performance. Increasing the ALC hold time prevents the ALC from reacting too quickly to brief periods of silence such as those that may appear in music recordings; having a shorter hold time, may be useful in voice applications where a faster reaction time helps to adjust the volume setting for speakers with different volumes. The waveform below shows the operation of the ALCHLD parameter. 16ms delay for ALCHT = 0100 PGA Input PGA Output PGA Gain Hold Delay Change Figure 7: ALC Hold Delay Change NAU8501 Datasheet Rev 1.9 Page 21 of 80 Jul, 2018 3.11 Noise Gate (Normal Mode Only) A noise gate threshold prevents ALC amplification of noise when there is no input signal, or no signal above an expected background noise level. The noise gate is enabled by setting register 35, bit 3 (NGEN), HIGH, and the threshold level is set in register 35, bits 0 to 2 (NGTH). This does not remove noise from the signal; when there is no signal or a very quiet signal (pause) composed mostly of noise, the ALC holds the gain constant instead of amplifying the signal towards the target threshold. The NAU8501 accomplishes this by comparing the input signal level against the noise gate threshold. The noise gate only operates in conjunction with the ALC and only in Normal mode. The noise gate is asserted when: Equation 1: (Signal at ADC – PGA gain – MIC Boost gain) < NGTH (Noise Gate Threshold Level) PGA Input PGA Output PGA Gain Figure 8: ALC Operation Without Noise Gate PGA Input Noise Gate Threshold PGA Output PGA Gain Figure 9: Noise Gate Operation NAU8501 Datasheet Rev 1.9 Page 22 of 80 Jul, 2018 3.12 ALC Example with ALC Min/Max Limits and Noise Gate Operation Output Level The drawing below shows the effects of ALC operation over the full scale signal range. The drawing is color coded to be more clear as follows: Blue Original Input signal (linear line from zero to maximum) Green PGA gain value over time (inverse to signal in target range) Red Output signal (held to a constant value in target range) Input < noise ALC operation range gate threshold Target ALCSL -6dB Gain (Attenuation) Clipped at ALCMNGAIN -12dB +33dB 0dB PGA Gain -12dB -39dB -39dB -6dB +6dB Input Level Register Bits Name Value 32 7-8 ALCSEL 11 32 3-5 ALCMAXGAIN 111 32 0-2 ALCMINGAIN 33 0-3 ALCLVL 35 3 NGEN 1 35 0-2 NGTH 000 000 1011 Description ALC enabled both channels Max ALC gain @ 35.25dB Min ALC gain @ -12dB Target ALC gain @ -6dBFS Noise gate enabled Noise gate @ -39dB Figure 10: ALC Response Envelope 3.12.1 ALC Register Map Overview ALC can be enabled for either or both the left and right ADC channels. All ALC functions and mode settings are common to the left and right channels. When either the right or left PGA is disabled, the respective PGA will remain at the most recent gain value as set by the ALC. Registers that control the ALC features and functions are: R32 R33 R34 R35 R70 R70 R71 R76 R77 Enable left/right ALC functions; set maximum gain, minimum gain ALC hold time, ALC target signal level ALC limiter mode selection, attack parameters, decay parameters Enable noise gate, noise gate parameters Selection of signal level averaging options and ALC table options Realtime readout of left channel gain value in use by ALC (same as left in stereo operation) Realtime readout of right channel gain value in use by ALC (same as right in stereo operation) Realtime readout of input signal level from averaging peak-to-peak input signal detector Realtime readout of input signal level from averaging input signal peak detector The following table shows some of the ALC parameter values and their ranges. The complete list of settings and values is included in the Detailed Register Map. NAU8501 Datasheet Rev 1.9 Page 23 of 80 Jul, 2018 Registe r Parameter Bits Name Default ALCMING AIN ALCMAXG AIN Programmable Range Setting Value 000 -12dB 111 35.25dB Minimum Gain of PGA 32 0-2 Maximum Gain of PGA 32 3-5 ALC Function 32 7-8 ALCEN 00 Disable d ALC Target Level 33 0-3 ALCLVL 1011 -6dBFS ALC Hold Time 33 4-7 ALCHLD 0000 0ms ALC Attack time 34 0-3 ALCATK 0010 500μs ALC Decay Time 34 4-7 ALCDCY 0011 4ms Limiter Function 34 8 ALCMODE 0 Disable d Range: -12dB to +30dB @ 6dB increments Range: -6.75dB to +35.25dB @ 6dB increments 00 = Disable 01 = Enable right channel 10 = Enable left channel 11 = Enable both channels Range: -22.5dB to -1.5dBFS @ 1.5dB increments Range: 0ms to 1024ms at 1010 and above (times are for 0.75dB steps, and double with every step) ALCM=0 – Range: 125μs to 128ms ALCM=1 – Range: 31μs to 32ms (times are for 0.75dB steps, and double with every step) ALCM = 0 – Range: 500μs to 512ms ALCM = 1 – Range: 125μs to 128ms (times are for 0.75dB steps, and double with every step) 0 = ALC mode 1 = Limiter mode Table 4: Registers associated with ALC and Limiter Control 3.13 Limiter Mode When register 34, bit 8, is HIGH and ALC is enabled in register 32, bits 7-8 (ALCEN), the ALC block operates in limiter mode. In this mode, the PGA gain is constrained to be less than or equal to the PGA gain setting when the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than in normal mode as indicated by the different lookup tables for these parameters for limiter mode. The following waveform illustrates the behavior of the ALC in limiter mode in response to changes in various ALC parameters. PGA Input PGA Output PGA Gain Limiter Enabled Figure 11: ALC Limiter Mode Operation NAU8501 Datasheet Rev 1.9 Page 24 of 80 Jul, 2018 4 ADC Digital Block ADC Digital Filters ΣΔ ADC Digital Filter Gain 5-Band Equalizer High Pass Filter Notch Filter Digital Audio Interface The ADC digital block performs 24-bit analog-to-digital conversion and signal processing, making available a high quality audio sample stream the audio path digital interface. This block consists of a sigma-delta modulator, digital decimator/ filter, 5-band graphic equalizer, 3D effects, high pass filter, and a notch filter. The equalizer and 3D audio function block is a single resource that may be used by either the ADC or DAC, but not both at the same time. The ADC coding scheme is in twos complement format and the full-scale input level is proportional to VDDA. With a 3.3V supply voltage, the full-scale level is 1.0VRMS. Registers that affect the ADC operation are: R2 Power management enable/disable left/right ADC R5 Digital passthrough of ADC output data into DAC input R7 Sample rate indication bits (affect filter frequency scaling) R14 Oversampling, polarity inversion, and filter controls for left/right ADC R14 ADC high pass filter Audio Mode or Application Mode selection R15 Left channel ADC digital volume control and update bit function R16 Right channel ADC digital volume control and update bit function 4.1 Sampling / Oversampling Rate, Polarity Control, Digital Passthrough The audio sample rate of the ADC is determined entirely by the IMCLK internal Master Clock frequency, which is 128 times the base audio sample rate. A technique known as oversampling is used to improve noise and distortion performance of the ADC, but this does not affect the final audio sample rate. The default oversampling rate of the ADC is 64X (64 times the audio sample rate), but this can be changed to 128X for greatly improved audio performance. The higher rate increases power consumption by only approximately three milliwatts per channel, so for most applications, the improved quality is a good choice. There is almost zero increased power to also run the DACs at 128X oversampling, and the best overall quality will be achieved when both the DACs and ADCs are operated at the same oversampling rate. The polarity of either ADC output signal can be changed independently on either ADC logic output as a feature sometimes useful in management of the audio phase. This feature can help minimize any audio processing that may be otherwise required as the data are passed to other stages in the system. Digital audio passthrough allows the output of the ADCs to be directly sent to the DACs as the input signal to the DAC for DAC output. In this mode of operation, the output data from the ADCs are still available on the ADCOUT logic pin. However, any external input signal for the DAC will be ignored. The passthrough function is useful for many test and application purposes, and the DAC output may be utilized in any way that is normally supported for the DAC analog output signals. NAU8501 Datasheet Rev 1.9 Page 25 of 80 Jul, 2018 4.2 ADC Digital Volume Control and Update Bit Functionality The effective output audio volume of each ADC can be changed using the digital volume control feature. This processes the output of the ADC to scale the output by the amount indicated in the volume register setting. Included is a “digital mute” value which will completely mute the signal output of the ADC. The digital volume setting can range from 0dB through -127dB in 0.5dB steps. Important: The R15 and R16 update bits are write-only bits. The primary intended purpose of the update bit is to enable simultaneous changes to both the left and right ADC volume values, even though these values must be written sequentially. When there is a write operation to either R15 or R16 volume settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. When there is a write operation to either R15 or R16 and the update bit is set (value = 1), then the new value in the register being written is immediately put into effect, and any pending value in the other ADC volume register is put into effect at the same time. 4.3 ADC Programmable High Pass Filter Each ADC is optionally supported by a high pass filter in the digital output path. Filter operation and settings are always the same for both left and right channels. The high pass filter has two different operating modes. In the audio mode, the filter is a simple first order DC blocking filter, with a cut-off frequency of 3.7Hz. In the application specific mode, the filter is a second order audio frequency filter, with a programmable cut-off frequency. The cutoff frequency of the high pass filter is scaled depending on the sampling frequency indicated to the system by the setting in Register 7. Registers that affect operation of the programmable high pass filter are: R7 Sample rate indication to the system (affects filter coefficient internal scaling) R14 High-pass enable/disable, operating mode, and cut-off frequency The following table provides the exact cutoff frequencies with different sample rates as indicated to the system by means of Register 7. The table shows the assumed actual numerical sample rates as determined by the system clocks. Detailed response curves are provided in the Appendix section of this document. Register 14, bits 4 to 6 (HPF) 000 001 010 011 100 101 110 111 R7(SMPLR) = 101 or 100 Sample Rate in kHz (FS) R7(SMPLR) = 011 or 010 R7(SMPLR) = 001 or 000 8 11.025 12 16 22.05 24 32 44.1 48 82 102 131 163 204 261 327 408 113 141 180 225 281 360 450 563 122 153 156 245 306 392 490 612 82 102 131 163 204 261 327 408 113 141 180 225 281 360 450 563 122 153 156 245 306 392 490 612 82 102 131 163 204 261 327 408 113 141 180 225 281 360 450 563 122 153 156 245 306 392 490 612 Table 5: High Pass Filter Cut-off Frequencies in Hz (with HPFAM register 14, bit 7 = 1) NAU8501 Datasheet Rev 1.9 Page 26 of 80 Jul, 2018 4.4 Programmable Notch Filter Each ADC is optionally supported by a notch filter in the digital output path. Filter operation and settings are always the same for both left and right channels. A notch filter is useful to a very narrow band of audio frequencies in a stop band around a given center frequency. The notch filter is enabled by setting register 27, bit 7 (NFCEN), to 1. The center frequency is programmed by setting registers 27, 28, 29, and 30, bits 0 to 6 (NFA0[13:7], NFA0[6:0], NFA1[13:7], NFA1[6:0]), with two’s compliment coefficient values calculated using table __. Registers that affect operation of the notch filter are: R27 R27 R28 R29 R30 Notch filter enable/disable Notch filter a0 coefficient high order bits and update bit Notch filter a0 coefficient low order bits and update bit Notch filter a1 coefficient high order bits and update bit Notch filter a1 coefficient low order bits and update bit Important: The register update bits are write-only bits. The update bit function is important so that all filter coefficients actively being used are changed simultaneously, even though these register values must be written sequentially. When there is a write operation to any of the filter coefficient settings, but the update bit is not set (value = 0), the value is stored as pending for the future, but does not go into effect. When there is a write operation to any coefficient register, and the update bit is set (value = 1), then the new value in the register being written is immediately put into effect, and any pending coefficient value is put into effect at the same time. Coefficient values are in the form of 2’s-complement integer values, and must be calculated based upon the desired filter properties. The mathematical operations for calculating these coefficients are detailed in the following table. A0  2 π fb   1 − tan   2 fs     2 π fb   1 + tan   2 f  s   A1 Notation Register Value (DEC) NFCA0 = -A0 x 213 − (1 + A0 )  2 π fc   x cos    fs   fc = center frequency (Hz) fb = -3dB bandwidth (Hz) fs = sample frequency (Hz) NFCA1 = -A1 x 212 Note: Values are rounded to the nearest whole number and converted to 2’s complement Table 6: Equations to calculate notch filter coefficients NAU8501 Datasheet Rev 1.9 Page 27 of 80 Jul, 2018 4.5 5-Band Equalizer The NAU8501 includes a 5-band graphic equalizer with low distortion, low noise, and wide dynamic range. The equalizer is applied to both left and right channels. The equalizer is grouped with the 3D Stereo Enhancement signal processing function. Both functions may be assigned to support either the ADC path, or the DAC path, but not both paths simultaneously. Registers that affect operation of the 5-Band Equalizer are: R18 R18 R19 R20 R21 R22 Assign equalizer to DAC path or to ADC path (default = ADC path) Band 1 gain control and cut-off frequency Band 2 gain control, center cut-off frequency, and bandwidth Band 3 gain control, center cut-off frequency, and bandwidth Band 4 gain control, center cut-off frequency, and bandwidth Band 5 gain control and cut-off frequency Each of the five equalizer bands is independently adjustable for maximum system flexibility, and each offers up to 12dB of boost and 12dB of cut with 1dB resolution. The high and the low bands are shelving filters (high-pass and low-pass, respectively), and the middle three bands are peaking filters. Details of the register value settings are described below. Response curve examples are provided in the Appendix of this document. Register Value 00 01 10 11 1 (High Pass) Register 18 Bits 5 & 6 EQ1CF 80Hz 105Hz 135Hz 175Hz 2 (Band Pass) Register 19 Bits 5 & 6 EQ2CF 230Hz 300Hz 385Hz 500Hz Equalizer Band 3 (Band Pass) Register 20 Bits 5 & 6 EQ3CF 650Hz 850Hz 1.1kHz 1.4kHz 4 (Band Pass) Register 21 Bits 5 & 6 EQ4CF 1.8kHz 2.4kHz 3.2kHz 4.1kHz 5 (Low Pass) Register 22 Bits 5 & 6 EQ5CF 5.3kHz 6.9kHz 9.0kHz 11.7kHz Table 7: Equalizer Center/Cutoff Frequencies Register Value Binary Hex 00000 00h 00001 01h 00010 02h ---01100 0Ch 01101 17h ---11000 18h 11001 to 11111 19h to 1Fh Gain Registers +12db +11dB +10dB Increments 1dB per step 0dB -11dB Increments 1dB per step -12dB Reserved Bits 0 to 4 in registers 18 (EQ1GC) 19 (EQ2GC) 20 (EQ3GC) 21 (EQ4GC) 22 (EQ5GC) Table 8: Equalizer Gains NAU8501 Datasheet Rev 1.9 Page 28 of 80 Jul, 2018 4.6 3D Stereo Enhancement NAU8501 includes digital circuitry to provide flexible 3D enhancement to increase the perceived separation between the right and left channels, and has multiple options for optimum acoustic performance. The equalizer is grouped with the 3D Stereo Enhancement signal processing function. Both functions may be assigned to support either the ADC path, or the DAC path, but not both paths simultaneously. Registers that affect operation of 3D Stereo Enhancement are: R18 Assign equalizer to DAC path or to ADC path (default = ADC path) R41 3D Audio depth enhancement setting The amount of 3D enhancement applied can be programmed from the default 0% (no 3D effect) to 100% in register 41, bits 0 to 3 (DEPTH3D), as shown in Table __. Note: 3D enhancement uses increased gain to achieve its effect, so that the source signal may need to be attenuated by up to 6dB to avoid clipping. Register 41 Bits 0 to 3 3DDEPTH 3D Effect 0000 0001 0010 0% 6.7%dB 13.4%dB --- Increments 6.67% for each binary step in the input word 1110 1111 93.3% 100% Table 9: 3D Enhancement Depth NAU8501 Datasheet Rev 1.9 Page 29 of 80 Jul, 2018 4.7 Companding Companding is used in digital communication systems to optimize signal-to-noise ratios with reduced data bit rates, using non-linear algorithms. These compress wide-range linear audio data into an 8-bit quasi-logarithmic quantization. The compressed data are then transmitted over a network, and then expanded back again into linear audio data. NAU8501 supports the compression feature of the two main telecommunications companding standards: A-law and µ-law. The A-law algorithm is primarily used in European communication systems and the µlaw algorithm is primarily used by North America, Japan, and Australia. . Companding converts 13-bits (µ-law) or 12-bits (A-law) of linear PCM codes into 8-bits using non-linear quantization, and then back again into linear PCM codes. The companded signal is an 8-bit word containing a sign (1-bit), exponent (3-bits) and mantissa (4-bits) Following are the data compression equations set in the ITU-T G.711 standard and implemented in the NAU8501: 4.8 µ-law F(x) = ln( 1 + µ|x|) / ln( 1 + µ) -1 ≤ x ≤ 1 with µ=255 for the U.S. and Japan 4.9 A-law F(x) = A|x| / ( 1 + lnA) for x ≤ 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) for 1/A ≤ x ≤ 1 with A=87.6 for Europe The register affecting companding operation is: R5 Enable 8-bit mode; enable ADC companding The compressed signal is an 8-bit word consisting of a sign bit, three bits for the exponent, and four bits for the mantissa. When compression is enabled, the PCM interface must be set to an 8-bit word length. When in 8-bit mode, the Register 4 word length control (WLEN) is ignored. Compression Mode No Compression (default) ADC 1- law μ-law Bit 4 0 Register 5 Bit3 Bit 2 0 0 1 1 Bit 1 0 1 0 Table 10: Companding Control 4.10 8-bit Word Length Writing a 1 to register 5, bit 5 (CMB8), will cause the PCM interface to use 8-bit word length for data transfer, overriding the word length configuration setting in WLEN (register 4, bits 5 and 6.). NAU8501 Datasheet Rev 1.9 Page 30 of 80 Jul, 2018 5 Analog Outputs There are two line level analog audio outputs. These outputs are useful for monitoring the analog input signal that is available at the input of the ADCs. Each output has an independently programmable gain function, output mute function, and output disable function. The gain can be programmed from -24dB through +6dB in 2dB steps. These outputs are derived from the signals at the inputs of the two ADC converters. These signals are then buffered, optionally muted, and then passed to the line level output driver. Registers that affect operation of the line level output path are: R3 Power control for the left and right internal buffer amplifier R50 left AUX and ADC Mix/Boost source select, and gain settings R51 right AUX and ADC Mix/Boost source select, and gain settings 5.1 Line Level Outputs (LLINOUT and RLINOUT) These are high quality general purpose output drivers intended for driving medium impedance loads such as inputs to other amplifiers (such as a headphone amplifier) and long signal lines. The signal source for each of these outputs is from the associated left and right internal buffer from the inputs to the ADCs. Power for this section is provided from the VDDA pin. Each driver may be selectively enabled/disabled as part of the power management features, and each output can be individually controlled over a gain range of -57dB through +6dB in 1dB steps. Gain changes for the two outputs can be coordinated through use of an update bit feature as part of the register controls. Additionally, clicks that could result from gain changes can be suppressed using an optional zero crossing feature. Registers that affect the line outputs are: R2 Power management control for the left and right line output amplifier R52 Volume, mute, update, and zero crossing controls for left line output driver R53 Volume, mute, update, and zero crossing controls for right line output driver Important: The R52 and R53 update bits are write-only bits. The primary intended purpose of the update bit is to enable simultaneous changes to both the left and right line output volume values, even though these two register values must be written sequentially. When there is a write operation to either R52 or R53 volume settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. When there is a write operation to either R52 or R53 and the update bit is set (value = 1), then the new value in the register being written is immediately put into effect, and any pending value in the other line output volume register is put into effect at the same time. Zero-Crossing controls are implemented to suppress clicking sounds that may occur when volume setting changes take place while an audio input signal is active. When the zero crossing function is enabled (logic = 1), any volume change for the affected channel will not take place until the audio input signal passes through the zero point in its peak-to-peak swing. This prevents any instantaneous voltage change to the audio signal caused by volume setting changes. If the zero crossing function is disabled (logic = 0), volume changes take place instantly on condition of the Update Bit, but without regard to the instantaneous voltage level of the affected audio input signal. NAU8501 Datasheet Rev 1.9 Page 31 of 80 Jul, 2018 6 Miscellaneous Functions 6.1 Slow Timer Clock An internal Slow Timer Clock is supplied to automatically control features that happen over a relatively periods of time, or time-spans. This enables the NAU8501 to implement long time-span features without any host/processor management or intervention. Two features are supported by the Slow Timer Clock. These are an optional automatic time out for the zerocrossing holdoff of PGA volume changes, and timing for debouncing of the mechanical jack detection feature. If either feature is required, the Slow Timer Clock must be enabled. The Slow Timer Clock is initialized in the disabled state. The Slow Timer Clock is controlled by only the following register: R7 Sample rate indication select, and Slow Timer Clock enable The Slow Timer Clock rate is derived from MCLK using an integer divider that is compensated for the sample rate as indicated by the R7 sample rate register. If the sample rate register value precisely matches the actual sample rate, then the internal Slow Timer Clock rate will be a constant value of 128ms. If the actual sample rate is, for example, 44.1kHz and the sample rate selected in R7 is 48kHz, the rate of the Slow Timer Clock will be approximately 10% slower in direct proportion of the actual vs. indicated sample rate. This scale of difference should not be important in relation to the dedicated end uses of the Slow Timer Clock. NAU8501 Datasheet Rev 1.9 Page 32 of 80 Jul, 2018 6.2 General Purpose Inputs and Outputs (GPIO1, GPIO2, GPIO3) and Jack Detection Three pins are provided in the NAU8501 that may be used for limited logic input/output functions. GPIO1 has multiple possible functions, and may be either a logic input or logic output. GPIO2 and GPIO3 may be either line level analog inputs, or logic inputs dedicated to the purpose of jack detection. GPIO2 and GPIO3 do not have any logic output capability or function. Only one GPIO can be selected for jack detection. If a GPIO is selected for the jack detection feature, the Slow Timer Clock must be enabled. The jack detection function is automatically “debounced” such that momentary changes to the logic value of this input pin are ignored. The Slow Timer Clock is necessary for the debouncing feature. Registers that control the GPIO functionality are: R8 GPIO functional selection options R9 Jack Detection feature input selection and functional options If a GPIO is selected for the jack detection function, the required Slow Timer Clock determines the duration of the time windows for the input logic debouncing function. Because the logic level changes happen asynchronously to the Slow Timer Clock, there is inherently some variability in the timing for the jack detection function. A continuous and persistent logic change on the GPIO pin used for jack detection will result in a valid internal output signal within 2.5 to 3.5 periods of the Slow Timer Clock. Any logic change of shorter duration will be ignored. The threshold voltage for a jack detection logic-low level is no higher than 1.0Vdc. The threshold voltage for a jack detection logic-high level is no lower than 1.7Vdc. These levels will be reduced as the VDDC core logic voltage pin is reduced below 1.9Vdc. If the RLIN or LLIN input pin is used for the GPIO function, the analog signal path should be configured to be disconnected from its respective PGA input. This will not cause harm to the device, but could cause unwanted noise introduced through the PGA path. 6.3 Automated Features Linked to Jack Detection Some functionality can be automatically controlled by the jack detection logic. This feature can be used to enable the internal analog amplifier bias voltage generator, and/or enable analog output drivers automatically as a result of detecting a logic change at a GPIO pin assigned to the purpose of jack detection. This eliminates any requirement for the host/processor to perform these functions. The internal analog amplifier bias generator creates the VREF voltage reference and bias voltage used by the analog amplifiers. The ability to control it is a power management feature. This is implemented as a logical “OR” function of either the debounced internal jack detection signal, or the ABIASEN control bit in Register 1. The bias generator will be powered if either of these control signals is enabled (value = 1). Power management control of the line outputs is also optionally and selectively subject to control linked with the jack detection signal. Register settings determine which outputs may be enabled, and whether they are enabled by a logic 1 or logic 0 value. Output control is a logical “AND” operation of the jack detection controls, and of the register control bits that normally control the outputs. Both controls must be in the “ON” condition for a given output to be enabled. Registers that affect these functions are: R9 GPIO pin selection for jack detect function, jack detection enable, VREF jack enable R13 bit mapped selection of which outputs are to be enabled when jack detect is in a logic 1 state R13 bit mapped selection of which outputs are to be enabled when jack detect is in a logic 0 state NAU8501 Datasheet Rev 1.9 Page 33 of 80 Jul, 2018 7 Clock Selection and Generation The NAU8501 has two basic clock modes that support the ADC data converters. It can accept external clocks in the slave mode, or in the master mode, it can generate the required clocks from an external reference frequency using an internal PLL (Phase Locked Loop). The internal PLL is a fractional type scaling PLL, and therefore, a very wide range of external reference frequencies can be used to create accurate audio sample rates. Separate from this ADC clock subsystem, audio data are clocked to and from the NAU8501 by means of the control logic described in the Digital Audio Interfaces section. The audio bit rate and audio sample rate for this data flow are managed by the Frame Sync (FS) and Bit Clock (BCLK) pins in the Digital Audio Interface. It is important to understand that the sampling rate for the ADC data converters is not determined by the Digital Audio Interface, and instead, this rate is derived exclusively from the Internal Master Clock (IMCLK). It is therefore a requirement that the Digital Audio Interface and data converters be operated synchronously, and that the FS, BCLK, and IMCLK signals are all derived from a common reference frequency. If these three clocks signals are not synchronous, audio quality will be reduced. The IMCLK is always exactly 256 times the sampling rate of the data converters. IMCLK is output from the Master Clock Prescaler. The prescaler reduces by an integer division factor the input frequency input clock. The source of this input frequency clock is either the external MCLK pin, or the output from the internal PLL Block. Registers that are used to manage and control the clock subsystem are: R1 Power management, enable control for PLL (default = disabled) R6 Master/slave mode, clock scaling, clock selection R7 Sample rate indication (scales DSP coefficients and timing – does NOT affect actual sample rate R8 MUX control and division factor for PLL output on GPIO1 R36 PLL Prescaler, Integer portion of PLL frequency multiplier R37 Highest order bits of 24-bit fraction of PLL frequency multiplier R38 Middle order bits of 24-bit fraction of PLL frequency multiplier R39 Lowest order bits of 24-bit fraction of PLL frequency multiplier In Master Mode, the IMCLK signal is used to generate FS and BCLK signals that are driven onto the FS and BCLK pins and input to the Digital Audio Interface. FS is always IMCLK/256 and the duty cycle of FS is automatically adjusted to be correct for the mode selected in the Digital Audio Interface. The frequency of BCLK may optionally be divided to optimize the bit clock rate for the application scenario. In Slave Mode, there is no connection between IMCLK and the FS and BCLK pins. In this mode, FS and BLCK are strictly input pins, and it is the responsibility of the system designer to insure that FS, BCLK, and IMCLK are synchronous and scaled appropriately for the application. NAU8501 Datasheet Rev 1.9 Page 34 of 80 Jul, 2018 DAC ADC PLL Prescaler R36[4] Master Clock Prescaler R6[7,6,5] MCLK 0 f1 1 PLL f2 f2=R(f1) f/4 fPLL 0 f/N 1 IMCLK = 256fS f/2 Master Clock Select PLL BLOCK R6[8] BCLK Output Scaler f/N f/256 R6[4,3,2] CSB / GPIO1 f/N GPIO1 MUX Control R8[2,1,0] PLL to GPIO1 Output Scaler Master / Slave Select R8[5,4] R6[0] 1 0 FS Digital Audio Interface BCLK Figure 12: PLL and Clock Select Circuit 7.1 Phase Locked Loop (PLL) General Description The PLL may be optionally used to multiply an external input clock reference frequency by a high resolution fractional number. To enable the use of the widest possible range of external reference clocks, the PLL block includes an optional divide-by-two prescaler for the input clock, a fixed divide-by-four scaler on the PLL output, and an additional programmable integer divider that is the Master Clock Prescaler. The high resolution fraction for the PLL is the ratio of the desired PLL oscillator frequency (f2), and the reference frequency at the PLL input (f1). This can be represented as R = f2/f1, with R in the form of a decimal number: xy.abcdefgh. To program the NAU8501, this value is separated into an integer portion (“xy”), and a fractional portion, “abcdefgh”. The fractional portion of the multiplier is a value that when represented as a 24-bit binary number (stored in three 9-bit registers on the NAU8501), very closely matches the exact desired multiplier factor. To keep the PLL within its optimal operating range, the integer portion of the decimal number (“xy”), must be any of the following decimal values: 6, 7, 8, 9, 10, 11, or 12. The input and output dividers outside of the PLL are often helpful to scale frequencies as needed to keep the “xy” value within the required range. Also, the optimum PLL oscillator frequency is in the range between 90MHz and 100MHz, and thus, it is best to keep f2 within this range. In summary, for any given design, choose:           IMCLK = desired Master Clock = (256)*(desired codec sample rate) f2 = (4)*(P)(IMCLK), where P is the Master Clock Prescale integer value; optimal f2: 90MHz< f2 0.546*fs dB 0.546 fs -60 dB Group Delay 28.25 1/fs -3dB 3.7 Hz -0.5dB 10.4 Hz -0.1dB 21.6 Hz ADC High Pass Filter High Pass Filter Corner Frequency Table 19: Digital Filter Characteristics TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region 3. Note that this delay applies only to the filters and does not include other latencies, such as from the serial data interface Figure 35: ADC Filter Frequency Response NAU8501 Datasheet Rev 1.9 Page 57 of 80 Jul, 2018 Figure 36: ADC Filter Ripple 0 Gain in dB -1 -2 -3 -4 -5 -6 5 0 10 20 20 15 30 30 25 35 Figure 37: ADC Highpass Filter Response, Audio Mode 0 -20 d B -40 r -60 -80 100 300 500 700 900 Hz Figure 38: ADC Highpass Filter Response, HPF enabled, FS = 48kHz NAU8501 Datasheet Rev 1.9 Page 58 of 80 Jul, 2018 0 -20 d B -40 r -60 -80 100 700 500 300 900 Hz Figure 39: ADC Highpass Filter Response, HPF enabled, FS = 24kHz 0 -20 d B -40 r -60 -80 100 500 300 700 900 Hz Figure 40: ADC Highpass Filter Response, HPF enabled, FS = 12kHz +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 41: EQ Band 1 Gains for Lowest Cut-Off Frequency +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 42: EQ Band 2 Peak Filter Gains for Lowest Cut-Off Frequency with EQ2BW = 0 NAU8501 Datasheet Rev 1.9 Page 59 of 80 Jul, 2018 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 43: EQ Band 2, EQ2BW = 0 versus EQ2BW = 1 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k Hz Figure 44: EQ Band 3 Peak Filter Gains for Lowest Cut-Off Frequency with EQ3BW = 0 +15 Figure 45: EQ Band 3, EQ3BW = 0 versus EQ3BW = 1 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k Hz +15 T +10 +5 d B r 0 -5 -10 -15 Figure 46: EQ Band 4 Peak Filter Gains for Lowest Cut-Off Frequencies with EQ4BW = 0 NAU8501 Datasheet Rev 1.9 Page 60 of 80 Jul, 2018 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Hz Figure 47: EQ Band 4, EQ4BW = 0 versus EQ4BW =1 +15 +10 +5 d B r 0 -5 -10 -15 20 50 100 200 500 1k 2k 5k Hz Figure 48: EQ Band 5 Gains for Lowest Cut-Off Frequency NAU8501 Datasheet Rev 1.9 Page 61 of 80 Jul, 2018 12 Appendix B: Companding Tables 12.1 µ-Law / A-Law Codes for Zero and Full Scale µ-Law Level A-Law Sign bit (D7) Chord bits (D6,D5,D4) Step bits (D3,D2,D1,D0) Sign bit (D7) Chord bits (D6,D5,D4) Step bits (D3,D2,D1,D0) + Full Scale 1 000 0000 1 010 1010 + Zero 1 111 1111 1 101 0101 - Zero 0 111 1111 0 101 0101 - Full Scale 0 000 0000 0 010 1010 Table 20: Companding Codes for Zero and Full-Scale 12.2 µ-Law / A-Law Output Codes (Digital mW) µ-Law Sample A-Law Sign bit (D7) Chord bits (D6,D5,D4) Step bits (D3,D2,D1,D0) Sign bit (D7) Chord bits (D6,D5,D4) Step bits (D3,D2,D1,D0) 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100 Table 21: Companding Output Codes NAU8501 Datasheet Rev 1.9 Page 62 of 80 Jul, 2018 13 Appendix C: Details of Register Operation Register Function Name Dec Hex 0 00 Bit Description 8 7 6 5 43 2 1 0 Any write operation to this register resets all registers to default values Software Reset Reserved Power control for internal PLL 0 = unpowered 1 = enabled Power control for microphone bias buffer amplifier (MICBIAS output, pin#32) 0 = unpowered and MICBIAS pin in high-Z condition 1 = enabled Power control for internal analog bias buffers 0 = unpowered 1 = enabled Power control for internal tie-off buffer used in non-boost mode (-1.0x gain) conditions 0 = internal buffer unpowered 1 = enabled Select impedance of reference string used to establish VREF for internal bias buffers 00 = off (input to internal bias buffer in high-Z floating condition) 01 = 80kΩ nominal impedance at VREF pin 10 = 300kΩ nominal impedance at VREF pin 11 = 3kΩ nominal impedance at VREF pin PLLEN MICBIASEN 1 01 Power Management 1 ABIASEN IOBUFEN REFIMP Default >> 0 0 0 0 0 0 0 0 0 RLINEN LLINEN SLEEP RBSTEN 2 02 Power Management 2 LBSTEN RPGAEN LPGAEN RADCEN LADCEN Default >> 0x000 reset value Right Line Output driver Enable 0 = output pin in high-Z condition 1 = enabled Left Line Output driver Enabled 0 = output pin in high-Z condition 1 = enabled Sleep enable 0 = device in normal operating mode 1 = device in low-power sleep condition Right channel input mixer, RADC Mix/Boost stage power control 0 = RADC Mix/Boost stage OFF 1 = RADC Mix/Boost stage ON Left channel input mixer, LADC Mix/Boost stage power control 0 = LADC Mix/Boost stage OFF 1 = LADC Mix/Boost stage ON Right channel input programmable amplifier (PGA) power control 0 = Right PGA input stage OFF 1 = enabled Left channel input programmable amplifier power control 0 = Left PGA input stage OFF 1 = enabled Right channel analog-to-digital converter power control 0 = Right ADC stage OFF 1 = enabled Left channel analog-to-digital converter power control 0 = Left ADC stage OFF 1 = enabled 0 0 0 0 0 0 0 0 0 0x000 reset value Reserved Right bypass buffer to Line Output 0 = bypass buffer disabled 1 = enabled Left bypass buffer to Line Output 0 = bypass buffer disabled 1 = enabled RBYPEN 3 03 Power Management 3 LBYPEN Reserved Default >> 0 0 0 0 0 0 0 NAU8501 Datasheet Rev 1.9 0 0 0x000 reset value Page 63 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Bit clock phase inversion option for BCLK, pin#8 0 = normal phase 1 = input logic sense inverted Phase control for I2S audio data bus interface 0 = normal phase operation 1 = inverted phase operation PCMA and PCMB left/right word order control 0 = MSB is valid on 2nd rising edge of BCLK after rising edge of FS 1 = MSB is valid on 1st rising edge of BCLK after rising edge of FS Word length (24-bits default) of audio data stream 00 = 16-bit word length 01 = 20-bit word length 10 = 24-bit word length 11 = 32-bit word length Audio interface data format (default setting is I2S) 00 = right justified 01 = left justified 10 = standard I2S format 11 = PCMA or PCMB audio data format option BCLKP LRP WLEN 4 04 Audio Interface AIFMT Reserved ADC audio data left-right ordering 0 = left ADC data is output in left phase of LRP 1 = left ADC data is output in right phase of LRP (left-right reversed) Mono operation enable 0 = normal stereo mode of operation 1 = mono mode with audio data in left phase of LRP ADCPHS MONO Default >> 0 0 1 0 1 0 0 0 0 0x050 reset value Reserved 8-bit word enable for companding mode of operation 0 = normal operation (no companding) 1 = 8-bit operation for companding mode CMB8 Reserved 5 05 ADC companding mode control 00 = off (normal linear operation) 01 = reserved 10 = u-law companding 11 = A-law companding Companding ADCCM Reserved Default >> 0 0 0 0 0 0 0 CLKM MCLKSEL 6 06 Clock control 1 BCLKSEL 0 0 0x000 reset value master clock source selection control 0 = MCLK, pin#11 used as master clock 1 = internal PLL oscillator output used as master clock Scaling of master clock source for internal 256fs rate ( divide by 2 = default) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 Scaling of output frequency at BCLK pin#8 when chip is in master mode 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = reserved 111 = reserved Reserved NAU8501 Datasheet Rev 1.9 Page 64 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Enables chip master mode to drive FS and BCLK outputs 0 = FS and BCLK are inputs 1 = FS and BCLK are driven as outputs by internally generated clocks CLKIOEN Default >> 1 0 1 0 0 0 0 0 0 4WSPIEN 0x140 reset value 4-wire control interface enable Reserved 7 07 Clock control 2 Audio data sample rate indication (48kHz default). Sets up scaling for internal filter coefficients, but does not affect in any way the actual device sample rate. Should be set to value most closely matching the actual sample rate determined by 256fs internal node. 000 = 48kHz 001 = 32kHz 010 = 24kHz 011 = 16kHz 100 = 12kHz 101 = 8kHz 110 = reserved 111 = reserved Slow timer clock enable. Starts internal timer clock derived by dividing master clock. 0 = disabled 1 = enabled SMPLR SCLKEN Default >> 0 0 0 0 0 0 0 0 0 0x000 reset value Reserved Clock divisor applied to PLL clock for output from a GPIO pin 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 GPIO1 polarity inversion control 0 = normal logic sense of GPIO signal 1 = inverted logic sense of GPIO signal CSB/GPIO1 function select (input default) 000 = use as input subject to MODE pin#18 input logic level 001 = reserved 010 = Temperature OK status output ( logic 0 = thermal shutdown) 011 = Reserved 100 = output divided PLL clock 101 = PLL locked condition (logic 1 = PLL locked) 110 = output set to logic 1 condition 111 = output set to logic 0 condition GPIO1PLL GPIO1PL 8 08 GPIO GPIO1SEL Default >> 0 0 0 0 0 0 0 0 0 JCKMIDEN JACDEN 9 09 0x000 reset value Automatically enable internal bias amplifiers on jack detection state as sensed through GPIO pin associated to jack detection function Bit 7 = logic 1: enable bias amplifiers on jack at logic 0 level Bit 8 = logic 1: enable bias amplifiers on jack at logic 1 level Jack detection feature enable 0 = disabled 1 = enable jack detection associated functionality Select jack detect pin (GPIO1 default) 00 = GPIO1 is used for jack detection feature 01 = GPIO2 is used for jack detection feature 10 = GPIO3 is used for jack detection feature 11 = reserved Jack detect 1 JCKDIO Reserved Default >> 10 0A Reserved 11 0B Reserved 12 0C Reserved 0 0 0 0 0 0 0 NAU8501 Datasheet Rev 1.9 0 0 0x000 reset value Page 65 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Reserved Outputs drivers that are automatically enabled whenever the designated jack detection input is in the logic = 1 condition, and the jack detection feature is enabled Bit 4 = 0: no change to Left and Right Line Output drivers Bit 4 = 1: enable Left and Right Line Output drivers JCKDOEN1 13 0D Reserved Jack detect 2 Outputs drivers that are automatically enabled whenever the designated jack detection input is in the logic = 0 condition, and the jack detection feature is enabled Bit 0 = 1: enable Left and Right Line Output drivers Bit 1 = 1: no change to Left and Right Line Output drivers JCKDOEN0 Default >> 0 0 0 0 0 0 0 0 0 HPFEN HPFAM HPF 14 0E ADC control 0x000 reset value High pass filter enable control for filter of ADC output data stream 0 = high pass filter disabled 1 = high pass filter enabled High pass filter mode selection 0 = normal audio mode, 1st order 3.7Hz high pass filter for DC blocking 1 = application specific mode, variable 2nd order high pass filter Application specific mode cutoff frequency selection ADC oversampling rate selection (64X default) 0 = 64x oversampling rate for reduced power 1 = 128x oversampling for better SNR ADCOS Reserved ADC right channel polarity control 0 = normal polarity 1 = sign of RADC output is inverted from normal polarity ADC left channel polarity control 0 = normal polarity 1 = sign of LADC output is inverted from normal polarity RADCPL LADCPL Default >> 1 0 0 0 0 0 0 0 0 LADCVU 15 0F Left ADC volume LADCGAIN Default >> 0 1 1 1 1 1 1 1 1 10 Right ADC volume RADCGAIN Default >> 0x0FF reset value ADC volume update bit feature. Write-only bit for synchronized L/R ADC changes If logic = 0 on R16 write, new R16 value stored in temporary register If logic = 1 on R16 write, new R16 and pending R15 values become active ADC left digital volume control (0dB default attenuation value). Expressed as an attenuation value in 0.5dB steps as follows: 0000 0000 = digital mute condition 0000 0001 = -127.0dB (highly attenuated) 0000 0010 = -126.5dB attenuation - all intermediate 0.5 step values through maximum volume – 1111 1110 = -0.5dB attenuation 1111 1111 = 0.0dB attenuation (no attenuation) RADCVU 16 0x100 reset value ADC volume update bit feature. Write-only bit for synchronized L/R ADC changes If logic = 0 on R15 write, new R15 value stored in temporary register If logic = 1 on R15 write, new R15 and pending R16 values become active ADC right digital volume control (0dB default attenuation value). Expressed as an attenuation value in 0.5dB steps as follows: 0000 0000 = digital mute condition 0000 0001 = -127.0dB (highly attenuated) 0000 0010 = -126.5dB attenuation - all intermediate 0.5 step values through maximum volume – 1111 1110 = -0.5dB attenuation 1111 1111 = 0.0dB attenuation (no attenuation) 0 1 1 1 1 1 1 NAU8501 Datasheet Rev 1.9 1 1 0x0FF reset value Page 66 of 80 Jul, 2018 Register Function Name Dec Hex 17 11 Bit Description 8 7 6 5 43 2 1 0 Reserved Equalizer and 3D audio processing block assignment. 0 = block operates on digital stream from ADC 1 = block operates on digital stream to DAC (default on reset) EQM Reserved Equalizer band 1 low pass -3dB cut-off frequency selection 00 = 80Hz 01 = 105Hz (default) 10 = 135Hz 11 = 175Hz EQ Band 1 digital gain control. Expressed as a gain or attenuation in 1dB steps 01100 = 0.0dB default unity gain value EQ1CF 18 12 EQ1 low cutoff 00000 = +12dB 00001 = +11dB - all intermediate 1.0dB step values through minimum gain – 11000 = -12dB 11001 and larger values are reserved EQ1GC Default >> 1 0 0 1 0 1 1 0 0 0x12C reset value Equalizer Band 2 bandwidth selection 0 = narrow band characteristic (default) 1 = wide band characteristic EQ2BW Reserved Equalizer Band 2 center frequency selection 00 = 230Hz 01 = 300Hz (default) 10 = 385Hz 11 = 500Hz EQ Band 2 digital gain control. Expressed as a gain or attenuation in 1dB steps 01100 = 0.0dB default unity gain value EQ2CF 19 13 EQ2 – peak 1 00000 = +12dB 00001 = +11dB - all intermediate 1.0dB step values through minimum gain – 11000 = -12dB 11001 and larger values are reserved EQ2GC Default >> 0 0 0 1 0 1 1 EQ3BW 0 0 0x02C reset value Equalizer Band 3 bandwidth selection 0 = narrow band characteristic (default) 1 = wide band characteristic Reserved 20 14 EQ3 – peak 2 EQ3CF NAU8501 Datasheet Rev 1.9 Equalizer Band 3 center frequency selection 00 = 650Hz 01 = 850Hz (default) 10 = 1.1kHz 11 = 1.4kHz Page 67 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 EQ Band 3 digital gain control. Expressed as a gain or attenuation in 1dB steps 01100 = 0.0dB default unity gain value 00000 = +12dB 00001 = +11dB - all intermediate 1.0dB step values through minimum gain – 11000 = -12dB 11001 and larger values are reserved EQ3GC Default >> 0 0 0 1 0 1 1 0 0 0x02C reset value Equalizer Band 4 bandwidth selection 0 = narrow band characteristic (default) 1 = wide band characteristic EQ4BW Reserved Equalizer Band 4 center frequency selection 00 = 1.8kHz 01 = 2.4kHz (default) 10 = 3.2kHz 11 = 4.1kHz EQ Band 4 digital gain control. Expressed as a gain or attenuation in 1dB steps 01100 = 0.0dB default unity gain value EQ4CF 21 15 EQ4 – peak 3 00000 = +12dB 00001 = +11dB - all intermediate 1.0dB step values through minimum gain – 11000 = -12dB 11001 and larger values are reserved EQ4GC Default >> 0 0 0 1 0 1 1 0 0 0x02C reset value Reserved Equalizer Band 5 high pass -3dB cut-off frequency selection 00 = 5.3kHz 01 = 6.9kHz (default) 10 = 9.0kHz 11 = 11.7kHz EQ Band 5 digital gain control. Expressed as a gain or attenuation in 1dB steps 01100 = 0.0dB default unity gain value EQ5CF 22 16 EQ5 – high cutoff 00000 = +12dB 00001 = +11dB - all intermediate 1.0dB step values through minimum gain – 11000 = -12dB 11001 and larger values are reserved EQ5GC Default >> 23 17 Reserved 24 18 Reserved 25 19 Reserved 26 1A Reserved 0 0 0 1 0 1 1 NAU8501 Datasheet Rev 1.9 0 0 0x02C reset value Page 68 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Update bit feature for simultaneous change of all notch filter parameters. Write-only bit. Logic 1 on R27 register write operation causes new R27 value and any pending value in R28, R29, or R30 to go into effect. Logic 0 on R27 register write causes new value to be pending an update bit event on R27, R28, R29, or R30. Notch filter control bit 0 = disabled 1 = enabled NFCU1 27 1B Notch filter 1 NFCEN NFCA0[13:7] Default >> Notch filter A0 coefficient most significant bits. See text and table for details. 0 0 0 0 0 0 0 0 0 NFCU2 28 1C Notch filter 2 Reserved NFCAO[6:0] Default >> Notch filter A0 coefficient least significant bits. See text and table for details. 0 0 0 0 0 0 0 0 0 1D Notch filter 3 Reserved NFCA1[13:7] Default >> Notch filter A1 coefficient most significant bits. See text and table for details. 0 0 0 0 0 0 0 0 0 1E Notch filter 4 Reserved NFCA1[6:0] Default >> 31 1F 0x000 reset value Update bit feature for simultaneous change of all notch filter parameters. Write-only bit. Logic 1 on R30 register write operation causes new R30 value and any pending value in R27, R28, or R29 to go into effect. Logic 0 on R30 register write causes new value to be pending an update bit event on R27, R28, R29, or R30. NFCU4 30 0x000 reset value Update bit feature for simultaneous change of all notch filter parameters. Write-only bit. Logic 1 on R29 register write operation causes new R29 value and any pending value in R27, R28, or R30 to go into effect. Logic 0 on R29 register write causes new value to be pending an update bit event on R27, R28, R29, or R30. NFCU3 29 0x000 reset value Update bit feature for simultaneous change of all notch filter parameters. Write-only bit. Logic 1 on R28 register write operation causes new R28 value and any pending value in R27, R29, or R30 to go into effect. Logic 0 on R28 register write causes new value to be pending an update bit event on R27, R28, R29, or R30. Notch filter A1 coefficient least significant bits. See text and table for details. 0 0 0 0 0 0 0 0 0 0x000 reset value Reserved Automatic Level Control function control bits 00 = right and left ALCs disabled 01 = only right channel ALC enabled 10 = only left channel ALC enabled 11 = both right and left channel ALCs enabled ALCEN reserved Set maximum gain limit for PGA volume setting changes under ALC control 111 = +35.25dB (default) 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB Set minimum gain value limit for PGA volume setting changes under ALC control 000 = -12dB (default) 001 = -6.0dB 010 = 0.0dB 011 = +6.0dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB ALCMXGAIN 32 20 ALC control 1 ALCMNGAIN Default >> 33 0 0 0 1 1 1 0 21 NAU8501 Datasheet Rev 1.9 0 0 0x038 reset value Reserved Page 69 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Hold time before ALC automated gain increase 0000 = 0.00ms (default) 0001 = 2.00ms 0010 = 4.00ms - time value doubles with each bit value increment – 1001 = 512ms 1010 through 1111 = 1000ms ALC target level at ADC output 1111 = -1.5dB below full scale (FS) 1110 = -1.5dB FS (same value as 1111) 1101 = -3.0dB FS 1100 = -4.5dB FS 1011 = -6.0dB FS (default) - target level varies 1.5dB per binary step throughout control range – 0001 = -21.0dB FS 0000 = -22.5dB FS (lowest possible target signal level) ALCHT ALC control 2 ALCSL Default >> 0 0 0 0 0 1 0 1 1 ALC mode control setting 0 = normal ALC operation 1 = Limiter Mode operation ALC decay time duration per step of gain change for gain increase of 0.75dB of PGA gain. Total response time can be estimated by the total number of steps necessary to compensate for a given magnitude change in the signal. For example, a 6dB decrease in the signal would require eight ALC steps to compensate. Step size for each mode is given by: Normal Mode Limiter Mode 0000 = 500us 0000 = 125us 0001 = 1.0ms 0001 = 250us 0010 = 2.0ms (default) 0010 = 500us (default) ------- time value doubles with each binary bit value -------1000 = 128ms 1000 = 32ms 1001 = 256ms 1001 = 64ms 1010 through 1111 = 512ms 1010 through 1111 = 128ms ALC attack time duration per step of gain change for gain decrease of 0.75dB of PGA gain. Total response time can be estimated by the total number of steps necessary to compensate for a given magnitude change in the signal. For example, a 6dB increase in the signal would require eight ALC steps to compensate. Step size for each mode is given by: Normal Mode Limiter Mode 0000 = 125us 0000 = 31us 0001 = 250us 0001 = 62us 0010 = 500us (default) 0010 = 124us (default) ------- time value doubles with each binary bit value -------1000 = 26.5ms 1000 = 7.95ms 1001 = 53.0ms 1001 = 15.9ms 1010 through 1111 = 128ms 1010 through 1111 = 31.7ms ALCM ALCDCY 34 22 ALC control 3 ALCATK Default >> 35 23 Noise gate 0x00B reset value 0 0 0 1 1 0 0 Reserved NAU8501 Datasheet Rev 1.9 1 0 0x032 reset value Reserved Page 70 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 ALC noise gate function control bit 0 = disabled 1 = enabled ALC noise gate threshold level 000 = -39dB (default) 001 = -45dB 010 = -51dB 011 = -57dB 100 = -63dB 101 = -69dB 110 = -75dB 111 = -81dB ALCNEN ALCNTH Default >> 0 0 0 0 1 0 0 0 0 0x010 reset value Reserved Control bit for divide by 2 pre-scale of MCLK path to PLL clock input 0 = MCLK divide by 1 (default) 1 = MCLK divide by 2 Integer portion of PLL input/output frequency ratio divider. Decimal value should be constrained to 6, 7, 8, 9, 10, 11, or 12. Default decimal value is 8. See text for details. PLLMCLK 36 24 PLL N PLLN Default >> 0 0 0 0 0 1 0 0 0 0x008 reset value Reserved 37 25 PLL K 1 High order bits of fractional portion of PLL input/output frequency ratio divider. See text for details. PLLK[23:18] Default >> 0 0 0 0 0 1 1 0 0 PLLK[17:9] 38 26 PLL K 2 Default >> 0 1 0 0 1 0 0 1 1 27 PLL K 3 Default >> 40 28 0x093 reset value Low order bits of fractional portion of PLL input/output frequency ratio divider. See text for details. PLLK{8:0} 39 0x00C reset value Middle order bits of fractional portion of PLL input/output frequency ratio divider. See text for details. 0 1 1 1 0 1 0 0 1 0x0E9 reset value Reserved Reserved Reserved 41 29 3D control 3DDEPTH Default >> 42 2A Reserved 43 2B Reserved 3D Stereo Enhancement effect depth control 0000 = 0.0% effect (disabled, default) 0001 = 6.67% effect 0010 = 13.3% effect - effect depth varies by 6.67% per binary bit value – 1110 = 93.3% effect 1111 = 100% effect (maximum effect) 0 0 0 0 0 0 0 MICBIASV 44 2C Input control RLINRPGA RMICNRPGA NAU8501 Datasheet Rev 1.9 0 0 0x000 reset value Microphone bias voltage selection control. Values change slightly with R40 MISBIAS mode selection control. Open circuit voltage on MICBIAS pin#32 is shown as follows as a fraction of the VDDA pin#31 supply voltage. Normal Mode Low Noise Mode 00 = 0.9x 00 = 0.85x 01 = 0.65x 01 = 0.60x 10 = 0.75x 10 = 0.70x 11 = 0.50x 11 = 0.50x RLIN right line input path control to right PGA positive input 0 = RLIN not connected to PGA positive input (default) 1 = RLIN connected to PGA positive input RMICN right microphone negative input to right PGA negative input path control 0 = RMICN not connected to PGA negative input (default) 1 = RMICN connected to PGA negative input Page 71 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 RMICP right microphone positive input to right PGA positive input enable 0 = RMICP not connected to PGA positive input (default) 1 = RMICP connected to PGA positive input RMICPRPGA Reserved LLIN right line input path control to left PGA positive input 0 = LLIN not connected to PGA positive input (default) 1 = LLIN connected to PGA positive input LMICN left microphone negative input to left PGA negative input path control 0 = LMICN not connected to PGA negative input (default) 1 = LMICN connected to PGA negative input LMICP left microphone positive input to left PGA positive input enable 0 = LMICP not connected to PGA positive input (default) 1 = LMICP connected to PGA positive input LLINLPGA LMICNLPGA LMICPLPGA Default >> 0 0 0 1 1 0 0 1 1 LPGAU LPGAZC LPGAMT 45 2D Left input PGA gain 00 0000 = -12dB 00 0001 = -11.25dB - volume changes in 0.75dB steps per binary bit value – 11 1110 = +34.50dB 11 1111 = +35.25dB LPGAGAIN Default >> 0 0 0 0 1 0 0 0 0 RPGAZC RPGAMT 2E Right input PGA gain 00 0000 = -12dB 00 0001 = -11.25dB - volume changes in 0.75dB steps per binary bit value – 11 1110 = +34.50dB 11 1111 = +35.25dB RPGAGAIN Default >> 47 2F Left ADC boost 0x010 reset value PGA volume update bit feature. Write-only bit for synchronized L/R PGA changes If logic = 0 on R46 write, new R46 value stored in temporary register If logic = 1 on R46 write, new R46 and pending R45 values become active Right channel input zero cross detection enable 0 = gain changes to PGA register happen immediately 1 = gain changes to PGA happen pending zero crossing logic Right channel mute PGA mute control 0 = PGA not muted, normal operation (default) 1 = PGA in muted condition not connected to RADC Mix/Boost stage Right channel input PGA volume control setting. Setting becomes active when allowed by zero crossing and/or update bit features. 01 0000 = 0.0dB default setting RPGAU 46 0x033 reset value PGA volume update bit feature. Write-only bit for synchronized L/R PGA changes If logic = 0 on R45 write, new R45 value stored in temporary register If logic = 1 on R45 write, new R45 and pending R46 values become active Left channel input zero cross detection enable 0 = gain changes to PGA register happen immediately (default) 1 = gain changes to PGA happen pending zero crossing logic Left channel mute PGA mute control 0 = PGA not muted, normal operation (default) 1 = PGA in muted condition not connected to LADC Mix/Boost stage Left channel input PGA volume control setting. Setting becomes active when allowed by zero crossing and/or update bit features. 01 0000 = 0.0dB default setting 0 0 0 0 1 0 0 LPGABST NAU8501 Datasheet Rev 1.9 0 0 0x010 reset value Left channel PGA boost control 0 = no gain between PGA output and LPGA Mix/Boost stage input 1 = +20dB gain between PGA output and LPGA Mix/Boost stage input Page 72 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Reserved Gain value between LLIN line input and LPGA Mix/Boost stage input 000 = path disconnected (default) 001 = -12dB 010 = -9.0dB 011 = -6.0dB 100 = -3.0dB 101 = 0.0dB 110 = +3.0dB 111 = +6.0dB LPGABSTGAIN Reserved Default >> 1 0 0 0 0 0 0 0 0 0x100 reset value Right channel PGA boost control 0 = no gain between PGA output and RPGA Mix/Boost stage input 1 = +20dB gain between PGA output and RPGA Mix/Boost stage input RPGABST Reserved 48 30 Gain value between RLIN line input and RPGA Mix/Boost stage input 000 = path disconnected (default) 001 = -12dB 010 = -9.0dB 011 = -6.0dB 100 = -3.0dB 101 = 0.0dB 110 = +3.0dB 111 = +6.0dB Right ADC boost RPGABSTGAIN Reserved Default >> 1 0 0 0 0 0 0 0 0 0x100 reset value Reserved Thermal shutdown enable protects chip from thermal destruction on overload 0 = disable thermal shutdown (engineering purposes, only) 1 = enable (default) strongly recommended for normal operation Output resistance control option for tie-off of unused or disabled outputs. Unused outputs tie to internal voltage reference for reduced pops and clicks. 0 = nominal tie-off impedance value of 1kΩ (default) 1 = nominal tie-off impedance value of 30kΩ TSEN 49 31 Output control AOUTIMP Default >> 0 0 0 0 0 0 0 1 0 0x002 reset value Reserved 50 32 Left mixer Configure bypass path from LADC Mix/Boost output to LMAIN left output mixer. 00001 = path not connected 10110 = path connected LBYPCTRL Default >> 0 0 0 0 0 0 0 0 1 0x001 reset value Reserved 51 33 Right mixer Configure bypass path from RADC Mix/Boost output to LMAIN left output mixer. 00001 = path not connected 10110 = path connected RBYPCTRL Default >> 0 0 0 0 0 0 0 LOUTVU 52 34 Left LineOut Volume LOUTZC LOUTMUT NAU8501 Datasheet Rev 1.9 0 1 0x001 reset value Line output volume update bit feature. Write-only bit for synchronized changes of left and right line output amplifier output settings If logic = 0 on R52 write, new R52 value stored in temporary register If logic = 1 on R52 write, new R52 and pending R53 values become active Left channel input zero cross detection enable 0 = gain changes to left line output happen immediately (default) 1 = gain changes to left line output happen pending zero crossing logic Left line output mute control 0 = line output not muted, normal operation (default) 1 = line in muted condition Page 73 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Left line output output volume control setting. Setting becomes active when allowed by zero crossing and/or update bit features. 11 1001 = 0.0dB default setting 00 0000 = -57dB 00 0001 = -56dB - volume changes in 1.0dB steps per binary bit value – 11 1110 = +5.0dB 11 1111 = +6.0dB LOUTVOL Default >> 0 0 0 1 1 1 0 0 1 Line output volume update bit feature. Write-only bit for synchronized changes of left and right line output amplifier output settings If logic = 0 on R53 write, new R53 value stored in temporary register If logic = 1 on R53 write, new R53 and pending R52 values become active Right channel input zero cross detection enable 0 = gain changes to right line output happen immediately (default) 1 = gain changes to right line output happen pending zero crossing logic Right line output mute control 0 = output not muted, normal operation (default) 1 = output in muted condition Right line output output volume control setting. Setting becomes active when allowed by zero crossing and/or update bit features. 11 1001 = 0.0dB default setting ROUTVU ROUTZC 53 35 Right Line Out Volume ROUTMUT 00 0000 = -57dB 00 0001 = -56dB - volume changes in 1.0dB steps per binary bit value – 11 1110 = +5.0dB 11 1111 = +6.0dB ROUTVOL Default >> 54 36 Reserved 55 37 Reserved 56 38 Reserved 57 39 Reserved 0x039 reset value 0 0 0 1 1 1 0 0 1 0x039 reset value Reserved LPIPBST 58 Power 3A Management 4 LPADC Reduce ADC Mix/Boost amplifier supply current 50% in low power operating mode 0 = normal supply current operation (default) 1 = 50% reduced supply current mode Reduce ADC supply current 50% in low power operating mode 0 = normal supply current operation (default) 1 = 50% reduced supply current mode Reserved MICBIASM NAU8501 Datasheet Rev 1.9 Microphone bias optional low noise mode configuration control 0 = normal configuration with low-Z micbias output impedance 1 = low noise configuration with 200-ohm micbias output impedance Page 74 of 80 Jul, 2018 Register Function Name Dec Hex Bit Description 8 7 6 5 43 2 1 0 Regulator voltage control power reduction options 00 = normal 1.80Vdc operation (default) 01 = 1.61Vdc operation 10 = 1.40 Vdc operation 11 = 1.218 Vdc operation Master bias current power reduction options 00 = normal operation (default) 01 = 25% reduced bias current from default 10 = 14% reduced bias current from default 11 = 25% reduced bias current from default REGVOLT IBADJ Default >> 0 0 0 0 0 0 0 0 0 LTSLOT[8:0] 59 3B Left time slot Default >> 0 0 0 0 0 0 0 0 0 TRI Tri state ADC out after second half of LSB enable PCM8BIT 8-bit word length enable ADCOUT output driver 1 = enabled (default) 0 = disabled (driver in high-z state) ADCOUT passive resistor pull-up or passive pull-down enable 0 = no passive pull-up or pull-down on ADCOUT pin 1 = passive pull-up resistor on ADCOUT pin if PUDPS = 1 1 = passive pull-down resistor on ADCOUT pin if PUDPS = 0 ADCOUT passive resistor pull-up or pull-down selection 0 = passive pull-down resistor applied to ADCOUT pin if PUDPE = 1 1 = passive pull-down resistor applied to ADCOUT pin if PUDPE = 1 PUDEN PUDPE 3C 0x000 reset value Time slot function enable for PCM mode. PCMTSEN 60 0x000 reset value Left channel PCM time slot start count: LSB portion of total number of bit times to wait from frame sync before clocking audio channel data. LSB portion is combined with MSB from R60 to get total number of bit times to wait. Misc. PUDPS Reserved Right channel PCM time slot start count: MSB portion of total number of bit times to wait from frame sync before clocking audio channel data. MSB is combined with LSB portion from R61 to get total number of bit times to wait. Left channel PCM time slot start count: MSB portion of total number of bit times to wait from frame sync before clocking audio channel data. MSB is combined with LSB portion from R59 to get total number of bit times to wait. RTSLOT[9] LTSLOT[9] Default >> 61 3D Right time slot 62 63 3E 3F Device ID# 0 0 0x020 reset value Right channel PCM time slot start count: LSB portion of total number of bit times to wait from frame sync before clocking audio channel data. LSB portion is combined with MSB from R60 to get total number of bit times to wait. RTSLOT[8:0] Default >> Device Revision Number 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0x000 reset value Reserved REV Default >> Device Revision Number for readback over control interface = read-only value 0 0 1 1 1 1 1 0 1 0x0FD for RevC silicon 0 0 0 0 1 1 0 1 0 0x01A Device ID equivalent to control bus address = read-only value NAU8501 Datasheet Rev 1.9 Page 75 of 80 Jul, 2018 14 Appendix D: Register Overview DEC HEX NAME Bit 8 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 00 Software Reset RESET (SOFTWARE) 1 01 Power Management 1 Reserved PLLEN MICBIASEN ABIASEN IOBUFEN REFIMP 2 02 Power Management 2 RLINEN LLINEN SLEEP RBSTEN LBSTEN RPGAEN LPGAEN RADCEN LADCEN 3 03 Power Management 3 Reserved RBYPEN LBYPEN Reserved General Audio Controls 4 04 Audio Interface BCLKP LRP WLEN AIFMT Reserved ADCPHS MONO 5 05 Companding Reserved CMB8 Reserved ADCCM Reserved 6 06 Clock Control 1 CLKM MCLKSEL BCLKSEL Reserved CLKIOEN 7 07 Clock Control 2 4WSPIEN Reserved SMPLR SCLKEN 8 08 GPIO Reserved GPIO1PLL GPIO1PL GPIO1SEL 9 09 Jack Detect 1 JCKMIDEN JCKDEN JCKDIO Reserved 10 0A Reserved Reserved 11 0B Reserved Reserved 12 0C Reserved Reserved 13 0D Jack Detect 2 Reserved JCKDOEN1 JCKDOEN0 14 0E ADC Control HPFEN HPFAM HPF ADCOS Reserved RADCPL LADCPL 15 F Left ADC Volume LADCVU LADCGAIN 16 10 Right ADC Volume RADCVU RADCGAIN 17 11 Reserved Equalizer 18 12 EQ1-low cutoff EQM Reserved EQ1CF EQ1GC 19 13 EQ2-peak 1 EQ2BW Reserved EQ2CF EQ2GC 20 14 EQ3-peak 2 EQ3BW Reserved EQ3CF EQ3GC 21 15 EQ4-peak3 EQ4BW Reserved EQ4CF EQ4GC 22 16 EQ5-high cutoff Reserved EQ5CF EQ5GC 23 17 Reserved Notch Filter 27 1B Notch Filter 1 NFCU1 NFCEN NFCA0[13:7] 28 1C Notch Filter 2 NFCU2 Reserved NFCA0[6:0] 29 1D Notch Filter 3 NFCU3 Reserved NFCA1[13:7] 30 1E Notch Filter 4 NFCU4 Reserved NFCA1[6:0] 31 1F Reserved ALC and Noise Gate Control 32 20 ALC Control 1 ALCEN Reserved ALCMXGAIN ALCMNGAIN 33 21 ALC Control 2 Reserved ALCHT ALCSL 34 22 ALC Control 3 ALCM ALCDCY ALCATK 35 23 Noise Gate Reserved ALCTBLSEL ALCNEN ALCNTH Phase Locked Loop 36 24 PLL N Reserved PLLMCLK PLLN 37 25 PLL K 1 Reserved PLLK[23:18] 38 26 PLL K 2 PLLK[17:9] 39 27 PLL K 3 PLLK[8:0] 40 28 Mic Bias Mode Reserved MICBIASM Miscellaneous 41 29 3D control Reserved 3DDEPTH 42 2A Reserved 43 2B Reserved 44 2C Input Control MICBIASV RLINRPGA RMICNRPGA RMICPRPGA Reserved LLINLPGA LMICNLPGA LMICPLPGA 45 2D Left Input PGA Gain LPGAU LPGAZC LPGAMT LPGAGAIN 46 2E Right Input PGA Gain RPGAU RPGAZC RPGAMT RPGAGAIN 47 2F Left ADC Boost LPGABST Reserved LPGABSTGAIN Reserved 48 30 Right ADC Boost RPGABST Reserved RPGABSTGAIN Reserved 49 31 Output Control Reserved TSEN AOUTIMP 50 32 Left Bypass Control Reserved LBYPCTRL 51 33 Right Bypass Control Reserved RBYPCTRL 52 34 L Line Out Volume LOUTVU LOUTZC LOUTMUT LOUTVOL 53 35 R Line Out Volume ROUTVU ROUTZC ROUTMUT ROUTVOL 54 36 Reserved 55 37 Reserved 56 38 Reserved 57 39 Reserved 58 3A Power Management 4 Reserved LPIPBST LPADC Reserved MICBIASM REGVOLT IBADJ PCM Time Slot and ADCOUT Impedance Option Control 59 3B Left Time Slot LTSLOT[8:0] 60 3C Misc PCMTSEN TRI PCM8BIT PUDEN PUDPE PUDPS Reserved RTSLOT[9] LTSLOT[9] 61 3D Right Time Slot RTSLOT[8:0] Silicon Revision and Device ID 62 3E Device Revision # Reserved REV-C 63 3F Device ID ID NAU8501 Datasheet Rev 1.9 Page 76 of 80 Jul, 2018 Default 000 000 050 000 140 000 000 000 000 0FF 0FF 000 100 0FF 0FF 12C 02C 02C 02C 02C 000 000 000 000 038 00B 032 010 008 00C 093 0E9 000 000 033 010 010 100 100 002 001 001 039 039 000 000 020 000 0FD 01A 15 Package Dimensions 32-lead plastic QFN 32L; 5X5mm2, 0.8mm thickness, 0.5mm lead pitch 32 25 1 24 8 17 9 16 25 32 24 1 17 8 16 NAU8501 Datasheet Rev 1.9 9 Page 77 of 80 Jul, 2018 16 Ordering Information Part Number Dimension Package Package Material NAU8501YG 4x4 mm QFN-32 Green NAU8501 _ _ Package Material: G = Pb-free Package Package Type: Y NAU8501 Datasheet Rev 1.9 = 32-Pin QFN Package Page 78 of 80 Jul, 2018 REVISION HISTORY VERSION DATE PAGE DESCRIPTION 0.6 July 29, 2009 n/a Draft Release 1.0 Nov. 07, 2009 n/a Draft Release 1.1 June 30, 2010 n/a First Release 1.2 July 20, 2010 n/a Major revision and update 1.3 July 22, 2010 All Change name to “data sheet” 1.4 October, 2013 48 6 1.5 Feb, 2014 5, 6, 38, 39, 49, 50 1.6 Nov. 2014 48 Corrected Tsdios setup time 1.7 Jan 2015 1 Updated AECQ100 description 1.8 March 2016 34 Revise f1 equation from * to / 1.9 July 2018 50 I2C filter Corrected 2 wire interface timing diagram Corrected Digital I/O voltage levels from DCVDD to DBVDD Replaced VDDSPK by VDDA2 Replaced AVDD by VDDA Modified application diagram Modified Figure 17 (Byte Write Sequence) Modified Figure 18 (2-Wire Read Sequence) Corrected rising/fall time specification of I2S Table 22: Revision History NAU8501 Datasheet Rev 1.9 Page 79 of 80 Jul, 2018 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. NAU8501 Datasheet Rev 1.9 Page 80 of 80 Jul, 2018