STDP4020, STDP4010
DisplayPort receiver
Datasheet
Rev A
MegaChips’ Proprietary Information
MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips
does not assume any responsibility or liability arising out of application or use of any product or
service described herein except as explicitly agreed upon.
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Page 1 of 43
STDP4020, STDP4010
Features
•
Enhanced DisplayPort® (DP) receiver
– DP 1.1a compliant
– Embedded DisplayPort (eDP) compliant
– 1, 2, or 4 lanes
•
Higher bandwidth “Turbo mode” (3.24 Gbps
per lane), supports:
– 1920 x 1080 (FHD) 120 Hz/10-bit color
video standard timings and 7.1 Ch audio
– 2560 x 1600 (WQXGA), 2560 x 2048
(QSXGA) 60 Hz/10-bit color graphics and
7.1 Ch audio
•
Interface compatibility with wide range of
display controller ICs
– LVTTL (60 wide) and LVDS (quad bus)
video interface
– 8-Ch I2S and SPDIF audio interface
•
Robust AUX channel
– Link service, maintenance
– I2C-over-AUX (MCCS, DDC)
– IR, full duplex UART protocol
•
HDCP repeater capability
– Acts as upstream receiver
•
AUX to I2C bridge for EDID, MCCS pass
through
•
Spread spectrum on DisplayPort, LVDS, and
TTL interfaces for EMI reduction
•
Supports deep color and color format
conversion
– RGB/YUV (4:4:4) – 10-bit color
– YUV (4:2:2/4:2:0) – 12-bit color
– RGB (4:4:4) to YUV (4:4:4) conversion and
vice-versa
•
Supports HBR/“Turbo” speed over HBR/RBRrated long cables (15 m and more)
•
Package
– 164 LFBGA (12 x 12 mm / 0.8 mm)
•
Power supply voltages
– 3.3 V I/O; 1.2 V core
Applications
•
•
Configurable through I2C host interface
•
Supports HDCP 1.3 with on-chip keys
Digital TV, LCD monitor, mobile display,
projector, etc
.
DP Input
Q-LVDS/
TTL Video
I2S/SPDIF
Transmitter
I2S/SPDIF
Audio
DisplayPort
Receiver
I2C Host
Interface
C4020-DAT-01p
Bus Formatter
LVDS/TTL Outputs
Crystal
Oscillator
(Optional)
GPIO
I2C
Master
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STDP4020, STDP4010
Contents
1.
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.
Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.
Feature attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.
BGA footprint and pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.
6.
4.1
Ball grid array diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Full pin list sorted by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2
Bootstrap configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
General purpose input/output (GPIO) pins . . . . . . . . . . . . . . . . . . . . . . . . 27
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1
7.
Marking field template and descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2
Maximum speed of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.1
DisplayPort receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4.2
Digital video output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4.3
LVDS transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4.4
I2C interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4.5
SPI interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
C4020-DAT-01p
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Page 3 of 43
STDP4020, STDP4010
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 7.
Table 6.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Key to BGA diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DisplayPort receiver pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reference clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital video outputs - LVDS & TTL (suggested mapping) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multi-function and system interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Multi-function - digital audio output, general purpose input/output, bootstrap pins. . . . . . . 22
No connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
System power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Bootstrap configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Software implemented bootstrap configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Field descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DisplayPort receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Digital video output port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LVDS TX1 even channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LVDS TX1 odd channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LVDS TX2 even channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
LVDS TX2 odd channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I2C interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SPI interface timing, VDD = 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
C4020-DAT-01p
MegaChips’ Proprietary Information
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STDP4020, STDP4010
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
System interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Marking template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Display output port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LVDS transmitter switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SPI output or serial interface SPI ROM input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SPI input or serial interface SPI ROM output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
C4020-DAT-01p
MegaChips’ Proprietary Information
Page 5 of 43
STDP4020, STDP4010
1.
Description
The STDP4020 is a DisplayPort receiver IC for the reception of secure, high-bandwidth uncompressed
digital audio-video signals targeted for applications such as DTV, LCD monitor, projector, and other types
of display systems. STDP4020 is a VESA DP 1.1a and eDP compliant device, implementing a single link
DisplayPort input port comprising four main lanes, auxiliary channel, and HPD. In addition to the
standard HBR (2.7 Gbps) and RBR (1.62 Gbps) speeds, this device supports turbo speed of 3.24 Gbps
per lane with a total link bandwidth of 12.96 Gbps. The higher bandwidth provides unique benefits to
users over other commercial DP receivers for embedded applications by offering additional margin to
support higher color depth, resolution, and refresh rate. For example, STDP4020 supports FHD nonreduced blanking video (1080p 30-bit color per pixel) at 120 Hz, plus 7.1 Ch audio for two-box TV
applications.The advanced equalizer built in this device offers guaranteed performance over long reach
cables. The auxiliary channel in STDP4020 acts as a bidirectional communication link, supporting
application-specific protocols such as MCCS, DDC, UART, IR, as well as the dedicated DisplayPort link
training and device management functions.
The STDP4020 supports RGB and YUV video color formats with color depth of 12 (YUV 4:2:2 only), 10,
and 8 bits. This device offers LVDS and LVTTL output interfaces configurable to map a wide range of
display controller products. The Quad LVDS interface supports video signals up to 400 MHz pixel rate
with flexible channel and lane swapping options. The 60-bit LVTTL output ports can be mapped to
transfer video data either in two pixels per clock or single pixel per clock up to 330 MHz pixel rate, which
opens up possibilities for 3D applications. The STDP4020 also supports both compressed and
uncompressed audio formats. The extracted audio signal is transferred on a digital audio output bus. This
device comprises four I2S audio output, supporting up to 8 channel LPCM audio and a single wire
S/PDIF output for encoded audio. The STDP4020 features the HDCP 1.3 content protection scheme with
an embedded key option for secure reception of digital audio-video content. In addition, it also supports
the HDCP repeater function and, thus acts as an upstream receiver suitable for two-box TV and
HDMI/DVI converter applications.
The STDP4020 is configurable from an external host controller through I2C host interface. This IC also
includes general-purpose inputs/outputs for controlling system components. The STDP4020 features a
color space converter (RGB to YUV and YUV to RGB) for flexible interface with external video
processing devices.
C4020-DAT-01p
MegaChips’ Proprietary Information
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STDP4020, STDP4010
STDP4020 family product includes the following part numbers:
Part number
Video input
Video output
Max video resolution
STDP4020
4 lanes DisplayPort
4 Ch LVDS/60 LVTTL
WQXGA/FHD 120 Hz
STDP4010
2 lanes DisplayPort
2 Ch LVDS/30 LVTTL
WUXGA/FHD 60 Hz
C4020-DAT-01p
MegaChips’ Proprietary Information
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STDP4020, STDP4010
2.
Application overview
The STDP4020 is designed as a DisplayPort front-end capture device for display applications. Typical
display design has a display controller (scaler) that acts as system master (host). The host controller
configures STDP4020 through a 2-wire host interface. The host and STDP4020 also use interrupt
mechanism whenever the slave needs attention. The STDP4020 may require an external SPI Flash to
store firmware for supporting custom specific applications. The audio and video output from STDP4020
can directly interface to the host display controller for further processing. The AUX I2C bypass channel
handles the I2C traffic between STDP4020 and host controller, as shown in the figure below.
Figure 1. System interface block diagram
SPI
Flash
SPI
Display
DP Connector
Host I2C
2
I C slave
Main Link
DP / LVDS
INTR
STDP4020
AUX CH
I2C Master
TTL / LVDS
Video Controller /
Host Controller
Video
HPD_out
SPDIF/I2S
2
AUX I C
Audio
DDC input
L/R audio
Audio
Amp
DP
EDID
Speakers
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Page 8 of 43
STDP4020, STDP4010
3.
Feature attributes
• Enhanced DisplayPort (DP) receiver compliant with DP1.1a and embedded (eDP) specification
• Supports higher bandwidth mode called “Turbo mode” (3.24 Gbps per lane) for embedded
applications. For example, supports FHD 120 Hz-10/12-bit video or QSXGA (2560 x 2048) 60
Hz/10-bit color graphics and 7.1 Ch audio
• Interface compatibility with wide range of display products. Supports LVTTL (60 wide) and quad
LVDS video interface
• Supports I2S 8 Ch and SPDIF audio output interface compliant with IEC60958 and IEC61937
audio formats.
• Robust AUX channel for Link service, maintenance and supports I2C over AUX, MCCS, DDC,
IR and full duplex UART protocol
• Supports HDCP 1.3 with on-chip key storage
• Acts HDCP repeater for an upstream receiver
• Supports AUX to I2C bridge for EDID, MCCS pass through
• Spread spectrum on DisplayPort, LVDS and TTL interfaces for EMI reduction
• Supports deep color and color format conversion: RGB (4:4:4) to YUV (4:4:4) and vice-versa
• Supports TTL up to 330 MHz pixel clock, which allows 3D video applications
• Supports HBR/“Turbo” speed over HBR/RBR rated long cables (15 m and more)
• Configurable through I2C host interface
• Package: 164 LFBGA (12 x 12 mm / 0.8 mm)
• Power supply voltages: 3.3 V I/O; 1.2 V core
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STDP4020, STDP4010
4.
BGA footprint and pin lists
4.1
Ball grid array diagram
The ball grid array (BGA) diagrams give the allocation of pins to the package, shown from the top looking
down using the PCB footprint.
Some signal names in BGA diagrams have been abbreviated. Refer toTable 2: Pin list on page 12 for full
signal names sorted by pin number.
Table 1. Key to BGA diagrams
Function
Type
DisplayPort input
SIG
Reference clocks
SIG
System controls
SIG
Multi-function and system interface connections
SIG
I2S/SPDIF audio output
SIG
LVDS/TTL Output_Even-0
SIG
LVDS/TTL Output_Even-1
SIG
LVDS/TTL Output_Odd-0
SIG
LVDS/TTL Output_Odd-1
SIG
Analog power
VCC/VDD
Analog ground
VSS/GND
System power
VCC/VDD
System ground
VSS/GND
No connect/Do not connect
NC/DNC
No ball
C4020-DAT-01p
MegaChips’ Proprietary Information
Page 10 of 43
Key
C4020-DAT-01p
PVSS3
I2S_1/BO
OT3/GPIO
_9
I2S_2/BO
OT4/GPIO
_10
Page 11 of 43
MegaChips’ Proprietary Information
E1_LVTX_
CH0N
E0_LVTX_
CH4N
E0_LVTX_
CH4P
2
AVDD_
OUT_LV
TX_33
AVSS_O
UT_LV T
X
1
N
P
3
E0_LVTX_
CH3P
E0_LVTX_
CH3N
E0_LVTX_
CH6P
E1_LVTX_
CH1N
4
E0_LVTX_
CLKP
E0_LVTX_
CLKN
E0_LVTX_
CH6N
E1_LVTX_
CH2N
E1_LVTX_
CH2P
E1_LVTX_
CH1P
E1_LVTX_
CH6P
E1_LVTX_
CLKN
E1_LVTX_
CLKP
E1_LVTX_
CH5N
IR_IN/GPI
O_12
E1_LVTX_
CH3N
E1_LVT
X_CH0P
E1_LVT
X_CH3P
TES TMOD
E1
TES TMOD
E0
AVDD_OU
T_LV TX_3
3
E1_LVTX_
CH4N
M
L
K
J
H
G
F
E1_LVT
X_CH4P
PVSS3
PVDD22
UART_RX
/GPIO_14
I2S_3/BO
OT5/GPIO
_11
E
AVSS_OU
T_LV TX
RESETn
VBUFC_R
PLL
I2S_MCLK
/GPIO_4
D
I2S_WCL
K/BOOT0/
GPIO_6
5
E0_LVTX_
CH2P
E0_LVTX_
CH2N
E1_LVTX_
CH6N
E1_LVTX_
CH5P
AVSS_OU
T_LV TX
DPRX_ML
_L3N
DPRX_ML
_L3P
PVSS3
GPIO_1
I2S_BCLK
/BOOT1/G
PIO_7
CLK_OU
T/GPIO_
5
6
E0_LVTX_
CH1P
E0_LVTX_
CH1N
E0_LVTX_
CH5N
PVDD1
PVSS3
PVSS3
GPIO_0
VDDA_3V
3
DPRX_ML
_L2N
DPRX_ML
_L2P
C
VDD_RPL
L
NC5
VSS_RPL
L
TCLK
I2S_0/B
OOT2/G
PIO_8
6
B
5
XTAL
4
A
3
2
1
UART_T
X/BOOT
6/GPIO_
13
7
7
E0_LVTX_
CH0P
E0_LVTX_
CH0N
E0_LVTX_
CH5P
AVDD_LV
TX_33
AVSS_LV
TX
PVSS3
PVSS3
PVSS3
PVSS3
PVDD1
DPRX_VS
SA
DPRX_VD
DA_1V2
DPRX_ML
_L1N
DPRX_ML
_L1P
8
8
O0_LVTX
_CH4P
O0_LVTX
_CH4N
9
O0_LVTX
_CH3P
O0_LVTX
_CH3N
O0_LVTX
_CH5N
AVDD_OU
T_LV TX_3
3
O0_LVTX
_CH5P
PVDD1
PVSS3
PVSS3
PVSS3
PVSS3
DPRX_VS
SA
DPRX_VD
DA_1V2
DPRX_AU
XP
DPRX_AU
XN
9
AVSS_OU
T_LV TX
PVSS3
PVSS3
PVSS3
PVSS3
PVDD1
DPRX_VS
SA
DPRX_VD
DA_1V2
DPRX_ML
_L0N
DPRX_ML
_L0P
10
O0_LVTX
_CLKP
O0_LVTX
_CLKN
O1_LVTX
_CH6P
O1_LVTX
_CH5P
AVSS_OU
T_LV TX
I2C_MST_
SCL/GPIO
_2
PVDD21
DPRX_VS
SA
DPRX_HP
D_OUT/G
PIO_26
DPRX_RE
XT
10
11
O0_LVTX
_CH2P
O0_LVTX
_CH2N
O0_LVTX
_CH6P
O1_LVTX
_CLKN
O1_LVTX
_CH6N
O1_LVTX
_CH5N
NC1
I2C_MST_
SDA/GPIO
_3
SPI_DO/G
PIO_20
I2C_SDA/
GPIO_22
NC3
DPRX_VD
DA_1V2
11
12
O0_LVTX
_CH1P
O0_LVTX
_CH1N
O0_LVTX
_CH6N
O1_LVTX
_CH3P
O1_LVTX
_CLKP
O1_LVTX
_CH2P
AVDD_OU
T_LV TX_3
3
NC2
SPI_CSn/
GPIO_17
SPI_CLK/
GPIO_18
IRQ/GPIO
_25
PVDD1
13
O0_LVTX
_CH0P
O0_LVTX
_CH0N
O1_LVTX
_CH4P
O1_LVTX
_CH3N
O1_LVTX
_CH2N
O1_LVTX
_CH1P
O1_LVTX
_CH0P
AVSS_OU
T_LV TX
SPI_DI/
GPIO_19
AUX_I2C_
SCL/GPIO
_15
I2C_SCL/
GPIO_21
AUX_UAR
T_ TX/BO
OT7/GPIO
_23
13
NC4
12
AUX_UAR
T_RX/GPI
O_24
14
AVSS_OU
T_LV TX
AVDD_OU
T_LV TX_3
3
O1_LVTX
_CH4N
O1_LVTX
_CH1N
O1_LVTX
_CH0N
PVSS3
AUX_I2C_
SDA/GPIO
_16
PVSS3
14
P
N
M
L
K
J
H
G
F
E
D
C
B
A
STDP4020, STDP4010
The STDP4020 is available in a 164-pin LFBGA package.
Figure 2. Pin diagram
STDP4020, STDP4010
4.2
Full pin list sorted by pin number
Table 2. Pin list
Pin number
A1
UART_TX/BOOT[6]/GPIO_13
A2
XTAL
A3
TCLK
A7
DPRX_ML_L1P
A8
DPRX_ML_L0P
A12
AUX_UART_RX/GPIO_24
A13
NC4
A14
PVSS3
B1
I2S_0/BOOT[2]/GPIO_8
B2
VSS_RPLL
B3
VDD_RPLL
B4
NC5
B6
DPRX_ML_L2P
B7
DPRX_ML_L1N
B8
DPRX_ML_L0N
B9
DPRX_AUXN
B11
DPRX_VDDA_1V2
B12
AUX_UART_TX/BOOT[7]/GPIO_23
B13
I2C_SCL/GPIO_21
B14
AUX_I2C_SDA/GPIO_16
C1
CLK_OUT/GPIO_5
C2
I2S_BCLK/BOOT[1]/GPIO_7
C3
GPIO_1
C4
PVSS3
C5
DPRX_ML_L3P
C6
DPRX_ML_L2N
C7, C8
C4020-DAT-01p
Net name
DPRX_VDDA_1V2
C9
DPRX_AUXP
C10
DPRX_REXT
C11
NC3
C12
PVDD1
C13
AUX_I2C_SCL/GPIO_15
C14
PVSS3
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STDP4020, STDP4010
Table 2. Pin list (continued)
Pin number
D2
I2S_MCLK/GPIO_4
D3
I2S_WCLK/BOOT[0]/GPIO_6
D4
VBUFC_RPLL
D5
DPRX_ML_L3N
D6
VDDA_3V3
D7, D8
DPRX_VSSA
D9
DPRX_VDDA_1V2
D10
DPRX_HPD_OUT/GPIO_26
D11
I2C_SDA/GPIO_22
D12
IRQ/GPIO_25
D13
SPI_DI/GPIO_19
E3
I2S_3/BOOT[5]/GPIO_11
E4
UART_RX/GPIO_14
E5
RESETn
E6
GPIO_0
E7, E8
PVDD1
E9, E10
DPRX_VSSA
E11
SPI_DO/GPIO_20
E12
SPI_CLK/GPIO_18
F2
AVSS_OUT_LVTX
F3
TESTMODE0
F4
I2S_2/BOOT[4]/GPIO_10
F5
PVDD22
F6, F7, F8, F9
PVSS3
F10
PVDD21
F11
I2C_MST_SDA/GPIO_3
F12
SPI_CSn/GPIO_17
F13
AVSS_OUT_LVTX
G1
E1_LVTX_CH4P
G2
E1_LVTX_CH4N
G3
TESTMODE1
G4
IR_IN/GPIO_12
G5
I2S_1/BOOT[3]/GPIO_9
G6, G7, G8, G9
G10
C4020-DAT-01p
Net name
PVSS3
I2C_MST_SCL/GPIO_2
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STDP4020, STDP4010
Table 2. Pin list (continued)
Pin number
G11
NC1
G12
NC2
G13
O1_LVTX_CH0P
G14
O1_LVTX_CH0N
H1
E1_LVTX_CH3P
H2
E1_LVTX_CH3N
H3
AVDD_OUT_LVTX_33
H4
E1_LVTX_CH5N
H5
AVSS_OUT_LVTX
H6, H7, H8, H9
PVSS3
H10
AVSS_OUT_LVTX
H11
O1_LVTX_CH5N
H12
AVDD_OUT_LVTX_33
H13
O1_LVTX_CH1P
H14
O1_LVTX_CH1N
J2
E1_LVTX_CLKP
J3
E1_LVTX_CLKN
J4
E1_LVTX_CH6P
J5
E1_LVTX_CH5P
J6, J7, J8, J9
C4020-DAT-01p
Net name
PVSS3
J10
O1_LVTX_CH5P
J11
O1_LVTX_CH6N
J12
O1_LVTX_CH2P
J13
O1_LVTX_CH2N
K3
E1_LVTX_CH2P
K4
E1_LVTX_CH2N
K5
E1_LVTX_CH6N
K6
PVDD1
K7
AVSS_LVTX
K8
AVSS_OUT_LVTX
K9
PVDD1
K10
O1_LVTX_CH6P
K11
O1_LVTX_CLKN
K12
O1_LVTX_CLKP
L2
E1_LVTX_CH1P
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STDP4020, STDP4010
Table 2. Pin list (continued)
Pin number
C4020-DAT-01p
Net name
L3
E1_LVTX_CH1N
L4
E0_LVTX_CH6N
L5
E0_LVTX_CH2N
L6
E0_LVTX_CH5N
L7
AVDD_LVTX_33
L8
AVDD_OUT_LVTX_33
L9
O0_LVTX_CH5N
L10
O0_LVTX_CLKN
L11
O0_LVTX_CH6P
L12
O1_LVTX_CH3P
L13
O1_LVTX_CH3N
M1
E1_LVTX_CH0P
M2
E1_LVTX_CH0N
M3
E0_LVTX_CH6P
M4
E0_LVTX_CLKN
M5
E0_LVTX_CH2P
M6
E0_LVTX_CH1N
M7
E0_LVTX_CH5P
M8
O0_LVTX_CH5P
M9
O0_LVTX_CH3N
M10
O0_LVTX_CLKP
M11
O0_LVTX_CH2N
M12
O0_LVTX_CH6N
M13
O1_LVTX_CH4P
M14
O1_LVTX_CH4N
N1
AVDD_OUT_LVTX_33
N2
E0_LVTX_CH4N
N3
E0_LVTX_CH3N
N4
E0_LVTX_CLKP
N6
E0_LVTX_CH1P
N7
E0_LVTX_CH0N
N8
O0_LVTX_CH4N
N9
O0_LVTX_CH3P
N11
O0_LVTX_CH2P
N12
O0_LVTX_CH1N
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STDP4020, STDP4010
Table 2. Pin list (continued)
Pin number
C4020-DAT-01p
Net name
N13
O0_LVTX_CH0N
N14
AVDD_OUT_LVTX_33
P1
AVSS_OUT_LVTX
P2
E0_LVTX_CH4P
P3
E0_LVTX_CH3P
P7
E0_LVTX_CH0P
P8
O0_LVTX_CH4P
P12
O0_LVTX_CH1P
P13
O0_LVTX_CH0P
P14
AVSS_OUT_LVTX
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STDP4020, STDP4010
5.
Connections
5.1
Pin list
I/O Legend: I = Input; O = Output; P = Power; G = Ground
Note:
Some pins can have multiple functionalities, which are configured under register control.
The alternate functionality for each pin is listed in the Description column.
Table 3. DisplayPort receiver pins
Pin
Assignment
I/O
Description
B8
DPRX_ML_L0N
I
DisplayPort Receiver Main Link Lane 0 Negative
Analog Input
A8
DPRX_ML_L0P
I
DisplayPort Receiver Main Link Lane 0 Positive
Analog Input
B7
DPRX_ML_L1N
I
DisplayPort Receiver Main Link Lane 1 Negative
Analog Input
A7
DPRX_ML_L1P
I
DisplayPort Receiver Main Link Lane 1 Positive
Analog Input
C6
DPRX_ML_L2N
I
DisplayPort Receiver Main Link Lane 2 Negative
Analog Input
B6
DPRX_ML_L2P
I
DisplayPort Receiver Main Link Lane 2 Positive
Analog Input
D5
DPRX_ML_L3N
I
DisplayPort Receiver Main Link Lane 3 Negative
Analog Input
C5
DPRX_ML_L3P
I
DisplayPort Receiver Main Link Lane 3 Positive
Analog Input
B9
DPRX_AUXN
I/O
DisplayPort Receiver Auxiliary Channel
Negative Analog Input/Output
C9
DPRX_AUXP
I/O
DisplayPort Receiver Auxiliary Channel Positive
Analog Input/Output
DisplayPort Receiver Hot Plug Detect Output
D10
DPRX_HPD_OUT/GPIO_26
I/O
C10
DPRX_REXT
I
C4020-DAT-01p
General Purpose Schmitt Trigger Input / Tristate Output 26 [5 V Tolerant]
Termination calibration reference resistor; 240
ohm 1% resistor should be connected from this
pin to 1.2 V analog power supply.
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STDP4020, STDP4010
Table 4. Reference clocks
Pin
Assignment
I/O
Description
A2
XTAL
I/O
Crystal Oscillator Input. Connect to external
crystal.
A3
TCLK
I/O
Reference Clock (TCLK) from a 27MHz Crystal or
TTL Oscillator. Connect to external crystal or
oscillator.
D4
VBUFC_RPLL
O
Analog Test Pin for Internal Clocks.
Table 5. Digital video outputs - LVDS & TTL (suggested mapping)
Pin
Assignment
I/O
M3
E0_LVTX_CH6P
O
Description
Positive output of LVDS TX E0 Channel 6
Even Green Channel Data 8
Negative output of LVDS TX E0 Channel 6
L4
E0_LVTX_CH6N
O
Even Green Channel Data 9
Positive output of LVDS TX E0 Channel 5
M7
E0_LVTX_CH5P
O
Even Red Channel Data 8
Negative output of LVDS TX E0 Channel 5
L6
E0_LVTX_CH5N
O
Even Red Channel Data 9
Positive output of LVDS TX E0 Channel 4
P2
E0_LVTX_CH4P
O
Even Blue Channel Data 0
Negative output of LVDS TX E0 Channel 4
N2
E0_LVTX_CH4N
O
Even Blue Channel Data 1
Positive output of LVDS TX E0 Channel 3
P3
E0_LVTX_CH3P
O
Even Blue Channel Data 4
Negative output of LVDS TX E0 Channel 3
N3
E0_LVTX_CH3N
O
Even Blue Channel Data 5
Positive output of LVDS TX E0 Clock Channel
N4
E0_LVTX_CLKP
O
Even Blue Channel Data 6
Negative output of LVDS TX E0 Clock Channel
M4
E0_LVTX_CLKN
O
Even Blue Channel Data 7
Positive output of LVDS TX E0 Channel 2
M5
E0_LVTX_CH2P
O
Even Green Channel Data 0
Negative output of LVDS TX E0 Channel 2
L5
E0_LVTX_CH2N
O
Even Green Channel Data 1
Positive output of LVDS TX E0 Channel 1
N6
E0_LVTX_CH1P
O
Even Green Channel Data 2
C4020-DAT-01p
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STDP4020, STDP4010
Table 5. Digital video outputs - LVDS & TTL (suggested mapping)
Pin
Assignment
I/O
M6
E0_LVTX_CH1N
O
Description
Negative output of LVDS TX E0 Channel 1
Even Green Channel Data 3
Positive output of LVDS TX E0 Channel 0
P7
E0_LVTX_CH0P
O
Even Green Channel Data 4
Negative output of LVDS TX E0 Channel 0
N7
E0_LVTX_CH0N
O
Even Green Channel Data 5
Positive output of LVDS TX E1 Channel 6
J4
E1_LVTX_CH6P
O
Odd Green Channel Data 8
Negative output of LVDS TX E1 Channel 6
K5
E1_LVTX_CH6N
O
Odd Green Channel Data 9
Positive output of LVDS TX E1 Channel 5
J5
E1_LVTX_CH5P
O
Odd Red Channel Data 8
Negative output of LVDS TX E1 Channel 5
H4
E1_LVTX_CH5N
O
Odd Red Channel Data 9
Positive output of LVDS TX E1 Channel 4
G1
E1_LVTX_CH4P
O
Odd Blue Channel Data 0
Negative output of LVDS TX E1 Channel 4
G2
E1_LVTX_CH4N
O
Odd Blue Channel Data 1
Positive output of LVDS TX E1 Channel 3
H1
E1_LVTX_CH3P
O
Odd Blue Channel Data 4
Negative output of LVDS TX E1 Channel 3
H2
E1_LVTX_CH3N
O
Odd Blue Channel Data 5
Positive output of LVDS TX E1 Clock Channel
J2
E1_LVTX_CLKP
O
Odd Blue Channel Data 6
Negative output of LVDS TX E1 Clock Channel
J3
E1_LVTX_CLKN
O
Odd Blue Channel Data 7
Positive output of LVDS TX E1 Channel 2
K3
E1_LVTX_CH2P
O
Odd Green Channel Data 0
Negative output of LVDS TX E1 Channel 2
K4
E1_LVTX_CH2N
O
Odd Green Channel Data 1
Positive output of LVDS TX E1 Channel 1
L2
E1_LVTX_CH1P
O
Odd Green Channel Data 2
Negative output of LVDS TX E1 Channel 1
L3
E1_LVTX_CH1N
O
Odd Green Channel Data 3
C4020-DAT-01p
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STDP4020, STDP4010
Table 5. Digital video outputs - LVDS & TTL (suggested mapping)
Pin
Assignment
I/O
M1
E1_LVTX_CH0P
O
Description
Positive output of LVDS TX E1 Channel 0
Odd Green Channel Data 4
Negative output of LVDS TX O1 Channel 3
M2
E1_LVTX_CH0N
O
Odd Green Channel Data 5
Positive output of LVDS TX O0 Channel 6
L11
O0_LVTX_CH6P
O
Data Enable Output. Default status HIGH.
Negative output of LVDS TX O0 Channel 6
M12
O0_LVTX_CH6N
O
Data Clock Output. Default status HIGH.
Positive output of LVDS TX O0 Channel 5
M8
O0_LVTX_CH5P
O
Even Blue Channel Data 8
Negative output of LVDS TX O0 Channel 5
L9
O0_LVTX_CH5N
O
Even Blue Channel Data 9
Positive output of LVDS TX O0 Channel 4
P8
O0_LVTX_CH4P
O
Even Blue Channel Data 2
Negative output of LVDS TX O0 Channel 4
N8
O0_LVTX_CH4N
O
Even Blue Channel Data 3
Positive output of LVDS TX O0 Channel 3
N9
O0_LVTX_CH3P
O
Even Green Channel Data 6
Negative output of LVDS TX O0 Channel 3
M9
O0_LVTX_CH3N
O
Even Green Channel Data 7
Positive output of LVDS TX O0 Clock Channel
M10
O0_LVTX_CLKP
O
Even Red Channel Data 0
Negative output of LVDS TX O0 Clock Channel
L10
O0_LVTX_CLKN
O
Even Red Channel Data 1
Positive output of LVDS TX O0 Channel 2
N11
O0_LVTX_CH2P
O
Even Red Channel Data 2
Negative output of LVDS TX O0 Channel 2
M11
O0_LVTX_CH2N
O
Even Red Channel Data 3
Positive output of LVDS TX O0 Channel 1
P12
O0_LVTX_CH1P
O
Even Red Channel Data 4
Negative output of LVDS TX O0 Channel 1
N12
O0_LVTX_CH1N
O
Even Red Channel Data 5
Positive output of LVDS TX O0 Channel 0
P13
O0_LVTX_CH0P
O
Even Red Channel Data 6
C4020-DAT-01p
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STDP4020, STDP4010
Table 5. Digital video outputs - LVDS & TTL (suggested mapping)
Pin
Assignment
I/O
N13
O0_LVTX_CH0N
O
Description
Negative output of LVDS TX O0 Channel 0
Even Red Channel Data 7
Positive output of LVDS TX O1 Channel 1
K10
O1_LVTX_CH6P
O
Vertical Sync Output. Default status HIGH.
Negative output of LVDS TX O1 Channel 6
J11
O1_LVTX_CH6N
O
Horizontal Sync Output. Default status HIGH.
Positive output of LVDS TX O1 Channel 5
J10
O1_LVTX_CH5P
O
Odd Blue Channel Data 8
Negative output of LVDS TX O1 Channel 5
H11
O1_LVTX_CH5N
O
Odd Blue Channel Data 9
Positive output of LVDS TX O1 Channel 4
M13
O1_LVTX_CH4P
O
Odd Blue Channel Data 2
Negative output of LVDS TX O1 Channel 4
M14
O1_LVTX_CH4N
O
Odd Blue Channel Data 3
Positive output of LVDS TX O1 Channel 3
L12
O1_LVTX_CH3P
O
Odd Green Channel Data 6
Negative output of LVDS TX O1 Channel 3
L13
O1_LVTX_CH3N
O
Odd Green Channel Data 7
Positive output of LVDS TX O1 Clock Channel
K12
O1_LVTX_CLKP
O
Odd Red Channel Data 0
Negative output of LVDS TX O1 Clock Channel
K11
O1_LVTX_CLKN
O
Odd Red Channel Data 1
Positive output of LVDS TX O1 Channel 2
J12
O1_LVTX_CH2P
O
Odd Red Channel Data 2
Negative output of LVDS TX O1 Channel 2
J13
O1_LVTX_CH2N
O
Odd Red Channel Data 3
Positive output of LVDS TX O1 Channel 1
H13
O1_LVTX_CH1P
O
Odd Red Channel Data 4
Negative output of LVDS TX O1 Channel 1
H14
O1_LVTX_CH1N
O
Odd Red Channel Data 5
Positive output of LVDS TX O1 Channel 0
G13
O1_LVTX_CH0P
O
Odd Red Channel Data 6
Negative output of LVDS TX O1 Channel 0
G14
O1_LVTX_CH0N
O
Odd Red Channel Data 7
C4020-DAT-01p
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STDP4020, STDP4010
Table 6. Multi-function - digital audio output, general purpose input/output, bootstrap pins
Pin
Assignment
I/O
D2
I2S_MCLK/GPIO_4
I/O
Description
I²S Audio Master Clock
General Purpose Schmitt Trigger Input / Tri-state
Output 4 [5V Tolerant]
I²S Audio Word Select
D3
I2S_WCLK/BOOT[0]/GPIO_6 I/O
Bootstrap 0. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 6 [5V Tolerant]
I²S Audio Bit Clock
C2
I2S_BCLK/BOOT[1]/GPIO_7
I/O
Bootstrap 1. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 7 [5V Tolerant]
I²S Audio Data 0 / SPDIF output
B1
I2S_0/BOOT[2]/GPIO_8
I/O
Bootstrap 2. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 8 [5V Tolerant]
I²S Audio Data 1 / SPDIF output
G5
I2S_1/BOOT[3]/GPIO_9
I/O
Bootstrap 3. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 9 [5V Tolerant]
I²S Audio Data 2 / SPDIF output
F4
I2S_2/BOOT[4]/GPIO_10
I/O
Bootstrap 4. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 10 [5V Tolerant]
I²S Audio Data 3 / SPDIF output
E3
I2S_3/BOOT[5]/GPIO_11
I/O
Bootstrap 5. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 11 [5V Tolerant]
Table 7. Multi-function and system interface connections
Pin
Assignment
I/O
Description
E5
RESETn
I/O
Reset (active low) signal. Connect to digital 3.3 V
with a 2.7 K ohm pull-up resistor.
F3
TESTMODE0
I
G3
TESTMODE1
I
C4020-DAT-01p
Reserve for testing. Must be connected to system
ground (GND)
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STDP4020, STDP4010
Table 7. Multi-function and system interface connections
Pin
Assignment
I/O
Description
SPI ROM Data Input.
D13
SPI_DI/GPIO_19
I/O
E11
SPI_DO/GPIO_20
I/O
E12
SPI_CLK/GPIO_18
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 19 [5V Tolerant]
SPI ROM Data Output.
General Purpose Schmitt Trigger Input / Tri-state
Output 20 [5V Tolerant]
SPI ROM Clock
General Purpose Schmitt Trigger Input / Tri-state
Output 18 [5V Tolerant]
SPI ROM Chip Select.
F12
SPI_CSn/GPIO_17
I/O
E6
GPIO_0
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 0 [5V Tolerant]
C3
GPIO_1
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 1 [5V Tolerant]
General Purpose Schmitt Trigger Input / Tri-state
Output 17 [5V Tolerant]
Master I²C Serial Clock (for accessing external I²C
devices). Pull up with 4.7K ohm resistor.
G10
I2C_MST_SCL/GPIO_2
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 2 [5V Tolerant]
Master I²C Serial Data (for accessing external I²C
devices). Pull up with 4.7K ohm resistor.
F11
I2C_MST_SDA/GPIO_3
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 3 [5V Tolerant]
Clock Output
C1
CLK_OUT/GPIO_5
I/O
G4
IR_IN/GPIO_12
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 5 [5V Tolerant]
Infra-red Receiver Data Input
General Purpose Schmitt Trigger Input / Tri-state
Output 12 [5V Tolerant]
UART Transmit Data Output.
A1
UART_TX/BOOT[6]/GPIO_1
3
I/O
Bootstrap 6. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 13 [5V Tolerant]
UART Receive Data Input. Pull up with 4.7K ohm
resistor.
E4
UART_RX/GPIO_14
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 14 [5V Tolerant]
C4020-DAT-01p
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STDP4020, STDP4010
Table 7. Multi-function and system interface connections
Pin
C13
Assignment
AUX_I2C_SCL/GPIO_15
I/O
Description
I/O
I²C Serial Clock for DP AUX channel. This pin,
along with AUX_I2C_SDA, creates external serial
interface for DP AUX channel. Connect to digital
3.3V with 4.7K ohm resistor.
General Purpose Schmitt Trigger Input / Tri-state
Output 15 [5V Tolerant]
B14
AUX_I2C_SDA/GPIO_16
I/O
I²C Data Clock for DP AUX channel. This pin,
along with AUX_I2C_SCL, creates external serial
interface for DP AUX channel. Connect to digital
3.3V with 4.7K ohm resistor.
General Purpose Schmitt Trigger Input / Tri-state
Output 16 [5V Tolerant]
I²C_SCL. Pull up to 3.3V with 4.7K ohm resistor.
B13
I2C_SCL/GPIO_21
I/O
D11
I2C_SDA/GPIO_22
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 21 [5V Tolerant]
I²C_SDA. Pull up to 3.3V with 4.7K ohm resistor.
General Purpose Schmitt Trigger Input / Tri-state
Output 22 [5V Tolerant]
UART Transmit Data Output for DP AUX channel.
B12
AUX_UART_TX/BOOT[7]/
GPIO_23
I/O
Bootstrap 7. Please refer to Bootstrap
Configuration Table for description.
General Purpose Schmitt Trigger Input / Tri-state
Output 23 [5V Tolerant]
UART Receive Data Input for DP AUX channel.
Pull up with 4.7K ohm resistor.
A12
AUX_UART_RX/GPIO_24
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 24 [5V Tolerant]
IRQ. Interrupt Output.
D12
IRQ/GPIO_25
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 25 [5V Tolerant]
Table 8. No connects
Pin
Assignment
I/O
G11
NC1
-
G12
NC2
-
C11
NC3
-
A13
NC4
-
B4
NC5
-
C4020-DAT-01p
Description
No connection.
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STDP4020, STDP4010
Table 9. System power and ground
Pin
Assignment
I/O
Description
C12, E7,
E8, K6,
K9
PVDD1
P
Digital 1.2V VDD. Connect to digital 1.2V with
0.1µF bypass capacitor.
F10
PVDD21
P
Digital 3.3V VDD. Connect to digital 3.3V with
0.1µF bypass capacitor. Must be connected at
same voltage level.
A14, C4,
C14, F6,
F7, F8,
F9, G6,
G7, G8,
PVSS3
G9, H6,
H7, H8,
H9, J6,
J7, J8, J9
G
Digital Ground. Each pin must be connected
directly to digital ground plane.
B11, C7,
C8, D9
DPRX_VDDA_1V2
P
DisplayPort Receiver Analog 1.2V Power Supply.
Must be bypassed with a 0.1µF capacitor to
analog ground plane on board.
D7, D8,
E9, E10
DPRX_VSSA
G
DisplayPort Receiver VSS. Must be directly
connected to analog ground plane on board.
B2
VSS_RPLL
G
Analog Ground for the DDS Reference PLL and
Digital Core. Must be directly connected to analog
ground plane on board.
B3
VDD_RPLL
P
Analog 1.2V Power Supply for RCLK PLL and
Digital Core. Must be bypassed with a 0.1µF
capacitor to analog ground plane on board.
D6
VDDA_3V3
P
Analog 3.3V VDD. Connect to analog 3.3V with
0.1µF bypass capacitor to analog ground plane on
board.
H3, H12,
L8, N1,
N14
AVDD_OUT_LVTX_33
P
Analog 3.3V VDD. Connect to analog 3.3V with
0.1µF bypass capacitor to analog ground plane on
board.
L7
AVDD_LVTX_33
P
Analog 3.3V VDD. Connect to analog 3.3V with
0.1µF bypass capacitor to analog ground plane on
board.
F2, F13,
H5, H10,
K8, P1,
P14
AVSS_OUT_LVTX
G
Analog ground. Must connect directly to analog
ground plane on board.
K7
AVSS_LVTX
G
Analog ground. Must connect directly to analog
ground plane on board.
F5
5.2
PVDD22
Bootstrap configuration
During hardware reset, on the rising edge of RESETn, logic high or low configuration on bootstrap pins
are latched and stored. 4.7K pull-up or pull-down resistors must be installed to indicate logic '1' or '0'
C4020-DAT-01p
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STDP4020, STDP4010
status on the bootstrap pins. Bootstrap operation is only guaranteed with external pull-up or pull-down
resistors. There are 8 bootstrap pins available on STDP4020. Some bootstraps may not be available for
normal use.
Table 10. Bootstrap configuration
Pin #
Assignment
Function
D3
BOOT[0]
Set to 0 (Pull Low to GND)
C2
BOOT[1]
Set to 0 (Pull Low to GND)
BOOT[2]
IC_OSC_SEL
Selects clock source between external clock source and internal
ring oscillator
0 = TCLK is from external source (XTAL or ext oscillator)
1 = TCLK is from internal ring oscillator (Strap to VDD)
BOOT[3]
TTL_LVDS_OUT
TTL/LVDS output mode selection
0 = Output is in LVDS format
1 = Output is in TTL format
BOOT[4]
OCM_BOOT_SEL
Selects OCM boot option
0 = OCM boot will be from internal ROM code
1 = OCM boot is from external ROM/Flash code
E3
BOOT[5]
WIDE_NARROW_BUS
Selects wide or narrow LVDS or TTL bus
LVDS
0 = DUAL LVDS
1 = QUAD LVDS
TTL
0 = Single
1 = Dual
A1
BOOT[6]
Set to 0 (Pull Low to GND) for normal operation
B12
BOOT[7]
I2C_DEV_ID[0]
Selects I2C slave Device ID for RD/WR access
001 = 0xE4, 0xE5; 000 = 0xE6, 0xE7
B1
G5
F4
Table 11. Software implemented bootstrap configuration
Pin #
C1
C4020-DAT-01p
Assignment
Function
CLK_OUT/GPIO_5
ASSR_ENABLE
Selects whether ASSR is enabled
0 = Disabled
1 = Enabled
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STDP4020, STDP4010
5.3
General purpose input/output (GPIO) pins
The STDP4020 contains 27 general-purpose input/output (GPIO) pins for system configuration purpose.
GPIO_0, GPIO_1 are dedicated general-purpose IO pins and the rest have shared functionality. Each
GPIO has independent direction control and open drain enable for reading and writing.
Note:
The GPIO functionality is available only for custom applications. Default settings allow
configuration of dedicated GPIO pins (GPIO_0 and GPIO_1) through host interface and the
rest of the GPIO configuration requires over-riding the default feature using external
firmware.
C4020-DAT-01p
MegaChips’ Proprietary Information
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STDP4020, STDP4010
6.
Package
Package type: 164 LFBGA (12 x 12 mm / ball pitch 0.8 mm)
Figure 3. Package specification
C4020-DAT-01p
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STDP4020, STDP4010
6.1
Marking field template and descriptors
The STDP4020 marking template is shown below.
Figure 4. Marking template
Field descriptors are shown below.
Table 12.Field descriptors
Field
Description
Marking
A
Standard MegaChips logo
M
B
2-character version code
AD
C
Product code
STDP4020 or
STDP4010
D
8-character diffusion code
9R”ABCDEF”
E
2-character assembly plant code
AA
F
3-character BE sequence code
“XYZ”
G
2-character diffusion plant code
9R
H
3-character country of origin code
TWN
I
2-character test plant code
AA
J
1-digit assembly year
“Y”
K
2-digit assembly week
“WW”
L
Ball A1 identifier
a DOT
C4020-DAT-01p
MegaChips’ Proprietary Information
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STDP4020, STDP4010
7.
Electrical specification
7.1
Absolute maximum ratings
Applied conditions greater than those listed under “Absolute maximum ratings” may cause permanent
damage to the device. The device should never exceed absolute maximum conditions since it may affect
device reliability.
Table 13. Absolute maximum ratings
Parameter
Symbol
Min
Typ
Max
Units
VVDD_3.3
-0.3
3.3
3.6
V
VVDD_1.2
-0.3
1.2
1.26
V
VIN5Vtol
-0.3
5.5
V
Input voltage (non 5V tolerant inputs) (1,2)
VIN
-0.3
3.6
V
ESD - Human Body Model (HBM)(4)
VESD
±2.0
kV
VESD
±200
V
VESD
±500
V
Latch-up
ILA
±100
mA
Ambient operating temperature
TA
0
70
°C
Storage temperature
TSTG
-40
150
°C
Operating junction temperature
TJ
0
125
°C
Thermal resistance (Junction to Ambient)(3)
θJA
36.6
°C/W
Thermal resistance (Junction to Case)(3)
θJC
18.1
°C/W
Peak IR reflow soldering temperature (
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