STDP4028
DisplayPort transmitter
Datasheet
Rev A
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MegaChips reserves the right to make any change herein at any time without prior notice. MegaChips
does not assume any responsibility or liability arising out of application or use of any product or
service described herein except as explicitly agreed upon.
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STDP4028
Features
•
•
•
•
Enhanced DisplayPort® (DP) transmitter
– DP 1.1a compliant
– Embedded DisplayPort (eDP) compliant
– 1, 2, or 4 lanes
Higher bandwidth “Turbo mode” (3.24 Gbps)
per lane, supports:
– 1920 x 1080 (FHD) 120 Hz/10-bit color
video standard timings and 7.1 Ch audio
– 2560 x 1600 (WQXGA), 2560 x 2048
(QSXGA) 60 Hz/10-bit color graphics and
7.1 Ch audio
Interface compatibility with wide range of
display controller ICs
– LVTTL (60 wide) and LVDS (quad bus)
video interface
– 8-Ch I2S and SPDIF audio interface
Robust AUX channel
– Link service, maintenance
– I2C-over-AUX (MCCS, DDC)
– IR, full duplex UART protocol
HDCP repeater capability
– Acts as downstream transmitter
•
Spread spectrum on DisplayPort, LVDS, and
TTL interfaces for EMI reduction
•
Supports deep color and color format
conversion
– RGB/YUV (4:4:4) – 10-bit color
– YUV (4:2:2/4:2:0) – 12-bit color
– RGB (4:4:4) to YUV (4:4:4) conversion and
vice-versa
•
Low power operation; 18 mW standby
•
I2C to AUX bridge for EDID, MCCS pass
through
•
Supports HBR/“Turbo” speed over HBR/RBRrated long cables (15 m and more)
•
Package
– 164 LFBGA (12 x 12 mm / 0.8 mm)
•
Power supply voltages
– 3.3 V I/O; 1.2 V core
Applications
•
Configurable through I2C host interface
•
Supports HDCP 1.3 with on-chip keys
QLVDS/
TTL (60)
Video
•
•
Digital TV, docking station, STB, game
console, etc.
LVDS/TTL
Receiver
DisplayPort
Transmitter
I2S/SPDIF
Audio
I2S/SPDIF
Receiver
I2C Host
Interface
C4028-DAT-01p
Crystal
Oscillator
GPIO
I2C
Master
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DP Output
STDP4028
Contents
1.
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.
Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.
Feature attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.
BGA footprint and pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.
6.
4.1
Ball grid array diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
Full pin list sorted by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2
Bootstrap configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
General purpose input/output (GPIO) pins . . . . . . . . . . . . . . . . . . . . . . . . 25
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1
7.
Marking field template and descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2
Maximum speed of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4.1
Digital video input port DC characteristics . . . . . . . . . . . . . . . . . . . . . . . 31
7.4.2
LVDS video input DC/AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4.3
Digital audio input I2S timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4.4
DisplayPort transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.4.5
I2C interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4.6
SPI interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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STDP4028
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Key to BGA diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DisplayPort transmitter outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reference clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital video inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Multi-function - digital audio output, general purpose input/output, bootstrap pins. . . . . . . 20
Multi-function and system interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
No connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
System power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bootstrap configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Field descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Digital video input port DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVDS video input DC/AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Digital audio input I2S timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DisplayPort transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
I2C interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SPI interface timing, VDD = 3.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
C4028-DAT-01p
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STDP4028
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
System interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Marking template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Digital video input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVDS single-ended waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Receiver strobe positions LVDS input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Receiver margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Digital audio I2S input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SPI output or serial interface SPI ROM input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SPI input or serial interface SPI ROM output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
C4028-DAT-01p
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STDP4028
1.
Description
The STDP4028 is a DisplayPort transmitter IC for the secure transmission of high-bandwidth,
uncompressed digital audio-video signals targeted for applications such as DTV, LCD monitor, docking
station, STB and other types of consumer audio-video systems. STDP4028 is VESA DP 1.1a and eDP
compliant device, implementing a single link DisplayPort output port comprising four main lanes, auxiliary
channel, and HPD. In addition to the standard HBR (2.7 Gbps) and RBR (1.62 Gbps) speeds, this device
supports “turbo” speed of 3.24 Gbps per lane with a total link bandwidth of 12.96 Gbps. The higher
bandwidth provides unique benefits to users over other commercial DP transmitters for embedded
applications by offering additional margin to support higher color depth, resolution, and refresh rate. For
example, STDP4028 supports FHD non-reduced blanking video (1080p 30-bit color per pixel) at 120 Hz,
plus 7.1 Ch audio in two-box TV applications. The high-speed auxiliary channel in STDP4028 acts as a
bidirectional communication link, supporting application-specific protocols such as MCCS, DDC, UART,
IR, as well as, the dedicated DisplayPort link training and device management functions. The STDP4028
supports RGB and YUV video color formats with color depth of 12 (YUV 4:2:2 only), 10, and 8 bits.
This device offers LVDS and LVTTL input interface configurable to map a wide range of display controller
products. The Quad LVDS interface supports video signals up to 400 MHz pixel rate with flexible channel
and lane swapping options. The 60-bit LVTTL input ports on STDP4028 can be mapped to transfer video
data either in two pixels per clock or single pixel per clock of a chosen color depth. The STDP4028 also
supports both compressed and uncompressed audio formats.
This device comprises four I2S audio inputs, supporting up to 8 channels LPCM audio and a single wire
SPDIF input for encoded audio. The STDP4028 features HDCP 1.3 content protection scheme with an
embedded key option for secure transmission of digital audio-video content. In addition, it supports the
HDCP repeater function and, thus acts as a downstream transmitter suitable for two-box TV and
HDMI/DVI to DP converter applications.The STDP4028 is configurable from an external host through the
I2C host interface. This IC also includes general-purpose inputs/outputs for controlling system
components. The STDP4028 features a color space converter (RGB to YUV and YUV to RGB) for
flexible interface with external video processing devices.
C4028-DAT-01p
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STDP4028
2.
Application overview
The STDP4028 is designed as DisplayPort transmitter device for transferring high bandwidth video and
audio in PC and CE applications. Typical audio-video source system has a graphics or video processing
device that acts as system master (host). The host controller configures STDP4028 through an I2C host
interface. The host and STDP4028 also use interrupt mechanism whenever the slave needs attention.
The STDP4028 may require an external SPI Flash to store firmware for supporting custom specific
applications. The audio and video signal from the host controller is converted in to DisplayPort streams
through STDP4028 and transfer to an external display system over standard DisplayPort cable. The I2C
to AUX bypass channel handles the I2C traffic between STDP4028 and host controller as shown in the
figure below.
Figure 1. System interface block diagram
DP
EDID
SPI
Flash
Flash
I 2C
I2C
I2C slave
INTR
Host Controller
TTL( 60 bit)
HS, VS, CLK, DE
STDP4028
Main Link
AUX CH
HPD_in
I2S/SPDIF
C4028-DAT-01p
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DP Connector
I2C Master
DP Connector
SPI
DP Rx
DP Rx
STDP4028
3.
Feature attributes
• Video
– Up to 2560 x 2048-60 Hz, 2560 x 1600-60 Hz, FHD 120 Hz at 10-bits per color
– 8/10/12 bits per color option
– RGB/YUV color format
• Audio
– 8-Ch I2S; word length up to 64 x Fs; bit depth up to 24 bits, sample rate up to 192 kHz
– SPDIF; 2-Ch LPCM, AC3, DTS, bit depth up to 24 bits, sample rate up to 192 kHz
• Input interface
– Video: TTL 60/48 bits wide; QLVDS 8/10 bits per color
– Audio: I2S 8-Ch, SPDIF x1
• Output interface
– DP 1.1a (4 lanes, AUX, HPD); supported link speed 3.24 Gbps, 2.7 Gbps, 1.62 Gbps
• Spread spectrum
– Supported on DP output and LVDS/TTL inputs
• AUX capabilities
– UART, I2C-over-AUX (MCCS, DDC, etc.) IR
• HDCP
– On-chip keys, HDCP repeater
• Color format conversion
– RGB 4:4:4 to YUV 4:4:4 and vice-versa
• System configuration
– I2C host interface for control by an external system microprocessor
• Package
– 164 LFBGA (12 x 12 mm), 1 mm thickness, 0.8 pitch
• Power
– Standby power 18 mW
• ESD
– 2 KV HBM, 200 V MM, 750 V CDM
C4028-DAT-01p
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STDP4028
4.
BGA footprint and pin lists
4.1
Ball grid array diagram
The ball grid array (BGA) diagrams give the allocation of pins to the package, shown from the top looking
down using the PCB footprint.
Some signal names in BGA diagrams have been abbreviated. Refer toTable 2: Pin list on page 11 for full
signal names sorted by pin number.
Table 1. Key to BGA diagrams
Function
Type
DisplayPort input
SIG
Reference clocks
SIG
System controls
SIG
Multi-function and system interface connections
SIG
I2S/SPDIF audio output
SIG
LVDS/TTL Output_Even-0
SIG
LVDS/TTL Output_Even-1
SIG
LVDS/TTL Output_Odd-0
SIG
LVDS/TTL Output_Odd-1
SIG
Analog power
VCC/VDD
Analog ground
VSS/GND
System power
VCC/VDD
System ground
VSS/GND
No connect/Do not connect
NC/DNC
No ball
C4028-DAT-01p
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Key
STDP4028
The STDP4028 is available in a 164-pin LFBGA package.
Figure 2. Pin diagram
C4028-DAT-01p
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STDP4028
4.2
Full pin list sorted by pin number
Table 2. Pin list
Pin number
A1
PVSS3
A2
VSS_RPLL
A3
VDD_RPLL
A7
DPTX_ML_L1N
A8
DPTX_ML_L2N
A12
AUX_UART_RX_GPIO_22
A13
I2C_SDA_GPIO_25
A14
PVSS3
B1
UART_RX_GPIO_14
B2
NC
B3
NC
B4
TX_XTAL
B6
DPTX_ML_L0N
B7
DPTX_ML_L1P
B8
DPTX_ML_L2P
B9
DPTX_ML_L3N
B11
DPTX_VDDA_1V2
B12
AUX_UART_TX_BOOT4_GPIO_21
B13
I2C_SCL_GPIO_24
B14
AUX_I2C_SDA_GPIO_16
C1
I2S_BCLK_GPIO_7
C2
UART_TX_BOOT1_GPIO_13
C3
VBUFC_RPLL
C4
TX_TCLK
C5
VSSA_TX
C6
DPTX_ML_L0P
C7, C8
C4028-DAT-01p
Net name
DPTX_VDDA_1V2
C9
DPTX_ML_L3P
C10
DPTX_AUXN
C11
DPTX_REXT
C12
DPTX_HDP_IN_GPIO_23
C13
AUX_I2C_SCL_GPIO_15
C14
SPI_DO
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STDP4028
Table 2. Pin list (continued)
Pin number
D2
I2S_0_GPIO_8
D3
I2S_3_GPIO_11
D4
GPIO_1_BOOT2
D5
VDD33_TX
D6
VDDA_3V3
D7, D8
DPTX_VSSA
D9
DPTX_VDDA_1V2
D10
DPTX_AUXP
D11
NC
D12
IRQ_BOOT7_GPIO_12
D13
SPI_DI
E3
CLK_OUT_GPIO_5_BOOT0
E4
I2S_WCLK_GPIO_4
E5
PWM0_GPIO_0_BOOT3
E6
RESETn
E7, E8
PVDD1
E9, E10
DPTX_VSSA
E11
NC
E12
SPI_CLK
F2
AVSS_OUT_LVRX
F3
TESTMODE0
F4
I2S_2_GPIO_10
F5
I2S_1_GPIO_9
F6, F7, F8, F9
PVSS3
F10
SPI_CSn
F11
GPIO_3_BOOT6
F12
NC
F13
AVSS_OUT_LVRX
G1
E1_LVRX_CH0N
G2
E1_LVRX_CH0P
G3
TESTMODE1
G4
IR_IN_GPIO_6
G5
PVDD22
G6, G7, G8, G9
G10
C4028-DAT-01p
Net name
PVSS3
GPIO_2_BOOT5
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STDP4028
Table 2. Pin list (continued)
Pin number
G11
PVDD21
G12
NC
G13
O1_LVRX_CH4N
G14
O1_LVRX_CH4P
H1
E1_LVRX_CH1N
H2
E1_LVRX_CH1P
H3
AVDD_OUT_LVRX_33
H4
E1_LVRX_CH5P
H5
AVSS_OUT_LVRX
H6, H7, H8, H9
PVSS3
H10
AVSS_OUT_LVRX
H11
O1_LVRX_CH5P
H12
AVDD_OUT_LVRX_33
H13
O1_LVRX_CH3N
H14
O1_LVRX_CH3P
J2
E1_LVRX_CH2N
J3
E1_LVRX_CH2P
J4
E1_LVRX_CH6N
J5
E1_LVRX_CH5N
J6, J7, J8, J9
C4028-DAT-01p
Net name
PVSS3
J10
O1_LVRX_CH5N
J11
O1_LVRX_CH6P
J12
O1_LVRX_CLKN
J13
O1_LVRX_CLKP
K3
E1_LVRX_CLKN
K4
E1_LVRX_CLKP
K5
E1_LVRX_CH6P
K6
PVDD1
K7
AVSS_LVRX
K8
AVSS_OUT_LVRX
K9
PVDD1
K10
O1_LVRX_CH6N
K11
O1_LVRX_CH2P
K12
O1_LVRX_CH2N
L2
E1_LVRX_CH3N
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STDP4028
Table 2. Pin list (continued)
Pin number
C4028-DAT-01p
Net name
L3
E1_LVRX_CH3P
L4
E0_LVRX_CH6P
L5
E0_LVRX_CLKP
L6
E0_LVRX_CH5P
L7
AVDD_LVRX_12
L8
AVDD_OUT_LVRX_33
L9
O0_LVRX_CH5P
L10
O0_LVRX_CH2P
L11
O0_LVRX_CH6N
L12
O1_LVRX_CH1N
L13
O1_LVRX_CH1P
M1
E1_LVRX_CH4N
M2
E1_LVRX_CH4P
M3
E0_LVRX_CH6N
M4
E0_LVRX_CH2P
M5
E0_LVRX_CLKN
M6
E0_LVRX_CH3P
M7
E0_LVRX_CH5N
M8
O0_LVRX_CH5N
M9
O0_LVRX_CH1P
M10
O0_LVRX_CH2N
M11
O0_LVRX_CLKP
M12
O0_LVRX_CH6P
M13
O1_LVRX_CH0N
M14
O1_LVRX_CH0P
N1
AVDD_OUT_LVRX_33
N2
E0_LVRX_CH0P
N3
E0_LVRX_CH1P
N4
E0_LVRX_CH2N
N6
E0_LVRX_CH3N
N7
E0_LVRX_CH4P
N8
O0_LVRX_CH0P
N9
O0_LVRX_CH1N
N11
O0_LVRX_CLKN
N12
O0_LVRX_CH3P
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STDP4028
Table 2. Pin list (continued)
Pin number
C4028-DAT-01p
Net name
N13
O0_LVRX_CH4P
N14
AVDD_OUT_LVRX_33
P1
AVSS_OUT_LVRX
P2
E0_LVRX_CH0N
P3
E0_LVRX_CH1N
P7
E0_LVRX_CH4N
P8
O0_LVRX_CH0N
P12
O0_LVRX_CH3N
P13
O0_LVRX_CH4N
P14
AVSS_OUT_LVRX
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STDP4028
5.
Connections
5.1
Pin list
I/O Legend: I = Input; O = Output; P = Power; G = Ground
Note:
Some pins can have multiple functionalities, which are configured under register control.
The alternate functionality for each pin is listed in the Description column.
Table 3. DisplayPort transmitter outputs
Pin
Assignment
I/O
Description
B6
DPTX_ML_L0N
O
Negative output of DPTX Main Link Lane0
C6
DPTX_ML_L0P
O
Positive output of DPTX Main Link Lane0
A7
DPTX_ML_L1N
O
Negative output of DPTX Main Link Lane1
B7
DPTX_ML_L1P
O
Positive output of DPTX Main Link Lane1
A8
DPTX_ML_L2N
O
Negative output of DPTX Main Link Lane2
B8
DPTX_ML_L2P
O
Positive output of DPTX Main Link Lane2
B9
DPTX_ML_L3N
O
Negative output of DPTX Main Link Lane3
C9
DPTX_ML_L3P
O
Positive output of DPTX Main Link Lane3
C10
DPTX_AUXN
I/O
Negative input/output of DPTX Aux Channel
D10
DPTX_AUXP
I/O
Positive input/output of DPTX Aux Channel
C12
DPTX_HPD_IN/GPIO_23
I/O
C11
DPTX_REXT
I
DisplayPort Receiver Hot Plug Detect Input
General Purpose Schmitt Trigger Input / Tristate Output 26 [5V Tolerant]
Termination calibration reference resistor; 240
ohm 1% resistor should be connected from this
pin to 1.2 V analog power supply.
Table 4. Reference clocks
Pin
Assignment
I/O
Description
B4
TX_XTAL
I/O
Crystal Oscillator Input. Connect to external
crystal.
C4
TX_TCLK
I/O
Reference Clock (TCLK) from a 27 MHz Crystal or
TTL Oscillator. Connect to external crystal or
oscillator.
C3
VBUFC_RPLL
O
Analog Test Pin for Internal Clocks. No connect.
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STDP4028
Table 5. Digital video inputs
Pin
Assignment
I/O
Description
K4
E1_LVRX_CLKP
I
Positive input of LVDS RX E1 Clock
Channel
TTL Even Red Channel Data 4
K3
E1_LVRX_CLKN
I
Negative input of LVDS RX E1 Clock
Channel
TTL Even Red Channel Data 7
Positive input of LVDS RX E1 Channel 0
G2
E1_LVRX_CH0P
I
TTL VSYNC
Negative input of LVDS RX E1 Channel 0
G1
E1_LVRX_CH0N
I
TTL HSYNC
Positive input of LVDS RX E1 Channel 1
H2
E1_LVRX_CH1P
I
TTL Even Red Channel Data 1
Negative input of LVDS RX E1 Channel 1
H1
E1_LVRX_CH1N
I
TTL Even Red Channel Data 0
Positive input of LVDS RX E1 Channel 2
J3
E1_LVRX_CH2P
I
TTL DE
Negative input of LVDS RX E1 Channel 2
J2
E1_LVRX_CH2N
I
TTL Even Red Channel Data 9
Positive input of LVDS RX E1 Channel 3
L3
E1_LVRX_CH3P
I
TTL Even Red Channel Data 6
Negative input of LVDS RX E1 Channel 3
L2
E1_LVRX_CH3N
I
TTL Even Red Channel Data 5
Positive input of LVDS RX E1 Channel 4
M2
E1_LVRX_CH4P
I
TTL Even Red Channel Data 2
Negative input of LVDS RX E1 Channel 4
M1
E1_LVRX_CH4N
I
TTL Even Red Channel Data 3
J5
E1_LVRX_CH5N
I
TTL Even Red Channel Data 8
H4
E1_LVRX_CH5P
I
TTL Even Blue Channel Data 0
K5
E1_LVRX_CH6P
I
TTL Odd Red Channel Data 0
J4
E1_LVRX_CH6N
I
TTL Even Blue Channel Data 1
I
Negative input of LVDS RX O1 Clock
Channel
J12
O1_LVRX_CLKN
TTL Odd Blue Channel Data 8
J13
O1_LVRX_CLKP
I
Positive input of LVDS RX O1 Clock
Channel
TTL Odd Blue Channel Data 7
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STDP4028
Table 5. Digital video inputs
Pin
Assignment
I/O
M14
O1_LVRX_CH0P
I
Description
Positive input of LVDS RX O1 Channel 0
TTL Odd Green Channel Data 6
Negative input of LVDS RX O1 Channel 0
M13
O1_LVRX_CH0N
I
TTL Odd Green Channel Data 5
Positive input of LVDS RX O1 Channel 1
L13
O1_LVRX_CH1P
I
TTL Odd Green Channel Data 3
Negative input of LVDS RX O1 Channel 1
L12
O1_LVRX_CH1N
I
TTL Odd Blue Channel Data 0
Positive input of LVDS RX O1 Channel 2
K11
O1_LVRX_CH2P
I
TTL Odd Green Channel Data 4
Negative input of LVDS RX O1 Channel 2
K12
O1_LVRX_CH2N
I
TTL Odd Green Channel Data 2
Positive input of LVDS RX O1 Channel 3
H14
O1_LVRX_CH3P
I
TTL Odd Blue Channel Data 4
Negative input of LVDS RX O1 Channel 3
H13
O1_LVRX_CH3N
I
TTL Odd Blue Channel Data 5
Positive input of LVDS RX O1 Channel 4
G14
O1_LVRX_CH4P
I
TTL Odd Blue Channel Data 2
Negative input of LVDS RX O1 Channel 4
G13
O1_LVRX_CH4N
I
TTL Odd Blue Channel Data 3
J10
O1_LVRX_CH5N
I
TTL Odd Green Channel Data 8
H11
O1_LVRX_CH5P
I
TTL Odd Blue Channel Data 6
K10
O1_LVRX_CH6N
I
TTL Odd Green Channel Data 9
J11
O1_LVRX_CH6P
I
TTL Odd Blue Channel Data 9
I
Negative input of LVDS RX E0 Clock
Channel
M5
E0_LVRX_CLKN
TTL Even Green Channel Data 2
L5
E0_LVRX_CLKP
I
Positive input of LVDS RX E0 Clock
Channel
TTL Even Green Channel Data 3
Negative input of LVDS RX E0 Channel 0
P2
E0_LVRX_CH0N
I
TTL Even Green Channel Data 0
Positive input of LVDS RX E0 Channel 0
N2
E0_LVRX_CH0P
I
TTL Even Green Channel Data 1
Negative input of LVDS RX E0 Channel 1
P3
E0_LVRX_CH1N
I
TTL Even Green Channel Data 6
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STDP4028
Table 5. Digital video inputs
Pin
Assignment
I/O
N3
E0_LVRX_CH1P
I
Description
Positive input of LVDS RX E0 Channel 1
TTL Even Green Channel Data 7
Negative input of LVDS RX E0 Channel 2
N4
E0_LVRX_CH2N
I
TTL Even Green Channel Data 4
Positive input of LVDS RX E0 Channel 2
M4
E0_LVRX_CH2P
I
TTL Even Green Channel Data 5
Negative input of LVDS RX E0 Channel 3
N6
E0_LVRX_CH3N
I
TTL Even Blue Channel Data 7
Positive input of LVDS RX E0 Channel 3
M6
E0_LVRX_CH3P
I
TTL Even Blue Channel Data 8
Negative input of LVDS RX E0 Channel 4
P7
E0_LVRX_CH4N
I
TTL Odd Red Channel Data 1
Positive input of LVDS RX E0 Channel 4
N7
E0_LVRX_CH4P
I
TTL DCLK
M7
E0_LVRX_CH5N
I
TTL Even Blue Channel Data 6
L6
E0_LVRX_CH5P
I
TTL Even Blue Channel Data 9
M3
E0_LVRX_CH6N
I
TTL Even Green Channel Data 9
L4
E0_LVRX_CH6P
I
TTL Even Green Channel Data 8
N11
O0_LVRX_CLKN
I
Negative input of LVDS RX O0 Clock
Channel
TTL Odd Red Channel Data 8
M11
O0_LVRX_CLKP
I
Positive input of LVDS RX O0 Clock
Channel
TTL Odd Red Channel Data 7
Negative input of LVDS RX O0 Channel 0
P8
O0_LVRX_CH0N
I
TTL Odd Green Channel Data 0
Positive input of LVDS RX O0 Channel 0
N8
O0_LVRX_CH0P
I
TTL Odd Green Channel Data 1
Negative input of LVDS RX O0 Channel 1
N9
O0_LVRX_CH1N
I
TTL Even Blue Channel Data 4
Positive input of LVDS RX O0 Channel 1
M9
O0_LVRX_CH1P
I
TTL Even Blue Channel Data 3
Negative input of LVDS RX O0 Channel 2
M10
O0_LVRX_CH2N
I
TTL Even Blue Channel Data 2
Positive input of LVDS RX O0 Channel 2
L10
O0_LVRX_CH2P
I
TTL Odd Red Channel Data 2
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STDP4028
Table 5. Digital video inputs
Pin
Assignment
I/O
P12
O0_LVRX_CH3N
I
Description
Negative input of LVDS RX O0 Channel 3
TTL Odd Red Channel Data 6
Positive input of LVDS RX O0 Channel 3
N12
O0_LVRX_CH3P
I
TTL Odd Red Channel Data 5
Negative input of LVDS RX O0 Channel 4
P13
O0_LVRX_CH4N
I
TTL Odd Red Channel Data 4
Positive input of LVDS RX O0 Channel 4
N13
O0_LVRX_CH4P
I
TTL Odd Blue Channel Data 1
M8
O0_LVRX_CH5N
I
TTL Even Blue Channel Data 5
L9
O0_LVRX_CH5P
I
TTL Odd Red Channel Data 9
L11
O0_LVRX_CH6N
I
TTL Odd Green Channel Data 7
M12
O0_LVRX_CH6P
I
TTL Odd Red Channel Data 3
Table 6. Multi-function - digital audio output, general purpose input/output, bootstrap pins
Pin
Assignment
I/O
E4
I2S_WCLK_GPIO_4
I/O
Description
I2S_WCLK
GPIO_4
I2S_BCLK
C1
I2S_BCLK_GPIO_7
I/O
GPIO_7
I2S_0
D2
I2S_0_GPIO_8
I/O
GPIO_8
I2S_1
F5
I2S_1_GPIO_9
I/O
GPIO_9
I2S_2
F4
I2S_2_GPIO_10
I/O
GPIO_10
I2S_3
D3
I2S_3_GPIO_11
I/O
GPIO_11
Table 7. Multi-function and system interface connections
Pin
Assignment
I/O
Description
E6
RESETn
I/O
Reset (active low) signal. Connect to digital 3.3 V
with a 2.7 K ohm pull-up resistor.
F3
TESTMODE0
I
G3
TESTMODE1
I
Reserve for testing. Must be connected to system
ground (GND)
D13
SPI_DI
I/O
SPI ROM Data Input.
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STDP4028
Table 7. Multi-function and system interface connections
Pin
Assignment
I/O
Description
C14
SPI_DO
I/O
SPI ROM Data Output.
E12
SPI_CLK
I/O
SPI ROM Clock
F10
SPI_CSn
I/O
SPI ROM Chip Select.
PWM0
E5
PWM0_GPIO_0_BOOT3
I/O
BOOTSTRAP[3] Please refer to Bootstrap
configuration table for description
General Purpose Schmitt Trigger Input / Tri-state
Output 0 [5V Tolerant]
General Purpose Schmitt Trigger Input / Tri-state
Output 1 [5V Tolerant]
D4
GPIO_1_BOOT2
I/O
BOOTSTRAP[2] Please refer to Bootstrap
configuration table for description
General Purpose Schmitt Trigger Input / Tri-state
Output 2 [5V Tolerant]
G10
GPIO_2_BOOT5
I/O
BOOTSTRAP[5] Please refer to Bootstrap
configuration table for description
BOOTSTRAP[6] Please refer to Bootstrap
configuration table for description
F11
GPIO_3_BOOT6
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 3 [5V Tolerant]
CLK_OUT
E3
CLK_OUT_GPIO_5_BOOT0
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 5 [5V Tolerant]
BOOTSTRAP[0] Please refer to Bootstrap
configuration table for description
Infra-red Receiver Data Input
G4
IR_IN_GPIO_6
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 6 [5V Tolerant]
IRQ
D12
IRQ_BOOT7_GPIO_12
I/O
BOOTSTRAP[7] Please refer to Bootstrap
configuration table for description
General Purpose Schmitt Trigger Input / Tri-state
Output 12 [5V Tolerant]
UART Transmit Data Output.
C2
UART_TX_BOOT1_GPIO_1
3
I/O
BOOTSTRAP[1] Please refer to Bootstrap
configuration table for description
General Purpose Schmitt Trigger Input / Tri-state
Output 13 [5V Tolerant]
C4028-DAT-01p
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STDP4028
Table 7. Multi-function and system interface connections
Pin
Assignment
I/O
Description
UART Receive Data Input. Pull up with 4.7K ohm
resistor.
B1
UART_RX_GPIO_14
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 14 [5V Tolerant]
C13
AUX_I2C_SCL_GPIO_15
I/O
I²C Serial Clock for DP AUX channel. This pin,
along with AUX_I2C_SDA, creates external serial
interface for DP AUX channel. Connect to digital
3.3V with 4.7K ohm resistor.
General Purpose Schmitt Trigger Input / Tri-state
Output 15 [5V Tolerant]
B14
AUX_I2C_SDA_GPIO_16
I/O
I²C Data Clock for DP AUX channel. This pin,
along with AUX_I2C_SCL, creates external serial
interface for DP AUX channel. Connect to digital
3.3V with 4.7K ohm resistor.
General Purpose Schmitt Trigger Input / Tri-state
Output 16 [5V Tolerant]
UART Transmit Data Output for DP AUX channel
B12
AUX_UART_TX_BOOT4_GP
I/O
IO_21
BOOTSTRAP[4] Please refer to Bootstrap
configuration table for description
General Purpose Schmitt Trigger Input / Tri-state
Output 21 [5V Tolerant]
UART Receive Data Input for DP AUX channel.
Pull up with 4.7K ohm resistor.
A12
AUX_UART_RX_GPIO_22
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 22 [5V Tolerant]
I²C_SCL. Pull up to 3.3V with 4.7K ohm resistor.
B13
I2C_SCL_GPIO_24
I/O
A13
I2C_SDA_GPIO_25
I/O
General Purpose Schmitt Trigger Input / Tri-state
Output 24 [5V Tolerant]
I²C_SDA. Pull up to 3.3V with 4.7K ohm resistor.
General Purpose Schmitt Trigger Input / Tri-state
Output 25 [5V Tolerant]
Table 8. No connects
Pin
Assignment
I/O
F12
NC1
-
G12
NC2
-
D11
NC3
-
E11
NC4
-
B2
NC5
-
B3
NC6
-
Description
No connection.
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STDP4028
Table 9. System power and ground
Pin
Assignment
I/O
Description
D6
VDDA_3V3
P
Analog 3.3V VDD. Connect to analog 3.3V with
0.1µF bypass capacitor to analog ground plane on
board.
E7, E8,
K6, K9
PVDD1
P
Digital 1.2V VDD. Connect to digital 1.2V with
0.1µF bypass capacitor.
G11
PVDD21
P
Digital 3.3V VDD. Connect to digital 3.3V with
0.1µF bypass capacitor. Must be connected at
same voltage level.
G5
PVDD22
A1, A14,
F6, F7,
F8, F9,
G6, G7,
G8, G9,
H6, H7,
H8, H9,
J6, J7,
J8, J9
PVSS3
G
Digital Ground. Each pin must be connected
directly to digital ground plane.
B11, C7,
C8, D9
DPTX_VDDA_1V2
P
DisplayPort Transmitter Analog 1.2V Power
Supply. Must be bypassed with a 0.1µF capacitor
to analog ground plane on board.
D7, D8,
E9, E10
DPTX_VSSA
G
DisplayPort Transmitter VSS. Must be directly
connected to analog ground plane on board.
D5
VDD33_TX
P
Analog 3.3V VDD. Connect to analog 3.3V with
0.1µF bypass capacitor to analog ground plane on
board.
C5
VSSA_TX
G
Analog ground. Must connect directly to analog
ground plane on board
H3, H12,
L8, N1,
N14
AVDD_OUT_LVRX_33
P
Analog 3.3V VDD. Connect to analog 3.3V with
0.1µF bypass capacitor to analog ground plane on
board.
L7
AVDD_LVRX_12
P
Analog 1.2V VDD. Connect to analog 1.2V with
0.1µF bypass capacitor to analog ground plane on
board.
K7
AVSS_LVTX
G
Analog ground. Must connect directly to analog
ground plane on board.
F2, F13,
H5, H10,
K8, P1,
P14
AVSS_OUT_LVRX
G
Analog ground. Must connect directly to analog
ground plane on board.
A2
VSS_RPLL
G
Analog Ground for the DDS Reference PLL and
Digital Core. Must be directly connected to analog
ground plane on board.
A3
VDD_RPLL
P
Analog 1.2V Power Supply for RCLK PLL and
Digital Core. Must be bypassed with a 0.1µF
capacitor to analog ground plane on board.
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STDP4028
Note:
5.2
1
PVDD21 and PVDD22 must be connected to same power supply.
2
Add 47 K pull-down resistor for HPD_IN signal.
Bootstrap configuration
During hardware reset, on the rising edge of RESETn, logic high or low configuration on Bootstrap pins
are latched and stored. 4.7 K pull-up or pull-down resistors must be installed to indicate logic '1' or '0'
status on the bootstrap pins. Bootstrap operation is only guaranteed with external pull-up or pull-down
resistors. There are eight Bootstrap pins available on STDP4028. Some bootstraps may not be available
for normal use.
Table 10. Bootstrap configuration
Pin #
Assignment
Function
E3
BOOT[0]
Set to 1 (Pull High to Vdd)
C2
BOOT[1]
Set to 0 (Pull Low to GND)
D4
BOOT[2]
Set to 0 (Pull Low to GND) for normal operation
BOOT[3]
TTL_LVDS_OUT
TTL/LVDS output mode selection
0 = Output is in LVDS format
1 = Output is in TTL format
BOOT[4]
OCM_BOOT_SEL
0 = OCM boot will be from internal ROM code. (Internal ROM is
‘ON’ and mapped to top 32K of OCM address range)
1 = OCM boot is from external ROM/Flash code (Internal ROM is
‘OFF’ and external ROM/Flash mapped to top 512K of OCM
address range)
E5
B12
G10
F11
D12
C4028-DAT-01p
BOOT[5]
WIDE_NARROW_BUS
Selects wide or narrow LVDS or TTL bus
LVDS
0 = DUAL LVDS
1 = QUAD LVDS
TTL
0 = Single
1 = Dual
BOOT[6]
ASSR_ENABLE
Selects whether ASSR is enabled
0 = Disabled
1 = Enabled
BOOT[7]
I2C_DEV_ID
I2C slave Device ID select for RD/WR access.
0: 0xE6, 0xE7
1: 0xE4, 0xE5
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STDP4028
5.3
General purpose input/output (GPIO) pins
The STDP4028 contains 25 general-purpose input/output (GPIO) pins for system configuration purpose.
GPIO_0, GPIO_1 are dedicated general-purpose IO pins and the rest have shared functionality. Each
GPIO has independent direction control and open drain enable for reading and writing.
Note:
The GPIO functionality is available only for custom applications. Default settings allow
configuration of dedicated GPIO pins (GPIO_0 and GPIO_1) through host interface and the
rest of the GPIO configuration requires over-riding the default feature using external
firmware.
C4028-DAT-01p
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STDP4028
6.
Package
Package type: 164 LFBGA (12 x 12 mm / ball pitch 0.8 mm)
Figure 3. Package specification
C4028-DAT-01p
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STDP4028
6.1
Marking field template and descriptors
The STDP4028 marking template is shown below.
Figure 4. Marking template
Field descriptors are shown below.
Table 11.Field descriptors
Field
Description
Marking
A
Standard MegaChips logo
M
B
2-character version code
AB
C
Product code
STDP4028
D
8-character diffusion code
9R”ABCDEF”
E
2-character assembly plant code
AA
F
3-character BE sequence code
“XYZ”
G
2-character diffusion plant code
9R
H
3-character country of origin code
TWN
I
2-character test plant code
AA
J
1-digit assembly year
“Y”
K
2-digit assembly week
“WW”
L
Ball A1 identifier
a DOT
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STDP4028
7.
Electrical specification
7.1
Absolute maximum ratings
Applied conditions greater than those listed under “Absolute maximum ratings” may cause permanent
damage to the device. The device should never exceed absolute maximum conditions since it may affect
device reliability.
Table 12. Absolute maximum ratings
Parameter
Symbol
Min
Typ
Max
Units
VVDD_3.3
-0.3
3.3
3.6
V
VVDD_1.2
-0.3
1.2
1.26
V
VIN5Vtol
-0.3
-
5.5
V
Input voltage (non 5V tolerant inputs) (1,2)
VIN
-0.3
-
3.6
V
ESD - Human Body Model (HBM)(4)
VESD
-
-
±2.0
kV
VESD
-
-
±200
V
VESD
-
-
±500
V
Latch-up
ILA
-
-
±100
mA
Ambient operating temperature
TA
0
-
70
°C
Storage temperature
TSTG
-40
-
150
°C
Operating junction temperature
TJ
0
-
125
°C
Thermal resistance (Junction to Ambient)(3)
θJA
-
-
36.6
°C/W
Thermal resistance (Junction to Case)(3)
θJC
-
-
18.1
°C/W
Peak IR reflow soldering temperature (
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