74HC1G02GW,165

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74HC1G02; 74HCT1G02 2-input NOR gate Rev. 04 — 11 July 2007 Product data sheet 1. General description 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V. The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. The standard output currents are half those of the 74HC02 and 74HCT02. 2. Features n n n n n Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays SOT353-1 and SOT753 package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description 74HC1G02GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1 body width 1.25 mm −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads 74HCT1G02GW 74HC1G02GV 74HCT1G02GV 4. Marking Table 2. Marking codes Type number Marking 74HC1G02GW HB 74HCT1G02GW TB 74HC1G02GV H02 74HCT1G02GV T02 Version SOT753 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate 5. Functional diagram B 1 B 2 A Y 1 4 ≥1 4 Y 2 A mna104 mna103 Fig 1. Logic symbol mna105 Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74HC1G02 74HCT1G02 B 1 A 2 GND 3 5 VCC 4 Y 001aaf085 Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input A 2 data input GND 3 ground (0 V) Y 4 data output VCC 5 supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level Inputs Output A B Y L L H L H L H L L H H L 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 2 of 10 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1] Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7.0 V IIK input clamping current IOK output clamping current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA VO < −0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current −0.5 V < VO < VCC + 0.5 V - ±12.5 mA ICC supply current - 25 mA IGND ground current −25 - mA Tstg storage temperature −65 +150 °C - 200 mW Tamb = −40 °C to +125 °C total power dissipation Ptot [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Above 55 °C the value of Ptot derates linearly with 2.5 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions 74HC1G02 74HCT1G02 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature −40 +25 +125 −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 - - - VCC = 4.5 V - - 139 - - 139 ns/V VCC = 6.0 V - - 83 - - - ns/V ns/V 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - V For type 74HC1G02 VIH VIL HIGH-level input voltage LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 3 of 10 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol VOH VOL Parameter HIGH-level output voltage LOW-level output voltage −40 °C to +85 °C Conditions −40 °C to +125 °C Min Typ Max Min Max Unit VI = VIH or VIL IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - V IO = −2.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V IO = −2.6 mA; VCC = 6.0 V 5.63 5.81 - 5.2 - V IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 V IO = 2.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 2.6 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 - 1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 10 - 20 µA CI input capacitance - 1.5 - - - pF For type 74HCT1G02 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = −2.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 2.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 - 1.0 µA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 10 - 20 µA ∆ICC additional supply current per input; VCC = 4.5 V to 5.5 V; VI = VCC − 2.1 V; IO = 0 A - - 500 - 850 µA CI input capacitance - 1.5 - - - pF 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 4 of 10 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; tr = tf ≤ 6.0 ns; All typical values are measured at Tamb = 25 °C. For test circuit see Figure 6 Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ Max Min Max VCC = 2.0 V; CL = 50 pF - 25 115 - 135 ns VCC = 4.5 V; CL = 50 pF - 9 23 - 27 ns VCC = 5.0 V; CL = 15 pF - 7 - - - ns VCC = 6.0 V; CL = 50 pF - 8 20 - 23 ns - 18 - - - pF - 11 24 - 27 ns - 9 - - - ns - 19 - - - pF For type 74HC1G02 tpd CPD propagation delay A and B to Y; see Figure 5 [1] [2] power dissipation VI = GND to VCC capacitance For type 74HCT1G02 tpd propagation delay A and B to Y; see Figure 5 [1] VCC = 4.5 V; CL = 50 pF VCC = 5.0 V; CL = 15 pF CPD power dissipation VI = GND to VCC − 1.5 V capacitance [1] tpd is the same as tPLH and tPHL. [2] CPD is used to determine the dynamic power dissipation PD (µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts ∑ (CL × VCC2 × fo) = sum of outputs [2] 12. Waveforms A, B input VM VCC tPHL Y output tPLH PULSE GENERATOR VM VI VO DUT CL RT mna101 mna106 For HC1G02: VM = 0.5 × VCC; VI = GND to VCC Test data is given in Table 8. For HCT1G02: VM = 1.3 V; VI = GND to 3.0 V CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 5. Input to output propagation delays Fig 6. Load circuitry for switching times 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 5 of 10 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 7. Package outline SOT353-1 (TSSOP5) 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 6 of 10 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate Plastic surface-mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 Fig 8. Package outline SOT753 (SC-74A) 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 7 of 10 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate 14. Abbreviations Table 9. Abbreviations Acronym Description DUT Device Under Test TTL Transistor-Transistor Logic 15. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT1G02_4 20070711 Product data sheet - 74HC_HCT1G02_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Package SOT353 changed to SOT353-1 in Table 1 and Figure 7. Quick reference data and Soldering sections removed. Section 2 “Features” updated. 74HC_HCT1G02_3 20020517 Product specification - 74HC_HCT1G02_2 74HC_HCT1G02_2 20010302 Product specification - 74HC_HCT1G02_1 74HC_HCT1G02_1 19980831 Product specification - - 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 8 of 10 74HC1G02; 74HCT1G02 NXP Semiconductors 2-input NOR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74HC_HCT1G02_4 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 04 — 11 July 2007 9 of 10 NXP Semiconductors 74HC1G02; 74HCT1G02 2-input NOR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 3 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 8 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Contact information. . . . . . . . . . . . . . . . . . . . . . 9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 July 2007 Document identifier: 74HC_HCT1G02_4