74HC73DB,112

74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 7 — 13 September 2021 Product data sheet 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • CMOS low-power dissipation Wide supply voltage range from 2.0 to 6.0 V High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +80 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC73D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC73PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger 4. Functional diagram 14 1J 1 1CP 3 1K J Q 1Q 12 FF1 CP K Q 1Q 13 R 2 1R 14 1 7 2J 5 2CP 10 2K J Q 14 7 2Q 9 FF2 1 1CP 5 2CP CP K 1J 2J Q 3 10 2Q 8 1K 2K J CP Q R 6 2R 1R 2R 2 6 001aab981 Functional diagram Fig. 2. C 3 1Q 12 2Q 9 2 FF K R Fig. 1. Q 5 10 6 12 C1 1K 13 R 1J 9 C1 1K 8 R 001aab980 001aab979 Logic symbol C 7 1Q 13 2Q 8 1J Fig. 3. C IEC logic symbol C K Q J C C C C R CP Q C C Fig. 4. 001aab982 Logic diagram (one flip-flop) 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 2 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger 5. Pinning information 5.1. Pinning 74HC73 1CP 1 14 1J 1R 2 13 1Q 1K 3 12 1Q VCC 2CP 4 74HC73 1CP 1 14 1J 1R 2 13 1Q 1K 3 12 1Q VCC 4 11 GND 2CP 5 10 2K 2R 6 9 2Q 2J 7 8 2Q 11 GND 5 10 2K 2R 6 9 2Q 2J 7 8 2Q aaa-032289 001aab978 Fig. 5. Pin configuration SOT108-1 (SO14) Fig. 6. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1CP, 2CP 1, 5 clock input (HIGH-to-LOW edge-triggered); also referred to as nCP 1R, 2R 2, 6 asynchronous reset input (active LOW); also referred to as nR 1K, 2K 3, 10 synchronous K input; also referred to as nK VCC 4 positive supply voltage GND 11 ground (0 V) 1Q, 2Q 12, 9 true output; also referred to as nQ 1Q, 2Q 13, 8 complement output; also referred to as nQ 1J, 2J 14, 7 synchronous J input; also referred to as nJ 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition; X = don’t care; ↓ = HIGH-to-LOW clock transition. Input Output Operating mode nR nCP nJ nK nQ nQ L X X X L H asynchronous reset H ↓ h h q q toggle H ↓ l h L H load 0 (reset) H ↓ h l H L load 1 (set) H ↓ l l q q hold (no change) 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 3 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +7.0 V VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA IO output current VO = -0.5 V to VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature -40 - +125 °C Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V -40 °C to +85 °C -40 °C to +125 °C Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL HIGH-level input voltage LOW-level input voltage 74HC73 Product data sheet Conditions 25 °C Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 4 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger Symbol Parameter VOH VOL Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VI = VIH or VIL HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 μA II input leakage current VI = VCC or GND; VCC = 6.0 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 4.0 - 40.0 - 80.0 μA CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 9 Symbol Parameter Conditions tpd nCP to nQ; see Fig. 7 propagation delay 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns VCC = 6.0 V - 15 27 - 34 - 41 ns VCC = 5.0 V; CL = 15 pF - 16 - - - - - ns VCC = 2.0 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns VCC = 6.0 V - 15 27 34 - 41 ns VCC = 5.0 V; CL = 15 pF - 16 - - VCC = 2.0 V - 50 145 - 180 - 220 ns VCC = 4.5 V - 18 29 - 36 - 44 ns VCC = 6.0 V - 14 25 31 - 38 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - ns [1] nCP to nQ; see Fig. 7 ns nR to nQ, nQ; see Fig. 8 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 - © Nexperia B.V. 2021. All rights reserved 5 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger Symbol Parameter tt transition time tW pulse width Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 16 - 19 ns VCC = 2.0 V 80 22 - 100 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 VCC = 2.0 V 80 22 - 100 VCC = 4.5 V 16 8 - 20 VCC = 6.0 V 14 6 - 17 VCC = 2.0 V 80 22 - 100 VCC = 4.5 V 16 8 - 20 VCC = 6.0 V 14 6 - 17 VCC = 2.0 V 80 22 - 100 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 VCC = 2.0 V 3 -8 - 3 VCC = 4.5 V 3 -3 - 3 VCC = 6.0 V 3 -2 - 3 VCC = 2.0 V 6.0 23 - 4.8 VCC = 4.5 V 30 70 - 24 VCC = 6.0 V 35 83 - 28 - 77 - - 30 - nQ, nQ; see Fig. 7 [2] nCP input, HIGH or LOW; see Fig. 7 ns nR input, HIGH or LOW; see Fig. 8 - ns - 24 - ns - 20 ns recovery time nR to nCP; see Fig. 8 trec tsu set-up time th hold time fmax maximum frequency CPD power dissipation capacitance 120 - ns - 24 - ns - 20 ns nJ, nK to nCP; see Fig. 7 ns nJ, nK to nCP; see Fig. 7 3 - ns - 3 - ns - 3 ns nCP input; see Fig. 7 VCC = 5.0 V; CL = 15 pF [1] [2] [3] 120 per flip-flop; VI = GND to VCC [3] 4.0 - MHz - 20 - MHz - 24 - MHz - MHz - pF - - - tpd is the same as tPHL, tPLH. tt is the same as tTHL, tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 6 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger 10.1. Waveforms and test circuit VI nJ, nK input GND VM th tsu VI th tsu 1/f max VM nCP input GND tW tPHL VOH tPLH 90 % nQ output 90 % VM 10 % VOL 10 % tTHL VOH tTLH 90 % 90 % nQ output VM 10 % VOL tPLH 10 % tTLH tPHL tTHL 001aab983 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times, the output transition times and the maximum clock frequency VI VM nCP input GND tW VI trec VM nR input GND tPHL VOH nQ output VOL tPLH VOH nQ output 001aab984 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width and the nR to nCP removal time Table 8. Measurement points Input Output VI VM VM VCC 0.5VCC 0.5VCC 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 7 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger VI negative pulse VM VI GND VM 10 % GND positive pulse tW 90 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig. 9. Test circuit for measuring switching times Table 9. Test data Input Load VI tr, tf CL VCC 6 ns 15 pF, 50 pF 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 8 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 9 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 11. Package outline SOT402-1 (TSSOP14) 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 10 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger 12. Abbreviations Table 10. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC73 v.7 20200913 Product data sheet - Modifications: • 74HC73 v.6 20201204 Modifications: • • • Type number 74HC73DB (SOT337-1/SSOP140removed. Product data sheet - 74HC73 v.5 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Table 4: Derating values for Ptot total power dissipation updated. 74HC73 v.5 20151202 Modifications: • 74HC73 v.4 20080319 Modifications: • • • • 74HC73 v.6 Product data sheet - 74HC73 v.4 Type number 74HC73N (SOT27-1) removed. Product data sheet - 74HC73 v.3 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Quick reference data incorporated into Section 9 and Section 10. Section 8 tr, tf converted to Δt/ΔV. 74HC73 v.3 20041112 Product data sheet - 74HC_HCT73_CNV v.2 74HC_HCT73_CNV v.2 December 1990 Product specification - - 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 11 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC73 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 12 / 13 74HC73 Nexperia Dual JK flip-flop with reset; negative-edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 3 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................4 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms and test circuit........................................ 7 11. Package outline.......................................................... 9 12. Abbreviations............................................................ 11 13. Revision history........................................................11 14. Legal information......................................................12 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 13 September 2021 74HC73 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 13 September 2021 © Nexperia B.V. 2021. All rights reserved 13 / 13