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74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 10 — 2 April 2012
Product data sheet
1. General description
The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for
VCC operation at 3.3 V.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic
levels set up at the nDn inputs.
2. Features and benefits
16-bit edge-triggered flip-flop
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVT16374ADL
40 C to +85 C
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
74LVT16374ADGG
40 C to +85 C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
74LVT16374AEV
40 C to +85 C
VFBGA56
plastic very thin fine-pitch ball grid array
package; 56 balls; body 4.5 7 0.65 mm
SOT702-1
74LVTH16374ABX
40 C to +125 C
HXQFN60
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
SOT1134-2
74LVTH16374ADGG
4. Functional diagram
47
46
44
43
41
40
38
37
1
1OE
48
1CP
24
2OE
25
2CP
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1CP
1
1OE
1D0
1D1
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1D2
1D3
2
3
5
6
8
9
11
12
1D4
1D5
36
35
33
32
30
29
27
26
1D6
1D7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
25
2D0
2D1
2CP
2D2
24
2D3
2OE
2D4
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
2D5
2D6
13
14
16
17
19
20
22
23
2D7
47
EN1
C3
EN2
C4
3D
44
5
43
6
41
8
40
9
38
11
37
12
36
4D
74LVT_LVTH16374A
Product data sheet
2
13
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
001aaa254
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Logic symbol
2
3
001aac369
Fig 1.
1
46
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
2 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
nD0
nD1
D
nD2
D
CP
Q
CP
nD3
D
Q
CP
nD4
D
Q
CP
nD5
D
Q
nD6
D
CP
Q
CP
nD7
D
Q
CP
D
Q
CP
Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
001aac371
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74LVT16374A
74LVTH16374A
1OE
1
48 1CP
1Q0
2
47 1D0
1Q1
3
46 1D1
GND
4
45 GND
1Q2
5
44 1D2
1Q3
6
43 1D3
VCC
7
42 VCC
1Q4
8
41 1D4
1Q5
9
40 1D5
GND 10
39 GND
1Q6 11
38 1D6
1Q7 12
37 1D7
2Q0 13
36 2D0
2Q1 14
35 2D1
GND 15
34 GND
2Q2 16
33 2D2
2Q3 17
32 2D3
VCC 18
31 VCC
2Q4 19
30 2D4
2Q5 20
29 2D5
GND 21
28 GND
2Q6 22
27 2D6
2Q7 23
26 2D7
2OE 24
25 2CP
ball A1
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
001aak264
Transparent top view
001aak263
Fig 4.
Pin configuration for SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
74LVT_LVTH16374A
Product data sheet
74LVT16374A
74LVTH16374A
Fig 5.
Pin configuration for SOT702-1 (VFBGA56)
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
3 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
terminal 1
index area
D1
A32
A1
D5
A31
A30
B20
A29
B19
A28
B18
A27
D4
D8
A26
A2
A25
B17
B1
A3
A24
B16
B2
A4
A23
B15
B3
A5
A22
74LVT16374A
74LVTH16374A
B4
A6
B14
A21
B5
B13
A7
A20
B6
B12
B7
B11
A8
A19
A9
A18
GND(1)
A10
D6
D2
A11
B8
A12
B10
B9
A13
A14
A15
D7
A17
A16
D3
001aak265
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 6.
Pin configuration SOT1134-2 (HXQFN60)
74LVT_LVTH16374A
Product data sheet
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Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
4 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
SOT370-1 and
SOT362-1
SOT702-1
SOT1134-2
1OE, 2OE
1, 24
A1, K1
A30, A13
output enable input (active LOW)
1CP, 2CP
48, 25
A6, K6
A29, A14
clock input
1Q0 to 1Q7
2, 3, 5, 6, 8, 9, 11, 12
B2, B1, C2, C1, D2,
D1, E2, E1
B20, A31, D5, D1, A2, data output
B2, B3, A5
2Q0 to 2Q7
13, 14, 16, 17, 19, 20,
22, 23
F1, F2, G1, G2, H1,
H2, J1, J2
A6, B5, B6, A9, D2,
D6, A12, B8
GND
4, 10, 15, 21, 28, 34, 39, B3, D3, G3, J3, J4,
45
G4, D4, B4
A32, A3, A8, A11, A16, ground (0 V)
A19, A24, A27
data output
VCC
7, 18, 31, 42
C3, H3, H4, C4
A1, A10, A17, A26
supply voltage
1D0 to 1D7
47, 46, 44, 43, 41, 40,
38, 37
B5, B6, C5, C6, D5,
D6, E5, E6
B18, A28, D8, D4,
A25, B16, B15, A22
data input
2D0 to 2D7
36, 35, 33, 32, 30, 29,
27, 26
F6, F5, G6, G5, H6,
H5, J6, J5
A21, B13, B12, A18,
D3, D7, A15, B10
data input
n.c.
-
A2, A3, A4, A5,
A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
not connected
K2, K3, K4, K5
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
nOE
nCP
nDn
Load and read register
L
L
Hold
Disable outputs
[1]
Internal register
Output
l
L
L
h
H
H
L
NC
X
NC
NC
H
NC
X
NC
Z
H
nDn
nDn
Z
nQ0 to nQ7
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
5 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
0.5
+4.6
V
[1]
0.5
+7.0
V
[1]
0.5
+7.0
V
50
-
mA
VI
input voltage
VO
output voltage
output in OFF-state or
HIGH-state
IIK
input clamping current
VI < 0 V
IOK
output clamping current
VO < 0 V
50
-
mA
IO
output current
output in LOW-state
-
128
mA
output in HIGH-state
64
-
mA
65
+150
C
[2]
-
150
C
(T)SSOP48 package
[3]
-
500
mW
VFBGA56 and HXQFN60
package
[4]
-
1000
mW
storage temperature
Tstg
Tj
junction temperature
Ptot
total power dissipation
Tamb = 40 C to +85 C
[1]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2]
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3]
Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4]
Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Min
Typ
Max
Unit
VCC
supply voltage
Conditions
2.7
-
3.6
V
VI
input voltage
0
-
5.5
V
VIH
HIGH-level input voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
IOH
HIGH-level output current
32
-
-
mA
IOL
LOW-level output current
none
-
-
32
mA
current duty cycle 50 %;
fi 1 kHz
-
-
64
mA
in free-air
40
-
+85
C
-
-
10
ns/V
Tamb
ambient temperature
t/V
input transition rise and fall rate outputs enabled
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
6 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
VCC = 2.7 V; IIK = 18 mA
1.2
0.85
Tamb = 40 C to +85 C
VIK
input clamping voltage
VOH
HIGH-level output voltage IOH = 100 A; VCC = 2.7 V to 3.6 V
VOL
-
V
VCC 0.2 VCC
-
V
IOH = 8 mA; VCC = 2.7 V
2.4
2.5
-
V
IOH = 32 mA; VCC = 3.0 V
2.0
2.3
-
V
IOL = 100 A
-
0.07
0.2
V
IOL = 24 mA
-
0.3
0.5
V
IOL = 16 mA
-
0.25
0.4
V
IOL = 32 mA
-
0.3
0.5
V
-
0.4
0.55
V
-
0.1
0.55
V
-
0.1
1
A
-
0.4
10
A
VCC = 0 V or 3.6 V; VI = 5.5 V
-
0.4
10
A
VCC = 3.6 V; VI = VCC
-
0.1
1
A
VCC = 3.6 V; VI = 0 V
5
0.4
-
A
LOW-level output voltage VCC = 2.7 V
VCC = 3.0 V
IOL = 64 mA
VOL(pu)
power-up LOW-level
output voltage
VCC = 3.6 V; IO = 1 mA; VI = VCC or GND
II
input leakage current
control pins
[2]
VCC = 3.6 V; VI = VCC or GND
VCC = 0 V or 3.6 V; VI = 5.5 V
input data pins
[3]
IOFF
power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V
-
0.1
100
A
IBHL
bus hold LOW current
VCC = 3 V; VI = 0.8 V
75
135
-
A
IBHH
bus hold HIGH current
VCC = 3 V; VI = 2.0 V
IBHLO
bus hold LOW
overdrive current
input data pins;
VI = 0 V to 3.6 V; VCC = 3.6 V
[4]
IBHHO
bus hold HIGH
overdrive current
input data pins;
VI = 0 V to 3.6 V; VCC = 3.6 V
[4]
ILO
output leakage current
output in HIGH-state when VO > VCC;
VO = 5.5 V; VCC = 3.0 V
IO(pu/pd)
power-up/power-down
output current
VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or
VCC; nOE = don’t care
IOZ
OFF-state output current
VCC = 3.6 V; VI = VIH or VIL
ICC
supply current
[5]
75
A
500
-
-
A
-
-
500
A
-
50
125
A
-
1
100
A
output HIGH: VO = 3.0 V
-
0.5
5
A
5
0.5
-
A
-
0.07
0.12
mA
VCC = 3.6 V; VI = GND or VCC; IO = 0 A
outputs LOW
outputs disabled
Product data sheet
135
output LOW: VO = 0.5 V
outputs HIGH
74LVT_LVTH16374A
-
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
[6]
-
4.0
6.0
mA
-
0.07
0.12
mA
© NXP B.V. 2012. All rights reserved.
7 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
-
0.1
0.2
mA
ICC
additional supply current
CI
input capacitance
input pins; VI = 0 V or 3.0 V
-
3
-
pF
CO
output capacitance
output pins nQn; outputs disabled;
VO = 0 V or VCC
-
9
-
pF
per input pin; VCC = 3.0 V to 3.6 V; one input
at VCC 0.6 V, other inputs at VCC or GND
[7]
[1]
Typical values are measured at VCC = 3.3 V and at Tamb = 25 C.
[2]
For valid test results, data must not be loaded into the flips-flops (or latches) after applying power.
[3]
Unused pins at VCC or GND.
[4]
This is the bus hold overdrive current required to force the input to the opposite logic state.
[5]
This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V
a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only.
[6]
ICC is measured with outputs pulled to VCC or GND.
[7]
This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
Tamb = 40 C to +85 C
fmax
maximum frequency nCP; VCC = 3.3 V 0.3 V; see Figure 7
150
-
-
MHz
tPLH
LOW to HIGH
propagation delay
VCC = 3.3 V 0.3 V
1.5
2.9
5.0
ns
VCC = 2.7 V
-
-
5.6
ns
VCC = 3.3 V 0.3 V
1.5
3.0
5.0
ns
VCC = 2.7 V
-
-
5.6
ns
VCC = 3.3 V 0.3 V
1.5
3.2
4.8
ns
VCC = 2.7 V
-
-
6.0
ns
VCC = 3.3 V 0.3 V
1.5
3.0
4.6
ns
VCC = 2.7 V
-
-
5.2
ns
VCC = 3.3 V 0.3 V
1.5
3.9
5.4
ns
VCC = 2.7 V
-
-
6.0
ns
VCC = 3.3 V 0.3 V
1.5
3.4
4.6
ns
VCC = 2.7 V
-
-
5.0
ns
tPHL
tPZH
tPZL
tPHZ
tPLZ
HIGH to LOW
propagation delay
nCP to nQn; see Figure 7
nCP to nQn; see Figure 7
OFF-state to HIGH
propagation delay
nOE to nQn; see Figure 8
OFF-state to LOW
propagation delay
nOE to nQn; see Figure 8
HIGH to OFF-state
propagation delay
LOW to OFF-state
propagation delay
74LVT_LVTH16374A
Product data sheet
nOE to nQn; see Figure 8
nOE to nQn; see Figure 8
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
8 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol
Parameter
tsu
Min
Typ[1]
Max
Unit
2.0
0.7
-
ns
2.0
-
-
ns
0.8
0
-
ns
0.1
-
-
ns
VCC = 3.3 V 0.3 V
1.5
0.6
-
ns
VCC = 2.7 V
1.5
-
-
ns
VCC = 3.3 V 0.3 V
3.0
1.6
-
ns
VCC = 2.7 V
3.0
-
-
ns
Conditions
set-up time
nDn to nCP; HIGH or LOW; see Figure 9
[2]
VCC = 3.3 V 0.3 V
VCC = 2.7 V
hold time
th
nDn to nCP; HIGH or LOW; see Figure 9
[3]
VCC = 3.3 V 0.3 V
VCC = 2.7 V
pulse width
tW
[4]
nCP HIGH; see Figure 7
nCP LOW; see Figure 7
[1]
All typical values are at VCC = 3.3 V and Tamb = 25 C.
[2]
tsu is the same as tsu(H) and tsu(L).
[3]
th is the same as th(H) and th(L).
[4]
tW is the same as tW(H) and tW(L).
11. Waveforms
1/fmax
VI
nCP input
VM
VM
GND
tW
t PHL
t PLH
VOH
VM
nQn output
001aaa256
VOL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Propagation delay clock input to output, clock pulse width and maximum clock frequency
Table 8.
Measurement points
Input
Output
VM
VM
VX
VY
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
9 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
VI
nOE input
VM
GND
tPZL
tPLZ
3.0 V
VM
nYn output
VX
VOL
t PZH
t PHZ
VOH
nYn output
VY
VM
0V
001aae464
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8.
Enable and disable times
VI
VM
nCP input
GND
t su
t su
th
th
VI
VM
nDn input
GND
VOH
VM
nQn output
VOL
001aaa257
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9.
Data set-up and hold times
74LVT_LVTH16374A
Product data sheet
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74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
PULSE
GENERATOR
RL
VO
DUT
RT
CL
RL
001aae235
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 10. Test circuit for measuring switching times
Table 9.
Test data
Input
Load
VEXT
VI
fi
tW
tr, tf
CL
RL
tPHZ, tPZH
tPLZ, tPZL
tPLH, tPHL
2.7 V
10 MHz
500 ns
2.5 ns
50 pF
500
GND
6V
open
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
11 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
HE
v M A
Z
25
48
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
24
1
detail X
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
16.00
15.75
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT370-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-118
Fig 11. Package outline SOT370-1 (SSOP48)
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
12 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
HE
y
v M A
Z
48
25
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
24
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.8
0.4
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT362-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 12. Package outline SOT362-1 (TSSOP48)
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
13 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
B
D
SOT702-1
A
ball A1
index area
A
E
A2
A1
detail X
e1
1/2
C
∅v M
C A B
∅w M C
b
e
y1 C
e
y
K
J
H
e
G
F
e2
E
D
1/2
e
C
X
B
A
ball A1
index area
1
2
3
4
5
6
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1
0.3
0.2
0.7
0.6
0.45
0.35
4.6
4.4
7.1
6.9
0.65
3.25
5.85
0.15
0.08
0.08
0.1
OUTLINE
VERSION
SOT702-1
REFERENCES
IEC
JEDEC
JEITA
0
2.5
5 mm
scale
EUROPEAN
PROJECTION
ISSUE DATE
02-08-08
03-07-01
MO-225
Fig 13. Package outline SOT702-1 (VFBGA56)
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
14 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;
60 terminals; body 4 x 6 x 0.5 mm
A
B
D
SOT1134-2
terminal 1
index area
A
A2
E
A1
detail X
e2
b
e1
L1
L
A11
B10
A17
A10
eR
eT
y
y1 C
D3
D7
A16
B8
C
eT
1/2 e
D2
D6
C A B
C
eR
e
C A B
C
v
w
v
w
e
B11
B7
Eh
e3
e4
1/2 e
B17
B1
A1
terminal 1
index area
A26
D5
D1
A32
B20 B18
A27
Dh
D8
D4
eT
eR
X
K
eT
eR
0
5 mm
Dimensions
Unit
mm
A
A1
A2
b
max 0.50 0.08 0.42 0.28
nom
0.05 0.40 0.23
min
0.02 0.38 0.18
D
Dh
E
Eh
e
e1
e2
e3
e4
eR
4.1
4.0
3.9
1.95
1.85
1.75
6.1
6.0
5.9
3.95
3.85
3.75
0.5
1.0
2.5
3.0
4.5
0.5
eT
K
L
L1
v
w
0.25 0.28 0.195
0.49 0.20 0.23 0.145 0.1
0.15 0.18 0.095
y
0.05 0.08
y1
0.1
sot1134-2_po
References
Outline
version
IEC
JEDEC
JEITA
SOT1134-2
---
---
---
European
projection
Issue date
11-08-15
Fig 14. Package outline SOT1134-2 (HXQFN60)
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
15 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
BiCMOS
Bipolar Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
74LVT_LVTH16374A v.10 20120402
Modifications:
74LVT_LVTH16374A v.9
Modifications:
•
Change notice
Supersedes
Product data sheet
-
74LVT_LVTH16374A v.9
For type number 74LVTH16374ABX the sot code has changed to SOT1134-2.
20111122
•
Data sheet status
Product data sheet
-
74LVT_LVTH16374A v.8
Legal pages updated.
74LVT_LVTH16374A v.8
20110620
Product data sheet
-
74LVT_LVTH16374A v.7
74LVT_LVTH16374A v.7
20100322
Product data sheet
-
74LVT_LVTH16374A v.6
74LVT_LVTH16374A v.6
20100118
product data sheet
-
74LVT16374A v.5
74LVT16374A v.5
20040916
product data sheet
-
74LVT16374A v.4
74LVT16374A v.4
20021101
product specification
-
74LVT16374A v.3
74LVT16374A v.3
19991018
product specification
-
74LVT16374A v.2
74LVT16374A v.2
19980219
product specification
-
-
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
16 of 19
74LVT16374A; 74LVTH16374A
NXP Semiconductors
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVT_LVTH16374A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
17 of 19
NXP Semiconductors
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT_LVTH16374A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 2 April 2012
© NXP B.V. 2012. All rights reserved.
18 of 19
NXP Semiconductors
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 April 2012
Document identifier: 74LVT_LVTH16374A