74ALVCH16501DL,118

74ALVCH16501 18-bit universal bus transceiver; 3-state Rev. 7 — 24 November 2021 Product data sheet 1. General description The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH and OEBA is active LOW). This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Current drive ±24 mA at VCC = 3.0 V Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode Bus hold on all data inputs Output drive capability 50 Ω transmission lines at 85 °C 3-state non-inverting outputs for bus-oriented applications Latch-up performance exceeds 100 mA per JESD78 Class II Level B Complies with JEDEC standards: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Package 74ALVCH16501DGG Temperature range Name Description Version -40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 4. Functional diagram OEAB CPAB LEAB OEBA 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1 2 55 Fig. 1. A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17 B17 OEAB OEBA LEAB LEBA CPAB CPBA CPBA 54 LEBA 52 1 55 2 27 30 28 EN1 2C3 C3 G2 EN4 5C6 C6 G5 51 49 A0 48 47 A1 45 A2 44 A3 43 A4 42 A5 41 A6 40 A7 38 A8 37 A9 36 A10 34 A11 33 A12 31 A13 A14 27 A15 28 A16 30 A17 3 5 3D 1 1 4 1 6D 54 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 001aal718 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 001aal717 Logic symbol Fig. 2. IEC logic symbol VCC data input to internal circuit 001aal733 Fig. 3. Bus hold circuit 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 2 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state OEAB CPBA LEBA CPAB LEAB OEBA A1 C1 C1 1D 1D C1 C1 1D 1D B1 18 IDENTICAL CHANNELS 001aal719 Fig. 4. Logic diagram 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 3 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 5. Pinning information 5.1. Pinning 74ALVCH16501 OEAB 1 56 GND LEAB 2 55 CPAB A0 3 54 B0 GND 4 53 GND A1 5 52 B1 A2 6 51 B2 VCC 7 50 VCC A3 8 49 B3 A4 9 48 B4 A5 10 47 B5 GND 11 46 GND A6 12 45 B6 A7 13 44 B7 A8 14 43 B8 A9 15 42 B9 A10 16 41 B10 A11 17 40 B11 GND 18 39 GND A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 VCC 22 35 VCC A15 23 34 B15 A16 24 33 B16 GND 25 32 GND A17 26 31 B17 OEBA 27 30 CPBA LEBA 28 29 GND 001aal716 Fig. 5. Pin configuration SOT364-1 (TSSOP56) 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 4 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description OEAB 1 output enable A-to-B input (active HIGH) LEAB 2 latch enable A-to-B input A0 to A17 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 data inputs or outputs GND 4, 11, 18, 25, 29, 32, 39, 46, 53, 56 ground (0 V) VCC 7, 22, 35, 50 positive supply voltage OEBA 27 output enable B-to-A (active LOW) LEBA 28 latch enable B-to-A CPBA 30 clock input B-to-A B0 to B17 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs or outputs CPAB 55 clock input A-to-B 6. Functional description Table 3. Function table A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the enable or clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the enable or clock transition; X = don’t care; Z = high-impedance OFF-state; ↓ = HIGH-to-LOW clock transition; ↑ = LOW-to-HIGH clock transition. Output Inputs Operating mode OEAB LEAB CPAB An Bn L X X X Z disabled H H X H H transparent H H X L L H ↓ X h H H ↓ X l L H L ↑ h H H L ↑ l L H L H or L X H H L H or L X L 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 latch data and display clock data and display hold data and display © Nexperia B.V. 2021. All rights reserved 5 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +4.6 V -50 - VCC supply voltage IIK input clamping current VI < 0 V VI input voltage control inputs [1] -0.5 data inputs [1] -0.5 IOK output clamping current VO output voltage IO output current ICC IGND VO > VCC or VO < 0 V +4.6 ±50 -0.5 mA VCC + 0.5 V - ±50 mA supply current - 100 mA ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] VO = 0 V to VCC V VCC + 0.5 V [1] mA Tamb = -40 °C to +85 °C The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage Min Typ Max Unit CL = 30 pF 2.3 - 2.7 V CL = 50 pF 3.0 - 3.6 V low-voltage applications 1.2 - 3.6 V maximum speed performance VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature in free air -40 - +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 - 20 ns/V VCC = 3.0 V to 3.6 V 0 - 10 ns/V 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 6 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ [1] Max Unit - V Tamb = -40 °C to +85 °C VIH HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 VCC = 2.7 V to 3.6 V 2.0 1.5 - V VIL LOW-level input voltage VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V VOH VOL LOW-level output voltage VI = VIH or VIL IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V II input leakage current VI = VCC or GND; VCC = 2.3 V to 3.6 V - 0.1 5 μA IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 2.7 V to 3.6 V - 0.1 10 μA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current per data I/O pin; VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 150 750 μA IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V [2] 45 - - μA VCC = 3.0 V; VI = 0.8 V [2] 75 150 - μA IBHH bus hold HIGH current VCC = 2.3 V; VI = 1.7 V [2] -45 - - μA VCC = 3.0 V; VI = 2.0 V [2] -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V [2] 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V [2] -500 - - μA CI input capacitance - 4.0 - pF CI/O input/output capacitance - 8.0 - pF [1] [2] All typical values are measured at Tamb = 25 °C. Valid for data inputs of bus hold parts only. 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 7 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 10. Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = -40 °C to +85 °C fmax maximum frequency see Fig. 8 VCC = 2.3 V to 2.7 V [2] 150 333 - MHz VCC = 3.0 V to 3.6 V [3] 150 340 - MHz 150 333 - MHz VCC = 2.7 V tpd propagation delay An to Bn; Bn to An; see Fig. 6 [4] VCC = 2.3 V to 2.7 V [2] 1.0 2.8 5.1 ns VCC = 3.0 V to 3.6 V [3] 1.0 3.0 4.2 ns - 3.0 4.6 ns VCC = 2.7 V LEAB, LEBA to Bn, An; see Fig. 8 VCC = 2.3 V to 2.7 V [2] 1.1 3.5 6.1 ns VCC = 3.0 V to 3.6 V [3] 1.3 3.4 4.8 ns - 3.6 5.3 ns VCC = 2.7 V CPAB, CPBA to Bn, An; see Fig. 8 VCC = 2.3 V to 2.7 V [2] 1.0 3.3 6.1 ns VCC = 3.0 V to 3.6 V [3] 1.4 3.3 4.9 ns - 3.4 5.6 ns VCC = 2.7 V ten enable time OEBA to An; see Fig. 7 [4] VCC = 2.3 V to 2.7 V [2] 1.3 2.8 6.3 ns VCC = 3.0 V to 3.6 V [3] 1.1 2.5 5.0 ns - 3.3 6.0 ns VCC = 2.7 V OEAB to Bn; see Fig. 7 VCC = 2.3 V to 2.7 V [2] 1.0 2.5 5.8 ns VCC = 3.0 V to 3.6 V [3] 1.0 2.4 4.6 ns - 2.7 5.3 ns VCC = 2.7 V tdis disable time OEBA to An; see Fig. 7 [4] VCC = 2.3 V to 2.7 V [2] 1.3 2.5 5.3 ns VCC = 3.0 V to 3.6 V [3] 1.3 3.1 4.2 ns - 3.3 4.6 ns VCC = 2.7 V OEAB to Bn; see Fig. 7 VCC = 2.3 V to 2.7 V [2] 1.5 2.5 6.2 ns VCC = 3.0 V to 3.6 V [3] 1.4 2.9 5.0 ns - 3.6 5.7 ns VCC = 2.7 V 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 8 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state Symbol Parameter Conditions tW LEAB, LEBA HIGH; see Fig. 8 pulse width Min Typ [1] Max Unit VCC = 2.3 V to 2.7 V [2] 3.3 0.8 - ns VCC = 3.0 V to 3.6 V [3] 3.3 0.9 - ns 3.3 0.7 - ns VCC = 2.7 V CPAB, CPBA HIGH or LOW; see Fig. 8 VCC = 2.3 V to 2.7 V [2] 3.3 2.0 - ns VCC = 3.0 V to 3.6 V [3] 3.3 1.1 - ns 3.3 1.4 - ns VCC = 2.7 V tsu set-up time An, Bn to CPAB, CPBA; see Fig. 9 VCC = 2.3 V to 2.7 V [2] 1.7 0.1 - ns VCC = 3.0 V to 3.6 V [3] 1.3 -0.3 - ns 1.4 -0.1 - ns VCC = 2.7 V An, Bn to LEAB, LEBA; see Fig. 9 VCC = 2.3 V to 2.7 V [2] 1.1 0.1 - ns VCC = 3.0 V to 3.6 V [3] 1.0 0.3 - ns 1.0 -0.2 - ns VCC = 2.7 V th hold time An, Bn to CPAB, CPBA; see Fig. 9 VCC = 2.3 V to 2.7 V [2] 1.7 0.3 - ns VCC = 3.0 V to 3.6 V [3] 1.3 0.4 - ns 1.6 0.3 - ns VCC = 2.7 V An, Bn to LEAB, LEBA; see Fig. 9 VCC = 2.3 V to 2.7 V [2] 1.6 0.3 - ns VCC = 3.0 V to 3.6 V [3] 1.2 0.1 - ns 1.5 0.1 - ns outputs enabled - 21 - pF outputs disabled - 3 - pF VCC = 2.7 V power dissipation capacitance per buffer; VI = GND to VCC CPD [1] [2] [3] [4] [5] [5] All typical values are measured at Tamb = 25 °C. Typical values are measured at VCC = 2.5 V. Typical values are measured at VCC = 3.3 V. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; 2 Σ(CL × VCC × fo) = sum of outputs. 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 9 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 10.1. Waveforms and test circuit VI An, Bn input VM VM tPHL tPLH GND VOH Bn, An output VM VM VOL 001aal734 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig. 6. Propagation delay, data input (An, Bn) to data output (Bn, An) VI OEAB, OEBA input VM VM GND tPLZ An, Bn output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPZH tPHZ An, Bn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aal721 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig. 7. 3-state output enable and disable times 1 / fmax VI LExx input CPxx input GND An, Bn output VOH VM VM VM tW tPLH tPHL VM VOL VM 001aal720 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig. 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output, and pulse width 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 10 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state VI An, Bn input VM VM GND tsu VM th VM tsu th VI CPxx, LExx input VM VM GND 001aal722 Measurement points are given in Table 8. Fig. 9. Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs) Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 1.8 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to Zo of pulse generator. VEXT = External voltage for measuring switching times. Fig. 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 1.8 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVCH16501 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 11 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 11. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 11. Package outline SOT364-1 (TSSOP56) 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 12 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16501 v.7 20211124 Product data sheet - 74ALVCH16501 v.6 Modifications: • • 74ALVCH16501 v.6 20190313 - 74ALVCH16501 v.5 Modifications: • • • Section 1 and Section 2 updated. Errata corrected in Table 4. The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type numbers 74ALVCH16501DL (SOT371-1) removed. 74ALVCH16501 v.5 20120710 Modifications: • 74ALVCH16501 v.4 20111117 Modifications: • 74ALVCH16501 v.3 20100402 74ALVCH16501 v.2 19980929 74ALVCH16501 v.1 19980929 74ALVCH16501 Product data sheet Product data sheet Product data sheet - 74ALVCH16501 v.4 - 74ALVCH16501 v.3 Product data sheet - 74ALVCH16501 v.2 Product specification - 74ALVCH16501 v.1 Product specification - - Table 8 corrected (errata). Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 13 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 14 / 15 74ALVCH16501 Nexperia 18-bit universal bus transceiver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 5 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................6 9. Static characteristics....................................................7 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 12 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 24 November 2021 74ALVCH16501 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 24 November 2021 © Nexperia B.V. 2021. All rights reserved 15 / 15