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INTEGRATED CIRCUITS
74LVT162373
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
Product specification
IC23 Data Handbook
1999 Sep 23
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
FEATURES
74LVT162373
DESCRIPTION
• 16-bit transparent latch
• 3-State buffers
• Output capability: +12 mA / –12 mA
• TTL input and output switching levels
• Input and output interface capability to systems at 5 V supply
• Bus-hold data inputs eliminate the need for external pull-up
The 74LVT162373 is a high-performance BiCMOS product designed
for VCC operation at 3.3 V.
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When Latch Enable (LE) input is
High, the Q outputs follow the data (D) inputs. When Latch Enable is
taken Low, the Q outputs are latched at the levels of the D inputs
one setup time prior to the High-to-Low transition.
resistors to hold unused inputs
The 74LVT162373 is designed with 30 Ω series resistance in both
the High and Low states of the output. This design reduces the
noise in applications such as memory address drivers, clock drivers,
and bus receivers/transmitters.
• Live insertion/extraction permitted
• Outputs include series resistance of 30 Ω making external
resistors unnecessary
• Power-up reset
• Power-up 3-State
• No bus current loading when output is tied to 5 V bus
• Latch-up protection exceeds 500 mA per JEDEC Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL
CONDITIONS
Tamb = 25 °C
PARAMETER
TYPICAL
UNIT
3.0
ns
tPLH
tPHL
Propagation delay
nDx to nQx
CL = 50 pF;
VCC = 3.3 V
CIN
Input capacitance
VI = 0 V or 3.0 V
3
pF
COUT
Output capacitance
Outputs disabled; VO = 0 V or 3.0 V
9
pF
ICCZ
Total supply current
Outputs disabled; VCC = 3.6 V
70
µA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDERING CODE
DWG NUMBER
48-Pin Plastic SSOP Type III
–40 °C to +85 °C
74LVT162373 DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40 °C to +85 °C
74LVT162373 DGG
SOT362-1
1999 Sep 23
2
853-2172 22406
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
PIN CONFIGURATION
LOGIC SYMBOL
1OE
1
48
1LE
47
1Q0
2
47
1D0
1Q1
3
46
1D1
GND
4
45
GND
48
1LE
1Q2
5
44
1D2
1
1OE
1Q3
6
43
1D3
VCC
7
42
VCC
1Q4
8
41
1D4
1Q5
9
40
1D5
GND
10
39
GND
1Q6
11
38
1D6
1Q7
12
37
1D7
2Q0
13
36
2D0
25
2LE
24
2OE
2Q1
14
35
2D1
GND
15
34
GND
2Q2
16
33
2D2
2Q3
17
32
2D3
VCC
18
31
VCC
2Q4
19
30
2D4
2Q5
20
29
2D5
GND
21
28
GND
2Q6
22
27
2D6
41
40
38
37
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SA00044
LOGIC SYMBOL (IEEE/IEC)
23
26
2D7
1OE
1
1EN
24
25
2LE
1LE
48
C3
SA00043
2OE
24
2EN
2LE
25
C4
1D1
47
3D
2
1Q1
1D2
46
3
1Q2
1D3
44
5
1Q3
1D4
43
6
1Q4
1D5
41
8
1Q5
1D6
40
9
1Q6
1D7
38
11
1Q7
1D8
37
12
1Q8
2D1
36
13
2Q1
2D2
35
14
2Q2
2D3
33
16
2Q3
2D4
32
17
2Q4
2D5
30
19
2Q5
2D6
29
20
2Q6
2D7
27
22
2Q7
2D8
26
23
2Q8
2, 3, 5, 6, 8, 9, 11,
12, 13, 14, 16, 17,
19, 20, 22, 23
7, 18, 31, 42
43
2Q7
47, 46, 44, 43, 41,
40, 38, 37, 36, 35,
33, 32, 30, 29, 27, 26
4, 10, 15, 21,
28, 34, 39, 45
44
2OE
PIN NUMBER
48, 25
46
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
PIN DESCRIPTION
1, 24
74LVT162373
SYMBOL
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
1OE, 2OE
1LE, 2LE
GND
VCC
FUNCTION
Data inputs
Data outputs
Output Enable inputs
(active-Low)
Latch Enable inputs
(active-High)
Ground (0V)
Positive supply voltage
4D
1∇
2∇
SW00010
1999 Sep 23
3
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
74LVT162373
LOGIC DIAGRAM
nD0
nD1
D
E
nD2
nD3
D
Q
E
D
Q
E
nD4
D
Q
nD5
D
E
Q
E
nD6
D
Q
E
nD7
D
Q
E
D
Q
E
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00046
FUNCTION TABLE
INPUTS
H =
h =
L =
l =
NC=
X =
Z =
↓ =
OUTPUTS
nOE
nLE
nDx
INTERNAL
REGISTER
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
↓
↓
l
h
L
H
L
H
Latch and read register
L
L
X
NC
NC
H
H
L
H
X
nDx
NC
nDx
Z
Z
OPERATING MODE
nQ0 – nQ7
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off ” state
High-to-Low LE transition
SCHEMATIC OF EACH OUTPUT
VCC
27 Ω
OUTPUT
27 Ω
SW00503
1999 Sep 23
4
Hold
Disable outputs
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
74LVT162373
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
RATING
UNIT
–0.5 to +4.6
V
–50
mA
–0.5 to +7.0
V
VO < 0
–50
mA
Output in Off or High state
–0.5 to +7.0
V
Output in Low state
128
Output in High state
–64
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
VOUT
CONDITIONS
DC output
voltage3
IOUT
O
DC output current
Tstg
Storage temperature range
mA
–65 to +150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
VCC
PARAMETER
UNIT
DC supply voltage
MIN
MAX
2.7
3.6
V
0
5.5
V
VI
Input voltage
VIH
High-level input voltage
VIL
Input voltage
0.8
V
IOH
High-level output current
–12
mA
IOL
Low-level output current
12
mA
∆t/∆v
Input transition rise or fall rate; Outputs enabled
10
ns/V
Tamb
Operating free-air temperature range
+85
°C
1999 Sep 23
2.0
–40
5
V
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
74LVT162373
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = –40°C to +85°C
MIN
VIK
Input clamp voltage
VCC = 2.7V; IIK = –18mA
VOH
High-level output voltage
VCC = 3.0V; IOH = –12mA
VOL
Low–level output voltage
VCC = 3.0V; IOL = 16mA
VRST
Power-up output Low voltage5
VCC = 3.6V; IO = 1mA; VI = GND or VCC
VCC = 3.6V; VI = VCC or GND
II
Input leakage current
Control pins
Data
pins4
VCC = 3.6V; VI = 0
IOFF
Output off current
MAX
–0.85
–1.2
V
0.8
V
0.1
0.55
V
0.1
±1
0.4
10
0.1
1
–0.4
–5
0.1
±100
2.0
VCC = 0 or 3.6V; VI = 5.5V
VCC = 3.6V; VI = VCC
UNIT
TYP1
VCC = 0V; VI or VO = 0 to 4.5V
VCC = 3V; VI = 0.8V
75
135
VCC = 3V; VI = 2.0V
–75
–135
VCC = 0V to 3.6V; VCC = 3.6V
±500
µA
µA
µA
IHOLD
Bus Hold current D inputs7
IEX
Current into an output in the
High state when VO > VCC
VO = 5.5V; VCC = 3.0V
50
125
µA
Power up/down 3-State output
current3
VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE = Don’t care
1
±100
µA
IOZH
3-State output High current
VCC = 3.6V; VO = 3.0V; VI = VIH or VIL
0.5
5
IOZL
3-State output Low current
VCC = 3.6V; VO = 0.5V; VI = VIH or VIL
0.5
–5
VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0
0.07
0.12
4.0
6
0.07
0.12
0.1
0.2
IPU/PD
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0
VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO =
Additional supply current per
input pin2
VCC = 3V to 3.6V; One input at VCC-0.6V,
Other inputs at VCC or GND
06
µA
mA
mA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. ICCZ is measured with outputs pulled to VCC or GND.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1999 Sep 23
6
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
74LVT162373
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
LIMITS
SYMBOL
PARAMETER
VCC = 3.3V ±0.3V
VCC = 2.7V
MIN
TYP1
MAX
MAX
WAVEFORM
UNIT
tPLH
tPHL
Propagation delay
nDx to nQx
2
0.5
0.5
2.5
2.5
4.6
4.0
5.1
4.3
ns
tPLH
tPHL
Propagation delay
nLE to nQx
1
0.5
0.5
3.0
3.0
5.1
4.6
5.8
4.3
ns
tPZH
tPZL
Output enable time
to High and Low level
4
5
0.1
0.1
3.5
3.2
5.4
4.9
6.6
5.5
ns
tPHZ
tPLZ
Output disable time
from High and Low Level
4
5
0.1
0.1
3.5
3.2
5.4
5.1
5.7
5.0
ns
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
LIMITS
SYMBOL
PARAMETER
VCC = 3.3V ±0.3V
WAVEFORM
VCC = 2.7V
MIN
TYP
MIN
UNIT
tS(H)
tS(L)
Setup time
nDx to nLE
3
1.5
2.0
0.1
0.2
1.0
2.0
ns
th(H)
th(L)
Hold time
nDx to nLE
3
1.0
1.5
0
0
1.0
2.0
ns
tW(H)
nLE pulse width
High
1
1.5
0.5
1.5
ns
AC WAVEFORMS
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉÉ
For all waveforms, VM = 1.5V.
2.7V
2.7V
nLE
VM
VM
VM
VM
VM
VM
0V
tw(H)
th(H)
ts(L)
th(L)
2.7V
tPLH
VM
VM
ts(H)
0V
tPHL
nQx
nDx
VOH
nLE
VOL
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
VM
VM
0V
VM
SW00011
SW00013
Waveform 1. Propagation Delay, Latch Enable to Output,
and Latch Enable Pulse Width
Waveform 3. Data Setup and Hold Times
2.7V
nDx
VM
2.7V
VM
nOE
VM
VM
0V
tPLH
0V
tPHL
tPZH
tPHZ
VOH
nQx
VM
VOH
nQx
VM
VOL
VOH -0.3V
0V
SW00012
SW00014
Waveform 2. Propagation Delay for Data to Outputs
1999 Sep 23
VM
Waveform 4. 3-State Output Enable time to High Level
and Output Disable Time from High Level
7
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
74LVT162373
2.7V
nOE
VM
VM
0V
tPZL
tPLZ
3V
VM
nQx
VOL +0.3V
VOL
SW00015
Waveform 5. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORMS
6V
VCC
OPEN
VIN
VOUT
PULSE
GENERATOR
tW
90%
RL
GND
VM
NEGATIVE
PULSE
CL
10%
0V
RL
tTHL (tF)
tTLH (tR)
tTLH (tR)
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
SWITCH
tPHZ/tPZH
GND
tPLZ/tPZL
6V
tPLH/tPHL
open
VM
VM
10%
tW
0V
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
AMP (V)
90%
10%
SWITCH POSITION
TEST
AMP (V)
VM
10%
D.U.T.
RT
90%
74LVT16
Amplitude
Rep. Rate
tW
tR
2.7V
≤10MHz
500ns
≤2.5ns
tF
≤2.5ns
RT = Termination resistance should be equal to ZOUT of
pulse generators.
SW00003
1999 Sep 23
8
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
1999 Sep 23
9
74LVT162373
SOT370-1
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
1999 Sep 23
10
74LVT162373
SOT362-1
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
NOTES
1999 Sep 23
11
74LVT162373
Philips Semiconductors
Product specification
3.3 V LVT 16-bit transparent D-type latch
with 30 Ω termination resistors (3-State)
74LVT162373
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 09-99
Document order number:
1999 Sep 23
12
9397 750 06507
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湘ICP备2023018690号
