74ALVC373PW,112

74ALVC373 Octal D-type transparent latch; 3-state Rev. 3 — 30 April 2021 Product data sheet 1. General description The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8B (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC373D -40 °C to +85 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74ALVC373PW -40 °C to +85 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74ALVC373BQ -40 °C to +85 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT764-1 74ALVC373 Nexperia Octal D-type transparent latch; 3-state 4. Functional diagram 1 18 D7 Q7 19 17 D6 Q6 16 14 D5 Q5 15 13 D4 Q4 12 8 D3 Q3 9 7 D2 Q2 6 4 D1 Q1 5 3 D0 Q0 2 LE Fig. 1. 1 C1 3 OE 11 EN 11 4 5 7 6 8 9 13 12 14 15 17 16 18 19 mna881 mna880 Logic symbol Fig. 2. 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 Q3 9 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 LATCH 1 to 8 3-STATE OUTPUTS IEC logic symbol Q4 12 LE LE LE 11 LE D 1 OE Q Functional diagram D0 Fig. 4. D1 D Q D2 D LE LE Q D3 D LE LE mna189 LE mna882 Fig. 3. 2 1D Q D4 D LE LE Logic diagram (one latch) Q D5 D LE LE Q D6 D LE LE Q D7 D LE LE Q D LE LE Q LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna883 Fig. 5. Logic diagram 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 2 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state 5. Pinning information 5.1. Pinning OE 1 74ALVC373 Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 OE 1 20 VCC Q2 6 15 Q5 Q0 2 19 Q7 D0 3 18 D7 D2 7 14 D5 D1 4 17 D6 D3 8 Q1 5 16 Q6 Q3 9 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 GND(1) 13 D4 LE 11 GND 10 12 Q4 aaa-032651 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 11 LE aaa-032650 Fig. 6. 20 VCC 74ALVC373 terminal 1 index area Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20) Fig. 7. Pin configuration SOT764-1 (DHVQFN20) 5.2. Pin description Table 2. Pin description Symbol Pin Description D0, D1, D2, D3, D4, D5, D6, D7 3, 4, 7, 8, 13, 14, 17, 18 data input LE 11 latch enable input (active HIGH) OE 1 output enable input (active LOW) Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 2, 5, 6, 9, 12, 15, 16, 19 3-state latch output VCC 20 supply voltage GND 10 ground (0 V) 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 3 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state 6. Functional description Table 3. Functional table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = don’t care; Z = High-impedance OFF-state Operating modes Input Output Internal latch OE LE Dn Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L l L L L L h H H H X X X Z H L h H Z Latch register and disable outputs Qn 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +4.6 V -50 - [1] -0.5 +4.6 V - ±50 mA [1] -0.5 VCC + 0.5 V output 3-state -0.5 +4.6 V power-down mode; VCC = 0 V -0.5 +4.6 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage output HIGH or LOW state VI < 0 V IO output current ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] VO = 0 V to VCC mA Tamb = -40 °C to +85 °C The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 4 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Max Unit 1.65 3.6 V 0 3.6 V output HIGH or LOW state 0 VCC V output 3-state 0 3.6 V power-down mode; VCC = 0 V 0 3.6 V -40 +85 °C Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 3.6 V - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Conditions -40 °C to +85 °C VCC = 1.65 V to 1.95 V LOW-level output voltage Min Typ [1] Max 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC - 0.2 - - V IO = -6 mA; VCC = 1.65 V 1.25 1.51 - V IO = -12 mA; VCC = 2.3 V 1.8 2.10 - V IO = -18 mA; VCC = 2.3 V 1.7 2.01 - V IO = -12 mA; VCC = 2.7 V 2.2 2.53 - V IO = -18 mA; VCC = 3.0 V 2.4 2.76 - V IO = -24 mA; VCC = 3.0 V 2.2 2.68 - V 0.35 × VCC V VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 3.6 V VOL Unit VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 V IO = 6 mA; VCC = 1.65 V - 0.11 0.3 V IO = 12 mA; VCC = 2.3 V - 0.17 0.4 V IO = 18 mA; VCC = 2.3 V - 0.25 0.6 V IO = 12 mA; VCC = 2.7 V - 0.16 0.4 V IO = 18 mA; VCC = 3.0 V - 0.23 0.4 V IO = 24 mA; VCC = 3.0 V - 0.30 0.55 V II input leakage current VCC = 3.6 V; VI = 3.6 V or GND - ±0.1 ±5 μA IOZ OFF-state output current VI = VIH or VIL; VCC = 1.65 V to 3.6 V; VO = 3.6 V or GND; - ±0.1 ±10 μA IOFF power-off leakage supply VCC = 0 V; VI or VO = 0 V to 3.6 V - ±0.1 ±10 μA 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 5 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state Symbol Parameter Conditions -40 °C to +85 °C Unit Min Typ [1] Max ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 10 μA ΔICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 750 μA CI input capacitance - 3.5 - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 12. Symbol Parameter tpd propagation delay Conditions -40 °C to +85 °C Unit Min Typ [1] Max VCC = 1.65 V to 1.95 V 1.0 2.5 5.4 ns VCC = 2.3 V to 2.7 V 1.0 2.0 3.5 ns VCC = 2.7 V 1.0 2.3 3.6 ns VCC = 3.0 V to 3.6 V 1.0 2.2 3.3 ns VCC = 1.65 V to 1.95 V 1.0 2.8 6.0 ns VCC = 2.3 V to 2.7 V 1.0 2.1 3.8 ns VCC = 2.7 V 1.0 2.4 3.7 ns VCC = 3.0 V to 3.6 V 1.0 2.3 3.3 ns VCC = 1.65 V to 1.95 V 1.5 3.0 6.4 ns VCC = 2.3 V to 2.7 V 1.0 2.4 4.5 ns VCC = 2.7 V 1.5 3.0 4.6 ns VCC = 3.0 V to 3.6 V 1.0 2.3 4.0 ns VCC = 1.65 V to 1.95 V 1.5 3.4 7.0 ns VCC = 2.3 V to 2.7 V 1.0 2.2 4.4 ns VCC = 2.7 V 1.5 2.8 4.4 ns VCC = 3.0 V to 3.6 V 1.0 2.7 4.4 ns VCC = 1.65 V to 1.95 V 3.8 1.0 - ns VCC = 2.3 V to 2.7 V 3.3 0.8 - ns VCC = 2.7 V 3.3 2.0 - ns VCC = 3.0 V to 3.6 V 3.3 2.2 - ns VCC = 1.65 V to 1.95 V 0.8 0.1 - ns VCC = 2.3 V to 2.7 V 0.8 0.1 - ns VCC = 2.7 V 0.8 0.1 - ns VCC = 3.0 V to 3.6 V 0.8 0.1 - ns Dn to Qn; see Fig. 8 [2] LE to Qn; see Fig. 9 ten tdis tW tsu enable time disable time pulse width set-up time 74ALVC373 Product data sheet OE to Qn; see Fig. 10 OE to Qn; see Fig. 10 [2] [2] LE pulse width HIGH; see Fig. 9 Dn to LE; see Fig. 11 All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 6 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state Symbol Parameter th [3] -40 °C to +85 °C Unit Min Typ [1] Max VCC = 1.65 V to 1.95 V 0.8 -0.1 - ns VCC = 2.3 V to 2.7 V 0.8 -0.2 - ns VCC = 2.7 V 0.8 -0.3 - ns VCC = 3.0 V to 3.6 V 0.7 -0.1 - ns outputs HIGH or LOW state - 35 - pF outputs 3-state - 14 - pF Dn to LE; see Fig. 11 hold time CPD [1] [2] Conditions power dissipation capacitance per latch; VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 °C tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching 2 Σ(CL × VCC × fo) = sum of the outputs 10.1. Waveforms and test circuit VI VM Dn input GND tPHL tPLH VOH VM Qn output VOL mna884 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig. 8. Input Dn to output Qn propagation delay times VI LE input VM VM VM GND tW t PHL t PLH VOH Qn output VM VM VOL mgu773 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig. 9. Latch enable (LE) pulse width and latch enable input to output (Qn) propagation delays 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 7 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state VI OE input VM GND t PLZ Qn output LOW-to-OFF OFF-to-LOW t PZL VCC VM VX VOL t PHZ Qn output HIGH-to-OFF OFF-to-HIGH t PZH VOH VY VM GND outputs enabled outputs enabled outputs disabled mna395 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig. 10. Enable and disable times VI VM Dn input GND t su th t su th VI VM LE input GND mgu774 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig. 11. The data set-up and hold times for Dn input to LE input Table 8. Measurement points Supply voltage VCC VM Output Vx Vy 1.65 V to 1.95 V 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 8 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 12. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VI Load VEXT tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 9 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 10 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 13. Package outline SOT163-1 (SO20) 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 10 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 14. Package outline SOT360-1 (TSSOP20) 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 11 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm B D SOT764-1 A A A1 E c detail X terminal 1 index area terminal 1 index area e1 C e b 2 9 v w C A B C y1 C y L 1 10 Eh e 20 11 19 12 X Dh 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit mm A(1) A1 b max 1.00 0.05 0.30 nom 0.90 0.02 0.25 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 L v 0.2 4.6 4.5 4.4 3.15 3.00 2.85 2.6 2.5 2.4 1.15 1.00 0.85 0.5 3.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT764-1 --- MO-241 --- sot764-1_po European projection Issue date 03-01-27 14-12-12 Fig. 15. Package outline SOT764-1 (DHVQFN20) 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 12 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC373 v.3 20210430 Product data sheet - Modifications: • • • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 updated. Section 2: Reference to JESD36 removed. Section 7: Derating values for Ptot total power dissipation removed (errata). Fig. 9 and Fig. 11 corrected. Package outline drawing SOT764-1 (DHVQFN20) updated. 74ALVC373 v.2 20071018 Modifications: • • • • • 74ALVC373 v.1 74ALVC373 Product data sheet 74ALVC373 v.2 Product data sheet - 74ALVC373 v.1 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN20 package added. Section 7: derating values added for DHVQFN20 package. Section 11: outline drawing added for DHVQFN20 package. 20020226 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 - © Nexperia B.V. 2021. All rights reserved 13 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state 14. Legal information injury, death or severe property or environmental damage. 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 14 / 15 74ALVC373 Nexperia Octal D-type transparent latch; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 7 11. Package outline........................................................ 10 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 April 2021 74ALVC373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 15 / 15