PDI1284P11DGG,512

PDI1284P11 3.3 V parallel interface transceiver/buffer Rev. 4 — 6 July 2021 Product data sheet 1. General description The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19 signal lines defined by the IEEE 1284 interface specification for Byte, Nibble, EPP, and ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to interface 3.3 V or 5.0 V devices. The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR. The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs, depending on the state of the high drive enable pin HD. The A-bus has only totem pole style outputs. All inputs are TTL compatible with at least 400 mV of input hysteresis at VCC = 3.3 V. 2. Features and benefits • • • • • • • • • • • • • • Asynchronous operation 8-bit transceivers Six additional buffer/driver lines peripheral to cable Five additional control lines from cable 5 V tolerant ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Latch-up current protection exceeds 500 mA per JEDEC Std 19 Input hysteresis Low-noise operation IEEE 1284 compliant level 1 and 2 Overvoltage protection on B/Y side for off-state A side 3-state option B side active or resistive pull-up option Cable side supply voltage for 5 V or 3 V operation 3. Ordering information Table 1. Ordering information Type number Package PDI1284P11DGG Temperature range Name Description Version 0 °C to 70 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 4. Functional diagram HD HD DIR CNTL OEA HD A9 Y9 HD A10 Y10 HD A11 Y11 HD A12 Y12 HD A13 Y13 HD A1 B1 CNTL HD A2 B2 CNTL HD A3 B3 CNTL HD A4 B4 CNTL HD A5 B5 CNTL HD A6 B6 CNTL HD A7 B7 CNTL HD A8 B8 CNTL PLHI HD PLHO A14 C14 A15 C15 A16 C16 A17 C17 HLHO HLHI 001aai290 Fig. 1. Logic symbol PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 2 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 5. Pinning information 5.1. Pinning HD 1 48 DIR A9 2 47 Y9 A10 3 46 Y10 A11 4 45 Y11 A12 5 44 Y12 A13 6 43 Y13 VCC 7 42 VCC(B) A1 8 41 B1 A2 9 40 B2 GND 10 39 GND A3 11 38 B3 A4 12 37 B4 PDI1284P11 A5 13 36 B5 A6 14 35 B6 GND 15 34 OEA A7 16 33 B7 A8 17 32 B8 VCC 18 31 VCC(B) PLHI 19 30 PLHO A14 20 29 C14 A15 21 28 C15 A16 22 27 C16 A17 23 26 C17 HLHO 24 25 HLHI 001aai291 Fig. 2. Pin configuration SOT362-1 (TSSOP48) 5.2. Pin description Table 2. Pin description Symbol Pin Description HD 1 high drive enable/disable input A1, A2, A3, A4, A5, A6, A7, A8 8, 9, 11, 12, 13, 14, 16, 17 data input/output B1, B2, B3, B4, B5, B6, B7, B8 41, 40, 38, 37, 36, 35, 33, 32 IEEE 1284 standard output/input [1] A9, A10, A11, A12, A13 2, 3, 4, 5, 6 data input Y9, Y10, Y11, Y12, Y13 47, 46, 45, 44, 43 IEEE 1284 standard output [1] C14, C15, C16, C17 29, 28, 27, 26 control input (cable) [1] A14, A15, A16, A17 20, 21, 22, 23 control output (peripheral) VCC 7, 18 supply voltage GND 10, 15, 39 ground (0 V) PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 3 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer Symbol Pin Description PLHI 19 peripheral logic high input (peripheral) HLHO 24 host logic high output (cable) HLHI 25 host logic high input (cable) PLHO 30 peripheral logic high output (cable) VCC(B) 31, 42 supply voltage B (cable side 3 V/5 V) OEA 34 A side output enable input (active LOW) DIR 48 direction selection input [1] Pin with pull-up resistor to load cable. 6. Functional description Table 3. Function table [1] DIR OEA HD Input Output Output type X X X C14 to C17 A14 to A17 TP X X X HLHI HLHO TP X X L A9 to A13 Y9 to Y13 RP X X H A9 to A13 Y9 to Y13 TP X X L PLHI PLHO OC X X H PLHI PLHO TP H X L A1 to A8 B1 to B8 RP H X H A1 to A8 B1 to B8 TP L L X B1 to B8 A1 to A8 TP L H X - A1 to A8 Z [2] L H X B1 to B8 - RP [2] [1] [2] An = side driving internal IC; Bn = side driving external cable (bidirectional); Cn = side receiving control signals from external cable; H = HIGH voltage level; L = LOW voltage level; OC = Open Collector; X = don’t care (control signals in); Yn = side driving external cable (unidirectional); Z = high impedance (high-Z) or 3-state; TP = totem pole output; RP = resistive pull-up: 1.4 kΩ (nominal) on B/Y/C cable side and VCC. However, while a B/Y side output is LOW as driven by a LOW signal on the A side, that particular B/Y side resistor is switched off to stop current drain from VCC through it. When DIR = L and OEA = H, the output signal is isolated from the input signal. Signals B1 to B8 maintain a resistive pull-up of 1.4 kΩ on the input for this mode. PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 4 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage pins VCC -0.5 +4.6 V VCC(B) supply voltage B pins VCC(B); cable side 3 V/5 V -0.5 +6.5 V IIK input clamping current VI < 0 V - ±20 mA IOK output clamping current VO < 0 V - ±50 mA VI input voltage [1] -0.5 +5.5 V VO output voltage [1] -0.5 +5.5 V -0.5 VCC + 0.5 V B/Y side A side Vtrt transient voltage -2 +7 V ICC supply current - 200 mA IGND ground current -200 - mA IO output current - ±50 mA Tstg storage temperature -60 +150 °C Ptot total power dissipation - 500 mW [1] [2] B/Y side; 40 ns transient [2] output HIGH or LOW Tamb = 0 °C to +70 °C The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Vtrt guarantees only that the PDI1284P11 will not be damaged by reflections in application so long as the voltage levels remain in the specified range. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage pins VCC 3.0 3.6 V VCC(B) supply voltage B pins VCC(B); cable side 3 V/5 V 3.0 5.5 V VIH HIGH-level input voltage 2.0 - V VIL LOW-level input voltage VO output voltage - 0.8 V -0.5 +5.5 V pins An 0 VCC V pins Bn, Yn IOH HIGH-level output current pins Bn, Yn - -14 mA IOL LOW-level output current pins Bn, Yn - 14 mA Tamb ambient temperature free-air 0 70 °C PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 5 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 9. Static characteristics Table 6. Static characteristics Tamb = 0 °C to 70 °C; ground = 0 V; unless specified otherwise. Symbol Parameter Conditions VIL LOW-level input voltage HIGH-level input voltage VIH VH hysteresis voltage Min Typ Max Unit An, Bn, Cn and PLHI inputs; VCC = 3.0 V to 3.6 V - - 0.8 V HLHI input; VCC = 3.0 V - - 1.55 V An, Bn, PLHI inputs; VCC = 3.0 V to 3.6 V 2.0 - - V Cn inputs; VCC = 3.0 V to 3.6 V 2.3 - - V HLHI input; VCC = 3.6 V 2.6 - - V An, Bn inputs; VCC = 3.3 V; VIL = 0.8 V; VIH = 2.0 V [1] 0.4 0.47 - V Cn inputs; VCC = 3.3 V [1] 0.8 0.47 - V - - 0.2 V - - 0.4 V pins Bn, Yn; IOL = 14 mA; VCC = 3.0 V - - 0.77 V pin PLHO; IOL = 500 μA; VCC = 3.0 V - - 0.8 V 2.8 - - V pins An, HLHO; IOH = -4 mA; VCC = 3.0 V 2.4 - - V pins Bn, Yn; IOH = -14 mA; VCC = 3.0 V 2.23 - - V pin PLHO; IOH = 500 μA; VCC = 3.15 V 3.1 - - V - 5 - μA - 0.1 100 μA pin DIR = 3.6 V; VCC(B) = 3.6 V - 10 15 mA pin DIR = 3.6 V; VCC(B) = 5.5 V - 16 20 mA pin DIR = 0 V; VCC(B) = 3.6 V; pins Bn = 0 V - 30 40 mA pin DIR = 0 V; VCC(B) = 5.5 V; pins Bn = 0 V - 47 60 mA VCC(B) = 0 V - - ±100 μA VCC(B) = 4.5 V - - ±100 μA [3] - - ±1 μA [3] - - ±20 μA [1] 35 45 55 Ω 1.4 1.65 kΩ LOW-level output pins An, HLHO; IOL = 50 μA; VCC = 3.0 V voltage pins An, HLHO; IOL = 4 mA; VCC = 3.0 V VOL VOH ICC HIGH-level output voltage supply current pins An, HLHO; IOH = -500 μA; VCC = 3.0 V VI = 0 V or VCC; IO = 0 A [1] pins VCC and VCC(B); VCC = 3.6 V; VCC(B) = 3.6 V to 5.5 V; VI = 0 V or VCC; pins Bn = VCC(B); pins Cn = VCC(B) or floating pins VCC(B); VCC = 3.6 V; VI = 0 V or VCC; pins Cn = 0 V IOFF power-off leakage current pins Bn, Cn, Yn; VO = 5.5 V; VCC = 0 V II input leakage current IOZ OFF-state output 3-state; VO = VCC or 0 V current Ro output resistance VCC = 3.3 V; see Fig. 9 RPU pull-up resistance B/Y side; VCC = 3.3 V; output in high-Z with resistive pull-up VI = 0 V to VCC VO = 1.65 V ± 0.1 V; B/Y side [1] [2] [3] [2] [1] 1.15 Typical values at Tamb = 25 °C. Includes extra ICC(B) current from pull-up resistors, i.e. ICC(B) = (total number of LOW inputs on B and C sides) × (VCC(B) / RPU). The pull-up resistor on the B side outputs makes it impossible to test IOZ on the B side. This applies to the input current on the C side inputs as well. PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 6 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 10. Dynamic characteristics Table 7. Dynamic characteristics VCC = 3.0 V to 3.6 V; ground = 0 V; CL = 50 pF; RL = 500 Ω; Tamb = 0 °C to 70 °C; unless specified otherwise. Symbol Parameter Conditions Min Typ [1] Max tPLH LOW to HIGH propagation delay tPHL tpd Unit An to Bn or Yn; see Fig. 3 and Fig. 8 0 12.5 20 ns HIGH to LOW propagation delay An to Bn or Yn; see Fig. 3 and Fig. 8 0 13.9 23 ns propagation delay see Fig. 4 and Fig. 8 Bn to An 0 - 12 ns Cn to An - - 15 ns PLHI to PLHO - - 20 ns HLHI to HLHO - - 15 ns 0.05 0.2 0.4 V/ns [2] SR slew rate Bn/Yn; RL = 62 Ω; see Fig. 5 and Fig. 8 tdis disable time HD to Yn or Bn; see Fig. 6 and Fig. 8 [3] - - 20 ns HD to PLHO; see Fig. 6 and Fig. 7 [3] - - 20 ns RL = 250 Ω; see Fig. 6 and Fig. 7 [3] DIR to Bn; TP load on B/Y side - - 50 ns DIR to An - - 15 ns OEA to An - - 6 ns ten enable time ΔtPD [1] [2] [3] [4] propagation delay difference HD to Yn or Bn; see Fig. 6 and Fig. 7 [4] - - 20 ns HD to PLHO; see Fig. 6 and Fig. 7 [4] - - 20 ns RL = 250 Ω; see Fig. 6 and Fig. 7 [4] DIR to Bn; TP load on B/Y side - - 30 ns DIR to An - - 50 ns OEA to An - - 12 ns - - 10 ns tPZH - tPHZ; HD to output Value at Tamb = 25 °C and VCC = 3.3 V. tpd is the same as tPLH and tPHL. tdis is the same as tPHZ and tPLZ. ten is the same as tPZH and tPZL. 10.1. Waveforms and test circuit 2.4 V input 1.4 V 1.4 V 0.4 V tPLH tPHL VO output 1.4 V VO - 1.4 V 001aai293 Fig. 3. Input An to output Bn or Yn propagation delays PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 7 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer VI input VM GND tPHL tPLH VOH output VM VOL 001aai292 VM = 1.5 V. VCC never goes below 3.0 V. VOL and VOH are the typical voltage output levels that occur with the output load. Fig. 4. Input Bn, Cn to output An propagation delays 2.4 V input 0.4 V output 2.4 V 0.9 V 1.9 V 0.4 V t1 t2 t1 t2 001aai295 Measurement data is given in Table 8. SR is measured for both a LOW-to-HIGH and a HIGH-to-LOW transition. Fig. 5. Slew rate on B/Y side Table 8. Slew rate measurements tr tf tW RL 3 ns 62 Ω 3 ns PDI1284P11 Product data sheet 150 ns < tW < 10 μs VO transition (see Fig. 8) Rising Falling from VO = 0.4 V to VO = 0.9 V from VO = 2.4 V to VO = 1.9 V All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 8 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer DIR to A VM DIR to B VM VI HD to B VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPHZ output HIGH-to-OFF OFF-to-HIGH tPZH VOH VY VM GND outputs enabled outputs enabled outputs disabled 001aai294 Test circuit is shown in Fig. 7. Measurement points are given in Table 9. VOL and VOH are the typical voltage output levels that occur with the output load. Fig. 6. Enable and disable times VEXT VCC G VI RL VO DUT RT CL RL mna616 Test conditions are given in Table 9. Fig. 7. Test circuit for measuring enable and disable times Table 9. Test data for test circuit measuring enable disable times Bn to An Parameter VCC Input Output VEXT VI VM VM VX VY tPZH, tPHZ tPZL, tPLZ DIR to Bn, An; OEA to An < 2.7 V VCC 1.5 V 1.5 V VOL ± 0.3 V VOH - 0.3 V GND 2VCC 2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL ± 0.3 V VOH - 0.3 V GND 2VCC HD to Yn or Bn; HD to PHLO < 2.7 V VCC 1.5 V 1.5 V - VOH - 0.3 V open - 2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V - VOH - 0.3 V open - PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 9 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer VI negative pulse tW 90 % 90 % VM 10 % 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VCC 90 % VM G VM 10 % VI DUT 10 % tW CL VO VEXT GND RT RL 001aai296 001aai298 a. Input pulse definition b. Test circuit CL = load capacitance includes jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance of the pulse generator. Test conditions for propagation delays are given in Table 10, test conditions for slew rate are given in Table 8 Fig. 8. Test circuit for An, Bn and Yn outputs; slew rate B/Y side Table 10. Test conditions for An, Bn and Yn outputs Output VI VM Repetition tW rate tr An 3.0 V 1.5 V 1 MHz 500 ns 3 ns Bn, Yn 3.0 V 1.5 V 1 MHz 500 ns 3 ns tf Switch position tPLH, tPZH tPHL, tPHZ 3 ns GND GND 3 ns GND VEXT = 2.8 V VCC DUT IO VCC / 2 001aai299 IO is measured by forcing 0.5VCC on the output. The output impedance can then be calculated as Ro = 0.5VCC / |IO|. Fig. 9. Output impedance PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 10 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 11. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Fig. 10. Package outline SOT362-1 (TSSOP48) PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 11 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 12. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ECP Extended Capability Port EPP Enhanced Parallel Port ESD ElectroStatic Discharge HBM Human Body Model IEEE Institute of Electrical and Electronics Engineers LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes PDI1284P11 v.4 20210706 Product data sheet - Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number PDI1284P11DL (SOT370-1 / SSOP48) removed. Section 7: Derating values for Ptot total power dissipation removed. Fig. 10: Package outline drawing SOT362-1 (TSSOP48) updated. PDI1284P11_3 20080825 Modifications: • • • • • PDI1284P11_3 Product data sheet - PDI1284P11_2 The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Quick reference table removed. Table 7, tPHL: Maximum value of 20 ns replaced by 23 ns. Table 11: Abbreviations list added. PDI1284P11_2 19990917 Product specification - PDI1284P11_1 PDI1284P11_1 19970915 Product specification - - PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 12 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 13 / 14 PDI1284P11 Nexperia 3.3 V parallel interface transceiver/buffer Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................5 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 7 11. Package outline........................................................ 11 12. Abbreviations............................................................ 12 13. Revision history........................................................12 14. Legal information......................................................13 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 6 July 2021 PDI1284P11 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 6 July 2021 © Nexperia B.V. 2021. All rights reserved 14 / 14