NUC123LD4AN0

NUC123 ARM® Cortex® -M0 32-bit Microcontroller NuMicro® Family NUC123 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com May 8, 2020 Page 1 of 100 Rev.2.05 NUC123 SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. NUC123 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ....................................................................... 8 2 FEATURES ......................................................................................... 9 NuMicro® NUC123 Series Features ................................................................ 9 2.1 3 Abbreviations ..................................................................................... 12 4 PARTS INFORMATION LIST AND PIN CONFIGURATION .............................. 14 4.1 NuMicro® NUC123 Series Naming Rule ..........................................................14 4.2 NuMicro® NUC123 Series Selection Guide .......................................................15 4.2.1 NuMicro NUC123xxxANx Selection Guide .............................................................. 15 4.2.2 NuMicro NUC123xxxAEx Selection Guide .............................................................. 15 ® ® NuMicro® NUC123 Series Pin Configuration .....................................................16 4.3 4.3.1 NuMicro NUC123xxxANx Pin Diagram .................................................................. 16 4.3.2 NuMicro NUC123xxxAEx Pin Diagram .................................................................. 19 ® ® Pin Description ........................................................................................22 4.4 4.4.1 NuMicro NUC123 Pin Description ........................................................................ 22 ® BLOCK DIAGRAM ............................................................................... 27 5 NuMicro® NUC123 Block Diagram .................................................................27 5.1 FUNCTIONAL DESCRIPTION ................................................................. 28 6 NUC123 SERIES DATASHEET 6.1 ARM® Cortex® -M0 Core..............................................................................28 6.2 System Manager ......................................................................................30 6.2.1 Overview ....................................................................................................... 30 6.2.2 System Reset ................................................................................................. 30 6.2.3 Power modes and Wake-up sources ...................................................................... 36 6.2.4 System Power Distribution .................................................................................. 38 6.2.5 System Memory Map......................................................................................... 40 6.2.6 System Timer (SysTick) ..................................................................................... 42 6.2.7 Nested Vectored Interrupt Controller (NVIC) ............................................................. 43 6.3 Clock Controller .......................................................................................47 6.3.1 Overview ....................................................................................................... 47 6.3.2 System Clock and SysTick Clock .......................................................................... 50 6.3.3 Peripherals Clock ............................................................................................. 50 6.3.4 Power-down Mode Clock .................................................................................... 50 6.3.5 Frequency Divider Output ................................................................................... 51 6.4 Flash Memory Controller (FMC) ....................................................................52 May 8, 2020 Page 2 of 100 Rev.2.05 NUC123 6.4.1 Overview ....................................................................................................... 52 6.4.2 Features ........................................................................................................ 52 6.5 General Purpose I/O (GPIO) ........................................................................53 6.5.1 Overview ....................................................................................................... 53 6.5.2 Features ........................................................................................................ 53 6.6 PDMA Controller (PDMA) ...........................................................................54 6.6.1 Overview ....................................................................................................... 54 6.6.2 Features ........................................................................................................ 54 6.7 Timer Controller (TMR) ..............................................................................56 6.7.1 Overview ....................................................................................................... 56 6.7.2 Features ........................................................................................................ 56 6.8 PWM Generator and Capture Timer (PWM) .....................................................57 6.8.1 Overview ....................................................................................................... 57 6.8.2 Features ........................................................................................................ 57 6.9 Watchdog Timer (WDT) .............................................................................58 6.9.1 Overview ....................................................................................................... 58 6.9.2 Features ........................................................................................................ 58 6.10 Window Watchdog Timer (WWDT) ................................................................ 59 6.10.1 Overview ....................................................................................................... 59 6.10.2 Features ........................................................................................................ 59 UART Interface Controller (UART) .................................................................60 6.11.1 Overview ....................................................................................................... 60 6.11.2 Features ........................................................................................................ 60 6.12 PS/2 Device Controller (PS2D) .....................................................................61 Overview ....................................................................................................... 61 6.12.1 Features ........................................................................................................ 61 6.12.2 6.13 I C Serial Interface Controller (Master/Slave) (I2C)..............................................62 2 6.13.1 Overview ....................................................................................................... 62 6.13.2 Features ........................................................................................................ 62 6.14 Serial Peripheral Interface (SPI) ....................................................................63 Overview ....................................................................................................... 63 6.14.1 Features ........................................................................................................ 63 6.14.2 6.15 I S Controller (I2S) ....................................................................................64 2 6.15.1 Overview ....................................................................................................... 64 6.15.2 Features ........................................................................................................ 64 May 8, 2020 Page 3 of 100 Rev.2.05 NUC123 SERIES DATASHEET 6.11 NUC123 6.16 USB Device Controller (USB) .......................................................................65 6.16.1 Overview ....................................................................................................... 65 6.16.2 Features ........................................................................................................ 65 6.17 Analog-to-Digital Converter (ADC) .................................................................66 6.17.1 Overview ....................................................................................................... 66 6.17.2 Features ........................................................................................................ 66 7 PERIPHERAL APPLICATION SCHEME ..................................................... 67 8 ELECTRICAL CHARACTERISTICS (NUC123xxxANx) ................................... 68 8.1 Absolute Maximum Ratings .........................................................................68 8.2 DC Electrical Characteristics ........................................................................69 8.3 AC Electrical Characteristics ........................................................................73 8.3.1 External 4~24 MHz High Speed Oscillator ............................................................... 73 8.3.2 External 4~24 MHz High Speed Crystal .................................................................. 73 8.3.3 Internal 22.1184 MHz High Speed Oscillator ............................................................. 74 8.3.4 Internal 10 kHz Low Speed Oscillator ..................................................................... 74 Analog Characteristics ...............................................................................75 8.4 NUC123 SERIES DATASHEET 8.4.1 10-bit SARADC Specifications .............................................................................. 75 8.4.2 LDO and Power Management Specifications ............................................................ 75 8.4.3 Low Voltage Reset Specifications .......................................................................... 76 8.4.4 Brown-out Detector Specifications ......................................................................... 76 8.4.5 Power-On Reset (5V) Specifications ...................................................................... 76 8.4.6 USB PHY Specifications ..................................................................................... 77 8.5 Flash DC Electrical Characteristics ................................................................ 79 8.6 SPI Dynamic Characteristics ........................................................................80 ELECTRICAL CHARACTERISTICS (NUC123xxxAEx) ................................... 82 9 9.1 Absolute Maximum Ratings .........................................................................82 9.2 DC Electrical Characteristics ........................................................................83 9.3 AC Electrical Characteristics ........................................................................87 9.3.1 External 4~24 MHz High Speed Oscillator ............................................................... 87 9.3.2 External 4~24 MHz High Speed Crystal .................................................................. 87 9.3.3 Internal 22.1184 MHz High Speed Oscillator ............................................................. 88 9.3.4 Internal 10 kHz Low Speed Oscillator ..................................................................... 88 9.4 Analog Characteristics ...............................................................................89 9.4.1 10-bit SARADC Specifications .............................................................................. 89 9.4.2 LDO and Power Management Specifications ............................................................ 89 May 8, 2020 Page 4 of 100 Rev.2.05 NUC123 9.4.3 Low Voltage Reset Specifications .......................................................................... 90 9.4.4 Brown-out Detector Specifications ......................................................................... 90 9.4.5 Power-On Reset (5V) Specifications ...................................................................... 90 9.4.6 USB PHY Specifications ..................................................................................... 91 9.5 Flash DC Electrical Characteristics ................................................................ 93 9.6 SPI Dynamic Characteristics ........................................................................94 10 PACKAGE DIMENSIONS ...................................................................... 96 10.1 64L LQFP (7x7x1.4 mm footprint 2.0 mm)........................................................96 10.2 48L LQFP (7x7x1.4 mm footprint 2.0 mm)........................................................97 10.3 33L QFN (5x5x0.8 mm) ..............................................................................98 11 REVISION HISTORY ............................................................................ 99 NUC123 SERIES DATASHEET May 8, 2020 Page 5 of 100 Rev.2.05 NUC123 List of Figures ® Figure 4-1 NuMicro NUC123 Series Selection Code ................................................................... 14 ® Figure 4-2 NuMicro NUC123SxxANx LQFP 64-pin Diagram ....................................................... 16 ® Figure 4-3 NuMicro NUC123LxxANx LQFP 48-pin Diagram ....................................................... 17 ® Figure 4-4 NuMicro NUC123ZxxANx QFN 33-pin Diagram ......................................................... 18 ® Figure 4-5 NuMicro NUC123SxxAEx LQFP 64-pin Diagram ....................................................... 19 ® Figure 4-6 NuMicro NUC123LxxAEx LQFP 48-pin Diagram ....................................................... 20 ® Figure 4-7 NuMicro NUC123ZxxAEx QFN 33-pin Diagram ......................................................... 21 ® Figure 5-1 NuMicro NUC123 Block Diagram ............................................................................... 27 Figure 6-1 Functional Controller Diagram ...................................................................................... 28 Figure 6-2 System Reset Resources ............................................................................................. 31 Figure 6-3 nRESET Reset Waveform ............................................................................................ 33 Figure 6-4 Power-on Reset (POR) Waveform ............................................................................... 34 Figure 6-5 Low Voltage Reset Waveform ...................................................................................... 34 Figure 6-6 Brown-Out Detector Waveform .................................................................................... 35 Figure 6-7 Power Mode State Machine ......................................................................................... 36 ® Figure 6-8 NuMicro NUC123 Power Distribution Diagram ........................................................... 39 Figure 6-9 Clock Generator Global View Diagram......................................................................... 48 Figure 6-10 Clock Generator Global View Diagram....................................................................... 49 Figure 6-11 System Clock Block Diagram ..................................................................................... 50 NUC123 SERIES DATASHEET Figure 6-12 SysTick Clock Control Block Diagram ........................................................................ 50 Figure 6-13 Clock Source of Frequency Divider ............................................................................ 51 Figure 6-14 Block Diagram of Frequency Divider .......................................................................... 51 Figure 8-1 Typical Crystal Application Circuit ................................................................................ 73 Figure 8-2 SPI Master Dynamic Characteristics Timing ................................................................ 80 Figure 8-3 SPI Slave Dynamic Characteristics Timing .................................................................. 81 Figure 9-1 Typical Crystal Application Circuit ................................................................................ 87 Figure 9-2 SPI Master Dynamic Characteristics timing ................................................................. 94 Figure 9-3 SPI Slave Dynamic Characteristics Timing .................................................................. 95 May 8, 2020 Page 6 of 100 Rev.2.05 NUC123 List of Tables Table 1-1 Key Features Support Table ............................................................................................ 8 Table 3-1 List of Abbreviations ....................................................................................................... 13 Table 6-1 Reset Value of Registers ............................................................................................... 32 Table 6-2 Power Mode Difference Table ....................................................................................... 36 Table 6-3 Clocks in Power Modes ................................................................................................. 37 Table 6-4 Condition of Entering Power-down Mode Again ............................................................ 38 Table 6-5 Address Space Assignments for On-Chip Controllers ................................................... 41 Table 6-6 Exception Model ............................................................................................................ 44 Table 6-7 System Interrupt Map..................................................................................................... 45 Table 6-8 Vector Table Format ...................................................................................................... 46 Table 6-9 Clock Stable Count Value Table .................................................................................... 47 NUC123 SERIES DATASHEET May 8, 2020 Page 7 of 100 Rev.2.05 NUC123 1 GENERAL DESCRIPTION ® ® The NuMicro NUC123 series is a new 32-bit Cortex -M0 microcontroller with USB 2.0 Full-speed devices and a 10-bit ADC. The NUC123 series provides the high 72 MHz operating speed, large 20 Kbytes SRAM, 8 USB endpoints and three sets of SPI controllers, which make it powerful in USB communication and data processing. The NUC123 series is ideal for industrial control, consumer electronics, and communication system applications such as printers, touch panel, gaming keyboard, gaming joystick, USB audio, PC peripherals, and alarm systems. The NUC123 series runs up to 72 MHz and supports 32-bit multiplier, structure NVIC (Nested Vector Interrupt Control), dual-channel APB and PDMA (Peripheral Direct Memory Access) with CRC function. Besides, the NUC123 series is equipped with 36/68 Kbytes Flash memory, 12/20 Kbytes SRAM, and 4 Kbytes loader ROM for the ISP. It operates at a wide voltage range of 2.5V ~ 5.5V and temperature range of -40°C ~ +105°C and -40°C ~ +85°C. It is also equipped with plenty of peripheral 2 2 devices, such as 8-channel 10-bit ADC, UART, SPI, I C, I S, USB 2.0 FS devices, and offers lowvoltage reset and Brown-out detection, PWM (Pulse-width Modulation), capture and compare features, four sets of 32-bit timers, Watchdog Timer, and internal RC oscillator. All these peripherals have been incorporated into the NUC123 series to reduce component count, board space and system cost. Additionally, the NUC123 series is equipped with ISP (In-System Programming), IAP (In-ApplicationProgramming) and ICP (In-Circuit Programming) functions, which allows the user to update the program under software control through the on-chip connectivity interface, such as SWD, UART and USB. Product Line UART SPI I2C USB PS/2 I2S PWM ADC NUC123 2 3 2 1 1 1 4 8 Table 1-1 Key Features Support Table NUC123 SERIES DATASHEET May 8, 2020 Page 8 of 100 Rev.2.05 NUC123 2 2.1 FEATURES NuMicro® NUC123 Series Features  Core ® ® – ARM Cortex -M0 core runs up to 72 MHz – One 24-bit system timer – Supports low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 32 interrupt inputs, each with 4-levels of priority – Supports Serial Wire Debug with 2 watchpoints/4 breakpoints  Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V  Flash Memory – 36/68 KB Flash for program code – 4 KB flash for ISP loader – Supports In-System Program (ISP) application code update – 512 byte page erase for flash – Configurable Data Flash address and size for both 36KB and 68KB system – Supports 2-wire ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer  SRAM Memory – 12/20 KB embedded SRAM – Supports PDMA mode  PDMA (Peripheral DMA) – Supports 6 channels PDMA for automatic data transfer between SRAM and 2 peripherals such as SPI, UART, I S, USB 2.0 FS device, PWM and ADC – Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC16 and CRC-32  Clock Control Flexible selection for different applications Built-in 22.1184 MHz high speed oscillator (Trimmed to 1%) for system operation, and low power 10 kHz low speed oscillator for watchdog and wake-up operation – Supports one PLL, up to 144 MHz, for high performance system operation – External 4~24 MHz high speed crystal input for precise timing operation  GPIO – Four I/O modes:  Quasi bi-direction  Push-Pull output  Open-Drain output  Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level setting – Supports High Driver and High Sink I/O mode  Timer – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter – Independent clock source for each timer – Provides one-shot, periodic, toggle and continuous counting operation modes – Supports event counting function  Watchdog/Windowed-Watchdog Timer – May 8, 2020 Multiple clock sources Page 9 of 100 Rev.2.05 NUC123 SERIES DATASHEET – – NUC123 – 8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source) – Wake-up from Power-down or Idle mode – Interrupt or reset selectable on watchdog timer time-out – Interrupt on windowed-watchdog timer time-out – Reset on windowed-watchdog timer time-out or reload in an unexpected time window  PWM/Capture – Up to two built-in 16-bit PWM generators provided with four PWM outputs or two complementary paired PWM outputs – Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one Dead-zone generator for complementary paired PWM – Up to four 16-bit digital Capture timers (shared with PWM timers) provided with four rising/falling capture inputs – Supports Capture interrupt  UART NUC123 SERIES DATASHEET – – – – – – –  SPI Up to two UART controllers UART ports with flow control (TXD, RXD, CTS and RTS) UART0/1 with 16-byte FIFO for standard device Support IrDA (SIR) function Supports RS-485 9-bit mode and direction control. Programmable baud-rate generator up to 1/16 system clock Supports PDMA mode – – – – – – – – 2  IC Up to three sets of SPI controllers Supports SPI master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 8 to 32 bits MSB or LSB first data transfer Up to two slave/device select lines in Master mode Supports Byte Suspend mode in 16/24/32-bit transmission Supports PDMA transfer – – – – – – – – – – 2  IS – – – – – – May 8, 2020 2 Up to two sets of I C devices Master/Slave mode Bidirectional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Programmable clocks allowing versatile rate control Supports multiple address recognition (four slave address with mask option) Supports wake-up by address recognition (for 1st slave address only) Interface with external audio CODEC Operated as either master or Slave mode Capable of handling 8-, 16-, 24- and 32-bit word sizes Supports Mono and stereo audio data 2 Supports I S and MSB justified data format Two 8 word FIFO data buffers are provided, one for transmitting and the other for receiving Page 10 of 100 Rev.2.05 NUC123 – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving  PS/2 Device Controller – Host communication inhibit and request to send detection – Reception frame error detection – Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention – Double buffer for data reception – S/W override bus  USB 2.0 Full-Speed Device – One set of USB 2.0 FS Device 12 Mbps – On-chip USB transceiver – Provides 1 interrupt source with 4 interrupt events – Supports Control, Bulk In/Out, Interrupt and Isochronous transfers – Auto suspend function when no bus signaling for 3 ms – Provides 8 programmable endpoints – Includes 512 bytes internal SRAM as USB buffer – Provides remote wake-up capability  ADC – 10-bit SAR ADC with 150K SPS (for NUC123xxxANx) – 10-bit SAR ADC with 200K SPS (for NUC123xxxAEx) – Up to 8-ch single-end input – Single scan/single cycle scan/continuous scan – Each channel with individual result register – Scan on enabled channels – Threshold voltage detection – Conversion start by software programming or external input – Supports PDMA mode  Brown-out detector NUC123 SERIES DATASHEET – With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V – Supports Brown-out Interrupt and Reset option  Low Voltage Reset – Threshold voltage levels: 2.0 V  One built-in LDO  Operating Temperature: -40°C~85°C (for NUC123xxxANx)  Operating Temperature: -40°C~105°C (for NUC123xxxAEx)  Packages: – – – – May 8, 2020 All Green package (RoHS) LQFP 64-pin LQFP 48-pin QFN 33-pin Page 11 of 100 Rev.2.05 NUC123 3 ABBREVIATIONS NUC123 SERIES DATASHEET Acronym Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 22.1184 MHz Internal High Speed RC Oscillator HXT 4~20 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation QEI Quadrature Encoder Interface SD Secure Digital SPI Serial Peripheral Interface May 8, 2020 Page 12 of 100 Rev.2.05 NUC123 SPS Samples per Second TDES Triple Data Encryption Standard TK Touch Key TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer Table 3-1 List of Abbreviations NUC123 SERIES DATASHEET May 8, 2020 Page 13 of 100 Rev.2.05 NUC123 4 4.1 PARTS INFORMATION LIST AND PIN CONFIGURATION NuMicro® NUC123 Series Naming Rule ARM–Based 32-bit Microcontroller NUC 1 2 3 - X X X X X X CPU Core Option 1: Cortex® -M0 5/7: ARM7 9: ARM9 0: SRAM 20 KB 1: SRAM 12 KB Temperature N: -40oC ~ +85oC E: -40oC ~ +105oC Product Line Function 0: Advance Line 2: USB Line 3: Automotive Line 4: Connectivity Line 5: High Density Reserved SRAM Size Reserved 2: 12 KB 4: 20 KB 0~9: Sub Product Line NUC123 SERIES DATASHEET Package Type Flash ROM Z: QFN 33 5x5mm L: LQFP 48 7x7mm S: LQFP 64 7x7mm C: 36 KB D: 68 KB ® Figure 4-1 NuMicro NUC123 Series Selection Code May 8, 2020 Page 14 of 100 Rev.2.05 NUC123 NuMicro® NUC123 Series Selection Guide 4.2 NuMicro® NUC123xxxANx Selection Guide Flash (KB) SRAM (KB) ISP ROM (KB) I/O Timer UART SPI I2C USB LIN PS/2 I2S Comp. PWM ADC RTC EBI ISP\ICP\IAP 1.8V Power Pin Package Connectivity Part Number 4.2.1 NUC123ZD4AN0 68 20 4 Up to 20 4x32-bit 1 3 1 1 - - 1 - 2 3x10-bit - - v - QFN33 NUC123ZC2AN1 36 12 4 up to 20 4x32-bit 1 3 1 1 - - 1 - 2 3x10-bit - - v - QFN33 NUC123LD4AN0 68 20 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 NUC123LC2AN1 36 12 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 NUC123SD4AN0 68 20 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 NUC123SC2AN1 36 12 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 NuMicro® NUC123xxxAEx Selection Guide SPI IC USB LIN PS/2 I2S Comp. PWM ADC RTC EBI ISP\ICP\IAP 1.8V Power Pin Package 4 Up to 20 4x32-bit 1 3 1 1 - - 1 - 3 3x10-bit - - v - QFN33 NUC123ZC2AE1 36 12 4 up to 20 4x32-bit 1 3 1 1 - - 1 - 3 3x10-bit - - v - QFN33 NUC123LD4AE0 68 20 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 NUC123LC2AE1 36 12 4 up to 36 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP48 NUC123SD4AE0 68 20 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 NUC123SC2AE1 36 12 4 up to 47 4x32-bit 2 3 2 1 - 1 1 - 4 8x10-bit - - v - LQFP64 May 8, 2020 2 UART 20 Timer ISP ROM (KB) 68 I/O SRAM (KB) NUC123ZD4AE0 Page 15 of 100 Rev.2.05 NUC123 SERIES DATASHEET Flash (KB) Connectivity Part Number 4.2.2 NUC123 NuMicro® NUC123 Series Pin Configuration NuMicro® NUC123xxxANx Pin Diagram ® AVDD ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 VSS PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0 PC.9/SPI1_CLK VDD PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO VSS 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro NUC123SxxANx LQFP 64 pin 47 4.3.1.1 48 4.3.1 SPI2_SS0/ADC0/PD.0 49 32 PB.9/SPI1_SS1/TM1 SPI0_SS1/SPI2_CLK/ADC1/PD.1 50 31 PB.10/SPI0_SS1/TM2 SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 51 30 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 52 29 PC.1/SPI0_CLK/I2S_BCLK SPI2_MISO1/ADC4/PD.4 53 28 PC.2/SPI0_MISO0/I2S_DI SPI2_MOSI1/ADC5/PD.5 54 27 PC.3/SPI0_MOSI0/I2S_DO TM0_EXT/INT1/PB.15 55 26 PC.4/SPI0_MISO1/UART0_RXD XT1_OUT/PF.0 56 25 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 57 24 PB.3/UART0_nCTS/TM3_EXT nRESET 58 23 PB.2/UART0_nRTS/TM2_EXT VSS 59 22 PB.1/UART0_TXD VDD 60 21 PB.0/UART0_RXD PS2_DAT/I2C0_SDA/ADC6/PF.2 61 20 USB_D+ PS2_CLK/I2C0_SCL/ADC7/PF.3 62 19 USB_D- PVSS 63 18 USB_VDD33_CAP TM0/PB.8 64 17 USB_VBUS 12 13 14 15 16 SPI2_MOSI0/UART1_nRTS/PB.6 SPI2_MISO0/UART1_nCTS/PB.7 LDO_CAP VDD VSS 9 INT1/PD.11 11 8 CLKO/PD.10 SPI2_CLK/UART1_TXD/PB.5 7 PD.9 10 6 SPI1_MOSI0/PD.8 SPI1_SS1/SPI2_SS0/UART1_RXD/PB.4 5 I2C1_SDA/SPI2_MISO0/SPI1_MISO0/PA.10 3 CLKO/SPI1_SS0/PB.12 4 2 I2C1_SCL/SPI2_MOSI0/SPI1_CLK/PA.11 1 NUC123 SERIES DATASHEET PB.13 NUC123SxxANx LQFP 64-pin INT0/PB.14 4.3 ® Figure 4-2 NuMicro NUC123SxxANx LQFP 64-pin Diagram May 8, 2020 Page 16 of 100 Rev.2.05 NUC123 ® ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 35 34 33 32 31 30 29 28 27 26 25 NuMicro NUC123LxxANx LQFP 48 pin 36 4.3.1.2 AVDD 37 24 PB.9/SPI1_SS1/TM1 SPI2_SS0/ADC0/PD.0 38 23 PB.10/SPI0_SS1/TM2 SPI0_SS1/SPI2_CLK/ADC1/PD.1 39 22 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 40 21 PC.1/SPI0_CLK/I2S_BCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 41 20 PC.2/SPI0_MISO0/I2S_DI SPI2_MISO1/ADC4/PD.4 42 19 PC.3/SPI0_MOSI0/I2S_DO SPI2_MOSI1/ADC5/PD.5 43 18 PC.4/SPI0_MISO1/UART0_RXD XT1_OUT/PF.0 44 17 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 45 16 USB_D+ nRESET 46 15 USB_D- PS2_DAT/I2C0_SDA/ADC6/PF.2 47 14 USB_VDD33_CAP PS2_CLK/I2C0_SCL/ADC7/PF.3 48 13 USB_VBUS 7 8 9 SPI2_CLK/UART1_TXD/PB.5 SPI2_MOSI0/UART1_nRTS/PB.6 SPI2_MISO0/UART1_nCTS/PB.7 12 6 SPI1_SS1/SPI2_SS0/UART1_RXD/PB.4 VSS 5 I2C1_SDA/SPI2_MISO0/SPI1_MISO0/PA.10 11 4 I2C1_SCL/SPI2_MOSI0/SPI1_CLK/PA.11 VDD 3 INT0/PB.14 10 2 LDO_CAP 1 PVSS NUC123 SERIES DATASHEET TM0/PB.8 NUC123LxxANx LQFP 48-pin ® Figure 4-3 NuMicro NUC123LxxANx LQFP 48-pin Diagram May 8, 2020 Page 17 of 100 Rev.2.05 NUC123 ® ICE_CLK ICE_DAT PC.8/SPI1_SS0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 23 22 21 20 19 18 17 NuMicro NUC123ZxxANx QFN 33 pin 24 4.3.1.3 AVDD 25 16 PC.0/SPI0_SS0/I2S_LRCLK SPI0_SS1/SPI2_CLK/ADC1/PD.1 26 15 PC.1/SPI0_CLK/I2S_BCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 27 14 PC.2/SPI0_MISO0/I2S_DI SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 28 13 PC.3/SPI0_MOSI0/I2S_DO XT1_OUT/PF.0 29 12 USB_D+ XT1_IN/PF.1 30 11 USB_D- nRESET 31 10 USB_VDD33_CAP PVSS 32 9 USB_VBUS NUC123ZxxANx QFN 33-pin 2 3 4 5 6 7 8 I2C1_SCL/SPI2_MOSI0/SPI1_CLK/PA.11 SPI1_SS1/SPI2_SS0/UART1_RXD/PB.4 SPI2_CLK/UART1_TXD/PB.5 LDO_CAP VDD VSS NUC123 SERIES DATASHEET I2C1_SDA/SPI2_MISO0/SPI1_MISO0/PA.10 INT0/PB.14 1 33 VSS ® Figure 4-4 NuMicro NUC123ZxxANx QFN 33-pin Diagram May 8, 2020 Page 18 of 100 Rev.2.05 NUC123 NuMicro® NUC123xxxAEx Pin Diagram ® AVDD ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 VSS PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0/PWM0 PC.9/SPI1_CLK VDD PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO VSS 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NuMicro NUC123SxxAEx LQFP 64 pin 47 4.3.2.1 48 4.3.2 SPI2_SS0/ADC0/PD.0 49 32 PB.9/SPI1_SS1/TM1/PWM1 SPI0_SS1/SPI2_CLK/ADC1/PD.1 50 31 PB.10/SPI0_SS1/TM2 SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 51 30 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 52 29 PC.1/SPI0_CLK/I2S_BCLK SPI2_MISO1/ADC4/PD.4 53 28 PC.2/SPI0_MISO0/I2S_DI SPI2_MOSI1/ADC5/PD.5 54 27 PC.3/SPI0_MOSI0/I2S_DO TM0_EXT/INT1/PB.15 55 26 PC.4/SPI0_MISO1/UART0_RXD XT1_OUT/PF.0 56 25 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 57 24 PB.3/UART0_nCTS/TM3_EXT nRESET 58 23 PB.2/UART0_nRTS/TM2_EXT VSS 59 22 PB.1/UART0_TXD VDD 60 21 PB.0/UART0_RXD PS2_DAT/I2C0_SDA/ADC6/PF.2 61 20 USB_D+ PS2_CLK/I2C0_SCL/ADC7/PF.3 62 19 USB_D- PVSS 63 18 USB_VDD33_CAP TM0/PB.8 64 17 USB_VBUS 14 15 16 LDO_CAP VDD VSS 9 INT1/PD.11 13 8 CLKO/PD.10 SPI2_MISO0/UART1_nCTS/PB.7 7 PD.9 12 6 SPI1_MOSI0/PD.8 SPI2_MOSI0/UART1_nRTS/PB.6 5 I2C1_SDA/SPI2_MISO0/SPI1_MISO0/PA.10 11 4 I2C1_SCL/SPI2_MOSI0/SPI1_CLK/PA.11 SPI2_CLK/UART1_TXD/PB.5 3 CLKO/SPI1_SS0/PB.12 10 2 SPI1_SS1/SPI2_SS0/UART1_RXD/PB.4 1 PB.13 NUC123 SERIES DATASHEET INT0/PB.14 NUC123SxxAEx LQFP 64-pin ® Figure 4-5 NuMicro NUC123SxxAEx LQFP 64-pin Diagram May 8, 2020 Page 19 of 100 Rev.2.05 NUC123 ® ICE_CLK ICE_DAT PA.12/PWM0 PA.13/PWM1 PA.14/PWM2 PA.15/PWM3/I2S_MCLK/CLKO PC.8/SPI1_SS0/PWM0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 35 34 33 32 31 30 29 28 27 26 25 NuMicro NUC123LxxAEx LQFP 48 pin 36 4.3.2.2 AVDD 37 24 PB.9/SPI1_SS1/TM1/PWM1 SPI2_SS0/ADC0/PD.0 38 23 PB.10/SPI0_SS1/TM2 SPI0_SS1/SPI2_CLK/ADC1/PD.1 39 22 PC.0/SPI0_SS0/I2S_LRCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 40 21 PC.1/SPI0_CLK/I2S_BCLK SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 41 20 PC.2/SPI0_MISO0/I2S_DI SPI2_MISO1/ADC4/PD.4 42 19 PC.3/SPI0_MOSI0/I2S_DO SPI2_MOSI1/ADC5/PD.5 43 18 PC.4/SPI0_MISO1/UART0_RXD XT1_OUT/PF.0 44 17 PC.5/SPI0_MOSI1/UART0_TXD XT1_IN/PF.1 45 16 USB_D+ nRESET 46 15 USB_D- PS2_DAT/I2C0_SDA/ADC6/PF.2 47 14 USB_VDD33_CAP PS2_CLK/I2C0_SCL/ADC7/PF.3 48 13 USB_VBUS 7 8 9 SPI2_CLK/UART1_TXD/PB.5 SPI2_MOSI0/UART1_nRTS/PB.6 SPI2_MISO0/UART1_nCTS/PB.7 12 6 SPI1_SS1/SPI2_SS0/UART1_RXD/PB.4 VSS 5 I2C1_SDA/SPI2_MISO0/SPI1_MISO0/PA.10 11 4 I2C1_SCL/SPI2_MOSI0/SPI1_CLK/PA.11 VDD 3 INT0/PB.14 10 2 LDO_CAP 1 PVSS NUC123 SERIES DATASHEET TM0/PB.8 NUC123LxxAEx LQFP 48-pin ® Figure 4-6 NuMicro NUC123LxxAEx LQFP 48-pin Diagram May 8, 2020 Page 20 of 100 Rev.2.05 NUC123 ® ICE_CLK ICE_DAT PC.8/SPI1_SS0/PWM0 PC.9/SPI1_CLK PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0 PC.12/SPI1_MISO1/PWM2/I2S_MCLK PC.13/SPI1_MOSI1/PWM3/CLKO 23 22 21 20 19 18 17 NuMicro NUC123ZxxAEx QFN 33 pin 24 4.3.2.3 AVDD 25 16 PC.0/SPI0_SS0/I2S_LRCLK SPI0_SS1/SPI2_CLK/ADC1/PD.1 26 15 PC.1/SPI0_CLK/I2S_BCLK SPI0_MISO1/SPI2_MISO0/ADC2/PD.2 27 14 PC.2/SPI0_MISO0/I2S_DI SPI0_MOSI1/SPI2_MOSI0/ADC3/PD.3 28 13 PC.3/SPI0_MOSI0/I2S_DO XT1_OUT/PF.0 29 12 USB_D+ XT1_IN/PF.1 30 11 USB_D- nRESET 31 10 USB_VDD33_CAP PVSS 32 9 USB_VBUS NUC123ZxxAEx QFN 33-pin 2 3 4 5 6 7 8 I2C1_SCL/SPI2_MOSI0/SPI1_CLK/PA.11 SPI1_SS1/SPI2_SS0/UART1_RXD/PB.4 SPI2_CLK/UART1_TXD/PB.5 LDO_CAP VDD VSS NUC123 SERIES DATASHEET I2C1_SDA/SPI2_MISO0/SPI1_MISO0/PA.10 INT0/PB.14 1 33 VSS ® Figure 4-7 NuMicro NUC123ZxxAEx QFN 33-pin Diagram May 8, 2020 Page 21 of 100 Rev.2.05 NUC123 4.4 4.4.1 Pin Description NuMicro® NUC123 Pin Description Pin No LQFP 64- LQFP 48- QFN 33pin pin pin 1 3 3 5* 4 5* Type Description NUC123 SERIES DATASHEET PB.14 I/O INT0 I PB.13 I/O Digital GPIO pin PB.12 I/O Digital GPIO pin SPI1_SS0 I/O SPI1 1st slave select pin CLKO O Frequency Divider output pin PA.11 I/O Digital GPIO pin SPI1_CLK I/O SPI1 serial clock pin SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin I2C1_SCL I/O I2C1 clock pin PA.10 I/O Digital GPIO pin SPI1_MISO0 I/O SPI1 1st MISO (Master In, Slave Out) pin SPI2_MISO0 I/O SPI2 1st MISO (Master In, Slave Out) pin I2C1_SDA I/O I2C1 data input/output pin PD.8 I/O Digital GPIO pin SPI1_MOSI0 I/O SPI1 1st MOSI (Master Out, Slave In) pin PD.9 I/O Digital GPIO pin PD.10 I/O Digital GPIO pin CLKO O Frequency Divider output pin PD.11 I/O Digital GPIO pin Digital GPIO pin 1 2 4 Pin Name 2 3* 6 7 External interrupt 0 input pin 8 9 INT1 I PB.4 I/O UART1_RXD 10 11 12 6 7 I 4 5 External interrupt 1 input pin Digital GPIO pin UART1 data receiver input pin SPI2_SS0 I/O SPI2 1st slave select pin SPI1_SS1 I/O SPI1 2nd slave select pin PB.5 I/O Digital GPIO pin UART1_TXD O UART1 data transmitter output pin SPI2_CLK I/O SPI2 serial clock pin PB.6 I/O Digital GPIO pin UART1_nRTS O UART1 request to send output pin 8 May 8, 2020 Page 22 of 100 Rev.2.05 NUC123 13 9 SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin PB.7 I/O Digital GPIO pin UART1_nCTS I SPI2_MISO0 I/O UART1 clear to send input pin SPI2 1st MISO (Master In, Slave Out) pin LDO_CAP P LDO output pin VDD P Power supply for I/O ports and LDO source for internal PLL and digital function. Voltage range is 2.5V ~ 5V. 8 VSS P Ground 13 9 USB_VBUS USB Power supply from USB host or hub 18 14 10 USB_VDD33_CAP USB Internal power regulator output 3.3V decoupling pin 19 15 11 USB_D- USB USB differential signal D- 20 16 12 USB_D+ USB USB differential signal D+ 14 10 6 15 11 7 16 12 17 PB.0 I/O Digital GPIO pin 21 UART0_RXD I UART0 data receiver input pin PB.1 I/O Digital GPIO pin UART0_TXD O UART0 data transmitter output pin PB.2 I/O Digital GPIO pin UART0_nRTS O UART0 request to send output pin TM2_EXT I Timer2 external capture input pin 22 23 PB.3 24 26 27 28 17 18 19 20 13 14 UART0_nCTS I UART0 clear to send input pin TM3_EXT I Timer3 external capture input pin PC.5 I/O Digital GPIO pin SPI0_MOSI1 I/O SPI0 2nd MOSI (Master Out, Slave In) pin UART0_TXD O UART0 data transmitter output pin PC.4 I/O Digital GPIO pin SPI0_MISO1 I/O SPI0 2nd MISO (Master In, Slave Out) pin UART0_RXD I 21 May 8, 2020 UART0 data receiver input pin PC.3 I/O Digital GPIO pin SPI0_MOSI0 I/O SPI0 1st MOSI (Master Out, Slave In) pin I2S_DO O I2S data output pin PC.2 I/O Digital GPIO pin SPI0_MISO0 I/O SPI0 1st MISO (Master In, Slave Out) pin I I2S data input pin PC.1 I/O Digital GPIO pin SPI0_CLK I/O SPI0 serial clock pin I2S_DI 29 Digital GPIO pin NUC123 SERIES DATASHEET 25 I/O 15 Page 23 of 100 Rev.2.05 NUC123 30 31 32 22 16 23 24 33 34 35 NUC123 SERIES DATASHEET 36 37 40 41 I/O I2S bit clock pin PC.0 I/O Digital GPIO pin SPI0_SS0 I/O SPI0 1st slave select pin I2S_LRCLK I/O I2S left/right channel clock pin PB.10 I/O Digital GPIO pin SPI0_SS1 I/O SPI0 2nd slave select pin TM2 I/O Timer2 event counter input / toggle output pin PB.9 I/O Digital GPIO pin SPI1_SS1 I/O SPI1 2nd slave select pin TM1 I/O Timer1 event counter input / toggle output pin PWM1 I/O PWM1 PWM output / capture input pin (NUC123xxxAEx Only) VSS 25 26 27 28 30 I/O Digital GPIO pin SPI1_MOSI1 I/O SPI1 2nd MOSI (Master Out, Slave In) pin PWM3 I/O PWM3 PWM output / capture input pin CLKO O Frequency Divider output pin PC.12 I/O Digital GPIO pin SPI1_MISO1 I/O SPI1 2nd MISO (Master In, Slave Out) pin PWM2 I/O PWM2 PWM output / capture input pin I2S_MCLK O I2S master clock output pin PC.11 I/O Digital GPIO pin SPI1_MOSI0 I/O SPI1 1st MOSI (Master Out, Slave In) pin PC.10 I/O Digital GPIO pin SPI1_MISO0 I/O SPI1 1st MISO (Master In, Slave Out) pin 18 19 20 P Power supply for I/O ports and LDO source for internal PLL and digital function. Voltage range is 2.5V ~ 5V. PC.9 I/O Digital GPIO pin SPI1_CLK I/O SPI1 serial clock pin PC.8 I/O Digital GPIO pin SPI1_SS0 I/O SPI1 1st slave select pin PWM0 I/O PWM0 PWM output / capture input pin (NUC123xxxAEx Only) PA.15 I/O Digital GPIO pin PWM3 I/O PWM3 PWM output / capture input pin I2S_MCLK O I2S master clock output pin CLKO O Frequency Divider output pin 21 22 31 May 8, 2020 Ground PC.13 VDD 29 P 17 38 39 I2S_BCLK Page 24 of 100 Rev.2.05 NUC123 42 43 44 45 VSS PA.14 I/O Digital GPIO pin PWM2 I/O PWM2 PWM output / capture input pin PA.13 I/O Digital GPIO pin PWM1 I/O PWM1 PWM output / capture input pin PA.12 I/O Digital GPIO pin PWM0 I/O PWM0 PWM output / capture input pin ICE_DAT I/O Serial wired debugger data pin 33 34 35 23 47 36 24 48 37 25 Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin. ICE_CLK 50 52 53 54 38 39 40 41 42 43 I Serial wired debugger clock input pin Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin. AVDD AP Power supply for internal analog circuit PD.0 I/O Digital GPIO pin ADC0 AI ADC channel 0 analog input pin SPI2_SS0 I/O SPI2 1st slave select pin PD.1 I/O Digital GPIO pin SPI2_CLK I/O SPI2 serial clock pin SPI0_SS1 I/O SPI0 2nd slave select pin ADC1 AI ADC channel 1 analog input pin PD.2 I/O Digital GPIO pin SPI2_MISO0 I/O SPI2 1st MISO (Master In, Slave Out) pin SPI0_MISO1 I/O SPI0 2nd MISO (Master In, Slave Out) pin ADC2 AI ADC channel 2 analog input pin PD.3 I/O Digital GPIO pin SPI2_MOSI0 I/O SPI2 1st MOSI (Master Out, Slave In) pin SPI0_MOSI1 I/O SPI0 2nd MOSI (Master Out, Slave In) pin ADC3 AI ADC channel 3 analog input pin PD.4 I/O Digital GPIO pin ADC4 AI ADC channel 4 analog input pin SPI2_MISO1 I/O SPI2 2nd MISO (Master In, Slave Out) pin PD.5 I/O Digital GPIO pin ADC5 AI ADC channel 5 analog input pin SPI2_MOSI1 I/O SPI2 2nd MOSI (Master Out, Slave In) pin PB.15 I/O Digital GPIO pin INT1 I 26 27 28 NUC123 SERIES DATASHEET 51 Ground 32 46 49 P 55 May 8, 2020 External interrupt 1 input pin Page 25 of 100 Rev.2.05 NUC123 TM0_EXT 56 57 58 44 45 46 I Timer0 external capture input pin PF.0 I/O Digital GPIO pin XT1_OUT O External 4~24 MHz high speed crystal output pin PF.1 I/O Digital GPIO pin 29 30 XT1_IN I External 4~24 MHz high speed crystal input pin nRESET I External reset input: Low active, set this pin low reset chip to initial state. With internal pull-up. 31 Note: It is recommended to use 10 kΩ pull-up resistor and 10 μF capacitor on nRESET pin. 59 VSS P Ground 60 VDD P Power supply for I/O ports and LDO source for internal PLL and digital circuit. Voltage range is 2.5 V ~ 5V. PF.2 I/O Digital GPIO pin ADC6 AI ADC channel 6 analog input pin I2C0_SDA I/O I2C0 data input/output pin PS2_DAT I/O PS/2 data pin PF.3 I/O Digital GPIO pin ADC7 AI ADC channel 7 analog input pin I2C0_SCL I/O I2C0 clock pin PS2_CLK I/O PS/2 clock pin 61 62 47 48 63 1 64 2 32 NUC123 SERIES DATASHEET PVSS P PB.8 I/O Digital GPIO pin TM0 I/O Timer0 event counter input / toggle output pin PLL ground Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power May 8, 2020 Page 26 of 100 Rev.2.05 NUC123 5 BLOCK DIAGRAM 5.1 NuMicro® NUC123 Block Diagram Memory Timer/PWM Analog Interface 32-bit Timer x 4 APROM & DataFlash 36/68 KB ARM Watchdog Timer PDMA Cortex-M0 72MHz LDROM 4 KB SRAM 12/20 KB 10-bit ADC x 8 Windowed Watchdog Timer PWM/Capture Timer x 4 AHB/APB Bus LDO Clock Control Connectivity UART x 2 Power On Reset High Speed Oscillator 22.1184 MHz High Speed Crystal 4 ~ 24 MHz LVR Brownout Detection SPI x 3 General Purpose I/O I2C x 2 I2S Low Speed Oscillator 10 KHz I/O Ports Reset Pin PS/2 PLL USB External Interrupt ® Figure 5-1 NuMicro NUC123 Block Diagram NUC123 SERIES DATASHEET May 8, 2020 Page 27 of 100 Rev.2.05 NUC123 6 6.1 FUNCTIONAL DESCRIPTION ARM® Cortex® -M0 Core ® The Cortex -M0 processor, a configurable, multistage, 32-bit RISC processor, has an AMBA AHB-Lite interface and includes an NVIC component. The processor has optional hardware debug functionality, ® can execute Thumb code, and is compatible with other Cortex -M profile processors. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. Cortex-M0 components Cortex-M0 processor Nested Vectored Interrupt Controller (NVIC) Interrupts Wakeup Interrupt Controller (WIC) Debug Cortex-M0 Processor Core Bus Matrix Breakpoint and Watchpoint Unit Debugger interface AHB-Lite interface Debug Access Port (DAP) Serial Wire or JTAG debug port Figure 6-1 Functional Controller Diagram NUC123 SERIES DATASHEET The implemented device provides:   A low gate count processor: ® – ARMv6-M Thumb instruction set – Thumb-2 technology – ARMv6-M compliant 24-bit SysTick timer – A 32-bit hardware multiplier – System interface supporting little-endian data accesses – Ability to have deterministic, fixed-latency, interrupt handling – Load/store-multiples and multicycle-multiplies abandoned and restarted to facilitate rapid interrupt handling – C Application Binary Interface compliant exception model, which is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers – Low power sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature NVIC : May 8, 2020 Page 28 of 100 Rev.2.05 NUC123   – 32 external interrupt inputs, each with four levels of priority – Dedicated Non-Maskable Interrupt (NMI) input – Supports both level-sensitive and pulse-sensitive interrupt lines – Supports Wake-up Interrupt Controller (WIC) with ultra-low power sleep mode Debug support – Four hardware breakpoints – Two watchpoints – Program Counter Sampling Register (PCSR) for non-intrusive code profiling – Single step and vector catch capabilities Bus interfaces: – Single 32-bit AMBA-3 AHB-Lite system interface providing simple integration to all system peripherals and memory – Single 32-bit slave port supporting the DAP (Debug Access Port) NUC123 SERIES DATASHEET May 8, 2020 Page 29 of 100 Rev.2.05 NUC123 6.2 System Manager 6.2.1 Overview The system manager provides the functions of system control, power modes, wake-up sources, reset sources, system memory map, product ID and multi-function pin control. The following sections describe the functions for  System Reset  System Power Architecture  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset, and multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers 6.2.2 System Reset The system reset can be issued by one of the events listed below. These reset event flags can be read from RSTSRC register to determine the reset source. Hardware reset can reset chip through peripheral reset signals. Software reset can trigger reset through control registers.  NUC123 SERIES DATASHEET  Hardware Reset Sources – Power-on Reset (POR) – Low level on the nRESET pin – Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset) – Low Voltage Reset (LVR) – Brown-out Detector Reset (BOD Reset) Software Reset Sources – CHIP Reset will reset whole chip by writing 1 to CHIPRST (IPRSTC1[0]) – MCU Reset to reboot but keeping the booting setting from APROM or LDROM by writing 1 to SYSRESETREQ (AIRCR[2]) – CPU Reset for Cortex -M0 core Only by writing 1 to CPURST (IPRSTC1[1]) ® Power-on Reset or CHIP_RST (IPRST1[0]) resets the whole chip including all peripherals, external crystal circuit and BS (ISPCON[1]) bit. SYSRESETREQ (AIRCR[2]) resets the whole chip including all peripherals, but does not reset external crystal circuit and BS (ISPCON[1]) bit. May 8, 2020 Page 30 of 100 Rev.2.05 NUC123 Glitch Filter 36 us nRESET ~50k ohm @5v POR_DIS_CODE(PORCR[15:0]) Power-on Reset VDD LVR_EN(BODCR[7]) Reset Pulse Width 3.2ms Low Voltage Reset AVDD BOD_RSTEN(BODCR[3]) Brown-out Reset WDT/WWDT Reset System Reset Reset Pulse Width 64 WDT clocks CHIP Reset CHIP_RST(IPRSTC1[0]) MCU Reset SYSRESETREQ(AIRCR[2]) Software Reset Reset Pulse Width 2 system clocks CPU Reset CPU_RST(IPRSTC1[1]) Figure 6-2 System Reset Resources ® There are a total of 8 reset sources in the NuMicro family. In general, CPU reset is used to reset ® ® Cortex -M0 only; the other reset sources will reset Cortex -M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6-1. POR Register NRESET WDT LVR BOD CHIP MCU CPU RSTSRC Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1 CHIP_RST 0x0 - - - - - - - Reload from Reload CONFIG0 from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 (PWRCON [0]) Reload from Reload CONFIG0 from CONFIG0 Reload from CONFIG0 Reload Reload Reload from Reload from from CONFIG0 from CONFIG0 CONFIG0 CONFIG0 WDT_EN 0x1 0x1 - Reload from CONFIG0 Reload Reload Reload from Reload from from CONFIG0 from CONFIG0 CONFIG0 CONFIG0 (IPRSTC1[0]) BOD_EN (BODCR[0]) Reload from Reload CONFIG0 from CONFIG0 BOD_VL (BODCR[2:1]) BOD_RSTEN (BODCR[3]) XTL12M_EN - - 0x1 - - (APBCLK[0]) HCLK_S (CLKSEL0[2:0]) May 8, 2020 Reload from Reload CONFIG0 from CONFIG0 Page 31 of 100 Rev.2.05 NUC123 SERIES DATASHEET Reset Sources NUC123 WDT_S 0x3 0x3 - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 - - - - - - - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - (WTCR[7]) Reload from Reload CONFIG0 from CONFIG0 Reload from CONFIG0 Reload Reload Reload from from from CONFIG0 CONFIG0 CONFIG0 WTCR 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 - - WTCRALT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTRLD 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCR 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - - WWDTSR 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 - - WWDTCVR 0x3F 0x3F 0x3F 0x3F 0x3F 0x3F - - BS Reload from Reload CONFIG0 from CONFIG0 Reload from CONFIG0 Reload Reload Reload from from from CONFIG0 CONFIG0 CONFIG0 - DFBADR Reload from Reload CONFIG1 from CONFIG1 Reload from CONFIG1 Reload Reload Reload from from from CONFIG1 CONFIG1 CONFIG1 - CBS Reload from Reload CONFIG0 from CONFIG0 Reload from CONFIG0 Reload Reload Reload from from from CONFIG0 CONFIG0 CONFIG0 - Reload base on CONFIG0 Reload base on CONFIG0 Reload Reload Reload base base on base on on CONFIG0 CONFIG0 CONFIG0 - (CLKSEL1[1:0]) XTL12M_STB (CLKSTATUS[0]) PLL_STB (CLKSTATUS[2]) OSC10K_STB (CLKSTATUS[3]) OSC22M_STB (CLKSTATUS[4]) CLK_SW_FAIL (CLKSTATUS[7]) WTE (ISPCON[1]) NUC123 SERIES DATASHEET (ISPSTA[2:1)) VECMAP (ISPSTA[20:9]) Reload base on CONFIG0 (NUC123xxxAEx Only) Other Peripheral Registers Reset Value FMC Registers Reset Value - Note: ‘-‘ means that the value of register keeps original setting. Table 6-1 Reset Value of Registers 6.2.2.1 nRESET Reset The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be reset. The May 8, 2020 Page 32 of 100 Rev.2.05 NUC123 nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 V DD and the state keeps longer than 36 us (glitch filter). The RSTS_RESET (RSTSRC[1]) will be set to 1 if the previous reset source is nRESET reset. nRESET 0.7 VDD 36 us 0.2 VDD SS 36 us nRESET Reset SS Figure 6-3 shows the nRESET reset waveform. nRESET 0.7 VDD 36 us 0.2 VDD SS 36 us nRESET Reset SS 6.2.2.2 Power-On Reset (POR) The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the RSTS_POR (RSTSRC[0]) will be set to 1 to indicate there is a POR reset event. The RSTS_POR (RSTSRC[0]) bit can be cleared by writing 1 to it. Figure 6-4 shows the waveform of Power-On reset. May 8, 2020 Page 33 of 100 Rev.2.05 NUC123 SERIES DATASHEET Figure 6-3 nRESET Reset Waveform NUC123 VPOR 0.1V VDD Power On Reset Figure 6-4 Power-on Reset (POR) Waveform 6.2.2.3 Low Voltage Reset (LVR) If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVR_EN (BODCR[7]) to 1, after 100us delay, LVR detection circuit will be stable and the LVR function will be active. Then LVR function will detect AVDD during system operation. When the AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset. The LVR reset will control the chip in reset state until the AV DD voltage rises above VLVR and the state keeps longer than De-glitch time. The RSTS_RESET (RSTSRC[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6-5 shows the Low Voltage Reset waveform. AVDD NUC123 SERIES DATASHEET VLVR T1 ( 2.5V VDD V When system uses analog function, please refer to chapter 7.4 for corresponding analog operating voltage IDD1 36 mA IDD2 21 mA IDD3 35 mA IDD4 20 mA IDD5 7 mA IDD6 4 mA IDD7 6 mA IDD8 3 mA VDD = 5.5V at 72 MHz, All IP and PLL Enabled, XTAL = 12 MHz VDD = 5.5V at 72 MHz, Operating current All IP Disabled and PLL Enabled, XTAL = 12 MHz Normal Run mode at 72 MHz VDD = 3V at 72 MHz, All IP and PLL enabled, XTAL = 12 MHz All IP Disabled and PLL Enabled, XTAL = 12 MHz VDD = 5.5V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz VDD = 5.5V at 12 MHz, Operating current Normal Run mode at 12 MHz All IP and PLL Disabled, XTAL = 12 MHz VDD = 3V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz VDD = 3V at 12 MHz, All IP and PLL Disabled, XTAL = 12 MHz Operating current Normal Run mode May 8, 2020 VDD = 5V at 4 MHz, IDD9 4 Page 69 of 100 mA All IP Enabled and PLL Disabled, XTAL = 4 MHz Rev.2.05 NUC123 SERIES DATASHEET VDD = 3V at 72 MHz, NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT at 4 MHz VDD = 5V at 4 MHz, IDD10 3 mA IDD11 4 mA IDD12 2 mA IIDLE1 29 mA IIDLE2 14 mA IIDLE3 28 mA IIDLE4 13 mA IIDLE5 6 mA IIDLE6 3 mA IIDLE7 5 mA IIDLE8 2 mA IIDLE9 3 mA IIDLE10 2 mA IIDLE11 2 mA IIDLE12 1 mA All IP and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP and PLL Disabled, XTAL = 4 MHz VDD = 5.5V at 72 MHz, All IP and PLL Enabled, XTAL = 12 MHz VDD = 5.5V at 72 MHz, Operating current All IP Disabled and PLL Enabled, XTAL = 12 MHz Idle mode at 72 MHz VDD = 3V at 72 MHz, All IP and PLL Enabled, XTAL = 12 MHz VDD = 3V at 72 MHz, All IP Disabled and PLL Enabled, XTAL=12 MHz VDD = 5.5V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz NUC123 SERIES DATASHEET VDD = 5.5V at 12 MHz, Operating current All IP and PLL Disabled, XTAL = 12 MHz Idle mode at 12 MHz VDD = 3V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz VDD = 3 V at 12 MHz, All IP and PLL Disabled, XTAL = 12 MHz VDD = 5V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 5V at 4 MHz, Operating current All IP and PLL Disabled, XTAL = 4 MHz Idle mode at 4 MHz VDD = 3V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, May 8, 2020 Page 70 of 100 All IP and PLL Disabled, XTAL = 4 MHz Rev.2.05 NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT VDD = 5.5V at 10 kHz, IIDLE5 131 μA IIDLE6 129 μA IIDLE7 125 μA IIDLE8 124 μA IPWD1 12 μA IPWD2 9 μA Input Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional mode) IIN1 -64 μA VDD = 5.5V, VIN = 0V or VIN = VDD Input Current at /RESET[1] IIN2 -55 -45 -30 μA VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, PD, PE, PF ILK -2 - +2 μA VDD = 5.5V, 0 < VIN < VDD Logic 1 to 0 Transition Current PA~PF (Quasi-bidirectional mode) ITL [3] -650 - -200 μA VDD = 5.5V, VIN < 2.0V Input Low Voltage PA, PB, PC, PD, PE, PF (TTL input) -0.3 - 0.8 VIL1 Input High Voltage PA, PB, PC, PD, PE, PF (TTL input) VIH1 Input Low Voltage PA, PB, PC, PD, PE, PF (Schmitt input) All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled VDD = 5.5V at 10 kHz, Operating current All IP and PLL Disabled, LIRC 10 kHz Enabled Idle mode at 10 kHz VDD = 3V at 10 kHz, All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled VDD = 3 V at 10 kHz, Standby current Power-down mode - 0.6 2.0 - VDD +0.2 VDD = 5.5V V -0.5 - 0.35 VDD V Input High Voltage PA, PB, PC, PD, PE, PF (Schmitt input) VIH2 0.65 VDD - VDD+0.5 V Hysteresis voltage of PA~PE (Schmitt input) VHY Input Low Voltage XT1[*2] VIL3 (Schmitt input), /RESET May 8, 2020 when BOV function Disabled VDD = 2.5V VIL2 Positive going threshold VDD = 3.3V, No load NUC123 SERIES DATASHEET -0.3 VDD +0.2 (Schmitt input), /RESET when BOV function Disabled VDD = 4.5V - Negative going threshold VDD = 5.5V, No load V 1.5 Input High Voltage XT1[*2] All IP and PLL Disabled, LIRC 10 kHz Enabled 0.2 VDD 0 - VDD = 3.0V V 0.8 VDD = 4.5V V 0 - 0.4 VDD = 3.0V 3.5 - VDD +0.2 2.4 - VDD +0.2 VILS -0.5 - 0.2 VDD V VIHS 0.6 VDD - VDD+0.5 V V VDD = 5.5V VIH3 Page 71 of 100 VDD = 3.0V Rev.2.05 NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT ISR11 -300 -370 -450 μA VDD = 4.5V, VS = 2.4V ISR12 -50 -70 -90 μA VDD = 2.7V, VS = 2.2V ISR12 -40 -60 -80 μA VDD = 2.5V, VS = 2.0V ISR21 -20 -24 -28 mA VDD = 4.5V, VS = 2.4V ISR22 -4 -6 -8 mA VDD = 2.7V, VS = 2.2V ISR22 -3 -5 -7 mA VDD = 2.5V, VS = 2.0V ISK1 10 16 20 mA VDD = 4.5V, VS = 0.45V ISK1 7 10 13 mA VDD = 2.7V, VS = 0.45V ISK1 6 9 12 mA VDD = 2.5V, VS = 0.45V Brown-out voltage with BOV_VL [1:0] =00b VBO2.2 2.1 2.2 2.3 V Brown-out voltage with BOV_VL [1:0] =01b VBO2.7 2.6 2.7 2.8 V Brown-out voltage with BOV_VL [1:0] =10b VBO3.8 3.7 3.8 3.9 V Brown-out voltage with BOV_VL [1:0] =11b VBO4.5 4.4 4.5 4.6 V VBH 30 - 150 mV Source Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional Mode) Source Current PA, PB, PC, PD, PE, PF (Push-pull Mode) Sink Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional and Pushpull Mode) Hysteresis range of BOD voltage VDD = 2.5V - 5.5V Notes: 1. nRESET pin is a Schmitt trigger input. NUC123 SERIES DATASHEET 2. Crystal Input is a CMOS input. 3. Pins of PA, PB, PC, PD and PE can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5 V, 5he transition current reaches its maximum value when VIN approximates to 2V. May 8, 2020 Page 72 of 100 Rev.2.05 NUC123 8.3 AC Electrical Characteristics 8.3.1 External 4~24 MHz High Speed Oscillator tCLCL tCLCH 0.7 VDD 90% tCLCX 10% 0.3 VDD tCHCL tCHCX Note: Duty cycle is 50%. SYMBOL PARAMETER tCHCX MIN TYP MAX UNIT Clock High Time 10 - - ns tCLCX Clock Low Time 10 - - ns tCLCH Clock Rise Time 2 - 15 ns tCHCL Clock Fall Time 2 - 15 ns CONDITIONS MIN TYP MAX UNIT External crystal 4 12 24 MHz Temperature - -40 - 85 °C VDD - 2.5 5 5.5 V 8.3.2 CONDITIONS External 4~24 MHz High Speed Crystal PARAMETER Input clock frequency Typical Crystal Application Circuits CRYSTAL C1 C2 R 4 MHz ~ 24 MHz 10~20 pF 10~20 pF without XT1_OUT C2 XT1_IN R C1 Figure 8-1 Typical Crystal Application Circuit May 8, 2020 Page 73 of 100 Rev.2.05 NUC123 SERIES DATASHEET 8.3.2.1 NUC123 8.3.3 Internal 22.1184 MHz High Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage - 2.5 - 5.5 V Center Frequency - - 22.1184 - MHz +25°C; VDD =5 V -1 - +1 % -3 - +3 % VDD =5 V - 500 - μA CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 10 - kHz +25°C; VDD =5 V -30 - +30 % -50 - +50 % [1] Calibrated Internal Oscillator Frequency -40°C~+85°C; VDD =2.5 V~5.5 V Operation Current 8.3.4 Internal 10 kHz Low Speed Oscillator PARAMETER Calibrated Internal Oscillator Frequency -40°C~+85°C; VDD=2.5 V~5.5 V Note: Internal operation voltage comes from LDO. NUC123 SERIES DATASHEET May 8, 2020 Page 74 of 100 Rev.2.05 NUC123 8.4 Analog Characteristics 8.4.1 10-bit SARADC Specifications SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP UNIT 5.5 V AVDD = VDD AVDD = VDD = 5V, FSPS = 150k Operating Voltage AVDD Operating Current IADC 1.5 mA Resolution RADC 10 bit Reference Voltage VREF ADC input Voltage VIN 0 Sampling Rate FSPS 150k Integral Non-linearity Error (INL) INL ±1 LSB Differential Non-linearity Error (DNL) DNL ±1 LSB Gain Error EG ±2 LSB Offset Error EOFFSET 3 LSB Absolute Error EABS 4 LSB ADC Clock Frequency FADC 100k Clock Cycle ADCYC 36 AVDD V AVDD VREF Connected to AVDD in Chip V VDD = 5V, ADC Clock = 6 MHz Hz 6M Free Running Conversion Hz VDD = 5V Cycle LDO and Power Management Specifications PARAMETER MIN TYP MAX UNIT NOTE Input Voltage 2.5 5 5.5 V VDD input voltage Output Voltage 1.62 1.8 1.98 V VDD > 2.5V Temperature -40 25 85 °C Cbp - 1 - μF Resr = 1Ω Notes: 1. It is recommended that a 10 μF or higher capacitor and a 100nF bypass capacitor are connected between V DD and the closest VSS pin of the device. 2. To ensure power stability, a 1 μF (Cbp) or higher capacitor must be connected between LDO pin and the closest VSS pin of the device. May 8, 2020 Page 75 of 100 Rev.2.05 NUC123 SERIES DATASHEET 8.4.2 2.7 MAX NUC123 8.4.3 Low Voltage Reset Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 1.7 - 5.5 V Quiescent current VDD = 5.5 V - - 5 μA Temperature - -40 25 85 °C Temperature = 25°C 1.7 2.0 2.3 V Temperature = -40°C - 2.4 - V Temperature = 85°C - 1.6 - V - 0 0 0 V PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 2.5 - 5.5 V Quiescent current AVDD = 5.5 V - - 125 μA Temperature - -40 25 85 °C BOV_VL[1:0] = 11 4.4 4.5 4.6 V BOV_VL [1:0] = 10 3.7 3.8 3.9 V BOV_VL [1:0] = 01 2.6 2.7 2.8 V BOV_VL [1:0] = 00 2.1 2.2 2.3 V - 30 - 150 mV PARAMETER CONDITIONS MIN TYP MAX UNIT Temperature - -40 25 85 °C Reset voltage V+ - 2 - V Quiescent current Vin>reset voltage - 1 - nA Threshold voltage Hysteresis 8.4.4 Brown-out Detector Specifications NUC123 SERIES DATASHEET Brown-out voltage Hysteresis 8.4.5 Power-On Reset (5V) Specifications May 8, 2020 Page 76 of 100 Rev.2.05 NUC123 8.4.6 USB PHY Specifications 8.4.6.1 USB DC Electrical Characteristics SYMBOL PARAMETER VIH Input high (driven) VIL Input low VDI Differential input sensitivity VCM VSE CONDITIONS MIN TYP MAX 2.0 V 0.8 Differential common-mode range UNIT V |PADP-PADM| 0.2 Includes VDI range 0.8 2.5 V 0.8 2.0 V Single-ended receiver threshold Receiver hysteresis V 200 mV VOL Output low (driven) 0 0.3 V VOH Output high (driven) 2.8 3.6 V VCRS Output signal cross voltage 1.3 2.0 V RPU Pull-up resistor 1.425 1.575 kΩ RPD Pull-down resistor 14.25 15.75 kΩ VTRM Termination Voltage for upstream port pull up (RPU) 3.0 3.6 V ZDRV Driver output resistance Steady state drive* CIN Transceiver capacitance Pin to GND Ω 10 20 pF MAX UNIT Note: Driver output resistance doesn’t include series resistor resistance. USB Full-Speed Driver Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN TYP TFR Rising time CL = 50p 4 20 ns TFF Falling time CL = 50p 4 20 ns TFRFF Rising and falling time matching TFRFF = TFR/TFF 90 111.11 % CONDITIONS MIN MAX UNIT 8.4.6.3 USB Power Dissipation SYMBOL IVBUS PARAMETER VBUS current (steady state) May 8, 2020 Standby Page 77 of 100 TYP 50 μA Rev.2.05 NUC123 SERIES DATASHEET 8.4.6.2 NUC123 8.4.6.4 SYMBOL USB LDO Specification PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VBUS VBUS Pin Input Voltage 4.0 5.0 5.5 V VDD33 LDO Output Voltage 3.0 3.3 3.6 V Cbp External Bypass Capacitor 1.0 - μF NUC123 SERIES DATASHEET May 8, 2020 Page 78 of 100 Rev.2.05 NUC123 8.5 Flash DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.62 1.8 1.98 V[1] VDD Supply voltage TRET Data Retention TERASE Page Erase Time 20 ms TMER Mass Erase Time 40 ms TPROG Program Time 40 μs IDD1 Read Current IDD2 Program/Erase Current IPD Power Down Current Temp=85 °C 10 year 1 0.25 mA 7 mA 20 μA Note: VDD is source from chip LDO output voltage. NUC123 SERIES DATASHEET May 8, 2020 Page 79 of 100 Rev.2.05 NUC123 8.6 SPI Dynamic Characteristics SYMBOL PARAMETER MIN TYP MAX UNIT SPI Master mode (VDD = 4.5V ~ 5.5V, 30 pF loading Capacitor) tDS Data setup time TBD TBD - ns tDH Data hold time TBD - - ns tV Data output valid time - TBD TBD ns SPI Master mode (VDD = 3.0V ~ 3.6V, 30 pF loading Capacitor) tDS Data setup time TBD TBD - ns tDH Data hold time TBD - - ns tV Data output valid time - TBD TBD ns SPI Slave mode (VDD = 4.5V ~ 5.5V, 30 pF loading Capacitor) tDS Data setup time TBD - - ns tDH Data hold time TBD - - ns tV Data output valid time - TBD TBD ns SPI Slave mode (VDD = 3.0V ~ 3.6V, 30 pF loading Capacitor) tDS Data setup time TBD - - ns tDH Data hold time TBD - - ns tV Data output valid time - TBD TBD ns NUC123 SERIES DATASHEET TBD: To be defined. CLKP=0 SPICLK CLKP=1 tV MOSI Data Valid Data Valid tDS MISO Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tDH Data Valid tV Data Valid MOSI tDS MISO Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 tDH Data Valid Data Valid Figure 8-2 SPI Master Dynamic Characteristics Timing May 8, 2020 Page 80 of 100 Rev.2.05 NUC123 CLKP=0 SPICLK CLKP=1 tDS MOSI Data Valid tDH Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tv MISO Data Valid tDS MOSI Data Valid tDH Data Valid Data Valid Data Valid Data Valid tv MISO CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 Figure 8-3 SPI Slave Dynamic Characteristics Timing NUC123 SERIES DATASHEET May 8, 2020 Page 81 of 100 Rev.2.05 NUC123 9 ELECTRICAL CHARACTERISTICS (NUC123XXXAEX) 9.1 Absolute Maximum Ratings Symbol VDD  VSS VIN 1/tCLCL Parameter DC Power Supply Input Voltage Oscillator Frequency Min Max Unit -0.3 +7.0 V VSS - 0.3 VDD + 0.3 V 4 24 MHz TA Operating Temperature -40 +105 °C TST Storage Temperature -55 +150 °C IDD Maximum Current into VDD - 120 mA ISS Maximum Current out of VSS 120 mA Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA IIO Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of the device. NUC123 SERIES DATASHEET May 8, 2020 Page 82 of 100 Rev.2.05 NUC123 9.2 DC Electrical Characteristics (VDD-VSS=2.5 ~ 5.5 V, TA = 25C) SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT 5.5 V Operation voltage VDD 2.5 VDD rise rate to ensure internal operation correctly VRISE 0.05 V/ms -0.3 V Power ground VSS AVSS LDO output voltage VLDO 1.62 1.8 1.98 V Analog operating voltage AVDD 0 VDD V IDD1 39 mA IDD2 24 mA IDD3 37 mA IDD4 23 mA IDD5 10 mA IDD6 7 mA IDD7 8 mA IDD8 6 mA VDD = 2.5V ~ 5.5V up to 72 MHz VDD > 2.5V VDD = 5.5V at 72 MHz, All IP and PLL Enabled, XTAL = 12 MHz VDD = 5.5V at 72 MHz, Operating current All IP Disabled and PLL Enabled, XTAL = 12 MHz Normal Run mode at 72 MHz VDD = 3V at 72 MHz, All IP and PLL enabled, XTAL = 12 MHz All IP Disabled and PLL Enabled, XTAL = 12 MHz VDD = 5.5V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz VDD = 5.5V at 12 MHz, Operating current Normal Run mode at 12 MHz All IP and PLL Disabled, XTAL = 12 MHz VDD = 3V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz VDD = 3V at 12 MHz, All IP and PLL Disabled, XTAL = 12 MHz Operating current Normal Run mode May 8, 2020 VDD = 5V at 4 MHz, IDD9 6 Page 83 of 100 mA All IP Enabled and PLL Disabled, XTAL = 4 MHz Rev.2.05 NUC123 SERIES DATASHEET VDD = 3V at 72 MHz, NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT at 4 MHz VDD = 5V at 4 MHz, IDD10 5 mA IDD11 4 mA IDD12 3 mA IIDLE1 28 mA IIDLE2 12 mA IIDLE3 25 mA IIDLE4 10 mA IIDLE5 6 mA IIDLE6 3 mA IIDLE7 5 mA IIDLE8 2 mA IIDLE9 5 mA IIDLE10 4 mA IIDLE11 3 mA IIDLE12 2 mA All IP and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, All IP and PLL Disabled, XTAL = 4 MHz VDD = 5.5V at 72 MHz, All IP and PLL Enabled, XTAL = 12 MHz VDD = 5.5V at 72 MHz, Operating current All IP Disabled and PLL Enabled, XTAL = 12 MHz Idle mode at 72 MHz VDD = 3V at 72 MHz, All IP and PLL Enabled, XTAL = 12 MHz VDD = 3V at 72 MHz, All IP Disabled and PLL Enabled, XTAL=12 MHz VDD = 5.5V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz NUC123 SERIES DATASHEET VDD = 5.5V at 12 MHz, Operating current All IP and PLL Disabled, XTAL = 12 MHz Idle mode at 12 MHz VDD = 3V at 12 MHz, All IP Enabled and PLL Disabled, XTAL = 12 MHz VDD = 3 V at 12 MHz, All IP and PLL Disabled, XTAL = 12 MHz VDD = 5V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 5V at 4 MHz, Operating current All IP and PLL Disabled, XTAL = 4 MHz Idle mode at 4 MHz VDD = 3V at 4 MHz, All IP Enabled and PLL Disabled, XTAL = 4 MHz VDD = 3V at 4 MHz, May 8, 2020 Page 84 of 100 All IP and PLL Disabled, XTAL = 4 MHz Rev.2.05 NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT VDD = 5.5V at 10 kHz, IIDLE5 110 μA IIDLE6 110 μA IIDLE7 100 μA IIDLE8 100 μA IPWD1 15 μA IPWD2 13 μA Input Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional mode) IIN1 -64 μA VDD = 5.5V, VIN = 0V Input Current at /RESET[1] IIN2 -55 -45 -30 μA VDD = 3.3V, VIN = 0.45V Input Leakage Current PA, PB, PC, PD, PE, PF ILK -2 - +2 μA VDD = 5.5V, 0 < VIN < VDD Logic 1 to 0 Transition Current PA~PF (Quasi-bidirectional mode) ITL [3] -650 - -200 μA VDD = 5.5V, VIN < 2.0V Input Low Voltage PA, PB, PC, PD, PE, PF (TTL input) -0.3 - 0.8 VIL1 Input High Voltage PA, PB, PC, PD, PE, PF (TTL input) VIH1 Input Low Voltage PA, PB, PC, PD, PE, PF (Schmitt input) All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled VDD = 5.5V at 10 kHz, Operating current All IP and PLL Disabled, LIRC 10 kHz Enabled Idle mode at 10 kHz VDD = 3V at 10 kHz, All IP Enabled and PLL Disabled, LIRC 10 kHz Enabled VDD = 3 V at 10 kHz, Standby current Power-down mode - 0.6 2.0 - VDD +0.2 VDD = 5.5V V -0.5 - 0.35 VDD V Input High Voltage PA, PB, PC, PD, PE, PF (Schmitt input) VIH2 0.65 VDD - VDD+0.5 V Hysteresis voltage of PA~PE (Schmitt input) VHY Input Low Voltage XT1[*2] VIL3 (Schmitt input), /RESET May 8, 2020 when BOV function Disabled VDD = 2.5V VIL2 Positive going threshold VDD = 3.3V, No load NUC123 SERIES DATASHEET -0.3 VDD +0.2 (Schmitt input), /RESET when BOV function Disabled VDD = 4.5V - Negative going threshold VDD = 5.5V, No load V 1.5 Input High Voltage XT1[*2] All IP and PLL Disabled, LIRC 10 kHz Enabled 0.2 VDD 0 - VDD = 3.0V V 0.8 VDD = 4.5V V 0 - 0.4 VDD = 3.0V 3.9 - VDD +0.2 2.4 - VDD +0.2 VILS -0.5 - 0.2 VDD V VIHS 0.6 VDD - VDD+0.5 V V VDD = 5.5V VIH3 Page 85 of 100 VDD = 3.0V Rev.2.05 NUC123 SPECIFICATIONS PARAMETER SYM TEST CONDITIONS MIN TYP MAX UNIT ISR11 -300 -370 -450 μA VDD = 4.5V, VS = 2.4V ISR12 -50 -70 -90 μA VDD = 2.7V, VS = 2.2V ISR12 -40 -60 -80 μA VDD = 2.5V, VS = 2.0V ISR21 -24 -28 -32 mA VDD = 4.5V, VS = 2.4V ISR22 -4 -6 -8 mA VDD = 2.7V, VS = 2.2V ISR22 -3 -5 -7 mA VDD = 2.5V, VS = 2.0V ISK1 10 16 20 mA VDD = 4.5V, VS = 0.45V ISK1 7 10 13 mA VDD = 2.7V, VS = 0.45V ISK1 6 9 12 mA VDD = 2.5V, VS = 0.45V Brown-out voltage with BOV_VL [1:0] =00b VBO2.2 2.1 2.2 2.3 V Brown-out voltage with BOV_VL [1:0] =01b VBO2.7 2.6 2.7 2.8 V Brown-out voltage with BOV_VL [1:0] =10b VBO3.8 3.5 3.7 3.9 V Brown-out voltage with BOV_VL [1:0] =11b VBO4.5 4.2 4.4 4.6 V VBH 30 - 150 mV Source Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional Mode) Source Current PA, PB, PC, PD, PE, PF (Push-pull Mode) Sink Current PA, PB, PC, PD, PE, PF (Quasi-bidirectional and Pushpull Mode) Hysteresis range of BOD voltage VDD = 2.5V - 5.5V Notes: 1. nRESET pin is a Schmitt trigger input. NUC123 SERIES DATASHEET 2. Crystal Input is a CMOS input. 3. Pins of PA, PB, PC, PD and PE can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5 V, 5he transition current reaches its maximum value when VIN approximates to 2V. May 8, 2020 Page 86 of 100 Rev.2.05 NUC123 9.3 AC Electrical Characteristics 9.3.1 External 4~24 MHz High Speed Oscillator tCLCL tCLCH 0.7 VDD 90% tCLCX 10% 0.3 VDD tCHCL tCHCX Note: Duty cycle is 50%. SYMBOL PARAMETER tCHCX MIN TYP MAX UNIT Clock High Time 10 - - ns tCLCX Clock Low Time 10 - - ns tCLCH Clock Rise Time 2 - 15 ns tCHCL Clock Fall Time 2 - 15 ns CONDITIONS MIN TYP MAX UNIT External crystal 4 - 24 MHz Temperature - -40 - 105 °C VDD - 2.5 - 5.5 V 9.3.2 CONDITIONS External 4~24 MHz High Speed Crystal PARAMETER Input clock frequency Typical Crystal Application Circuits CRYSTAL C1 C2 R 4 MHz ~ 24 MHz 10~20 pF 10~20 pF without XT1_OUT C2 XT1_IN R C1 Figure 9-1 Typical Crystal Application Circuit May 8, 2020 Page 87 of 100 Rev.2.05 NUC123 SERIES DATASHEET 9.3.2.1 NUC123 9.3.3 Internal 22.1184 MHz High Speed Oscillator PARAMETER CONDITIONS MIN TYP MAX UNIT Supply voltage - 2.5 - 5.5 V Center Frequency - - 22.1184 - MHz +25°C; VDD =5 V -1 - +1 % -3 - +3 % VDD =5 V - 500 - μA CONDITIONS MIN TYP MAX UNIT Supply voltage[1] - 2.5 - 5.5 V Center Frequency - - 10 - kHz +25°C; VDD =5 V -30 - +30 % -50 - +50 % [1] Calibrated Internal Oscillator Frequency -40°C~+105°C; VDD=2.5 V~5.5 V Operation Current 9.3.4 Internal 10 kHz Low Speed Oscillator PARAMETER Calibrated Internal Oscillator Frequency -40°C~+105°C; VDD=2.5 V~5.5 V Note: Internal operation voltage comes from LDO. NUC123 SERIES DATASHEET May 8, 2020 Page 88 of 100 Rev.2.05 NUC123 9.4 Analog Characteristics 9.4.1 10-bit SARADC Specifications Specification PARAMETER Sym. TEST CONDITIONS Min. TYP. Unit 5.5 V Operating voltage AVDD Operating current IADC 1.5 mA Resolution RADC 10 bit Reference voltage VREF ADC input voltage VIN 0 Sampling rate FSPS 200k Integral non-linearity error 2.7 Max. AVDD V AVDD Hz ±1 LSB DNL ±1 LSB Gain error EG ±2 LSB Offset error EOFFSET 3 LSB Absolute error EABS 4 LSB ADC clock frequency FADC 100k ADCYC 16 Differential non-linearity (DNL) Clock cycle VREF connected to AVDD in chip Hz VDD = 5V, ADC clock = 3 MHz Free running conversion VDD = 5V Cycle LDO and Power Management Specifications PARAMETER MIN TYP MAX UNIT NOTE Input Voltage 2.5 5 5.5 V VDD input voltage Output Voltage 1.62 1.8 1.98 V VDD > 2.5V Temperature -40 25 105 °C Cbp - 1 - μF Resr = 1Ω Notes: 1. It is recommended that a 10μF or higher capacitor and a 100nF bypass capacitor are connected between V DD and the closest VSS pin of the device. 2. To ensure power stability, a 1μF (Cbp) or higher capacitor must be connected between LDO pin and the closest V SS pin of the device. May 8, 2020 Page 89 of 100 Rev.2.05 NUC123 SERIES DATASHEET 9.4.2 3M AVDD = VDD = 5V, FSPS = 200k V INL (INL) AVDD = VDD NUC123 9.4.3 Low Voltage Reset Specifications PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 1.7 - 5.5 V Quiescent current VDD = 5.5 V - - 5 μA Temperature - -40 25 105 °C Temperature = 25°C 1.7 2.0 2.3 V Temperature = -40°C - 1.8 - V Temperature = 85°C - 2.2 - V - 0 0 0 V PARAMETER CONDITIONS MIN TYP MAX UNIT Operation voltage - 2.5 - 5.5 V Quiescent current AVDD = 5.5 V - - 125 μA Temperature - -40 25 105 °C BOV_VL[1:0] = 11 4.2 4.4 4.6 V BOV_VL [1:0] = 10 3.5 3.7 3.9 V BOV_VL [1:0] = 01 2.6 2.7 2.8 V BOV_VL [1:0] = 00 2.1 2.2 2.3 V - 30 - 150 mV PARAMETER CONDITIONS MIN TYP MAX UNIT Temperature - -40 25 105 °C Reset voltage V+ - 2 - V Quiescent current Vin>reset voltage - 1 - nA Threshold voltage Hysteresis 9.4.4 Brown-out Detector Specifications NUC123 SERIES DATASHEET Brown-out voltage Hysteresis 9.4.5 Power-On Reset (5V) Specifications May 8, 2020 Page 90 of 100 Rev.2.05 NUC123 9.4.6 USB PHY Specifications 9.4.6.1 USB DC Electrical Characteristics SYMBOL PARAMETER VIH Input high (driven) VIL Input low VDI Differential input sensitivity VCM VSE CONDITIONS MIN TYP MAX 2.0 V 0.8 Differential common-mode range UNIT V |PADP-PADM| 0.2 Includes VDI range 0.8 2.5 V 0.8 2.0 V Single-ended receiver threshold Receiver hysteresis V 200 mV VOL Output low (driven) 0 0.3 V VOH Output high (driven) 2.8 3.6 V VCRS Output signal cross voltage 1.3 2.0 V RPU Pull-up resistor 1.425 1.575 kΩ RPD Pull-down resistor 14.25 15.75 kΩ VTRM Termination Voltage for upstream port pull up (RPU) 3.0 3.6 V ZDRV Driver output resistance Steady state drive* CIN Transceiver capacitance Pin to GND Ω 10 20 pF MAX UNIT Note: Driver output resistance doesn’t include series resistor resistance. USB Full-Speed Driver Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN TYP TFR Rising time CL = 50p 4 20 ns TFF Falling time CL = 50p 4 20 ns TFRFF Rising and falling time matching TFRFF = TFR/TFF 90 111.11 % CONDITIONS MIN MAX UNIT 9.4.6.3 USB Power Dissipation SYMBOL IVBUS PARAMETER VBUS current (steady state) May 8, 2020 Standby Page 91 of 100 TYP 50 μA Rev.2.05 NUC123 SERIES DATASHEET 9.4.6.2 NUC123 9.4.6.4 SYMBOL USB LDO Specification PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VBUS VBUS Pin Input Voltage 4.0 5.0 5.5 V VDD33 LDO Output Voltage 3.0 3.3 3.6 V Cbp External Bypass Capacitor 1.0 - μF NUC123 SERIES DATASHEET May 8, 2020 Page 92 of 100 Rev.2.05 NUC123 9.5 Flash DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 1.62 1.8 1.98 V[1] VDD Supply Voltage NENDUR Endurance TRET Data Retention TERASE Page Erase Time 20 ms TMER Mass Erase Time 40 ms TPROG Program Time 35 μs IDD1 Read Current TBD mA/MHz IDD2 Program/Erase Current IPD Power Down Current At 25°C 20000 cycles[2] 100 year - - 1 7 mA 20 μA Note1: VDD is source from chip LDO output voltage. Note2: Number of program/erase cycles. Note3: This table is guaranteed by design, not test in production. NUC123 SERIES DATASHEET May 8, 2020 Page 93 of 100 Rev.2.05 NUC123 9.6 SPI Dynamic Characteristics SYMBOL PARAMETER MIN TYP MAX UNIT SPI Master mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor) tDS Data setup time 4 2 - ns tDH Data hold time 0 - - ns tV Data output valid time - 7 11 ns SPI Master mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor) tDS Data setup time 5 3 - ns tDH Data hold time 0 - - ns tV Data output valid time - 13 18 ns SPI Slave mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor) tDS Data setup time 0 - - ns tDH Data hold time 2*PCLK+4 - - ns tV Data output valid time - 2*PCLK+11 2*PCLK+19 ns SPI Slave mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor) tDS Data setup time 0 - - ns tDH Data hold time 2*PCLK+6 - - ns tV Data output valid time - 2*PCLK+19 2*PCLK+25 ns NUC123 SERIES DATASHEET CLKP=0 SPICLK CLKP=1 tV MOSI Data Valid Data Valid tDS MISO Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tDH Data Valid tV Data Valid MOSI tDS MISO Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 tDH Data Valid Data Valid Figure 9-2 SPI Master Dynamic Characteristics timing May 8, 2020 Page 94 of 100 Rev.2.05 NUC123 CLKP=0 SPICLK CLKP=1 tDS MOSI Data Valid tDH Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tv MISO Data Valid tDS MOSI Data Valid tDH Data Valid Data Valid Data Valid Data Valid tv MISO CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 Figure 9-3 SPI Slave Dynamic Characteristics Timing NUC123 SERIES DATASHEET May 8, 2020 Page 95 of 100 Rev.2.05 NUC123 10 PACKAGE DIMENSIONS 10.1 64L LQFP (7x7x1.4 mm footprint 2.0 mm) NUC123 SERIES DATASHEET May 8, 2020 Page 96 of 100 Rev.2.05 NUC123 10.2 48L LQFP (7x7x1.4 mm footprint 2.0 mm) NUC123 SERIES DATASHEET May 8, 2020 Page 97 of 100 Rev.2.05 NUC123 10.3 33L QFN (5x5x0.8 mm) 32 25 1 24 8 17 9 16 25 32 24 1 17 8 NUC123 SERIES DATASHEET 16 May 8, 2020 9 Page 98 of 100 Rev.2.05 NUC123 11 REVISION HISTORY Date Revision Description 2012.04.01 1.00 Initial version. 2015.05.29 2.00 1. Merged NUC123xxxANx & NUC123xxxAEx into this document. 2015.11.04 2.01 1. Removed ADC function pins of NUC123 QFN33 package type in section 4.3.1.3, 4.3.2.3 and 4.4.1. 2016.01.12 2.02 1. Revised section 9.2 Source Current PA, PB, PC, PD, PE, PF (Push-pull Mode). 2016.07.06 2.03 1. Updated ADC function pins of NUC123 QFN33 package type in section 4.3.1.3, 4.3.2.3 and 4.4.1. 2017.05.03 2.04 1. Updated Typical Crystal Application Circuit for External 4~24 MHz High Speed Crystal in section 8.3.2.1. 2020.05.08 2.05 1. Added peripheral application scheme in chapter 7. 2. Added notes about the hardware reference design for ICE_DAT, ICE_CLK and nRESET pins in section 4.4 and chapter 7. NUC123 SERIES DATASHEET May 8, 2020 Page 99 of 100 Rev.2.05 NUC123 NUC123 SERIES DATASHEET Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. May 8, 2020 Page 100 of 100 Rev.2.05