NAU8812RG

NAU8812 Mono Audio Codec with Speaker Driver 1. GENERAL DESCRIPTION The NAU8812 is a cost effective and low power wideband MONO audio CODEC. It is designed for voice telephony related applications. Functions include Automatic Level Control (ALC) with noise gate, PGA, standard audio interface 2 I S, PCM with time slot assignment, and on-chip PLL. The device provides one differential microphone input and one single ended auxiliary input (multipurpose). There are few variable gain control stages in the audio path. It also includes MONO line output and integrated BTL speaker driver. The analog inputs have PGA on the front end, allowing dynamic range optimization with a wide range of input sources. The microphone amplifiers have a programmable gain from -12dB to +35.25dB to handle both amplified microphones. In addition to a digital high pass filter to remove DC offset voltages, the ADC also features voice band digital filtering. Voice-band data is accepted by the audio interface (I2S). The DAC converter path includes filtering and mixing, programmable-gain amplifiers (PGA), and soft muting. The digital interfaces, 2-Wire or SPI, have independent supply voltage to allow integration into multiple supply systems. The NAU8812 operates at supply voltages from 2.5V to 3.6V, although the digital core can operate at voltage as low as 1.71V to save power. The NAU8812 is specified for operation from -40°C to +85°C. AEC-Q100 & TS16949 compliant device is available upon request. 2. FEATURES 24-bit signal processing linear Audio CODEC  Audio DAC: 93dB SNR and -84dB THD  Audio ADC: 91dB SNR and -79dB THD  Support variable sample rates from 8 - 48kHz  Integrated BTL Speaker Driver 800mW (8Ω / 5V)  Integrated Headset Driver 40mW (16Ω / 3.3V) Additional features  Programmable ALC  ADC Notch Filter  Programmable High Pass Filter  Digital A/D-D/A Passthrough  Industrial temperature: range: –40°C to +85°C Analog I/O  Integrated programmable Microphone Amplifier  Integrated Line Input and Line Output  Earphone / Speaker / Line Output selection  Microphone / Line Inputs selection  Low Noise bias supplied for microphone  On-chip PLL Applications  VoIP Telephones]  Conference speaker-phone  IP PBX  Mobile Telephone Hands-free Kits  Residential & Consumer Intercoms Interfaces 2  I S digital interface PCM time slot assignment 2  SPI & 2-Wire serial control Interface (I C style; Read/Write capable) Low Power, Low Voltage  Analog Supply: 2.5V to 3.6V  Digital Supply: 1.71V to 3.6V  Nominal Operating Voltage: 3.3V NAU8812 Datasheet Rev2.9 Page 1 of 110 Jun, 2018 Line Driver AUX MIC- AUX ADC Filter Input Mixers Microphone Interface & Volume Control ADC Volume Control DAC HPF Gain Stage MIC+ Output Mixers DAC Filter BTL Speaker Driver & SPK+ Speaker Volume Limiter Notch Filter -1 SPK- PLL MICBIAS Micophone Bias Digital Audio Interface GPIO I2S CSb/GPIO PCM Audio I/O Serial Control Interface 2-wire SPI Digital I/O PIN CONFIGURATION VREF 1 28 AUX MIC - 2 27 VDDSPK MIC + 3 26 VDDSPK MICBIAS 4 25 SPKOUT - NC 5 24 VSSSPK VDDA 6 23 VSSSPK VSSA 7 22 SPKOUT + VSSA 8 21 MOUT VDDC 9 20 MODE VDDB 10 19 SDIO VSSD 11 18 SCLK ADCOUT 12 17 CSb/GPIO DACIN 13 16 MCLK FS 14 15 BCLK NAU8812 MONO AUDIO CODEC SSOP 28-Pin Figure 1: 28-Pin SSOP Package NAU8812 Datasheet Rev2.9 Page 2 of 110 Jun, 2018 MICBIAS MIC + MIC - VREF AUX VDDSPK VDDSPK SPKOUT - 32 31 30 29 28 27 26 25 NC 1 24 VSSSPK VDDA 2 23 VSSSPK VSSA 3 22 SPKOUT + VSSA 4 21 MOUT VDDL 5 20 NC VDDC 6 19 MODE VDDB 7 18 SO VSSD 8 17 SDIO 10 11 12 13 14 15 16 ADCOUT DACIN FS BCLK MCLK CSb/GPIO SCLK VSSD 9 NAU8812 MONO AUDIO CODEC QFN 32-Pin Figure 2: 32-Pin QFN Package NAU8812 Datasheet Rev2.9 Page 3 of 110 Jun, 2018 3. PIN DESCRIPTION Pin Name VREF 28-Pin 32-Pin A/D Pin Type 1 29 Decoupling internal analog mid supply reference A O MIC- 2 30 Microphone Negative Input A I MIC+ 3 31 Microphone Positive Input A I MICBIAS 4 32 Microphone Bias A O NC 5 1 No Connect VDDA 6 2 Analog Supply A I VSSA 7 3 Analog Ground A O VSSA 8 4 O - 5 D O VDDC 9 6 Analog Ground Logic supply voltage. This pin should not be connected up to an external supply Digital Supply Core A VDDL D I VDDB 10 7 Digital Supply Buffer D I VSSD 11 8 Digital Ground D O VSSD Functionality - 9 Digital Ground D O ADCOUT 12 10 Digital Audio Data Output D O DACIN 13 11 Digital Audio Data Input D I FS 14 12 Frame Sync D I/O BCLK 15 13 Bit Clock D I/O MCLK 16 14 Master Clock D I CSb/GPIO 17 15 SPI Chip Select or General Purposes 1 I/O D I/O SCLK 18 16 SPI or 2-Wire Serial Clock D I SDIO 19 17 SPI Data In or 2-Wire I/O D O - 18 SPI Data Output D O D I SO MODE 20 19 Interface Select (2-Wire or SPI) - 20 No Connect MOUT 21 21 MONO Output A O SPKOUT+ 22 22 Speaker Positive Output A O VSSSPK 23 23 Speaker Ground A O NC VSSSPK 24 24 Speaker Ground A O SPKOUT- 25 25 Speaker Negative Output A O VDDSPK 26 26 Speaker Supply A I VDDSPK 27 27 Speaker Supply A I AUX 28 28 Auxiliary Input A I Table 1: Pin Description for SSOP and QFN Packages Notes 1. 2. The 32-QFN package includes a bulk ground connection pad on the underside of the chip. This bulk ground should be thermally tied to the PCB, and electrically tied to the analog ground. Unused analog input pins should be left as no-connection. 3. Under all condition when digital pins are not used they should be tied to ground. 4. Pins designated as NC (Not Internally Connected) should be left as no-connection NAU8812 Datasheet Rev2.9 Page 4 of 110 Jun, 2018 NAU8812 Datasheet Rev2.9 Page 5 of 110 MICBIASEN[4] (0x2F) R R VDDA MICROPHONE BIAS PLLEN[5] (0x01) PMICBSTGAIN[6:4] (0x2F) = 000 PLL PMICBSTGAIN[6:4] (0x2F) Σ NC CONTROL INTERFACE ADCEN[0] (0x02) ADC VSSA VSSA LIMITER DIGITAL AUDIO INTERFACE NOTCH FILTER ALC HPF DACEN[0] (0x03) DAC (Sidetone) BYPASS VDDSPK VREF MICBIAS PMICPGA PGAMT[6] (0x2D) PGABST[8] (0x2F) AUX BYPASS VSSSPK VREF PGAGAIN (0x2D) AUXBSTGAIN[2:0] (0x2F) = 000 BSTEN[4] (0x02) VSSD NMICPGA[1] (0x2C) -12 dB to +35.25 dB AUXBSTGAIN[2:0] (0x2F) VDDC AUXPGA[2] (0x2C) VDDB PGAEN[2] (0x02) AUXEN[6] (0x01) VDDSPK VREF AUXM[3] (0x2C) 20k VSSSPK MIC+ MIC- AUX 20k AUXM[3] (0x2C) BYPSPK[1] (0x32) DACSPK[0] (0X32) AUXSPK[5] (0x32) BYPMOUT[1] (0x38) DACMOUT[0] (0x38) AUXMOUT[2] (0x38) SPKGAIN[5:0] (0x36) SPKMXEN[2] (0x03) Σ Σ MOUTMXEN[3] (0x03) SPK3V[2] (0x31) MOUT3V[3] (0x31) 1.5X 1.0X 1.5X 1.0X 1.5X 1.0X SPKOUT- SPKOUT+ MOUT 4. BLOCK DIAGRAM DACIN VDDA BCLK FS ADCOUT SO SCLK SDIO MODE CSb/GPIO MCLK Figure 3: NAU8812 General Block Diagram Jun, 2018 5. Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................................. 1 2. FEATURES .................................................................................................................................................... 1 PIN CONFIGURATION ............................................................................................................................................. 2 3. PIN DESCRIPTION ........................................................................................................................................ 4 4. BLOCK DIAGRAM ......................................................................................................................................... 5 5. TABLE OF CONTENTS ................................................................................................................................. 6 6. LIST OF FIGURES ....................................................................................................................................... 10 7. LIST OF TABLES ........................................................................................................................................ 12 8. ABSOLUTE MAXIMUM RATINGS ............................................................................................................... 13 9. OPERATING CONDITIONS ......................................................................................................................... 13 10. ELECTRICAL CHARACTERISTICS............................................................................................................. 14 11. FUNCTIONAL DESCRIPTION ..................................................................................................................... 17 11.1. INPUT PATH ......................................................................................................................................... 17 11.1.1. The Single Ended Auxiliary Input (AUX) ...................................................................................... 17 11.1.2. The differential microphone input (MIC- & MIC+ pins) ................................................................ 19 11.1.2.1. Positive Microphone Input (MIC+) ........................................................................................ 20 11.1.2.2. Negative Microphone Input (MIC-) ....................................................................................... 20 11.1.2.3. PGA Gain Control ................................................................................................................. 21 11.1.3. PGA Boost Stage .......................................................................................................................... 21 11.2. MICROPHONE BIASING ...................................................................................................................... 23 11.3. ADC DIGITAL FILTER BLOCK ............................................................................................................. 24 11.3.1. Programmable High Pass Filter (HPF) ......................................................................................... 25 11.3.2. Programmable Notch Filter (NF) .................................................................................................. 25 11.3.3. Digital ADC Gain Control .............................................................................................................. 26 11.4. PROGRAMMABLE GAIN AMPLIFIER (PGA) ....................................................................................... 26 11.4.1. Automatic level control (ALC) ...................................................................................................... 26 11.4.1.1. Normal Mode ......................................................................................................................... 29 11.4.1.2. ALC Hold Time (Normal mode Only) ....................................................................................... 29 11.4.2. Peak Limiter Mode ........................................................................................................................ 30 11.4.3. Attack Time ................................................................................................................................... 31 11.4.4. Decay Times ................................................................................................................................. 31 11.4.5. Noise gate (normal mode only) .................................................................................................... 31 11.4.6. Zero Crossing ............................................................................................................................... 32 11.5. DAC DIGITAL FILTER BLOCK ............................................................................................................. 33 11.5.4. Hi-Fi DAC De-Emphasis and Gain Control................................................................................... 34 11.5.5. Digital DAC Output Peak Limiter .................................................................................................. 35 11.5.6. Volume Boost ............................................................................................................................... 35 11.6. ANALOG OUTPUTS.............................................................................................................................. 36 11.6.1. Speaker Mixer Outputs ................................................................................................................. 36 11.6.2. MONO Mixer Output...................................................................................................................... 37 11.6.3. Unused Analog I/O ........................................................................................................................ 38 11.7. GENERAL PURPOSE I/O ..................................................................................................................... 39 11.7.1. Slow Timer Clock .......................................................................................................................... 40 NAU8812 Datasheet Rev2.9 Page 6 of 110 Jun, 2018 11.7.2. Jack Detect ................................................................................................................................... 40 11.7.3. Thermal Shutdown ....................................................................................................................... 41 11.8. CLOCK GENERATION BLOCK ............................................................................................................ 42 11.9. CONTROL INTERFACE ........................................................................................................................ 46 11.9.1. SPI Serial Control ......................................................................................................................... 46 11.9.1.1. 16-bit Write Operation (default) ............................................................................................ 47 11.9.1.2. 24-bit Write Operation .......................................................................................................... 47 11.9.1.3. 32-bit Read Operation........................................................................................................... 48 2 11.9.2. 2-WIRE Serial Control Mode (I C Style Interface) ........................................................................ 48 11.9.2.1. 2-WIRE Protocol Convention ............................................................................................... 49 11.9.2.2. 2-WIRE Write Operation ....................................................................................................... 49 11.9.2.3. 2-WIRE Read Operation ........................................................................................................ 50 11.10. DIGITAL AUDIO INTERFACES............................................................................................................. 51 11.10.1. Right Justified audio data ............................................................................................................ 52 11.10.2. Left Justified audio data ............................................................................................................... 53 2 11.10.3. I S audio data ................................................................................................................................ 54 11.10.4. PCM audio data ............................................................................................................................. 55 11.10.5. PCM Time Slot audio data ............................................................................................................ 56 11.10.6. Companding ................................................................................................................................. 57 11.11. POWER SUPPLY .................................................................................................................................. 58 11.11.1. Power-On Reset ............................................................................................................................ 58 11.11.2. Power Related Software Considerations ..................................................................................... 58 11.11.3. Software Reset.............................................................................................................................. 59 11.11.4. Power Up/Down Sequencing ........................................................................................................ 59 11.11.5. Reference Impedance (REFIMP) and Analog Bias ...................................................................... 60 11.11.6. Power Saving ................................................................................................................................ 60 11.11.7. Estimated Supply Currents .......................................................................................................... 61 12. REGISTER DESCRIPTION .......................................................................................................................... 62 12.1. SOFTWARE RESET ............................................................................................................................. 64 12.2. POWER MANAGEMENT REGISTERS ................................................................................................. 64 12.2.1. Power Management 1 ................................................................................................................... 64 12.2.2. Power Management 2 ................................................................................................................... 65 12.2.3. Power Management 3 ................................................................................................................... 65 12.3. AUDIO CONTROL REGISTERS ........................................................................................................... 65 12.3.1. Audio Interface Control ................................................................................................................ 65 12.3.2. Audio Interface Companding Control .......................................................................................... 66 12.3.3. Clock Control Register ................................................................................................................. 67 12.3.4. Audio Sample Rate Control Register ........................................................................................... 68 12.3.5. GPIO Control Register .................................................................................................................. 69 12.3.6. DAC Control Register ................................................................................................................... 69 12.3.7. DAC Gain Control Register .......................................................................................................... 70 12.3.8. ADC Control Register ................................................................................................................... 70 12.3.9. ADC Gain Control Register .......................................................................................................... 71 12.4. DIGITAL TO ANALOG CONVERTER (DAC) LIMITER REGISTERS ..................................................... 72 12.5. NOTCH FILTER REGISTERS ............................................................................................................... 73 12.6. AUTOMATIC LEVEL CONTROL REGISTER ........................................................................................ 74 12.6.1. ALC1 REGISTER ........................................................................................................................... 74 NAU8812 Datasheet Rev2.9 Page 7 of 110 Jun, 2018 12.6.2. ALC2 REGISTER ........................................................................................................................... 75 12.6.3. ALC3 REGISTER ........................................................................................................................... 76 12.7. NOISE GAIN CONTROL REGISTER .................................................................................................... 77 12.8. PHASE LOCK LOOP (PLL) REGISTERS ............................................................................................. 78 12.8.1. PLL Control Registers .................................................................................................................. 78 12.8.2. Phase Lock Loop Control (PLL) Registers .................................................................................. 78 12.9. INPUT, OUTPUT, AND MIXERS CONTROL REGISTER....................................................................... 79 12.9.1. Attenuation Control Register ....................................................................................................... 79 12.9.2. Input Signal Control Register ....................................................................................................... 79 12.9.3. PGA Gain Control Register .......................................................................................................... 80 12.9.4. ADC Boost Control Registers ...................................................................................................... 81 12.9.5. Output Register ............................................................................................................................ 81 12.9.6. Speaker Mixer Control Register ................................................................................................... 82 12.9.7. Speaker Gain Control Register .................................................................................................... 82 12.9.8. MONO Mixer Control Register ...................................................................................................... 83 12.9.9. Trimming Register ........................................................................................................................ 83 12.10. PCM TIME SLOT CONTROL & ADCOUT IMPEDANCE OPTION CONTROL ....................................... 84 12.10.1. PCM1 TIMESLOT CONTROL REGISTER ...................................................................................... 84 12.10.2. PCM2 TIMESLOT CONTROL REGISTER ...................................................................................... 84 12.11. REGISTER ID (READ ONLY) ................................................................................................................ 85 12.11.1. Device revision register................................................................................................................ 85 12.11.2. 2-WIRE ID Register (READ ONLY) ................................................................................................ 85 12.11.3. Additional ID (READ ONLY) .......................................................................................................... 85 12.12. Reserved .............................................................................................................................................. 86 12.13. OUTPUT Driver Control Register ........................................................................................................ 86 12.14. AUTOMATIC LEVEL CONTROL ENHANCED REGISTER ................................................................... 87 12.14.1. ALC1 Enhanced Register ............................................................................................................. 87 12.14.2. ALC Enhanced 2 Register ............................................................................................................ 87 12.15. MISC CONTROL REGISTER ................................................................................................................ 88 12.16. Output Tie-Off REGISTER ................................................................................................................... 89 12.17. ALC PEAK-TO-PEAK READOUT REGISTER ...................................................................................... 89 12.18. ALC PEAK READOUT REGISTER ....................................................................................................... 89 12.19. AUTOMUTE CONTROL AND STATUS READ REGISTER ................................................................... 90 12.20. Output Tie-off Direct Manual Control REGISTER ............................................................................... 90 13. CONTROL INTERFACE TIMING DIAGRAM ................................................................................................ 91 13.1. SPI WRITE TIMING DIAGRAM .............................................................................................................. 91 13.2. SPI READ TIMING DIAGRAM ............................................................................................................... 91 13.3. 2-WIRE TIMING DIAGRAM ................................................................................................................... 93 14. AUDIO INTERFACE TIMING DIAGRAM ...................................................................................................... 94 14.1. AUDIO INTERFACE IN SLAVE MODE .................................................................................................. 94 14.2. AUDIO INTERFACE IN MASTER MODE ............................................................................................... 94 14.3. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Audo Data) ............................................................. 95 14.4. PCM AUDIO INTERFACE IN MASTER MODE (PCM Audo Data) .......................................................... 95 14.5. PCM AUDIO INTERFACE IN SLAVE MODE (PCM Time Slot Mode ) .................................................... 96 14.6. PCM AUDIO INTERFACE IN MASTER MODE (PCM Time Slot Mode ) ................................................. 96 14.7. System Clock (MCLK) Timing Diagram........................................................................................ 97 14.8. µ-LAW ENCODE DECODE CHARACTERISTICS ................................................................................. 98 14.9. A-LAW ENCODE DECODE CHARACTERISTICS ................................................................................ 99 NAU8812 Datasheet Rev2.9 Page 8 of 110 Jun, 2018 14.10. µ-LAW / A-LAW CODES FOR ZERO AND FULL SCALE ................................................................... 100 14.11. µ-LAW / A-LAW OUTPUT CODES (DIGITAL MW) ............................................................................. 100 15. DIGITAL FILTER CHARACTERISTICS...................................................................................................... 101 16. TYPICAL APPLICATION ........................................................................................................................... 103 17. PACKAGE SPECIFICATION ..................................................................................................................... 105 17.1. 28 Pin SSOP32-Pin QFN .................................................................................................................... 105 18. ORDERING INFORMATION ...................................................................................................................... 107 19. REVISION HISTORY.................................................................................................................................. 108 IMPORTANT NOTICE .......................................................................................................................................... 110 NAU8812 Datasheet Rev2.9 Page 9 of 110 Jun, 2018 6. List of Figures Figure 1: 28-Pin SSOP Package .............................................................................................................................. 2 Figure 2: 32-Pin QFN Package................................................................................................................................. 3 Figure 3: NAU8812 General Block Diagram.............................................................................................................. 5 Figure 4: Auxiliary Input Circuit Block Diagram with AUXM[3] = 0 ........................................................................... 18 Figure 5: Auxiliary Input Circuit Block Diagram with AUXM[3] = 1 ........................................................................... 18 Figure 6: Input PGA Circuit Block Diagram ............................................................................................................. 19 Figure 7: Boost Stage Block Diagram ..................................................................................................................... 21 Figure 8: Microphone Bias Schematic .................................................................................................................... 23 Figure 9: ADC Digital Filter Path Block Diagram ..................................................................................................... 24 Figure 10: ALC Block Diagram ............................................................................................................................... 27 Figure 11: ALC Response Graph ........................................................................................................................... 27 Figure 12: ALC Normal Mode Operation................................................................................................................. 29 Figure 13: ALC Hold Time ...................................................................................................................................... 30 Figure 14: ALC Limiter Mode Operations ................................................................................................................ 30 Figure 15: ALC Operation with Noise Gate disabled ............................................................................................... 31 Figure 16: ALC Operation with Noise Gate Enabled ............................................................................................... 32 Figure 17: DAC Digital Filter Path........................................................................................................................... 33 Figure 18: DAC Digital Limiter Control .................................................................................................................... 35 Figure 19: Speaker and MONO Analogue Outputs ................................................................................................. 36 Figure 20: Tie-off Options for the Speaker and MONO output Pins ......................................................................... 38 Figure 21: PLL and Clock Select Circuit ................................................................................................................. 42 Figure 22: Register write operation using a 16-bit SPI Interface .............................................................................. 47 Figure 23: Register Write operation using a 24-bit SPI Interface ............................................................................. 48 Figure 24: Register Read operation through a 32-bit SPI Interface.......................................................................... 48 Figure 25: Valid START Condition .......................................................................................................................... 49 Figure 26: Valid Acknowledge ................................................................................................................................ 49 Figure 27: Valid STOP Condition............................................................................................................................ 49 Figure 28: Slave Address Byte, Control Address Byte, and Data Byte ..................................................................... 49 Figure 29: Byte Write Sequence ............................................................................................................................. 50 Figure 30: 2-Wire Read Sequence ......................................................................................................................... 50 Figure 31: Right Justified Audio Interface (Normal Mode) ....................................................................................... 52 Figure 32: Right Justified Audio Interface (Special mode) ....................................................................................... 52 Figure 33: Left Justified Audio Interface (Normal Mode).......................................................................................... 53 Figure 34: Left Justified Audio Interface (Special mode) ......................................................................................... 53 Figure 35: I2S Audio Interface (Normal Mode) ........................................................................................................ 54 Figure 36: I2S Audio Interface (Special mode)........................................................................................................ 54 Figure 37: PCM Mode Audio Interface (Normal Mode) ............................................................................................ 55 NAU8812 Datasheet Rev2.9 Page 10 of 110 Jun, 2018 Figure 38: PCM Mode Audio Interface (Special mode)............................................................................................ 55 Figure 39: PCM Time Slot Mode (Time slot = 0) (Normal Mode) ............................................................................. 56 Figure 40: PCM Time Slot Mode (Time slot = 0) (Special mode) ............................................................................. 56 Figure 41: The Programmable ADCOUT Pin .......................................................................................................... 84 Figure 42: SPI Write Timing Diagram ..................................................................................................................... 91 Figure 43: SPI Read Timing Diagram ..................................................................................................................... 91 Figure 44: 2-Wire Timing Diagram .......................................................................................................................... 93 Figure 45: Audio Interface Slave Mode Timing Diagram ......................................................................................... 94 Figure 46: Audio Interface in Master Mode Timing Diagram .................................................................................... 94 Figure 47: PCM Audio Interface Slave Mode Timing Diagram ................................................................................. 95 Figure 48: PCM Audio Interface Slave Mode Timing Diagram ................................................................................. 95 Figure 49: PCM Audio Interface Slave Mode (PCM Time Slot Mode )Timing Diagram ............................................ 96 Figure 50: PCM Audio Interface Master Mode (PCM Time Slot Mode )Timing Diagram ........................................... 96 Figure 51: MCLK Timing Diagram .......................................................................................................................... 97 Figure 52: DAC Filter Frequency Response.......................................................................................................... 102 Figure 53: ADC Filter Frequency Response.......................................................................................................... 102 Figure 54: DAC Filter Ripple................................................................................................................................. 102 Figure 55: ADC Filter Ripple................................................................................................................................. 102 Figure 56: Application Diagram 28-Pin SSOP ....................................................................................................... 103 Figure 57: Application Diagram for 32-Pin QFN .................................................................................................... 104 NAU8812 Datasheet Rev2.9 Page 11 of 110 Jun, 2018 7. List of Tables Table 1: Pin Description for SSOP and QFN Packages ............................................................................................ 4 Table 2: Register associated with Input PGA Contro............................................................................................... 19 Table 3: Microphone Non-Inverting Input Impedances ............................................................................................. 20 Table 4: Microphone Inverting Input Impedances.................................................................................................... 20 Table 5: Registers associated with ALC and Input PGA Gain Control ..................................................................... 21 Table 6: Registers associated with PGA Boost Stage Control ................................................................................. 22 Table 7: Register associated with Microphone Bias ................................................................................................ 23 Table 8: Microphone Bias Voltage Control .............................................................................................................. 24 Table 9: Register associated with ADC................................................................................................................... 25 Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1) ................................................................................... 25 Table 11: Registers associated with Notch Filter Function ...................................................................................... 25 Table 12: Equations to Calculate Notch Filter Coefficients ...................................................................................... 26 Table 13: Register associated with ADC Gain ........................................................................................................ 26 Table 14: Registers associated with ALC Control ................................................................................................... 28 Table 15: ALC Maximum and Minimum Gain Values .............................................................................................. 28 Table 16: Registers associated with DAC Gain Control........................................................................................... 33 Table 17: Speaker Output Controls ........................................................................................................................ 37 Table 18: MONO Output Controls........................................................................................................................... 37 Table 19: General Purpose Control ........................................................................................................................ 40 Table 20: Jack Insert Detect mode ......................................................................................................................... 40 Table 21: Jack Insert Detect controls ...................................................................................................................... 41 Table 22: Thermal Shutdown ................................................................................................................................. 41 Table 23: Registers associated with PLL ................................................................................................................ 43 Table 24: Registers associated with PLL ................................................................................................................ 44 Table 25: PLL Frequency Examples ....................................................................................................................... 45 Table 26: Control Interface Selection...................................................................................................................... 46 Table 27: Standard Interface modes ....................................................................................................................... 51 Table 28: Audio Interface Control Registers............................................................................................................ 51 Table 29: Companding Control ............................................................................................................................... 57 Table 30: Power up sequence ................................................................................................................................ 60 Table 31: Power down Sequence ........................................................................................................................... 60 Table 32: Registers associated with Power Saving ................................................................................................. 61 Table 33: VDDA 3.3V Supply Current ..................................................................................................................... 61 Table 34: SPI Timing Parameters ........................................................................................................................... 92 Table 35: 2-WireTiming Parameters ....................................................................................................................... 93 Table 36: Audio Interface Timing Parameters ......................................................................................................... 97 Table 37: MCLK Timing Parameter ........................................................................................................................ 97 NAU8812 Datasheet Rev2.9 Page 12 of 110 Jun, 2018 8. ABSOLUTE MAXIMUM RATINGS CONDITION MIN MAX Units VDDB, VDDC, VDDA supply voltages -0.3 +3.63 V VDDSPK supply voltage (MOUT=0, SPKBST=0) -0.3 +3.63 V VDDSPK supply voltage (MOUTBST=1, SPKBST=1) -0.3 +5.50 V Core Digital Input Voltage range VSSD – 0.3 VDDC + 0.30 V Buffer Digital Input Voltage range VSSD – 0.3 VDDB + 0.30 V Analog Input Voltage range VSSA – 0.3 VDDA + 0.30 V Industrial operating temperature -40 +85 0 C Storage temperature range -65 +150 0 C CAUTION: Do not operate at or near the maximum ratings listed for extended period of time. Exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 9. OPERATING CONDITIONS Condition Symbol Min Value Analogue supplies range VDDA 2.50 Digital supply range (Buffer) VDDB 1.71 Digital supply range (Core) VDDC VDDSPK Speaker supply Ground VSSD, VSSA, VSSSPK Typical Value Max Value Units 1 3.60 V 2 3.60 V 1.71 2 3.60 V 2.50 5.50 V 0 V Note: 1. VDDA must be ≥ VDDC. 2. VDDB must be ≥ VDDC. NAU8812 Datasheet Rev2.9 Page 13 of 110 Jun, 2018 10. ELECTRICAL CHARACTERISTICS o VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue to Digital Converter (ADC) Full scale input signal Signal to Noise Ratio 1 2 Total Harmonic Distortion 3 VINFS PGABST = 0dB PGAGAIN = 0dB SNR Gain = 0dB, A-weighted THD Input = -1dBFS, Gain = 0dB 87 1.0 0 VRMS dBV 91 dB -79 -65 dB Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) Full Scale output signal MOUTBST=0 1.0x (VREF) MOUTBST=1 1.5 x VREF 1 VRMS SNR A-weighted (ADC/DAC oversampling rate of 128) THD RL = 10 kΩ; -1.0dBfs Full-scale Input Signal Level VINFS Gain = 0dB 1 0 VRMS dBV Input Resistance RAUX AUXM=0 20 kΩ Input Capacitance CAUX 10 pF 1 0 VRMS dBV Signal to Noise Ratio 2 Total Harmonic Distortion 3 90 93 -84 dB -70 dB Auxiliary Analogue Input (AUX) 1 Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) PGABST = 0dB 1 Full-scale Input Signal Level VINFS PGAGAIN = 0dB Programmable input PGA gain -12 Programmable Gain Step Size 35.25 Guaranteed monotonic PGABST = 0 Programmable Boost PGA gain 0.75 Auxiliary Input resistance RAUX Positive Microphone Input resistance RMIC+ Input Capacitance CMIC dB 20 Mute Attenuation PGA equivalent output noise dB 0 PGABST = 1 dB 100 dB 0 to 20kHz, Gain set to 35.25dB 110 µV PGA Gain = 35.25dB 1.6 kΩ PGA Gain = 0dB 47 kΩ PGA Gain = -12dB 75 kΩ PMICPGA = 1 94 kΩ 10 pF Speaker Output PGA Programmable Gain Programmable Gain Step Size -57 6 Guaranteed monotonic 1 o VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. NAU8812 Datasheet Rev2.9 Page 14 of 110 Jun, 2018 dB dB PARAMETER SYMBOL TEST CONDITIONS MIN BTL Speaker Output (SPKOUT+, SPKOUT- with 8Ω bridge tied load) SPKBST = 0 VDDSPK = VDDA 7 Full scale output SPKBST = 1 VDDSPK = 1.5 * VDDA Output Power PO Signal to Noise Ratio SNR PSRR VDDA / 3.3 VRMS (VDDA / 3.3) * 1.5 90 dB VDDSPK = 1.5*VDDA RL = 8Ω 90 dB -63 dB -56 dB -60 dB -61 dB PO =1W -34 dB VDDSPK = 3V, SPKBST = 0 50 dB VDDSPK = 1.5*VDDA, SPKBST = 1 50 dB VDDA / 3.3 VRMS 90 dB -84 dB -85 dB (MICBIASV = 0) 0.9* VDDA V (MICBIASV = 1) 0.65* VDDA V 3 mA MICBIASM = 0 (1kHz to 20kHz) 14 nV/√Hz MICBIASM = 1 (1kHz to 20kHz) 4 nV/√Hz VDDSPK=3.3V PO =360mW RL = 8Ω VDDSPK = 1.5*VDDA PO =800mW Power Supply Rejection Ratio (50Hz - 22kHz) UNIT VDDSPK = 3.3V RL = 8Ω PO =400mW THD MAX Output power is very closely correlated with THD; see below PO =180mW Total Harmonic Distortion TYP Headphone’ output (SPKOUTP, SPKOUTN with resistive load to ground) Full scale output 7 Signal to Noise Ratio SNR Total Harmonic Distortion THD A-weighted Po = 20mW RL=16Ω Po = 20mW RL=32Ω VDDSPK=3.3V Microphone Bias Bias Voltage VMICBIAS Bias Current Source IMICBIAS Output Noise Voltage VN Automatic Level Control (ALC)/Limiter – ADC only Target Record Level -28.5 Programmable Gain -12 Programmable Gain Step Size Gain Hold Time 4, 6 Guaranteed Monotonic tHOLD NAU8812 Datasheet Rev2.9 MCLK=12.288MHz Page 15 of 110 -6 dB 35.25 dB dB 0.75 0 / 2.67 / …/ 43691 (time doubles with each step) Jun, 2018 ms o VDDC = 1.8V, VDDA = VDDB = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25 C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Automatic Level Control (ALC)/Limiter – ADC only Gain Ramp-Up (Decay) Time 5, 6 Gain Ramp-Down (Attack) Time 5, 6 tDCY tATK ALC Mode ALCM=0 MCLK=12.288MHz 3.3 / 6.6 / 13.1 / … / 3360 (time doubles every step) ms Limiter Mode ALCM=1 MCLK=12.288MHz 0.73 / 1.45 / 2.91 / … / 744 (time doubles every step) ms ALC Mode ALCM=0 MCLK=12.288MHz 0.83 / 1.66 / 3.33 / … / 852 (time doubles every step) ms Limiter Mode ALCM=1 MCLK=12.288MHz 0.18 / 0.36 / 0.73 / … / 186 (time doubles every step) ms Digital Input / Output 0.7 × VDDB Input HIGH Level VIH Input LOW Level VIL Output HIGH Level VOH IOL = 1mA Output LOW Level VOL IOH = -1mA V 0.3 × VDDB 0.9 × VDDB V 0.1 x VDDB Notes 1. Full Scale is relative to VDDA (FS = VDDA/3.3.). Input level to AUX is limited to a maximum of -3dB so that THD+N performance will not be reduced. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 3. THD+N (dB) - THD+N are a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. 5. Ramp-up and Ramp-Down times are defined as the time it takes to change the PGA gain by 6dB of its gain range. 6. All hold, ramp-up and ramp-down times scale proportionally with MCLK 7. The maximum output voltage can be limited by the speaker power supply. If MOUTBST or SPKBST is, set then VDDSPK should be 1.5xVDDA to prevent clipping taking place in the output stage (when PGA gains are set to 0dB). NAU8812 Datasheet Rev2.9 Page 16 of 110 V Jun, 2018 V 11. FUNCTIONAL DESCRIPTION The NAU8812 is a MONO Audio CODEC with very robust ADC and DAC. The device provides one single ended auxiliary input (AUX pin) and one differential microphone input (MIC- & MIC+ pins). The auxiliary input (AUX) can be configured to sum multiple signals into a single input. It has three different amplification paths with a total gain of up to +55.25dB. The differential input also has amplification paths similar to auxiliary input. The device also has an internal configurable biasing circuit for biasing the microphone, which in turn reduces external components. The PGA output has programmable ADC gain. An advanced Sigma Delta DAC is used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 kHz to 48 kHz. The Digital Filter blocks include ADC high pass filters, and Notch filter. The device has two output mixers, one for MONO output and the other for the speaker output. It also has one input mixer. The NAU8812 has two different types of serial control interface 2-Wire and SPI for device control. 2-Wire and SPI 2 are hardware selectable through MODE pin on the device. The device also supports I S, PCM time slotting, Left Justified and Right Justified for audio interface. The device can operate as a master or slave device. It can operate with sample rates ranging from 8 kHz to 48 kHz, depending on the values of MCLK and its prescaler. The NAU8812 includes a PLL block, where it takes the external clock (MCLK pin) to generate other clocks for the audio data transfer such as Bit clock (BCLK), Frame sync (FS), and 2 I S clocks. The PLL can also configure a separate programmable clock for the use in the system through CSb/GPIO pin. The power control registers help save power by controlling the major individual functional blocks of the NAU8812. 11.1. INPUT PATH The NAU8812 has two different types of microphone inputs single ended and differential. Figure 3 shows the different paths that the input signals can take. All inputs are maintained at a DC bias at approximately half of the VDDA supply voltage. Connections to these inputs should be AC-coupled by means of DC blocking capacitors suitable for the device application. 11.1.1. The Single Ended Auxiliary Input (AUX) The single ended auxiliary input (AUX) has three different paths to MONO output (MOUT).  Directly connected to the MONO Mixer or Speaker Mixer to MOUT or SPKOUT+ and SPKOUT- respectively  Connect through the PGA Boost Mixer which has a range of -12dB to +6dB  Connect through both the input PGA Gain (range of -12dB to +35.25 dB) and PGA Boost Mixer (range of 0db or +20dB) NAU8812 Datasheet Rev2.9 Page 17 of 110 Jun, 2018 The last two paths above go through the ADC filters where the ALC loop controls the amplitude of the input signal. The device also has an internal configurable biasing circuit for biasing the microphone, reducing external components. An internal inverting operational amplifier circuit allows the auxiliary input pin to connect multiple signals for mixing. This can be achieved by setting AUXM[3] address (0x2C) to LOW. The combination of the 20k ohm resistors can vary due to process variation in the gain stage. The block can also be configured to be used as a buffer by setting AUXM[3] address (0x2C) to HIGH. The internal inverting circuit block can be enable/disable by setting AUXEN[6] address (0x01). AUXM[3] (0x2C) R 20k 20k AUX Pin Output to PGA Gain MONO Mixer Speaker Mixer AUXM[3] (0x2C) VREF AUXEN[6] (0x01) Figure 4: Auxiliary Input Circuit Block Diagram with AUXM[3] = 0 AUXM[3] (0x2C) R R 20k 20k R AUX Pin Output to PGA Gain MONO Mixer Speaker Mixer AUXM[3] (0x2C) VREF AUXEN[6] (0x01) Figure 5: Auxiliary Input Circuit Block Diagram with AUXM[3] = 1 NAU8812 Datasheet Rev2.9 Page 18 of 110 Jun, 2018 11.1.2. The differential microphone input (MIC- & MIC+ pins) The NAU8812 features a low-noise, high common mode rejection ratio (CMRR), differential microphone inputs (MIC& MIC+ pins) which are connected to a PGA Gain stage. The differential input structure is essential in noisy digital systems where amplification of low-amplitude analog signals is necessary such as notebooks and PDAs. When properly employed, the differential input architecture offers an improved power-supply rejection ratio (PSRR) and higher ground noise immunity. PGAGAIN[5:0] (0x2D) AUXPGA[2] (0x2C) From AUX stage AUXPGA[2] (0x2C) R R NMICPGA[1] (0x2C) NMICPGA[1] (0x2C) R MIC- R PGAGAIN[5:0] (0x2D) PMICPGA[0] (0x2C) MIC+ To PGA Boost R -12 dB to +35.25 dB VREF PGAGAIN[5:0] (0x2D) Figure 6: Input PGA Circuit Block Diagram Bit(s) Addr Parameter Programmable Range PMICPGA[0] 0x2C Positive Microphone to PGA 0 = Input PGA Positive terminal to VREF 1 = Input PGA Positive terminal to MICP NMICPGA[1] 0x2C Negative Microphone to PGA 0 = MICN not connected to input PGA 1 = MICN to input PGA Negative terminal. Table 2: Register associated with Input PGA Contro NAU8812 Datasheet Rev2.9 Page 19 of 110 Jun, 2018 11.1.2.1. Positive Microphone Input (MIC+) The positive microphone input (MIC+) can be used as part of the differential input. It connects to the positive terminal of the PGA gain amplifier by setting PMICPGA[0] address (0x2C) to HIGH or can be connected to VREF by setting PMICPGA[0] address (0x2C) to LOW. When the associated control bit is set logic = 1, the MIC+ pin is connected to a resistor of approximately 1kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC level of the MIC+ pin close to VREF at all times. Note: In single ended applications where the MIC+ input is used without using MIC-, the PGA gain values will be valid only if the MIC- pin is terminated to a low impedance signal point. This termination should normally be an AC coupled path to signal ground. This input impedance is constant regardless of the gain value. The following table gives the nominal input impedance for this input. Impedance for specific gain values not listed in this table can be estimated through interpolation between listed values. MIC+ to non-inverting PGA input Nominal Input Impedance Gain (dB) Impedance (kΩ) Gain (dB) Impedance (kΩ) -12 -9 -6 -3 0 3 6 9 12 18 30 35.25 94 94 94 94 94 94 94 94 94 94 94 94 -12 -9 -6 -3 0 3 6 9 12 18 30 35.25 75 69 63 55 47 39 31 25 19 11 2.9 1.6 Table 3: Microphone Non-Inverting Input Impedances 11.1.2.2. MIC- to inverting PGA input Nominal Input Impedance Table 4: Microphone Inverting Input Impedances Negative Microphone Input (MIC-) The negative microphone input (MIC-) has two distinctive configuration; differential input or single ended input. This input connects to the negative terminal of the PGA gain amplifier by setting NMICPGA[1] address (0x2C) to HIGH. When the MIC- is used as a single ended input, MIC+ should be conned to VREF by setting PMICPGA[0] address (0x2C) bit to LOW. The AUX input signal can also be mixed with the MIC- input signal by setting AUXPGA[2] address (0x2C) to HIGH. NAU8812 Datasheet Rev2.9 Page 20 of 110 Jun, 2018 When the associated control bit NMICPGA[1] address 0X2C is set to logic = 0, the MIC- pin is connected to a resistor of approximately 30kΩ which is tied to VREF. The purpose of the tie to VREF is to reduce any pop or click sound by keeping the DC level of the MIC- pin close to VREF at all times. It is important for a system designer to know that the MIC-input impedance varies as a function of the selected PGA gain. This is normal and expected for a difference amplifier type topology. The above table gives the nominal resistive impedance values for this input over the possible gain range. Impedance for specific gain values not listed in this table can be estimated through interpolation between listed values. 11.1.2.3. PGA Gain Control The PGA amplification is common to all three input pins MIC-, MIC+, AUX, and enabled by PGAEN[2] address (0x02). It has a range of -12dB to +35.25dB in 0.75dB steps, controlled by PGAGAIN[5:0] address (0x2D). Input PGA gain will not be used when ALC is enabled using ALCEN[8] address (0x20). Addr Bit 8 Bit 7 Bit 6 Bit5 0x2D 0 PGAZC PGAMT 0x20 ALCEN 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PGAGAIN[5:0] ALCMXGAIN[2:0] Default 0x010 ALCMNGAIN[2:0] 0x038 Table 5: Registers associated with ALC and Input PGA Gain Control 11.1.3. PGA Boost Stage The boost stage has three inputs connected to the PGA Boost Mixer. All three inputs can be individually connected or disconnected from the PGA Boost Mixer. The boost stage can be enabled by setting BSTEN[4] address (0x02) to HIGH. The following figure shows the PGA Boost stage. AUXBSTGAIN[2:0] (0x2F) Output from AUX stage PGABST[8] PGAMT[6] (0x2F) (0x2D) Output from PGA Gain To ADC PMICBSTGAIN[6:4] (0x2F) MIC+ Pin Figure 7: Boost Stage Block Diagram NAU8812 Datasheet Rev2.9 Page 21 of 110 Jun, 2018 The signal from AUX stage can be amplified at the PGA Boost stage before connecting to the Boost Mixer by setting a binary value from “001” - “111” to AUXBSTGAIN[2:0] address (0x2F). The path is disconnected by setting “000” to the AUXBSTGAIN bits. Signal from PGA stage to the PGA Boost Mixer is disconnected or muted by setting PGAMT[6] address (0x2D) to HIGH. In this path the PGA boost can be a fixed value of +20dB or 0dB, controlled by the PGABST[8] address (0x2F) bit. The signal from MIC+ pin to the PGA Boost Mixer is disconnected by setting ‘000’ binary value to PMICBSTGAIN[6:4] address (0x2F) and any other combination connects the path. Bit(s) Addr Parameter Programmable Range BSTEN[4] 0x02 Enable PGA Boost Block 0 = Boost stage OFF 1 = Boost stage ON PGAMT[6] 0x2D Mute control for input PGA 0=Input PGA not muted 1=Input PGA muted AUXBSTGAIN[2:0] 0x2F Boost AUX signal Range: -12dB to +6dB @ 3dB increment PMICBSTGAIN[6:4] 0x2F Boost MIC+ signal Range: -12dB to +6dB @ 3dB increment PGABST[8] 0x2F Boost PGA stage 0 = PGA output has +0dB 1 = PGA output has +20dB Table 6: Registers associated with PGA Boost Stage Control NAU8812 Datasheet Rev2.9 Page 22 of 110 Jun, 2018 11.2. MICROPHONE BIASING MICBIASM[0] (0x28) VREF MICBIAS R R MICBIASV[1:0] (0x2C) Figure 8: Microphone Bias Schematic The MICBIAS pin is a low-noise microphone bias source for an external microphone, which can provide a maximum of 3mA of bias current. This DC bias voltage is suitable for powering either traditional ECM (electret) type microphones, or for MEMS types microphones with an independent power supply pin. Seven different bias voltages are available for optimum system performance, depending on the specific application. The microphone bias pin normally requires an external filtering capacitor as shown on the schematic in the Application section. The output bias can be enabled by setting MICBIASEN[4] address (0x01) to HIGH. It has various voltage values selected by a combination of bits MICBIASM[4] address (0x3A) and MICBIASV[8:7] address (0x2C). The low-noise feature results in greatly reduced noise in the external MICBIAS voltage by placing a resistor of approximately 200-ohms in series with the output pin. This creates a low pass filter in conjunction with the external microphone-bias filter capacitor, but without any additional external components. Bit(s) Addr Parameter MICBIASEN[4] 0x01 MICBIASM[4] (0x3A) Microphone bias mode selection MICBIASV[8:7] (0x2C) Microphone bias voltage selection Microphone bias enable Programmable Range 0 = Disable 1 = Enable 0 = Disable 1 = Enable Table 7: Register associated with Microphone Bias Below are the unloaded values when MICBIASM[4] is set to 1 and 0. When loaded, the series resistor will cause the voltage to drop, depending on the load current. NAU8812 Datasheet Rev2.9 Page 23 of 110 Jun, 2018 Microphone Bias Voltage Control MICBIASV[8:7] MICBIASM[4] = 0 MICBIASM[4]= 1 0 0 0.9* VDDA 0.85* VDDA 0 1 0.65* VDDA 0.60* VDDA 1 0 0.75* VDDA 0.70* VDDA 1 1 0.50* VDDA 0.50* VDDA Table 8: Microphone Bias Voltage Control 11.3. ADC DIGITAL FILTER BLOCK Figure 9: ADC Digital Filter Path Block Diagram ADC Digital Filters Digital Decimator ADC Digital Filter / Gain High Pass Filter Digital Audio Interface Notch Filter The ADC digital filter block performs a 24-bit signal processing. The block consists of an oversampled analog sigmadelta modulator, digital decimator, digital filter, high pass filter, and a notch filter. The oversampled analog sigmadelta modulator provides a bit stream to the decimation stages and filter. The ADC coding scheme is in twoscomplement format and the full-scale input level is proportional to VDDA. With a 3.3V supply voltage, the full-scale level is 1.0VRMS and any voltage greater than full scale may overload the ADC and cause distortion. The ADC is enabled by setting ADCEN[0] address (0x02) bit. Polarity and oversampling rate of the ADC output signal can be changed by ADCPL[0] address (0x0E) and ADCOS[3] address (0x0E) respectively. Bit(s) Addr Parameter Programmable Range ADCPL[0] 0x0E ADCOS[3] 0x0E HPFEN[8] 0x0E HPFAM[7] 0x0E Audio or Application Mode 0 = Audio (1 order, fc ~ 3.7 Hz) nd 1 = Application (2 order, fc =HPF) HPF[6:4] 0x0E High Pass Filter frequencies 82 Hz to 612 Hz dependant on the sample rate ADCEN[0] 0x02 Enable ADC 0 = Disable 1 = Enable 0 = Normal 1 = Inverted ADC Polarity ADC Over Sample Rate High Pass Filter Enable 0=64x (Lowest power) 1=128x (best SNR at typical condition) 0 = Disable 1 = Enable st NAU8812 Datasheet Rev2.9 Page 24 of 110 Jun, 2018 SMPLR[3:1] 0x07 Sample rate 8k Hz to 48 kHz Table 9: Register associated with ADC 11.3.1. Programmable High Pass Filter (HPF) The high pass filter (HPF) has two different modes that it can operate in either Audio or Application mode HPFAM[7] address (0x0E). In Audio Mode (HPFAM=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application mode (HPFAM=1) the filter is second order, with a cut-off frequency selectable via the HPF[2:0] register bits. Cut-off frequency of the HPF depends on sample frequency selected by SMPLR[3:1] address (0x07). The HPF is enabled by setting HPFEN[8] address (0x0E) to HIGH. Table below shows the cut-off frequencies with different sampling rate. HPF[2:0] 8 SMPLR=101/100 11.025 12 fs (kHz) SMPLR=011/010 16 22.05 24 SMPLR=001/000 32 44.1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1) 11.3.2. Programmable Notch Filter (NF) The NAU8812 has a programmable notch filter where it passes all frequencies except those in a stop band centered on a given center frequency. The filter gives lower distortion and flattens response. The notch filter is enabled by setting NFCEN[7] address (0x1B) to HIGH. The variable center frequency is programmed by setting two’s complement values to NFCA0[6:0] address (0x1C), NFCA0[13:7] address (0x1B) and NFCA1[6:0] address (0x1E), NFCA1[13:7] address (0x1D) registers. The coefficients are updated in the circuit when the NFCU[8] bit is set HIGH in a write to any of the registers NF1-NF4 address (0x1B, 0x1C, 0x1D, 0x1E). Addr Bit 8 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x1B NFCU NFCEN NFCA0[13:7] 0x000 0x1C NFCU 0 NFCA0[6:0] 0x000 0x1D NFCU 0 NFCA1[13:7] 0x000 0x1E NFCU 0 NFCA1[6:0] 0x000 Table 11: Registers associated with Notch Filter Function NAU8812 Datasheet Rev2.9 Page 25 of 110 Jun, 2018 A0 Coefficient A1  2 π fb 1 − tan   2 fs   2 π fb 1 + tan   2 fs          − (1 + A0 ) Notation  2 π fc   x cos    fs   Register Value (DEC) fc = center frequency (Hz) fb = -3dB bandwidth (Hz) fs = sample frequency (Hz) 13 NFCA0 = -A0 x 2 12 NFCA1 = -A1 x 2 (then convert to 2’s complement) Table 12: Equations to Calculate Notch Filter Coefficients 11.3.3. Digital ADC Gain Control The digital ADC can be muted by setting “0000 0000” to ADCGAIN[7:0] address (0x0F). Any other combination digitally attenuates the ADC output signal in the range -127dB to 0dB in 0.5dB increments]. Addr Name Bit 8 0x0F ADCG 0 Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 ADCGAIN Bit 1 Bit 0 Default 0x0FF Table 13: Register associated with ADC Gain 11.4. PROGRAMMABLE GAIN AMPLIFIER (PGA) NAU8812 has a programmable gain amplifier (PGA) which controls the gain such that the signal level of the PGA remains substantially constant as the input signal level varies within a specified dynamic range. The PGA has two functions  Automatic level control (ALC) or  Input peak limiter The Automatic Level Control (ALC) seeks to control the PGA gain in response to the amplitude of the input signal such that the PGA output maintains a constant envelope. A digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level ALCSL[3:0] address (0x21). Note: When the ALC automatic level control is enabled, the function of the ALC is to automatically adjust PGAGAIN[5:0] address (0x2D) volume setting. 11.4.1. Automatic level control (ALC) The ALC seeks to control the PGA gain such that the PGA output maintains a constant envelope. This helps to prevent clipping at the input of the sigma delta ADC while maximizing the full dynamic range of the ADC. The ALC monitors the output of the ADC, measured after the digital decimator has converted it to 1.23 fixed-point formats. The ADC output is fed into a peak detector, which updates the measured peak value whenever the absolute value of the input signal is higher than the current measured peak. The measured peak gradually decays to zero unless a new peak is detected, allowing for an accurate measurement of the signal envelope. Based on a comparison between the measured peak value and the target value, the ALC block adjusts the gain control, which is fed back to the PGA. NAU8812 Datasheet Rev2.9 Page 26 of 110 Jun, 2018 Rate Convert/ Decimator Input Pin PGA ADC Sinc Filter Digital Decimator Digital Filter ALC Figure 10: ALC Block Diagram The ALC is enabled by setting ALCEN[8] address (0x20) bit to HIGH. The ALC has two functional modes, which is set by ALCM[8] address (0x22).  Normal mode (ALCM = LOW)  Peak Limiter mode (ALCM = HIGH) When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the PGAGAIN[5:0] address (0x2D). A digital peak detector monitors the input signal amplitude Output Level and compares it to a register defined threshold level ALCSL[3:0] address (0x21). Input < noise gate threshold ALC operation range Target ALCSL -6dB Gain (Attenuation) Clipped at ALCMNGAIN -12dB +33 dB PGA Gain 0 dB -12 dB ALCNEN = 1 ALCNTH = -39dB MIC Boost Gain = 0dB ALCSL = -6dB ALCMNGAIN = -12dB ALCMXGAIN = +35.25dB -39dB -39dB -6dB +6dB Input Level Figure 11: ALC Response Graph The registers listed in the following section allow configuration of ALC operation with respect to:  ALC target level  Gain increment and decrement rates  Minimum and maximum PGA gain values for ALC operating range  Hold time before gain increments in response to input signal  Inhibition of gain increment during noise inputs NAU8812 Datasheet Rev2.9 Page 27 of 110 Jun, 2018  Limiter mode operation Bit(s) Addr ALCMNGAIN[2:0] Parameter Programmable Range Minimum Gain of PGA Range: -12dB to +30dB @ 6dB increment Maximum Gain of PGA Range: -6.75dB to +35.25dB @ 6dB increment ALCEN[8] Enable ALC function 0 = Disable 1 = Enable ALCSL[3:0] ALC Target Range: -28.5dB to -6dB @ 1.5dB increment ALC Hold Time Range: 0ms to 1s, time doubles with every step) ALCZC[8] ALC Zero Crossing 0 = Disable 1 = Enable ALCATK[3:0] ALC Attack time ALCM=0 - Range: 125us to 128ms ALCM=1 - Range: 31us to 32ms (time doubles with every step) ALC Decay time ALCM=0 - Range: 500us to 512ms ALCM=1 - Range: 125us to 128ms (Both ALC time doubles with every step) ALC Select 0 = ALC mode 1 = Limiter mode ALCMXGAIN[2:0] ALCHT[3:0] 0x20 0x21 0x22 ALCDCY[3:0] ALCM[8] Table 14: Registers associated with ALC Control The operating range of the ALC is set by ALCMXGAIN[5:3] address (0x20) and ALCMNGAIN[2:0] address (0x20) bits such that the PGA gain generated by the ALC is between the programmed minimum and maximum levels. When the ALC is enabled, the PGA gain is disabled. In Normal mode, the ALCMXGAIN bits set the maximum level for the PGA in the ALC mode but in the Limiter mode ALCMXGAIN has no effect because the maximum level is set by the initial PGA gain setting upon enabling of the ALC. ALCMAXGAIN Maximum Gain (dB) ALCMINGAIN Minimum Gain (dB) 111 110 35.25 29.25 000 001 -12 -6 ALC Max Gain Range 35.25dB to -6dB @ 6dB increments 001 000 ALC Min Gain Range -12dB to 30dB @ 6dB increments -0.75 -6.75 110 111 24 30 Table 15: ALC Maximum and Minimum Gain Values NAU8812 Datasheet Rev2.9 Page 28 of 110 Jun, 2018 11.4.1.1. Normal Mode Normal mode is selected when ALCM[8] address (0x22) is set LOW and the ALC is enabled by setting ALCEN[8] address (0x20) HIGH. This block adjusts the PGA gain setting up and down in response to the input level. A peak detector circuit measures the envelope of the input signal and compares it to the target level set by ALCSL[3:0] address (0x21). The ALC decreases the gain when the measured envelope is greater than the target and increases the gain when the measured envelope is less than - 1.5dB. The following waveform illustrates the behavior of the ALC. PGA Input PGA Output PGA Gain Figure 12: ALC Normal Mode Operation 11.4.1.2. ALC Hold Time (Normal mode Only) The hold parameter ALCHT[3:0] configures the time between detection of the input signal envelope being outside of the target range and the actual gain increase. Input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter for optimal performance. Increasing the ALC hold time prevents the ALC from reacting too quickly to brief periods of silence such as those that may appear in music recordings; having a shorter hold time, on the other hand, may be useful in voice applications where a faster reaction time helps to adjust the volume setting for speakers with different volumes. The waveform below shows the operation of the ALCHT parameter. NAU8812 Datasheet Rev2.9 Page 29 of 110 Jun, 2018 PGA Input PGA Output PGA Gain Hold Delay Change Figure 13: ALC Hold Time 11.4.2. Peak Limiter Mode Peak Limiter mode is selected when ALCM[8] address (0x22) is set to HIGH and the ALC is enabled by setting ALCEN[8] address (0x20). In limiter mode, the PGA gain is constrained to be less than or equal to the gain setting at the time the limiter mode is enabled. In addition, attack and decay times are faster in limiter mode than in normal mode as indicated by the different lookup tables for these parameters for limiter mode. The following waveform illustrates the behavior of the ALC in Limiter mode in response to changes in various ALC parameters. PGA Input PGA Output PGA Gain Limiter Enabled Figure 14: ALC Limiter Mode Operations When the input signal exceeds 87.5% of full scale, the ALC block ramps down the PGA gain at the maximum attack rate (ALCATK=0000) regardless of the mode and attack rate settings until the ADC output level has been reduced below the threshold. This limits ADC clipping if there is a sudden increase in the input signal level. NAU8812 Datasheet Rev2.9 Page 30 of 110 Jun, 2018 11.4.3. Attack Time When the absolute value of the ADC output exceeds the level set by the ALC threshold, ALCSL[3:0] address (0x21), attack mode is initiated at a rate controlled by the attack rate register ALCATK[3:0] address (0x22). The peak detector in the ALC block loads the ADC output value when the absolute value of the ADC output exceeds the current measured peak; otherwise, the peak decays towards zero, until a new peak has been identified. This sequence is continuously running. If the peak is ever below the target threshold, then there is no gain decrease at the next attack timer time; if it is ever above the target-1.5dB, then there is no gain increase at the next decay timer time. 11.4.4. Decay Times The decay time ALCDCY[6:4] address (0x22) is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode. 11.4.5. Noise gate (normal mode only) A noise gate is used when there is no input signal or the noise level is below the noise gate threshold. The noise gate is enabled by setting ALCNEN[3] address (0x23) to HIGH. It does not remove noise from the signal. The noise gate threshold ALCNTH[2:0] address (0x23) is set to a desired level so when there is no signal or a very quiet signal (pause), which is composed mostly of noise, the ALC holds the gain constant instead of amplifying the signal towards the target threshold. The noise gate only operates in conjunction with the ALC and ONLY in Normal mode. The noise gate flag is asserted when (Signal at ADC – PGA gain – MIC Boost gain) < ALCNTH (ALC Noise Gate Threshold) (dB) Levels at the extremes of the range may cause inappropriate operation, so care should be taken when setting up the function. PGA Input PGA Output PGA Gain Figure 15: ALC Operation with Noise Gate disabled NAU8812 Datasheet Rev2.9 Page 31 of 110 Jun, 2018 PGA Input Noise Gate Threshold PGA Output PGA Gain Figure 16: ALC Operation with Noise Gate Enabled 11.4.6. Zero Crossing The PGA gain comes from either the ALC block when it is enabled or from the PGA gain register setting when the ALC is disabled. Zero crossing detection may be enabled to cause PGA gain changes to occur only at an input zero crossing. Enabling zero crossing detection limits clicks and pops that may occur if the gain changes while the input signal has a high volume. There are two zero crossing detection enables:  Register ALCZC[8] address (0x21) – is only relevant when the ALC is enabled.  Register PGAZC[7] address (0x2D) – is only relevant when the ALC is disabled. If the zero crossing function is enabled (using either register) and SCLKEN[0] address (0x07) is asserted, the zero cross timeout function may take effect. If the zero crossing flag does not change polarity within 0.25 seconds of a PGA gain update (either via ALC update or PGA gain register update), then the gain will update. This backup system prevents the gain from locking up if the input signal has a small swing and a DC offset that prevents the zero crossing flag from toggling. NAU8812 Datasheet Rev2.9 Page 32 of 110 Jun, 2018 11.5. DAC DIGITAL FILTER BLOCK DAC Digital Filters Digital Audio Interface Digital Peak Limiter Digital Gain Digital Filters Interpolation Sigma Delta Modulator DAC Figure 17: DAC Digital Filter Path The DAC digital block uses 24-bit signal processing to generate analog audio with a 16-bit digital sample stream input. This block consists of a sigma-delta modulator, high pass filter, digital gain/filters, de-emphasis, and analog mixers. The DAC coding scheme is in twos complement format and the full-scale output level is proportional to VDDA. With a 3.3V supply voltage, the full-scale output level is 1.0VRMS. The DAC is enabled by setting DACEN[0] address (0x03) bit HIGH. Bit(s) Addr Parameter Programmable Range 0 = Disable 1 = Enable DACEN[0] 0x03 DAC enable ADDAP[0] 0x05 Pass-through of ADC output data into DAC input 0 = Disable 1 = Enable DACPL[0] DAC Polarity 0 = No Inversion 1 = DAC Output Inverted AUTOMT[2] Auto Mute 0 = Disable 1 = Enable DEEMP[5:4] Sample Rate 32 kHz, 44.1 kHz, and 48 kHz DACMT[6] Soft Mute 0 = Disable 1 = Enable DAC Volume Control Range: -127dB to 0dB @ 0.5dB increment, 00 hex is Muted DAC Limiter Attack Range: 68us to 139ms DAC Limiter Decay Range: 544us to 1.1s DAC Limiter Enable 0 = Disable 1 = Enable DAC Limiter Volume Boost Range: 0dB to +12dB @ 1dB increment DAC Limiter Threshold Range: -6dB to -1bB @ 1dB increment 0x0A DACGAIN[7:0] 0x0B DACLIMATK[3:0] DACLIMDCY[7:4] 0x18 DACLIMEN[8] DACLIMBST[3:0] 0x19 DACLIMTHL[6:4] Table 16: Registers associated with DAC Gain Control NAU8812 Datasheet Rev2.9 Page 33 of 110 Jun, 2018 11.5.1. DAC Soft Mute The NAU8812 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is disabled by default. This feature provides a tool that is useful for using the DACs without introducing pop and click sounds. To play back an audio signal, it must first be disabled by setting the DACMT[6] address (0x0A) bit to LOW. 11.5.2. DAC Auto Mute The output of the DAC can be muted by the analog auto mute function. The auto mute function is enabled by setting AUTOMT[2] address (0x0A) to HIGH and applied to the DAC output when it sees 1024 consecutive zeros at its input. If at any time there is a non-zero sample value, the DAC will be un-muted, and the 1024 count will be reinitialized to zero. 11.5.3. DAC Sampling / Oversampling rate, Polarity, DAC Volume control and Digital Pass-through The sampling rate of the DAC is determined entirely by the frequency of its input clock and the oversampling rate setting. The oversampling rate of the DAC can be changed to 64x or 128x. In the 128x oversampling mode it gives an improved audio performance at slightly higher power consumption. Because the additional supply current is only 1mA, in most applications the 128x oversampling is preferred for maximum audio performance. The polarity of the DAC output signal can be changed as a feature sometimes useful in management of the audio phase. This feature can help minimize any audio processing that may be otherwise required as the data are passed to other stages in the system. The effective output audio volume of the DAC can be changed using the digital volume control feature. This processes the output of the DAC to scale the output by the amount indicated in the volume register setting. Included is a “digital mute” value which will completely mute the signal output of the DAC. The digital volume setting can range from 0dB through -127dB in 0.5dB steps. Digital audio pass-through allows the output of the ADC to be directly sent to the DAC as the input signal to the DAC for DAC output. In this mode of operation, the external digital audio signal for the DAC will be ignored. The passthrough function is useful for many test and application purposes, and the DAC output may be utilized in any way that is normally supported for the DAC analog output signals. 11.5.4. Hi-Fi DAC De-Emphasis and Gain Control The NAU8812 has Hi-Fi DAC gain control for signal conditioning. The level of attenuation for an eight-bit code X is given by: 0.5 × (X-255) dB for 1 ≤ X ≤ 255; MUTE for X = 0 It includes on-chip digital de-emphasis and is available for sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The digital de-emphasis can be enabled by setting DEEMP[5:4] address (0x0A) bits depending on the input sample rate. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 µs pre-emphasis equalization as NAU8812 Datasheet Rev2.9 Page 34 of 110 Jun, 2018 a means of noise reduction. The DAC output can be inverted (phase inversion) by setting DACPL[1:0] address (0x0A) to HIGH, non-inverted output is set by default. 11.5.5. Digital DAC Output Peak Limiter Output Peak-Limiters reduce the dynamic range by ensuring the signal will not exceed a certain threshold, while maximizing the RMS of the resulted audio signal, and minimizing audible distortions. NAU8812 has a digital output limiter function. In the figure below, the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic. The limiter has a programmable threshold, DACLIMTHL[6:4] address (0x19), which ranges from -1dB to -6dB in 1dB increments. The digital peak limiter seeks to keep the envelope of the output signal within the target threshold +/- 0.5dB. The attack and decay rates programmed in registers DACLIMATK[3:0] address (0x18) and DACLIMDCY[7:4] address (0x18) specify how fast the digital peak limiter decrease and increase the gain, respectively, in response to the envelope of the output signal falling outside of this range. In normal operation LIMBST=000 signals below this threshold are unaffected by the limiter. DAC Input Data DAC Output Signal Threshold -1dB 0dB Digital Gain Figure 18: DAC Digital Limiter Control -0.5dB -1dB 11.5.6. Volume Boost The limiter has programmable upper gain, which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the DACLIMBST[3:0] register bits. The output limiter volume boost can also be used as a stand-alone digital gain boost when the limiter is disabled. NAU8812 Datasheet Rev2.9 Page 35 of 110 Jun, 2018 11.6. ANALOG OUTPUTS The NAU8812 features two different types of outputs, a single-ended MONO output (MOUT) and a differential speaker outputs (SPKOUT+ and SPKOUT-). The speaker amplifiers designed to drive a load differentially; a configuration referred to as Bridge-Tied Load (BTL). MOUTBST[3] (0x31) Output from Auxiliary Amplifier VDDSPK MOUTMXEN[3] (0x03) DACOUT[0] (0x38) MOUT DAC Output MONO MIXER MOUTBST GAIN 1.0x 0 1.5x 1 DC output 1.0 x VREF 1.5 x VREF -10dB or +0dB SIDETONE Output from PGA Boost VSSSPK VDDSPK Zero Cross Detection SPEAKER MIXER -1 SPKOUTSPKBST GAIN 0 1.0x 1 1.5x DC output 1.0 x VREF 1.5 x VREF SPKOUT+ -10dB or 0dB SPKMXEN[2] (0x03) SPKVOL[5:0] (0x36) Zero Cross Detection Buffer SPKBST[2] (0x31) VSSSPK Figure 19: Speaker and MONO Analogue Outputs Important: For analog outputs depopping purpose, when powering up speakers, headphone, AUXOUTs, certain delays are generated after enabling sequence. However, the delays are created by MCLK and sample rate register. For correct operation, sending I2S signal no earlier than 250ms after speaker or headphone enabled and MCLK appearing 11.6.1. Speaker Mixer Outputs The speaker amplifiers are designed to drive a load differentially; a configuration referred to as Bridge-Tied Load (BTL). The differential speaker outputs can drive a single 8Ω speaker or two headphone loads of 16Ω or 32Ω or a line output. Driving the load differentially doubles the output voltage. The output of the speaker can be manipulated by changing attenuation and the volume (loudness of the output signal). The output stage is powered by the speaker supply, VDDSPK, which are capable of driving up to 1.5VRMS signals (equivalent to 3VRMS into a BTL speaker). The speaker outputs can be controlled and can be muted individually. The output pins are at reference DC level when the output is muted. NAU8812 Datasheet Rev2.9 Page 36 of 110 Jun, 2018 Bit(s) Addr Parameter Programmable Range SPKMXEN[2] 0x03 Speaker Mixer enable 0 – Disabled 1 – Enabled PSPKEN[5] 0x03 Speaker positive terminal enable 0 – Disabled 1 – Enabled NSPKEN[6] 0x03 Speaker negative terminal enable 0 – Disabled 1 – Enabled SPKATT[1] 0x28 Speaker output attenuation 0 - 0dB 1 - -10dB SPKBST[2] 0x31 Speaker output Boost 0 – (1.0x VREF) Boost 1- (1.5 x VREF) Boost SPKGAIN[5:0] 0x36 Speaker output Volume Range: -57dB to +6dB @ 6dB increment SPKMT[6] 0x36 Speaker output Mute 0 – Speaker Enabled 1 – Speaker Muted Table 17: Speaker Output Controls 11.6.2. MONO Mixer Output The single ended output can drive headphone loads of 16Ω or 32Ω or a line output. The MOUT can be manipulated by changing attenuation and the volume (loudness of the output signal). The output stage is powered by the speaker supply, VDDSPK, which are capable of driving up to 1.5VRMS signals. The MONO output can be enabled for signal output or muted. The output pins are at reference DC level when the output is muted. Bit(s) Addr Parameter Programmable Range MOUTMXEN[3] 0x03 MONO mixer enable 0 – Disabled 1 – Enabled MOUTEN[7] 0x03 MONO output enable 0 – Disabled 1 – Enabled MOUTATT[2] 0x28 MONO output attenuation 0 - 0dB 1 - -10dB MOUTBST[3] 0x31 MONO output boost 0 – (1.0x VREF) Boost 1- (1.5 x VREF) Boost MOUTMXMT[6] 0x38 MONO Output Mixer Mute 0 – MONO Mixer Normal Mode 1 – MONO Mixer Muted MOUTMT[4] 0x45 MONO Output Mute 0 – MONO Output Normal Mode 1 – MONO Output Muted Table 18: MONO Output Controls NAU8812 Datasheet Rev2.9 Page 37 of 110 Jun, 2018 11.6.3. Unused Analog I/O AUX 30k AUXEN[6] (0x01) MIC- SMOUT[3] (0x4F) MOUTBST[3] = 0 (0x31) 30k 1K NMICPGA[1] (0x2C) MIC+ MOUT 30K 40k PMICPGA[0] (0x2C) MOUTBST[3] = 1 (0x31) SPSPK[4] (0x4F) 1.0 x VREF 1K VREF SPKOUT+ SNSPK[5] (0x4F) SBUFH[7] (0x4F) DCBUFEN[8] (0x01) SPKBST[2] = 1 (0x31) SBUFL[6] (0x4F) IOBUFEN[2] (0x01) SPKBST[2] = 0 (0x31) 30K 1K SPKOUT- 1.5 x VREF 30K AOUTIMP[0] (0x31) R R Figure 20: Tie-off Options for the Speaker and MONO output Pins In audio and voice systems, any time there is a sudden change in voltage to an audio signal, an audible pop or click sound may be the result. Systems that change inputs and output configurations dynamically, or which are required to manage low power operation, need special attention to possible pop and click situations. The NAU8812 includes many features which may be used to greatly reduce or eliminate pop and click sounds. The most common cause of a pop or click signal is a sudden change to an input or output voltage. This may happen in either a DC coupled system, or in an AC coupled system. The strategy to control pops and clicks is similar for either a DC coupled system, or an AC coupled system. The case of the AC coupled system is the most common and the more difficult situation, and therefore, the AC coupled case will be the focus for this information section. When an input or output pin is being used, the DC level of that pin will be very close to half of the VDDA voltage that is present on the VREF pin. The only exception is that when outputs are operated in the 5-Volt mode known as the 1.5x boost condition, then the DC level for those outputs will be equal to 1.5xVREF. In all cases, any input or output capacitors will become charged to the operating voltage of the used NAU8812 Datasheet Rev2.9 Page 38 of 110 Jun, 2018 input or output pin. The goal to reduce pops and clicks is to insure that the charge voltage on these capacitors does not change suddenly at any time. When an input or output is in a not-used operating condition, it is desirable to keep the DC voltage on that pin at the same voltage level as the DC level of the used operating condition. This is accomplished using special internal DC voltage sources that are at the required DC values. When an input or output is in the not-used condition, it is connected to the correct internal DC voltage as not to have a pop or click. This type of connection is known as a “tieoff” condition. Two internal DC voltage sources are provided for making tie-off connections. One DC level is equal to the VREF voltage value, and the other DC level is equal to 1.5x the VREF value. All inputs are always tied off to the VREF voltage value. Outputs will automatically be tied to either the VREF voltage value or to the 1.5xVREF value, depending on the value of the “boost” control bit for that output. That is to say, when an output is set to the 1.5x gain condition, then that same output will automatically use the 1.5xVREF value for tie-off in the not-used condition. The input pull-ups are connected to IOBUFEN[2] address (0x01) buffer with a voltage source (VREF). The output pull-ups can be connected two different buffers depending on the voltage source. IOBUFEN[2] address (0x01) buffer is enabled if the voltage source is (VREF) and DCBUFEN[8] address (0x01) buffer is enabled if the voltage source is (1.5 x VREF). IOBUFEN[2] address (0x01) buffer is shared between input and output pins. To conserve power, these internal voltage buffers may be enabled/disabled using control register settings. To better manage pops and clicks, there is a choice of impedance of the tie-off connection for unused outputs. The nominal values for this choice are 1kΩ and 30kΩ. The low impedance value will better maintain the desired DC level in the case when there is some leakage on the output capacitor or some DC resistance to ground at the NAU8812 output pin. A tradeoff in using the low-impedance value is primarily that output capacitors could change more suddenly during power-on and power-off changes. Automatic internal logic determines whether an input or output pin is in the used or un-used condition. This logic function is always active. An output is determined to be in the un-used condition when it is in the disabled unpowered condition, as determined by the power management registers. An input is determined to be in the un-used condition when all internal switches connected to that input are in the “open” condition. 11.7. GENERAL PURPOSE I/O The CSb/GPIO pin can be configured in two ways, chip select for SPI interface and general purpose GPIO. Therefore, the general-purpose configuration is only available in the 2-Wire interface mode, which is configured by setting GPIOSEL[2:0] address (0x08) to 001 – 101. “000” configures the pin to be a chip select for SPI mode. The CSb/GPIO pin is not available in the SPI interface mode. When the pin is configured as an input, it can be used as chip select signal for SPI interface or for jack detect. When the pin is configured as output, it can be used for signaling analog mute, temperature alert, PLL frequency output, and PLL frequency lock. The CSb/GPIO pin can also output the master clock through a PLL or directly. The path also included a divider for different clocks needed in the system. Note that SCLKEN must be enabled when using the Jack Detect function. NAU8812 Datasheet Rev2.9 Page 39 of 110 Jun, 2018 Addr D8 D7 D6 0x08 0 0 0 0x07 0 0 0 D5 D4 D3 GPIOPLL[1:0] 0 D2 GPIOPL 0 D1 D0 0x000 GPIOSEL[2:0] SMPLR[2:0] Default SCLKEN 0x000 Table 19: General Purpose Control 11.7.1. Slow Timer Clock An internal Slow Timer Clock is supplied to automatically control features that happen over a relatively long period of time, or time-spans. This enables the NAU8812 to implement long time-span features without any host/processor management or intervention. The Slow Timer Clock supports two features automatic time out for the zero-crossing holdoff of PGA volume changes, and timing for debouncing of the mechanical jack detection feature. If either feature is required, the Slow Timer Clock must be enabled. The Slow Timer Clock is initialized in the disabled state. The Slow Timer Clock rate is derived from MCLK using an integer divider that is compensated for the sample rate as indicated by the register address (0x07). If the sample rate register value precisely matches the actual sample rate, then the internal Slow Timer Clock rate will be a constant value of 128ms. If the actual sample rate is, for example, 44.1kHz and the sample rate selected in register 0x07 is 48kHz, the rate of the Slow Timer Clock will be approximately 10% slower in direct proportion of the actual vs. indicated sample rate. This scale of difference should not be important in relation to the dedicated end uses of the Slow Timer Clock. 11.7.2. Jack Detect Jack detect is a specific GPIO function. Jack detect is only available in 2-Wire mode only. Jack detect is selected by setting GPIOSEL[2:0] address (0x08) to “001”. The GPIOPL[3] bit address (0x08) inverts the CSb/GPIO pin when set to 1. The table below shows all the combinations for jack insert detects. The CSb/GPIO pin has an internal de-bounce circuit so that when the jack detect feature is enabled it does not toggle multiple times due to input glitches. Slow clock mode must be enabled when using jack insert detect by setting SCLKEN[0] address (0x07). GPIOPL CSb/GPIO NSPKEN/ PSPKEN MOUTEN Speaker Enabled MONO output Enabled 0 0 1 X Yes No 0 1 X 1 No Yes 1 0 X 1 No Yes 1 1 1 X Yes No Table 20: Jack Insert Detect mode NAU8812 Datasheet Rev2.9 Page 40 of 110 Jun, 2018 Bit(s) Addr Parameter Programmable Range 0 - CSb Input 1 - Jack Detect 2 - Temperature OK 3 - AMUTE Active 4 - PLL Frequency Output 5 - PLL Lock (0- Locked, 1 – Not Locked) 6 - HIGH 7 - LOW GPIOSEL[2:0] 0x08 GPIO select GPIOPL[3] 0x08 GPIO polarity GPIOPLL[4:5] 0x08 GPIO PLL divider PSPKEN[5] 0x03 Speaker positive terminal enable NSPKEN[6] 0x03 Speaker negative terminal enable MOUTEN[7] 0x03 MONO Output enable SCLKEN[0] 0x07 Slow clock enable 0 – Non- Inverted 1 – Inverted 0 - Divide by 1 1 - Divide by 2 2 - Divide by 3 3 - Divide by 4 0 – Muted 1 – Enabled 0 – Muted 1 – Enabled 0 – Muted 1 – Enabled Period 2 21 * MCLK Table 21: Jack Insert Detect controls 11.7.3. Thermal Shutdown The device contains an on-chip temperature sensor that senses the temperature inside the package. By enabling the temperature sensor interrupt in GPIOSEL[2:0] address (0x08), an interrupt will be generated if the temperature reaches a threshold of approximately 125°C. This facilitates control of the temperature should the device get close to the junction temperature. Note that there is no filtering associated with this temperature alarm since the package has an intrinsic thermal time constant. The thermal temperature is enabled by setting TSEN[1] address (0x31). Bit(s) Addr Parameter TSEN[1] 0x31 Temperature Sense Enable Programmable Range 0: Thermal Shutdown Disable 1: Thermal Shutdown Enable Table 22: Thermal Shutdown NAU8812 Datasheet Rev2.9 Page 41 of 110 Jun, 2018 11.8. CLOCK GENERATION BLOCK ADCOS[3] (0x0E) f1 MCLK MCLKSEL[7:5] (0x06) fPLL PLLMCLK[4] (0x24) PLL1 R=f2/f1 f2 IMCLK f/N f/4 f/N f/N ADC DAC f/2 DACOS[3] (0x0A) CLKM[8] (0x06) PLL BLOCK BCLKSEL[4:2] (0x06) GPIO1 /CSb IMCLK/ 256 CLKIOEN[0] (0x06) f/N … IMCLK/ N Digital Audio Interface FS BCLK GPIO1PLL[5:4] (0x08) GPIO1SEL[2:0] (0x08) Figure 21: PLL and Clock Select Circuit The NAU8812 has two basic clock modes that support the ADC and DAC data converters. It can accept external clocks in the slave mode, or in the master mode, it can generate the required clocks from an external reference frequency using an internal PLL (Phase Locked Loop). The internal PLL is a fractional type scaling PLL, and therefore, a very wide range of external reference frequencies can be used to create accurate audio sample rates. Separate from this ADC and DAC clock subsystem, audio data are clocked to and from the NAU8812 by means of the control logic described in the Digital Audio Interfaces section. The Frame Sync (FS) and Bit Clock (BCLK) pins in the Digital Audio Interface manage the audio bit rate and audio sample rate for this data flow. It is important to understand that the Digital Audio Interface does not determine the sampling rate for the ADC and DAC data converters, and instead, this rate is derived exclusively from the Internal Master Clock (IMCLK). It is therefore a requirement that the Digital Audio Interface and data converters be operated synchronously, and that the FS, BCLK, and IMCLK signals are all derived from a common reference frequency. If these three clocks signals are not synchronous, audio quality will be reduced. The IMCLK is always exactly 256 times the sampling rate of the data converters. IMCLK is output from the Master Clock Prescaler. The prescaler reduces by an integer division factor the input frequency input clock. The source of this input frequency clock is either the external MCLK pin, or the output from the internal PLL Block. NAU8812 Datasheet Rev2.9 Page 42 of 110 Jun, 2018 Addr D8 D7 D6 D5 D4 0x01 DCBUFEN 0 AUXEN PLLEN MICBIASEN 0x06 CLKM 0x07 0 0 0 0 0 0x24 0 0 0 0 PLLMCLK 0x25 0 0 0 MCLKSEL[2:0] D3 D2 D1 ABIASEN IOBUFEN BCLKSEL[2:0] Default REFIMP 0 SMPLR[2:0] D0 CLKIOEN 0x140 SCLKEN 0x000 PLLN[3:0] PLLK[23:18] 0x008 0x00C 0x26 PLLK[17:9] 0x093 0x27 PLLK[8:0] 0x0E9 Table 23: Registers associated with PLL In Master Mode, the IMCLK signal is used to generate FS and BCLK signals that are driven onto the FS and BCLK pins and input to the Digital Audio Interface. FS is always IMCLK/256 and the duty cycle of FS is automatically adjusted to be correct for the mode selected in the Digital Audio Interface. The frequency of BCLK may optionally be divided to optimize the bit clock rate for the application scenario. In Slave Mode, there is no connection between IMCLK and the FS and BCLK pins. In this mode, FS and BLCK are strictly input pins, and it is the responsibility of the system designer to insure that FS, BCLK, and IMCLK are synchronous and scaled appropriately for the application. 11.8.1. Phase Locked Loop (PLL) General description The PLL may be optionally used to multiply an external input clock reference frequency by a high resolution fractional number. To enable the use of the widest possible range of external reference clocks, the PLL block includes an optional divide-by-two prescaler for the input clock, a fixed divide-by-four scaler on the PLL output, and an additional programmable integer divider that is the Master Clock Prescaler. The high resolution fraction for the PLL is the ratio of the desired PLL oscillator frequency (f2), and the reference frequency at the PLL input (f1). This can be represented as R = f2/f1, with R in the form of a decimal number: xy.abcdefgh. To program the NAU8812, this value is separated into an integer portion (“xy”), and a fractional portion, “abcdefgh”. The fractional portion of the multiplier is a value that when represented as a 24-bit binary number (stored in three 9-bit registers on the NAU8812), very closely matches the exact desired multiplier factor. To keep the PLL within its optimal operating range, the integer portion of the decimal number (“xy”), must be any of the following decimal values: 6, 7, 8, 9, 10, 11, or 12. The input and output dividers outside of the PLL are often helpful to scale frequencies as needed to keep the “xy” value within the required range. Also, the optimum PLL oscillator frequency is in the range between 90MHz and 100MHz, and thus, it is best to keep f2 within this range. NAU8812 Datasheet Rev2.9 Page 43 of 110 Jun, 2018 In summary, for any given design, choose: Equations Description IMCLK = (256) * (desired codec sample rate) IMCLK = desired Master Clock f2 = (4 * P * IMCLK) where P is the Master Clock divider integer value; optimal f2: 90MHz< f2 300 uA 161k/595k < 100 uA 40uA ABIASEN[3] 600uA 0x01 MICBIASEN[4] 500 uA PLLEN[5] 2.5mA Clocks Applied DCBUFEN[8] 80uA ADCEN[0] x64 - ADCOS= 0 => 2.0mA x128 - ADCOS= 1 => 3.0mA PGAEN[2] 0x02 400uA BSTEN[4] 200 uA DACEN[0] X64 (DACOS=0)=>1.6mA x128(DACOS=1)=>1.7mA SPKMXEN[2] 400uA MOUTMXEN[3] 200uA 0x03 NSPKEN[6] 1mA from VDDSPK + 100uA (VDDA = 5V mode) PSPKEN[5] 1mA from VDDSPK + 100uA (VDDA = 5V mode) MOUTEN[7] 100uA Table 33: VDDA 3.3V Supply Current NAU8812 Datasheet Rev2.9 Page 61 of 110 Jun, 2018 12. REGISTER DESCRIPTION Register Address Register Bits Register Names DEC HEX 0 0 Default D8 D7 D6 D5 D4 Software Reset D3 D2 D1 D0 RESET (SOFTWARE) 000 POWER MANAGEMENT 1 01 Power Management 1 DCBUFEN 0 AUXEN PLLEN MICBIASEN ABIASEN IOBUFEN 2 02 Power Management 2 0 0 0 0 BSTEN 0 PGAEN 3 03 Power Management 3 0 MOUTEN NSPKEN PSPKEN 0 REFIMP MOUTMXEN SPKMXEN 000 0 ADCEN 000 0 DACEN 000 AUDIO CONTROL 4 04 Audio Interface 5 05 Companding BCLKP FSP 0 0 WLEN[1:0] 6 06 Clock Control 1 CLKM 7 07 Clock Control 2 0 0 0 8 08 GPIO CTRL 0 0 0 GPIOPLL[1:0] GPIOPL 10 0A DAC CTRL 0 0 DACMT DEEMP[1:0] DACOS 11 0B DAC Volume 0 14 0E ADC CTRL 15 0F ADC Volume 0 AIFMT[1:0] 0 DACPHS DACCM[1:0] MCLKSEL[2:0] ADCPHS ADCCM[1:0] BCLKSEL[2:0] 0 0 0 SMPLR[2:0] 0 050 ADDAP 000 CLKIOEN 140 SCLKEN 000 GPIOSEL[2:0] AUTOMT 0 000 DACPL DACGAIN HPFEN HPFAM HPF[2:0] 0FF ADCOS 0 000 0 0 ADCPL ADCGAIN 100 0FF DIGITAL TO ANALOG (DAC) LIMITER 24 18 DAC Limiter 1 DACLIMEN 25 19 DAC Limiter 2 0 DACLIMDCY[3:0] 0 DACLIMTHL[2:0] DACLIMATK[3:0] 032 DACLIMBST[3:0] 000 NOTCH FILTER 27 1B Notch Filter High NFCU NFCEN NFCA0[13:7] 000 28 1C Notch Filter Low NFCU 0 NFCA0[6:0] 000 29 1D Notch Filter High NFCU 0 NFCA1[13:7] 000 30 1E Notch Filter Low NFCU 0 NFCA1[6:0] 000 ALC CONTROL 32 20 ALC CTRL 1 ALCEN 33 21 ALC CTRL 2 ALCZC ALCHT[3:0] ALCSL[3:0] 00B 34 22 ALC CTRL 3 ALCM ALCDCY[3:0] ALCATK[3:0] 032 35 23 Noise Gate 0 0 0 0 0 ALCMXGAIN[2:0] 0 0 ALCMNGAIN[2:0] ALCNEN 038 ALCNTH[2:0] 000 PLL CONTROL 36 24 PLL N CTRL 0 0 0 37 25 PLL K 1 0 0 0 38 26 PLL K 2 39 27 PLL K 3 0 PLLMCLK PLLN[3:0] 008 PLLK[23:18] 00C PLLK[17:9] 093 PLLK[8:0] 0E9 INPUT, OUTPUT & MIXER CONTROL 40 28 Attenuation CTRL 44 2C Input CTRL 0 0 MICBIASV NAU8812 Datasheet Rev2.9 0 0 0 0 MOUTATT SPKATT 0 000 0 0 0 AUXM AUXPGA NMICPGA PMICPGA 003 Page 62 of 110 Jun, 2018 Register Address Register Bits Register Names DEC HEX Default D8 D7 D6 PGAMT 45 2D PGA Gain 0 PGAZC 47 2F ADC Boost PGABST 0 49 31 Output CTRL 0 0 50 32 Mixer CTRL 0 54 36 SPKOUT Volume 0 56 38 MONO Mixer Control 0 0 MOUTMT D5 D4 D3 D2 D1 D0 PGAGAIN[5:0] PMICBSTGAIN 0 0 0 0 0 0 AUXSPK 0 SPKZC SPKMT 010 AUXBSTGAIN 100 MOUTBST SPKBST TSEN AOUTIMP 002 0 0 BYPSPK DACSPK 001 SPKGAIN[5:0] 0 0 0 AUXMOUT 039 BYPMOUT DACMOUT 001 LOW POWER CONTROL 58 3A Power Management 4 LPIPBST LPADC LPSPKD LPDAC MICBIASM TRIMREG IBADJ 000 PCM TIME SLOT & ADCOUT IMPEDANCE OPTION CONTROL 59 3B Time Slot 60 3C ADCOUT Drive TSLOT[8:0] PCMTSEN TRI PCM8BIT PUDOEN 000 PUDPE PUDPS LOUTR PCMB TSLOT[9:8] 020 REGISTER ID 62 3E Silicon Revision 0 1 1 1 0 1 1 1 0 0EE 63 3F 2-Wire ID 0 0 0 0 1 1 0 1 0 01A 64 40 Additional ID 0 1 1 0 0 1 0 1 0 0CA 65 41 Reserved 1 0 0 1 0 0 1 0 0 124 69 45 High Voltage CTRL 0 0 0 0 MOUTMT 0 HVOPU 0 HVOP 001 70 46 ALC Enhancements 1 0 71 47 ALC Enhancements 2 PKLIMEN 73 49 Additional IF CTRL SPIEN 0 ALCPKSEL ALCNGSEL FSERRVAL[1:0] LPSPKA 0 000 000 NFDLY 0 PLLLOCKP DACOS256 000 MANVREFH MANVREFM MANVREFL 000 4B Power/Tie-off CTRL 76 4C ALC P2P Detector P2PDET (READ ONLY) 000 77 4D ALC Peak Detector PDET (READ ONLY) 000 78 4E Control and Status 0 0 AMTCTRL HVDET NSGATE AMUTE DMUTE 0 FTDEC 000 79 4F Output tie-off CTRL MANOUTEN SBUFH SBUFL SNSPK SPSPK SMOUT 0 0 0 000 Page 63 of 110 0 DACINMT 75 NAU8812 Datasheet Rev2.9 0 FSERFLSH FSERRENA ALCGAINL (READ ONLY) 0 Jun, 2018 12.1. SOFTWARE RESET Addr D8 D7 D6 D5 0x00 D4 D3 D2 D1 D0 Default 0x000 RESET (SOFTWARE) This is device Reset register. Performing a write instruction to this register with any data will reset all the bits in the register map to default. 12.2. POWER MANAGEMENT REGISTERS 12.2.1. Power Management 1 Addr D8 D7 D6 D5 D4 0x01 DCBUFEN 0 AUXEN PLLEN D3 D2 D1 MICBIASEN ABIASEN IOBUFEN D0 Default REFIMP[1:0] 0x000 Name Buffer for DC level shifting Enable AUX input buffer enable PLL enable Microphone Bias Enable Analogue amplifier bias control Unused input/output tie off buffer enable Bit DCBUFEN[8] AUXEN[6] PLLEN[5] MICBIASEN[4] ABIASEN[3] IOBUFEN[2] 0 Disable Disable Disable Disable Disable Disable 1 Enable (required for 1.5x gain) Enable Enable Enable Enable Enable The DCBUFEN[8] address (0x01) is a dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. There are three different reference impedance selections to choose from as follows: VREF REFERENCE IMPEDANCE SELECTION (“R” refers to “R” as shown in Figure3) REFIMP[1] REFIMP[0] Mode NAU8812 Datasheet Rev2.9 0 0 Disable 0 1 R = 80 kΩ 1 0 R = 300 kΩ 1 1 R = 3 kΩ Page 64 of 110 Jun, 2018 12.2.2. Power Management 2 Addr D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x02 0 0 0 0 BSTEN 0 PGAEN 0 ADCEN 0x000 Name Input Boost Enable MIC(+/-) PGA Enable ADC Enable Bit BSTEN[4] PGAEN[2] ADCEN[0] 0 Stage Disable Disable Disable 1 Stage Enable Enable Enable 12.2.3. Power Management 3 Addr D8 0x03 0 D7 D6 D5 D4 MOUTEN NSPKEN PSPKEN D3 0 D2 D1 D0 Default 0 DACEN 0x000 MOUTMXEN SPKMXEN Name MOUT Enable SPKOUTEnable SPKOUT+ Enable MONO Mixer Enable Speaker Mixer Enable DAC Enable Bit MOUTEN[7] NSPKEN[6] PSPKEN[5] MOUTMXEN[3] SPKMXEN[2] DACEN[0] 0 Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable 12.3. AUDIO CONTROL REGISTERS 12.3.1. Audio Interface Control Addr D8 D7 0x04 BCLKP FSP D6 D5 D4 WLEN[1:0] D3 AIFMT[1:0] D2 D1 DACPHS ADCPHS D0 Default 0 0x050 The following table explains the PCM control register bits. Name BCLK Polarity Frame Clock Polarity DAC Data ‘right’ or ‘left’ phases of FRAME clock ADC Data ‘right’ or ‘left’ phases of FRAME clock Bit BCLKP[8] FSP[7] DACPHS[2] ADCPHS[1] 0 Normal Normal DAC data appear in ‘left’ phase of FRAME ADC data appear in ‘left’ phase of FRAME 1 Inverted Inverted DAC data appears in ‘right’ phase of FRAME ADC data appears in ‘right’ phase of FRAME There are three different CODEC modes to choose from as follows: NAU8812 Datasheet Rev2.9 Page 65 of 110 Jun, 2018 Word Length Selection Audio Data Format Select WLEN[6] WLEN[5] Bits AIFMT[4] AIFMT[3] Format 0 0 16 0 0 Right Justified 0 1 20 0 1 Left Justified 1 0 24 1 0 IS 1 1 32 1 1 PCM A 2 12.3.2. Audio Interface Companding Control Addr D8 D7 D6 D5 0x05 0 0 0 CMB8 D4 D3 DACCM[1:0] D2 D1 ADCCM[1:0] D0 Default ADDAP 0x000 The NAU8812 provides a Digital Loopback ADDAP[0] address (0x05) bit. Setting ADDAP[0] bit to HIGH enables the loopback so that the ADC data can be fed directly into the DAC input. Companding Mode 8-bit word enable DAC Companding Selection ADC Companding Select CMB8[5] Mode DACCM[4] DACCM[3] Mode ADCCM[2] ADCCM[1] Mode 0 normal operation 0 0 Disabled 0 0 Disabled 1 8-bit operation 0 1 Reserved 0 1 Reserved 1 0 µ-Law 1 0 µ-Law 1 1 A-Law 1 1 A-Law DAC audio data input option to route directly to ADC data stream ADDAP[0] 0 1 NAU8812 Datasheet Rev2.9 Mode Normal Operation ADC output data stream routed to DAC input data path Page 66 of 110 Jun, 2018 12.3.3. Clock Control Register Addr D8 0x06 CLKM D7 D6 D5 D4 D3 MCLKSEL[2:0] D2 BCLKSEL[2:0] Master Clock Selection MCLKSEL [7] MCLKSEL [6] MCLKSEL [5] 0 0 0 0 0 1 0 1 0 0 1 1 0 D1 D0 Default 0 CLKIOEN 0x140 Bit Clock Select BCLKSEL [4] BCLKSEL [3] BCLKSEL [2] 0 0 0 0 0 1 ÷2 0 1 0 ÷1 (BCLK=MCLK) ÷2 (BCLK=MCLK/2) ÷4 1 ÷3 0 1 1 ÷8 0 ÷4 1 0 0 ÷ 16 1 0 1 ÷ 32 Mode ÷1 ÷ 1.5 Mode 1 0 1 ÷6 1 1 0 ÷8 1 1 0 Reserved 1 1 1 ÷ 12 1 1 1 Reserved Name Source of Internal Clock master clock source selection control Enables chip master mode to drive FS and BCLK outputs Bit CLKM[8] CLKIOEN[0] 0 MCLK (PLL Bypassed) MCLK pin used as master clock 1 MCLK (PLL Output) Internal PLL oscillator output used as master clock Slave Mode (FS and BCLK are inputs) Master Mode (FS and BCLK are driven as outputs by internally generated clocks) NAU8812 Datasheet Rev2.9 Page 67 of 110 Jun, 2018 12.3.4. Audio Sample Rate Control Register Addr D8 D7 D6 D5 D4 0x07 0 0 0 0 0 D3 D2 SMPLR[2:0] D1 D0 Default SCLKEN 0x000 The Audio sample rate configures the coefficients for the internal digital filters Sample Rate Selection SMPLR[3] SMPLR[2] SMPLR[1] Mode (Hz) 0 0 0 48 k 0 0 1 32 k 0 1 0 24 k 0 1 1 16 k 1 0 0 12 k 1 0 1 8k 1 1 0 Reserved 1 1 1 Reserved NAU8812 provides a slow clock to be used for both the jack insert detect debounce circuit and the zero cross timeout. Bit 0 1 NAU8812 Datasheet Rev2.9 Slow Clock Enable SCLKEN[0] MCLK 21 PLL Output (Period 2 Page 68 of 110 * MCLK) Jun, 2018 12.3.5. GPIO Control Register Addr D8 D7 D6 0x08 0 0 0 D5 D4 GPIOPLL[4:5] D3 D2 D1 GPIOPL D0 Default 0x000 GPIOSEL[2:0] General Purpose I/O Selection GPIOSEL [2] GPIOSEL [1] GPIOSEL [0] 0 0 0 CSb Input 0 0 1 Jack Insert Detect 0 1 0 Temperature OK 0 1 1 AMUTE Active 1 0 0 PLL CLK Output 1 0 1 PLL Lock 1 1 0 1 1 1 1 0 Mode (Hz) PLL Output Clock Divider GPIO Polarity GPIOPLL[5] GPIOPLL[4] Mode Bit GPIOPL[3] 0 0 ÷1 0 Normal 0 1 ÷2 1 Inverted 1 0 ÷3 1 1 ÷4 12.3.6. DAC Control Register Addr D8 D7 D6 0x0A 0 0 DACMT D5 D4 DEEMP[1:0] D3 D2 D1 D0 Default DACOS AUTOMT 0 DACPL 0x000 Name Soft Mute Enable Over Sample Rate Auto Mute enable Polarity Invert Bit DACMT[6] DACOS[3] AUTOMT[2] DACPL[0] 0 Disable 64x (Lowest power) Disable Normal 1 Enable 128x (best SNR) Enable DAC Output Inverted NAU8812 Datasheet Rev2.9 Page 69 of 110 Jun, 2018 De-emphasis DEEMP[5] DEEMP[4] Mode 0 0 No de-emphasis 0 1 32kHz sample rate 1 0 44.1kHz sample rate 1 1 48kHz sample rate 12.3.7. DAC Gain Control Register Addr D8 0x0B 0 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x0FF DACGAIN DAC Gain DACGAIN[7:0] Mode (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Digital Mute -127.0 0 0 0 0 0 0 1 0 -126.5 0 0 0 0 0 0 1 1 -126.0 DAC Gain Range -127dB to 0dB @ 0.5 increments 1 1 1 1 1 1 0 0 -1.5 1 1 1 1 1 1 0 1 -1.0 1 1 1 1 1 1 1 0 -0.5 1 1 1 1 1 1 1 1 0.0 12.3.8. ADC Control Register Addr D8 D7 0x0E HPFEN HPFAM D6 D5 D4 HPF[2:0] D3 D2 D1 D0 Default ADCOS 0 0 ADCPL 0x100 Name High Pass Filter Enable Audio or Application Mode Over Sample Rate ADC Polarity Bit HPFEN[8] HPFAM[7] ADCOS[3] ADCPL[0] 0 Disable Audio (1 order, fc ~ 3.7 Hz) 64x (Lowest power) Normal 128x (best SNR) Inverted 1 Enable st nd Application (2 NAU8812 Datasheet Rev2.9 order, fc = HPF) Page 70 of 110 Jun, 2018 High Pass Filter fs ( kHz) SMPLR=101 SMPLR=100 SMPLR=011 SMPLR=010 SMPLR=001 SMPLR=000 HPF[6] HPF[5] HPF[4] B2 B1 B0 8 11.025 12 16 22.05 24 32 44.1 48 0 0 0 82 113 122 82 113 122 82 113 122 0 0 1 102 141 153 102 141 153 102 141 153 0 1 0 131 180 156 131 180 156 131 180 156 0 1 1 163 225 245 163 225 245 163 225 245 1 0 0 204 281 306 204 281 306 204 281 306 1 0 1 261 360 392 261 360 392 261 360 392 1 1 0 327 450 490 327 450 490 327 450 490 1 1 1 408 563 612 408 563 612 408 563 612 12.3.9. ADC Gain Control Register Addr D8 0x0F 0 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x0FF ADCGAIN ADC Gain ADCGAIN[7:0] Mode (dB) B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 Unused 0 0 0 0 0 0 0 1 -127.0 0 0 0 0 0 0 1 0 -126.5 0 0 0 0 0 0 1 1 -126.0 ADC Gain Range -127dB to 0dB @ 0.5 increments 1 1 1 1 1 1 0 0 -1.5 1 1 1 1 1 1 0 1 -1.0 1 1 1 1 1 1 1 0 -0.5 1 1 1 1 1 1 1 1 0.0 NAU8812 Datasheet Rev2.9 Page 71 of 110 Jun, 2018 12.4. DIGITAL TO ANALOG CONVERTER (DAC) LIMITER REGISTERS Addr D8 0x18 DACLIMEN D7 0x19 0 D6 D5 D4 D3 DACLIMDCY[3:0] 0 DACLIMTHL[2:0] DAC Limiter Decay time (per 6dB gain change) for 44.1 kHz sampling. Note that these will scale with sample rate D2 D1 D0 Default DACLIMATK[3:0] 0x032 DACLIMBST[3:0] 0x000 DAC Limiter Attack time (per 6dB gain change) for 44.1 kHz sampling. Note that these will scale with sample rate DACLIMDCY[3:0] DACLIMATK[3:0] B3 B2 B1 B0 Decay Time B3 B2 B1 B0 Attack Time 0 0 0 0 544.0 us 0 0 0 0 68 us 0 0 0 1 1.1 ms 0 0 0 1 136 us 0 0 1 0 2.2 ms 0 0 1 0 272 us 0 0 1 1 4.4 ms 0 0 1 1 544 us 0 1 0 0 8.7 ms 0 1 0 0 1.1 ms 0 1 0 1 17.4 ms 0 1 0 1 2.2 ms 0 1 1 0 35.0 ms 0 1 1 0 4.4 ms 0 1 1 1 69.6 ms 0 1 1 1 8.7 ms 1 0 0 0 139.0 ms 1 0 0 0 17.4 ms 1 0 0 1 278.5 ms 1 0 0 1 35 ms 1 0 1 0 557.0 ms 1 0 1 0 69.6 ms 1 0 1 1 1 0 1 1 To 1 1 To 1.1 s 1 1 NAU8812 Datasheet Rev2.9 1 Page 72 of 110 1 139 ms 1 1 Jun, 2018 DAC Limiter volume Boost (can be used as a stand alone volume Boost when DACLIMEN=0) DACLIMBST[3:0] Boost (dB) B3 B2 B1 B0 DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) DACLIMTHL[3:0] B2 B1 B0 Threshold (dB) 0 0 0 -1 0 0 0 0 0 0 0 1 -2 0 0 0 1 +1 0 1 0 -3 0 0 1 0 +2 0 1 1 -4 0 0 1 1 +3 1 0 0 -5 0 1 0 0 +4 1 0 1 0 1 0 1 +5 0 1 1 0 +6 To 1 -6 1 1 DAC Digital Limiter 0 1 1 1 +7 1 0 0 0 +8 1 0 0 1 +9 1 0 1 0 +10 Bit DACLIMEN[8] 1 0 1 1 +11 0 Disabled 1 1 0 0 +12 1 Enabled 1 1 0 1 1 1 1 1 To Reserved 12.5. NOTCH FILTER REGISTERS Addr D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 0x1B NFCU NFCEN NFCA0[13:7] 0x000 0x1C NFCU 0 NFCA0[6:0] 0x000 0x1D NFCU 0 NFCA1[13:7] 0x000 0x1E NFCU 0 NFCA1[6:0] 0x000 The Notch Filter is enabled by setting NFCEN[7] address (0x1B) bit to HIGH. The coefficients, A0 and A1, should be converted to 2’s complement numbers to determine the register values. A0 and A1 are represented by the register bits NFCA0[13:0] and NFCA1[13:0]. Since there are four register of coefficients, a Notch Filter Update bit is provided so that the coefficients can be updated simultaneously. NFCU[8] is provided in all registers of the Notch Filter coefficients but only one bit needs to be toggled for LOW - HIGH - LOW for an update. If any of the NFCU[8] bits are left HIGH then the Notch Filter coefficients will continuously update. An example of how to calculate is provided in the Notch Filter section. NAU8812 Datasheet Rev2.9 Page 73 of 110 Jun, 2018 Name A0 A1 Coefficient  2πfb 1 − tan  2fs  2πfb 1 + tan  2fs       Notation Register Value (DEC) 13  2πf − (1 + A0 ) x cos c  fs     fc = center frequency (Hz) fb = -3dB bandwidth (Hz) fs = sample frequency (Hz) NFCA0 = -A0 x 2 12 NFCA1 = -A1 x 2 (then convert to 2’s complement) 12.6. AUTOMATIC LEVEL CONTROL REGISTER 12.6.1. ALC1 REGISTER Addr D8 D7 D6 0x20 ALCEN 0 0 D5 D4 D3 ALCMXGAIN[2:0] B2 B1 B0 0 0 0 0 0 1 0 1 0 D1 D0 ALCMNGAIN[2:0] Maximum Gain ALCMXGAIN[2:0] D2 0x038 Minimum Gain Mode ALCMNGAIN[2:0] Mode B2 B1 B0 -6.75dB 0 0 0 -12dB -0.75dB 0 0 1 -6dB 0 +5.25dB 0 1 0 0dB 1 1 +11.25dB 0 1 1 +6dB 1 0 0 +17.25dB 1 0 0 +12dB 1 0 1 +23.25dB 1 0 1 +18dB 1 1 0 +29.25dB 1 1 0 +24dB 1 1 1 +35.25dB 1 1 1 +30dB Name ALC Enable Bit ALCEN[8] 0 Disabled (PGA gain set by PGAGAIN register bits) 1 Enabled NAU8812 Datasheet Rev2.9 Default (ALC controls PGA gain) Page 74 of 110 Jun, 2018 12.6.2. ALC2 REGISTER Addr D8 0x21 ALCZC D7 D6 D5 D4 D3 D2 ALCHT[3:0] ALC HOLD TIME before gain is increased. ALCHT[3:0] D1 D0 Default 0x00B ALCSL[3:0] ALC TARGET – sets signal level at ADC input ALCSL[3:0] B7 B6 B5 B4 ALC Hold Time (sec) B3 B2 B1 B0 ALC Target Level (dB) 0 0 0 0 0 0 0 0 0 -28.5 fs 0 0 0 1 2 ms 0 0 0 1 -27 fs 0 0 1 0 4 ms 0 0 1 0 25.5 fs ALC Target Level Range -28.5dB to -6dB @ 1.5dB increments Time Doubles with every increment 1 0 0 0 256 ms 1 0 1 1 -12 fs 1 0 0 1 512 ms 1 1 0 0 -10.5 fs 1 0 1 0 1 1 0 1 -9 fs 1 1 1 1 1s To 1 1 1 0 -7.5 fs 1 1 1 1 -6 fs Name ALC Zero Crossing Detect Bit ALCZC[8] 0 Disabled 1 Enabled It is recommended that zero crossing should not be used in conjunction with the ALC or Limiter functions NAU8812 Datasheet Rev2.9 Page 75 of 110 Jun, 2018 12.6.3. ALC3 REGISTER Addr D8 0x22 ALCM D7 D6 D5 D4 D3 D2 ALCDCY[3:0] D1 D0 Default 0x032 ALCATK[3:0] ALC DECAY TIME ALCDCY[3:0] ALCM = 0 (Normal Mode) ALCM = 1 (Limiter Mode) B3 B2 B1 B0 Per Step Per 6dB 90% of Range Per Step Per 6dB 90% of Range 0 0 0 0 500 us 4 ms 28.78 ms 125 us 1 ms 7.2 ms 0 0 0 1 1 ms 8 ms 57.56 ms 250 us 2 ms 14.4 ms 0 0 1 0 2 ms 16 ms 115 ms 500 us 4 ms 28.8 ms Time doubles with every increment 1 0 0 0 128 ms 1s 7.37 s 32 ms 256 ms 1.8 s 1 0 0 1 256 ms 2s 14.7 s 64 ms 512 ms 3.7 s 1 0 1 0 512 ms 4s 29.5 s 128 ms 1s 7.37 s To 1 1 1 1 ALC ATTACK TIME ALCATK[3:0] ALCM = 0 (Normal Mode) ALCM = 1 (Limiter Mode) B3 B2 B1 B0 Per Step Per 6dB 90% of Range Per Step Per 6dB 90% of Range 0 0 0 0 125 us 1 ms 7.2 ms 31 us 248 us 1.8 ms 0 0 0 1 250 us 2 ms 14.4 ms 62 us 496 us 3.6 ms 0 0 1 0 500 us 4 ms 28.85 ms 124 us 992 us 7.15 ms Time doubles with every increment 1 0 0 0 26.5 ms 256 ms 1.53 s 7.9 ms 63.2 ms 455.8 ms 1 0 0 1 53 ms 512 ms 3.06 s 15.87 ms 127 ms 916 ms 1 0 1 0 128 ms 1s 7.89 s 31.7ms 254 ms 1.83 s To 1 1 1 1 NAU8812 Datasheet Rev2.9 Page 76 of 110 Jun, 2018 12.7. NOISE GAIN CONTROL REGISTER Addr D8 D7 D6 D5 D4 D3 0x23 0 0 0 0 0 ALCNEN Noise Gate Enable Bit ALCNEN[3] 0 Disabled 1 Enabled D2 D1 ALCNTH[2:0] D0 Default 0x000 Noise Gate Threshold ALCNTH[2:0] Mode NAU8812 Datasheet Rev2.9 B2 B1 B0 0 0 0 -39 dB 0 0 1 -45 dB 0 1 0 -51 dB 0 1 1 -57 dB 1 0 0 -63 dB 1 0 1 -69 dB 1 1 0 -75 dB 1 1 1 -81 dB Page 77 of 110 Jun, 2018 12.8. PHASE LOCK LOOP (PLL) REGISTERS 12.8.1. PLL Control Registers Addr D8 D7 D6 D5 D4 0x24 0 0 0 0 PLLMCLK D3 D2 D1 D0 0x008 PLLN[3:0] PLL Integer Default PLL Clock PLLN[3:0] B3 B2 B1 B0 0 0 0 1 Bit Frequency Ratio PLLMCLK[4] 0 MCLK not divided 1 Divide MCLK by 2 before input PLL Not Valid To 0 1 0 0 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 1 1 1 1 Not Valid 12.8.2. Phase Lock Loop Control (PLL) Registers Addr D8 D7 D6 0x25 0 0 0 D5 D4 D3 D2 PLLK[23:18] D1 D0 Default 0x00C 0x26 PLLK[17:9] 0x093 0x27 PLLK[8:0] 0x0E9 Fractional (K) part of PLLK1 – PLLK3 input/output frequency ratio NAU8812 Datasheet Rev2.9 Page 78 of 110 Jun, 2018 12.9. INPUT, OUTPUT, AND MIXERS CONTROL REGISTER 12.9.1. Attenuation Control Register Addr D8 D7 D6 D5 D4 D3 0x28 0 0 0 0 0 0 D2 D1 MOUTATT SPKATT D0 Default 0 0x000 D0 Default Attenuation Control Attenuation control for bypass path (output of input boost stage) to speaker mixer and MONO mixer input Name Bit MOUTATT[2] SPKATT[1] 0 0 dB 0 dB 1 -10 dB -10 dB 12.9.2. Input Signal Control Register Addr 0x2C D8 D7 D6 D5 D4 D3 0 0 0 AUXM MICBIASV D2 D1 AUXPGA NMICPGA PMICPGA 0x003 Auxiliary Input mode AUX amplifier output to input PGA signal source MICN to input PGA negative terminal Input PGA amplifier positive terminal to MIC+ or VREF Bit AUXM[3] AUXPGA[2] NMICPGA[1] PMICPGA[0] 0 Inverting Buffer AUX not connected to input PGA MICN not connected to input PGA Input PGA Positive terminal to VREF 1 Mixer (Internal Resistor bypassed) AUX to input PGA Negative terminal MICN to input PGA Negative terminal. Input PGA Positive terminal to MICP through variable resistor Microphone Bias Voltage Control MICBIASV[8:7] Address (0x2C) MICBIASM[4] = 0 Address (0x28) MICBIASM[4] = 1 Address (0x28) 0 0 0.9* VDDA 0.85* VDDA 0 1 0.65* VDDA 0.60* VDDA 1 0 0.75* VDDA 0.70* VDDA 1 1 0.50* VDDA 0.50* VDDA NAU8812 Datasheet Rev2.9 Page 79 of 110 Jun, 2018 12.9.3. PGA Gain Control Register Addr D8 D7 D6 0x2D 0 PGAZC PGAMT D5 D4 D3 D2 PGAGAIN[5:0] D1 D0 Default 0x010 Programmable Gain Amplifier Gain PGAGAIN[5:0] B5 B4 B3 B2 B1 B0 Gain 0 0 0 0 0 0 -12.00 dB 0 0 0 0 0 1 -11.25 dB 0 0 0 0 1 0 -10.50 dB ::: ::: ::: ::: ::: ::: ::: 0 0 1 1 1 1 -0.75 dB 0 1 0 0 0 0 0 dB 0 1 0 0 0 1 +0.75 dB PGA Gain Range -12dB to +35.25dB @ 0.75 increment ::: ::: ::: ::: ::: ::: ::: 1 1 1 1 0 1 33.75 1 1 1 1 1 0 34.50 1 1 1 1 1 1 35.25 PGA Zero Cross Enable Mute Control for PGA Bit PGAZC[7] PGAMT[6] 0 Update gain when gain register changes Normal Mode 1 Update gain on 1st zero cross after gain register write PGA Muted NAU8812 Datasheet Rev2.9 Page 80 of 110 Jun, 2018 12.9.4. ADC Boost Control Registers Addr D8 D7 0x2F PGABST 0 D6 D5 D4 D3 PMICBSTGAIN MIC+ pin to the input Boost Stage (NB, when using this path set PMICPGA=0): PMICBSTGAIN[2:0] B1 B0 0 0 0 0 0 1 Path Disconnected -12 0 1 0 0 1 1 0 1 D1 D0 Default 0x100 AUXBSTGAIN Auxiliary to Input Boost Stage AUXBSTGAIN[2:0] Gain (dB) B2 D2 0 Gain (dB) B2 B1 B0 0 0 0 0 0 1 Path Disconnected -12 -9 0 1 0 -9 1 -6 0 1 1 -6 0 -3 1 0 0 -3 0 1 0 1 0 1 0 1 1 0 +3 1 1 0 +3 1 1 1 +6 1 1 1 +6 Name Input Boost Bit PGABST[8] 0 PGA output has +0dB gain through input Boost stage 1 PGA output has +20dB gain through input Boost stage 12.9.5. Output Register Addr D8 D7 D6 D5 D4 0x31 0 0 0 0 0 D3 D2 MOUTBST SPKBST D1 D0 Default TSEN AOUTIMP 0x002 MONO Output Boost Stage Speaker Output Boost Stage Thermal Shutdown Analog Output Resistance Bit MOUTBST[3] SPKBST[2] TSEN[1] AOUTIMP[0] 0 (1.0 x VREF) Gain Boost (1.0 x VREF) Gain Boost Disabled ~1kΩ 1 (1.5 x VREF) Gain Boost (1.5 x VREF) Gain Boost Enabled ~30 kΩ NAU8812 Datasheet Rev2.9 Page 81 of 110 Jun, 2018 12.9.6. Speaker Mixer Control Register Addr D8 D7 D6 D5 D4 D3 D2 0x32 0 0 0 AUXSPK 0 0 0 D1 D0 BYPSPK DACSPK Auxiliary to Speaker Mixer Bypass path (output of Boost stage) to Speaker Mixer DAC to Speaker Mixer Bit AUXSPK[5] BYPSPK[1] DACSPK[0] 0 Disconnected Disconnected Disconnected 1 Connected Connected Connected Default 0x001 12.9.7. Speaker Gain Control Register Addr D8 D7 D6 0x36 0 SPKZC SPKMT D5 D4 D3 D2 D1 SPKGAIN[5:0] D0 Default 0x039 Speaker Gain SPKGAIN[5:0] B5 B4 B3 B2 B1 B0 Gain (dB) 0 0 0 0 0 0 -57.0 0 0 0 0 0 1 -56.0 0 0 0 0 1 0 -55.0 ::: ::: ::: ::: ::: ::: ::: 1 1 1 0 0 0 -1.0 1 1 1 0 0 1 0.0 1 1 1 0 1 0 +1.0 Speaker Gain Range -57 dB to +6 dB @ +1 increment ::: ::: ::: ::: ::: ::: ::: 1 1 1 1 0 1 +4.0 1 1 1 1 1 0 +5.0 1 1 1 1 1 1 +6.0 Speaker Gain Control Zero Cross Speaker Output Bit SPKZC[7] SPKMT[6] 0 Change Gain on Zero Cross ONLY Speaker Enabled 1 Change Gain Immediately Speaker Muted NAU8812 Datasheet Rev2.9 Page 82 of 110 Jun, 2018 12.9.8. MONO Mixer Control Register Addr D8 D7 D6 D5 D4 D3 0x38 0 0 MOUTMXMT 0 0 0 D2 D1 D0 Default AUXMOUT BYPMOUT DACMOUT 0x001 MOUT Mute Auxiliary to MONO Mixer Bypass path (output of Boost Stage) to MONO Mixer DAC to MONO Mixer Bit MOUTMXMT[6] AUXMOUT[2] BYPMOUT[1] DACMOUT[0] 0 Not Muted Disconnected Disconnected Disconnected 1 Muted Connected Connected Connected During mute, the MONO output will output VREF that can be used as a DC reference for a headphone out. 12.9.9. Trimming Register Addr D8 D7 D6 0x3A LPIPBST LPADC LPSPKD B1 D5 D4 D3 LPDAC MICBIASM D2 TRIMREG[3:2] D1 D0 Default 0x000 IBADJ[1:0] Trim Output Regulator (V) Adjust Master Bias of the Analog Portion TRIMREG[3:2] IBADJ[1:0] Default Current Consumption B0 0 0 1.800 0 1 1.610 25% Current Increase from Default 1 0 1.400 14% Current Decrease from Default 1 1 1.218 25% Current Decrease from Default Trim regulator bits can be used only when VDDD 0.546*fs -60 dB Group Delay 21/fs ADC High Pass Filter High Pass Filter Corner Frequency -3dB 3.7 -0.5dB 10.4 -0.1dB 21.6 Hz DAC Filter +/- 0.035dB 0 0.454*fs Passband -6dB 0.5*fs Passband Ripple +/-0.035 Stopband Stopband Attenuation dB 0.546*fs f > 0.546*fs -55 Group Delay dB 29/fs Table 57 Digital Filter Characteristics TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region 3. Note that this delay applies only to the filters and does not include NAU8812 Datasheet Rev2.9 Page 101 of 110 Jun, 2018 Figure 52: DAC Filter Frequency Response Figure 53: ADC Filter Frequency Response Figure 54: DAC Filter Ripple Figure 55: ADC Filter Ripple NAU8812 Datasheet Rev2.9 Page 102 of 110 Jun, 2018 16. TYPICAL APPLICATION C9 4.7uF VREF C8 1uF 28 2 27 3 26 AUX C10 1uF VDDSPK MIC C7 1uF R2 1.2k ohm 1 MIC + R1 1.2k ohm MICBIAS C6 4.7uF NC VDDA VDDA VSSA VSSA 25 5 24 VSSSPK 6 23 VSSSPK 22 SPKOUT + 7 8 NAU8812 MONO AUDIO CODEC SSOP 28-Pin C3 4.7uF 21 20 10 19 11 18 12 17 DACIN 13 16 FS 14 15 VSSD VSS VSS 9 VDDB C2 4.7uF C4 4.7uF 4 VDDB C1 4.7uF VDDSPK SPKOUT - VDDC VDDC VDDSPK MOUT C5 1uF MODE SDIO SCLK VSS ADCOUT CSb/GPIO MCLK BCLK Figure 56: Application Diagram 28-Pin SSOP NAU8812 Datasheet Rev2.9 Page 103 of 110 Jun, 2018 C8 1uF VSS C4 4.7 uF 25 SPKOUT - VDDSPK 26 27 AUX VREF C10 1uF 29 32 NC 30 M IC + MICBIAS C6 4.7uF M IC - R1 1.2 k ohm 31 R2 1.2 k ohm C9 4. 7uF 28 C7 1uF VDDSPK VDDSPK 1 24 2 23 VSSSPK VDDA VDDA VSSA VSSA C11 10nF VDDL 22 SPKOUT+ 21 MOUT 20 NC 6 19 MODE 7 18 SO 8 17 3 NAU8812 MONO AUDIO CODEC QFN32- Pin 4 5 VDDC VDDC VSSSPK C5 1uF 16 200 Ohm SDIO 33PF 33PF 200 Ohm SCLK 14 15 CSb/GP IO 12 13 BCLK MCLK VSSD VSS 11 VSSD FS C3 4.7uF DACIN C2 4.7uF 9 C1 4.7uF ADCOUT VDDB 10 VDDB Figure 57: Application Diagram for 32-Pin QFN Note 1: All non-polar capacitors are assumed to be low ESR type parts, such as with MLC construction or similar. If capacitors are not low ESR, additional 0.1uF and/or 0.01uF capacitors may be necessary in parallel with the bulk 4.7uF capacitors on the supply rails. Note 2: Load resistors to ground on outputs may be helpful in some applications to insure a DC path for the output capacitors to charge/discharge to the desired levels. If the output load is always present and the output load provides a suitable DC path to ground, then the additional load resistors may not be necessary. If needed, such load resistors are typically a high value, but a value dependent upon the application requirements. Note 3: To minimize pops and clicks, large polarized output capacitors should be a low leakage type. Note 4: Depending on the microphone device and PGA gain settings, common mode rejection can be improved by choosing the resistors on each node of the microphone such that the impedance presented to any noise on either microphone wire is equal. Note 5: SO and SDIO add low pass filter to prevent glitch; corner frequency for the low pass filter is 8MHz to 33MHz. NAU8812 Datasheet Rev2.9 Page 104 of 110 Jun, 2018 17. PACKAGE SPECIFICATION 17.1. 28 Pin SSOP D 28 15 DTEAIL A HE E 1 14 b A2 A SEATING PLANE θ Y e b SYMBOL A A1 A2 b c D E HE e L L1 Y θ A1 DIMENSION IN MM MIN. NOM MAX. 2.00 0.05 1.65 0.22 0.09 10.05 5.00 7.40 0.55 0 NAU8812 Datasheet Rev2.9 SEATING PLANE L L1 DETAIL A DIMENSION IN INCH MIN. NOM MAX. 0.079 0.002 1.85 0.065 0.069 0.073 0.015 0.38 0.009 0.010 0.25 0.004 10.20 10.35 0.395 0.401 0.407 5.30 5.60 0.197 0.209 0.220 7.80 8.20 0.291 0.307 0.323 0.0256 0.65 0.95 0.021 0.030 0.037 0.75 0.050 1.25 0.004 0.10 8 0 8 1.75 Page 105 of 110 Jun, 2018 32-Pin QFN 32 25 1 24 8 17 9 16 25 32 24 1 17 8 16 NAU8812 Datasheet Rev2.9 9 Page 106 of 110 Jun, 2018 18. ORDERING INFORMATION Part Number NAU8812RG NAU8812YG 19. Dimension Package 5x5 mm 10.2x7.8 mm SSOP-28 QFN-32 Package Material Green Green NAU8812 _ _ Package Material: G = Pb-free Package Package Type: R = 28-Pin SSOP Package Y = 32-Pin QFN Package NAU8812 Datasheet Rev2.9 Page 107 of 110 Jun, 2018 20. REVISION HISTORY VERSION DATE 1.0 September 2009 PAGE DESCRIPTION Preliminary release Updated Figure numbers 13 - 15 1.1 November 2009 36 Figure 19 updated 38 Figure 20 updated 69 Description of CLKM and CLKIOEN is updated 108 Updated type on the VERSION 3 13 - 15 1.2 December 2009 The word SPKBST was updated with VDDSPK Note Added Electrical Specification table format updated 66 Register 0x05 description updated 67 Register 0x06 description updated 1.3 January 2010 46 - 48 1.4 January 2010 107 Package description updated 1.5 February 2010 22 Figure 7 updated 14 Speaker THD for 2-stage updated 1.6 1.7 March 2010 April 2010 63, 87 Bit-8 of register 0x46 deleted from the document. 63, 87 Default value of register 0x47 updated 4 Block diagram updated 44 Table 24 updated 62 Table 34 updated 63, 86 2.0 2.1 January 2011 October 2013 Control interface description updated Register 0x41 Reserved updated 47 Removed trailing clock cycle from SPI timing diagram 63 Corrected Register 0x38 Register name 79 Improved description of Mic Bias set up 97 Added System Clock Timing Diagram 15 Corrected Digital I/O voltages from DCVDD to DBVDD 93 Corrected 2 wire timing diagram An additional remark of VDDSPK boost mode 13 – 15 2.2 Jan 2014 Modify Figure29 Byte Write Sequence 50 Modify Figure30 2-Wire Read Sequence 2.7 March 2016 37 Add Important Notice 2.8 June 2016 46 Revise f1 equation from * to / NAU8812 Datasheet Rev2.9 Page 108 of 110 Jun, 2018 2.9 June 2018 NAU8812 Datasheet Rev2.9 87 Silicon Revision ID changed 108 Package infromation 30 ALC description 106 Low pass filter added for I2C Page 109 of 110 Jun, 2018 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. NAU8812 Datasheet Rev2.9 Page 110 of 110 Jun, 2018