ISD2360
ISD ChipCorder®
ISD2360 Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of Audio Product Line based system design. Nuvoton
assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Jun 15, 2021
Page 1 of 35
Rev 1.7
ISD2360
TABLE OF CONTENTS
1
GENERAL DESCRIPTION........................................................................................................ 4
2
FEATURES ............................................................................................................................. 4
3
BLOCK DIAGRAM.................................................................................................................. 6
4
PINOUT CONFIGURATION .................................................................................................... 7
5
PIN DESCRIPTION – QFN32 .................................................................................................. 8
6
DEVICE OPERATION ........................................................................................................... 10
6.1
6.2
6.3
6.4
7
AUDIO STORAGE .......................................................................................................... 10
DEVICE CONFIGURATION ............................................................................................. 10
GPIO CONFIGURATION ................................................................................................ 11
OSCILLATOR AND SAMPLE RATES ................................................................................ 11
MEMORY FORMAT............................................................................................................. 12
7.1.1 Voice Prompts ...................................................................................................... 13
7.1.2 Voice Macros ........................................................................................................ 13
7.1.3 User Data ............................................................................................................. 15
7.2 MEMORY CONTENTS PROTECTION ............................................................................... 15
8
SPI INTERFACE .................................................................................................................... 15
9
SIGNAL PATH ...................................................................................................................... 17
10
GPIO VOICE MACRO TRIGGERS ...................................................................................... 18
10.1
ASSIGN PLAYBACK CHANNEL FOR THE GPIO TRIGGER........................................... 18
10.2
VOICE MACRO EXAMPLES ........................................................................................ 18
10.2.1
POI/PU/WAKEUP Voice Macros ..................................................................... 18
10.2.2
Example: Cycle through a sequence of messages. ............................................ 19
10.2.3
Example: Looping short sounds. Interrupt to stop playback. ........................... 20
10.2.4
Example: Uninterruptable Trigger, smooth audio............................................ 21
10.2.5
Example: Continuous Play until re-trigger....................................................... 22
10.2.6
Example: Level Hold Trigger............................................................................ 22
11
CHANNEL SELECTION AND EXECUTION CONTROL ......................................................... 23
11.1
SELECT CHANNEL FOR THE PLYABCK AND MIXING ................................................ 23
11.2
EXECUTION CONTROL............................................................................................... 23
11.2.1
Conditional Branch and Unconditional Jump .................................................. 24
11.2.2
Execution Delay / Pause ................................................................................... 24
12
ELECTRICAL CHARACTERISTICS ....................................................................................... 25
12.1
ABSOLUTE MAXIMUM RATINGS ............................................................................... 25
12.2
OPERATING CONDITIONS .......................................................................................... 25
12.3
AC PARAMETERS ...................................................................................................... 25
12.3.1
Internal Oscillator ............................................................................................. 25
12.3.2
Speaker Outputs ................................................................................................ 26
12.4
DC PARAMETERS ...................................................................................................... 26
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12.5
13
APPLICATION DIAGRAM ................................................................................................. 29
13.1
13.2
14
SPI TIMING ............................................................................................................... 28
SPI MODE APPLICATION ........................................................................................... 29
STANDALONE APPLICATION...................................................................................... 30
PACKAGE SPECIFICATION ............................................................................................... 31
ORDERING INFORMATION........................................................................................................ 33
15
REVISION HISTORY .......................................................................................................... 34
IMPORTANT NOTICE .......................................................................................................... 35
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Rev 1.7
ISD2360
1
GENERAL DESCRIPTION
The ISD2360 is a 3-channel digital ChipCorder® providing single-chip storage and playback of
high quality audio. The device features digital de-compression, comprehensive memory
management, flash storage, integrated audio signal path with up to 3 channel concurrent
playback and Class D speaker driver capable of delivering power of 0.95W. This family utilizes
flash memory to provide non-volatile audio playback with duration up to 64 seconds (based
on 8kHz/4bit ADPCM compression) for a single-chip audio playback solution.
The ISD2360 can be controlled and programmed through an SPI serial interface or operated
stand-alone by triggers applied to the device’s six GPIO pins.
The ISD2360 requires no external clock sources or components except a speaker to deliver
quality audio prompts or sound effects to enhance user interfaces.
In addition, the part can provide non-volatile flash storage in 1Kbyte sectors eliminating the
need for additional serial EEPROM/Flash devices.
ISD2360 provides wide range of sampling frequencies, high SNR performance, low power
consumption, fast programming time and integrated program verification.
2
FEATURES
Duration
o ISD2360 – 64 seconds based on 8kHz/4bit ADPCM in 2Mbit of flash storage (256KB)
Audio Management
o Store pre-recorded audio (Voice Prompts) using high quality digital compression
o Use simple index based command for playback – no address needed.
o Execute pre-programmed macro scripts (Voice Macros) designed to control the
configuration of the device and playback Voice Prompts sequences.
Path and playback Control
o Up to 3 channel audio streaming can be mixed and played back concurrently
o Each channel has independent counter which enables user micro-management on
VM execution
o Mask Jump allows branch execution depending on internal register or external GPIO
pin status
Control
o Serial SPI interface for microprocessor control and programming.
o Stand-alone control where customized Voice Macro scripts are assigned to GPIO
trigger pins.
Sample Rate
o 7 sampling frequencies 4, 5.3, 6.4, 8, 12.8, 16 and 32 kHz are available.
o Each Voice Prompt can have optimal sample rate.
Compression Algorithms
o µ-Law: 6, 7 or 8 bits per sample
o Differential µ-Law: 6, 7 or 8 bits per sample
o PCM: 8, 10 or 12 bits per sample
o Enhanced ADPCM: 2, 3, 4 or 5 bits per sample
o Variable-bit-rate optimized compression. This allows best possible compression
given a metric of SNR and background noise levels.
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ISD2360
Oscillator
o Internal oscillator with internal reference: factory trimmed to ±1% deviation at room
temperature.
Output
o PWM: Class D speaker driver to direct drive an 8Ω speaker or buzzer.
o Delivers:
- 4Ω load: 400mW @3.3V; 1.1W @5V; 1.3W @5.5V.
- 8Ω load: 330mW @3.3V; 850mW @5V; 1W @5.5V.
I/Os
o SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data
o 6 general purpose I/O pins multiplexed with SPI interface.
Flash Storage
o 2Mbit of storage for combined audio/data.
o Fast programming time (20µs/byte)
o Erase sector size 1Kbyte, sector erase time 2ms.
o Integrated memory checksum calculation for fast verification.
o Endurance >100K cycles. Retention > 10 years
Operating Voltage: 2.4-5.5V
Package:
o Green, QFN32
Temperature Options:
o Industrial: -40C to 85C
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ISD2360
3
BLOCK DIAGRAM
SP+
Digital Signal Path
Digital Filters
Digital Mixing
Resampling
Volume Control
PWM
Control
SP-
MOSI/GPIO(0)
SCLK/GPIO(1)
MISO/GPIO(2)
INTB/GPIO(3)
RDY/BSYB/GPIO(4)
GPIO(5)
SPI Interface
GPIO
Interface
Memory management and
Command Interpreter Ch1
De-Compression
Memory management and
Command Interpreter Ch2
De-Compression
Memory management and
Command Interpreter Ch3
De-Compression
Internal Flash
Memory
SSB
VSSDPWM
VSSD
VCCDPWM
Power
Conditioning
VCCD
Flash Memory Controller
Figure 3-1 ISD2360 Block Diagram
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ISD2360
4
PINOUT CONFIGURATION
Figure 4-1 ISD2360 32-Lead QFN Pin Configuration.
Figure 4-2 ISD2360 16-Lead SOP Pin Configuration.
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ISD2360
5
PIN DESCRIPTION – QFN32
Pin #
Pin Name
I/O
Function
1
NC
This pin should be left unconnected.
2
NC
This pin should be left unconnected.
3
MOSI / GPIO0
4
VSSD
Digital Ground.
5
NC
This pin should be left unconnected.
6
NC
This pin should be left unconnected.
7
NC
This pin should be left unconnected.
8
NC
This pin should be left unconnected.
9
NC
This pin should be left unconnected.
10
VCCD_PWM
I
Digital Power for the PWM Driver. It can be from a separate power supply other
than VCCD.
11
SPK+
O
PWM driver positive output. This SPK+ output, together with SPK- pin, provide a
differential output to drive 8Ω speaker or buzzer. During power down this pin is
in tri-state.
12
VSSD_PWM
I
Digital Ground for the PWM Driver.
13
VSSD_PWM
I
Digital Ground for the PWM Driver.
14
SPK-
O
PWM driver negative output. This SPK- output, together with SPK+ pin, provides
a differential output to drive 8Ω speaker or buzzer. During power down this pin is
tri-state.
15
VCCD_PWM
I
Digital Power for the PWM Driver. It can be from a separate power supply other
than VCCD.
16
NC
This pin should be left unconnected.
17
NC
This pin should be left unconnected.
18
NC
This pin should be left unconnected.
19
NC
This pin should be left unconnected.
20
NC
This pin should be left unconnected.
21
INTB / GPIO3
O
Active low interrupt request pin. This pin is an open-drain output.
Can be configured as a general purpose I/O pin.
22
RDY/BSYB /
GPIO4
O
An output pin to report the status of data transfer on the SPI interface. “High”
indicates that ISD2360 is ready to accept new SPI commands or data. Can be
configured as a general purpose I/O pin.
23
NC
This pin should be left unconnected.
24
NC
This pin should be left unconnected.
25
NC
This pin should be left unconnected.
26
VCCD
Jun 15, 2021
I
I
Master-Out-Slave-In. Serial input to the ISD2360 from the host.
Can be configured as a general purpose I/O pin.
Digital Power. It can be from a separate power supply other than V CCD_PWM.
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ISD2360
Pin #
Pin Name
I/O
Function
27
GPIO5
I/O
General purpose I/O pin
28
NC
29
MISO / GPIO2
O
Master-In-Slave-Out. Serial output from the ISD2360 to the host. This pin is in tristate when SSB=1.
Can be configured as a general purpose I/O pin.
30
SCLK / GPI1
I
Serial Clock input to the ISD2360 from the host.
Can be configured as a general purpose input pin.
31
SSB
I
Slave Select input to the ISD2360 from the host. When SSB is low device is
selected and responds to commands on the SPI interface. When asserted,
GPIO0/1/2 automatically configure to MOSI/SCLK and MISO respectively. SSB has
an internal pull-up to Vccd.
32
NC
Jun 15, 2021
This pin should be left unconnected.
This pin should be left unconnected.
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ISD2360
6
DEVICE OPERATION
Playback of audio stored on the ISD2360 can be accomplished by either sending SPI commands
via the serial interface or triggered by signal edges applied to GPIO pins. The device is
programmed via the SPI interface either in-system or utilizing commercially available gang
programmers.
6.1
AUDIO STORAGE
The audio compression and customization of the ISD2360 is rapidly achieved with the supplied
ISD2360VPE or Voice Prompt Editor. This software tool allows the developer to take audio
clips in standard wave file format and re-sample and compress them for download to the
ISD2360.
Audio is stored in the ISD2360 as series of Voice Prompts: these units of audio can be of any
length – the compression and sample rate of each Voice Prompt can be individually selected.
A powerful feature of the ISD2360 is presence of a scripting ability Voice Macros. A Voice
Macro can contain commands to play individual Voice Prompts and configure the ISD2360. A
Voice Macro can be associated with a GPIO pin such that it is triggered by a transition on that
pin. In this way stand-alone systems can be developed without the need for micro-controller
interaction. Voice Macros can also be executed via the SPI command interface. Both Voice
Prompts and Voice Macros are addressed via a simple sequential index address, no absolute
memory address is required, thus audio source material or voice macro function can be
updated (or changed for multi-language implementation) without the need to update
microcontroller code.
6.2
DEVICE CONFIGURATION
The ISD2360 is configured by writing to a set of configuration registers. This can be
accomplished either by sending configuration via the serial SPI interface or executing Voice
Macros containing configuration commands. Most configuration registers are reset to their
default values when the device is powered down to ensure lowest possible standby current.
Exceptions to this are registers that control the configuration of GPIO pins and Jump registers
that contain the Voice Macro index to execute for GPIO triggers. Configuration registers may
be initialized automatically in customizable Voice Macros that are executed on a power-on
reset or power-up condition.
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ISD2360
6.3
GPIO CONFIGURATION
The six GPIO pins of the ISD2360 can be configured for a variety of purposes. Each pin can be
configured to trigger a Voice Macro function. Each pin also has an alternate function allowing
the pins to be configured as SPI, interrupt or oscillator reference pins.
PS
PE
Logic
DOUT
PIN
OE
DIN
Figure 6-1 GPIO Structure
The structure of the GPIO pads is shown in Figure 6-1. Configuration registers allow the user
to control pull-up and pull down resistors, enable the pin as an output or set the output value.
See ISD2360 Design Guide for details on the configuration options.
6.4
OSCILLATOR AND SAMPLE RATES
The ISD2360 has an internal oscillator trimmed at manufacturing that requires no external
components to operate. This oscillator provides an internal clock source that operates the
ISD2360 at a maximum audio sample rate 𝐹𝑆𝑚𝑎𝑥 of 32kHz. The sample rates available for
audio storage at this maximum sample rate are shown in Table 6-1. The sample rate is selected
during compression using the ISD2360 Voice Prompt Editor software.
Table 6-1 Available Sample Rates.
SR[2:0] Ratio to 𝐹𝑆𝑚𝑎𝑥
Jun 15, 2021
Sample Rate 𝐹𝑆 (kHz)
0
8
4
1
6
5.44
2
5
6.4
3
4
8
4
2.5
12.8
5
2
16
6
1
32
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ISD2360
7
MEMORY FORMAT
The memory of the ISD2360 consists of byte addressable flash memory that is erasable in
1Kbyte sectors. Erased memory has a value of 0xFF. Writing to the memory allows host to
change bits from erased ‘1’ state to programmed ‘0’ state.
The memory of the ISD2360 is organized into four distinct regions as shown in Figure 7-1. The
four regions are:
1. Configuration and Index Table: The first region of memory contains configuration data
for the device and the index table that points to the Voice Prompt and Voice Macro
data. The ISD2360VPE creates this section for download to the device.
2. Voice Macros: This section contains the script code of all the projects Voice Macros.
3. Voice Prompts: This section contains the compressed audio data for all Voice Prompts.
4. User Data: An optional section containing memory sectors allocated by the developer
for generic use by the host controller.
Byte
Sector
Address Address
0
0
400h
1
800h
2
C00h
3
1800h
6
1FC00h
7F
20000h
80
Configuration and
Index Table
Voice Prompts
Voice Macros
PMP
User Data
Figure 7-1 ISD2360 Memory Organization
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ISD2360
7.1.1 Voice Prompts
Voice prompts are pre-recorded audio of any length, from short words, phrases or
sound effects to long passages of music. These Voice Prompts can be played back in
any order as determined by the application. A Voice Prompt consists of two
components:
1. An index entry in the Index Table pointing to the pre-recorded audio.
2. Compressed pre-recorded audio data.
A Voice Prompt is addressed using its index number to locate and play the prerecorded audio. This address free approach allows users to easily manage the prerecorded audio without the need to update the code on the host controller. In
addition, the users can store a multitude of pre-recorded audio without the overhead
of maintaining a complicated lookup table. To assist customers in creating the Voice
Prompts, ISD2360 Voice Prompt Editor and writer are available for development
purposes.
7.1.2 Voice Macros
Voice Macros are a script that allows users to customize their own play patterns such
as play Voice Prompts, insert silence, power-down the device and configure the signal
path, including volume control. Voice Macros are executed using a single SPI command
and are accessed using the same index structure as Voice Prompts. This means that a
Voice Macro (or Voice Prompt) can be updated on the ISD2360 without the need to
update code on the host micro-controller since absolute addresses are not needed.
The following locations have been reserved for special Voice Macros:
Index 0: Power-On Initialization (POI)
Index 1: Power-Up (PU)
Index 2: GPIO-Wakeup (WAKEUP)
These Voice Macros allow the users to customize the ISD2360 power-on, power-up
and GPIO wake-up procedures and are executed automatically when utilized. If these
Voice Macros are not used device will perform default operations on these events.
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ISD2360
An example to illustrate the usage of the PU Voice Macro is:
WR_CFG(VOLC, 0x0C)
; Set VOLC to 0x0C
WR_CFG(REG2, 0x44)
; Set REG2 to 0x44
WR_CFG (REG_GPIO_AF1 ,0xFF); Set REG_GPIO_AF1 to 0xFF
WR_CFG (REG_GPIO_AF0 ,0x10)
; Set REG_GPIO_AF0 to 0x10
FINISH
; Exit Voice Macro
The above PU Voice Macro will perform the following:
Choose Volume Control for -3dB level.
Configure and power up the signal path to decode compressed audio to speaker
driver.
Set up all GPIOs except GPIO4 for Falling edge trigger and set GPIO4 for both
falling and rising edge trigger.
The following is the complete list of the command available for use in Voice Macros:
WR_CFG_REG(reg n) – Set configuration register reg to value n.
PWR_DN – Power down the ISD2360.
PLAY_VP(i) – Play Voice Prompt index i.
PLAY_VP@(Rn) – Indirect Play Voice Prompt of index in register Rn
PLAY_VP_LP(i,cnt) – Loop Play Voice Prompt index i, cnt times.
PLAY_VP_LP@(Rn,cnt) – Indirect Loop Play Voice Prompt index in Rn, cnt times.
EXE_VM(i) – Execute Voice Macro index i.
EXE_VM@(Rn) – Indirect Execute Voice Macro index in register Rn
PLAY_SIL(n) – Play silence for n units. A unit is 32ms at master sampling rate of 32
kHz.
WAIT_INT – Wait until current play command finishes before executing next
macro instruction.
FINISH – Finish the voice macro and exit.
These commands are equivalent to the commands available via the SPI interface
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ISD2360
7.1.3 User Data
User Data consists of 1KByte multiples of erasable sectors allocated by the user. This
can be used as generic non-volatile storage by the host application. The developer has
the freedom not to allocate or reserve any memory sectors. A software tool, the
ISD2360 Voice Prompt Editor is available to assist customers in allocating such
memory.
7.2
MEMORY CONTENTS PROTECTION
Under certain circumstances, it is desirable to protect portions of the internal memory from
write/erase or interrogation (read). The ISD2360 provides a method to achieve this by
setting a protection memory pointer (PMP) that allows the users to protect memory for an
address range from the beginning of memory to this sector containing the PMP pointer. The
type of protection is set by three bits in the memory header byte.
Memory protection is activated on power-up of the chip. Therefore, each time the user
changes the setting of memory protection, the new setting will not be effective until the chip
is reset.
8
SPI INTERFACE
This is a standard four-wire serial interface used for communication between ISD2360 and the
host. It consists of an active low slave-select (SSB), a serial clock (SCLK), a data input (Master
Out Slave In - MOSI), and a data output (Master In Slave Out - MISO). In addition, for some
transactions requiring data flow control, a RDY/BSYB signal (pin) is available.
The ISD2360 supports SPI mode 3: (1) SCLK must be high when SPI bus is inactive, and (2) data
is sampled at SCLK rising edge. A SPI transaction begins on the falling edge of SSB and its
waveform is illustrated below:
SSB
SCLK
MISO
Z
MOSI
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
X
S7
S6
S5
S4
S3
S2
S1
S0
D7
D6
D5
D4
D3
D2
D1
D0
X
C7
C6
C5
C4
C3
C2
C1
C0
D7
D6
D5
D4
D3
D2
D1
D0
X
Figure 8-1 SPI Data Transaction.
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ISD2360
A transaction begins with sending a command byte (C7-C0) with the most significant bit (MSB
– C7) sent in first. During the byte transmission, the status (S7-S0) of the device is sent out via
the MISO pin. After the byte transmission, depending upon the command sent, one or more
bytes of data will be sent via the MISO pin.
RDY/BSYB pin is used to handshake data into or out of the device. Upon completion of a byte
transmission, RDY/BSYB pin could change its state after the rising edge of the SCLK if the builtin 32-byte data buffer is either full or empty. At this point, SCLK must remain high until
RDY/BSYB pin returns to high, indicating that the ISD2360 is ready for the next data
transmission. See below for timing diagram.
TR / B
SSB
SCLK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
RDY/BSYB
=1
MISO
MOSI
Z
=1
X
PD RDY INT FULL X
VG BUF
BSY FUL
X
C7
C2
C6
C5
C4
C3
C1
CMD
BSY
C0
PD RDY INT FULL X
VG BUF CMD
BSY FUL BSY
D7
D2
D6
D5
D4
D3
D1
D0
X
Figure 8-2 RDY/BSYB Timing for SPI Writing Transactions.
If the SCLK does not remain high, RDY bit of the status register will be set to zero and be
reported via the MISO pin so the host can take the necessary actions (i.e., terminate SPI
transmission and re-transmit the data when the RDY/BSYB pin returns to high).
For commands (i.e., DIG_READ, SPI_PCM_READ) that read data from the ISD2360 device,
MISO is used to read the data; therefore, the host must monitor the status via the RDY/BSYB
pin and take the necessary actions. The INT pin will go low to indicate (1) data
overrun/overflow when sending data to the ISD2360; or (2) invalid data from ISD2360. See
Figure 8-3 for the timing diagram.
To avoid RDY/BSYB polling for digital operations the following conditions must be met:
Ensure device is idle (CMD_BSY=0 in status) before operation.
Digital Write: Send 32 bytes of data or less in a digital write transaction or ensure that
there is a 24µs period between each byte sent where SCLK is held high.
Digital Read: Ensure a 2µs period between last address byte of digital read command
and first data byte where SCLK is held high.
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ISD2360
TR / B
SSB
SCLK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
RDY/BSYB
=1
MISO
MOSI
Z
=0
X
PD RDY INT FULL X
VG BUF CMD
PD RDY INT FULL X
BSY FUL BSY
VG BUF CMD
BSY FUL BSY
X
C7
C2
D2
C6
C5
C4
C3
C1
C0
D7
D6
D5
D4
D3
D1
D0
X
INT
Figure 8-3 SPI Transaction Ignoring RDY/BSYB
9
SIGNAL PATH
The signal path performs filtering, sample rate conversion, volume control and
decompression. A block diagram of the signal path is shown in Figure 9-1. The PWM driver
output pins SPK- and SPK+ provide a differential output to drive an 8Ω speaker or buzzer.
During power down these pins are in tri-state.
Pre-compressed audio transfers from memory or SPI interface through the de-compressor
block to PWM driver or SPI out. The audio level is adjustable via VOLC before going out on to
the PWM driver path. The possible path combinations are:
MEMORY → DECOMPRESS → SPKR (Playback to speaker)
MEMORY → DECOMPRESS → SPI_OUT (SPI playback)
SPI_IN → DECOMPRESS → SPKR (SPI decode to speaker)
For example, to playback audio to speaker, enable decompression and PWM (write 0x44 to
register 0x02) then send a PLAY_VP command to play audio.
Figure 9-1 ISD2360 Signal Path
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ISD2360
10
GPIO VOICE MACRO TRIGGERS
The ISD2360 Voice Macro capability and GPIO flexibility allows the user to configure the device
to operate independently of the SPI interface or host micro-controller.
GPIO triggering utilizes the Jump registers R0 through R6. When a GPIO trigger event occurs
the ISD2360 executes the Voice Macro whose index is stored in the corresponding Jump
register: that is GPIO0 will execute the VM whose index is stored in R0, GPIO1 in R1 etc. The
initial values of the R0-R6 registers can be set up in the POI Voice macro which is executed
when a power-on reset condition is detected. When the ISD2360 responds to a trigger event,
if a Voice Macro is currently being executed, that Voice Macro is first stopped before execution
of new Voice Macro.
10.1
ASSIGN PLAYBACK CHANNEL FOR THE GPIO TRIGGER
For each GPIO pins, Register 0x14 and 0x15 can assign the playback channel for that GPIO. So
once triggered, the playback audio streaming will be routed to that channel.
10.2
VOICE MACRO EXAMPLES
Below are some useful examples demonstrating the features Voice trigger macros. The
example project can be found in the ISD2360VPE distribution as the ISD2360example project.
10.2.1 POI/PU/WAKEUP Voice Macros
These special purpose Voice Macros allow the user to configure the ISD2360 for subsequent
trigger events. The POI macro is executed when the chip receives an internal power-on reset
condition or the SPI SW_RESET command is sent.
The POI Voice macro is used to configure the ISD2360 for subsequent trigger events, for
example:
a. CFG(REG2, 0x44)
; Configure signal path to playback
b. CFG(VOLC, 0x00)
; Set Volume to 0dB
c.
CFG(R5, 0x03)
; Set Jump register R5 to 0x03, GPIO5 to trigger VM#3
d. CFG(R4, 0x07)
; Set Jump register R4 to 0x07, GPIO4 to trigger VM#7
e. CFG(R3, 0x09)
; Set Jump register R3 to 0x09, GPIO3 to trigger VM#9
f.
CFG(R2, 0x0a)
; Set Jump register R2 to 0x0a, GPIO2 to trigger VM#A
g. CFG(R1, 0x0c)
; Set Jump register R1 to 0x0c, GPIO1 to trigger VM#C
h. CFG(R0, 0x0e)
; Set Jump register R0 to 0x0e, GPIO0 to trigger VM#E
i.
PLAY_VP(FastBeep)
; Play Voice Prompt FastBeep
j.
CFG(REG_GPIO_AF1, 0xff) ; Set up GPIOs to trigger off falling edges
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k. CFG(REG_GPIO_AF0, 0x00)
l.
PD
; Power Down
This POI macro will initialize the GPIO configuration such that all GPIO triggers are enabled for
falling edges and performs initialization of the jump registers to point to appropriate Voice
Macros. It also configures the play path and plays a beep. At the end of the macro the chip
powers down.
The GPIO_WAKEUP is executed whenever the device is triggered from a power down state.
a. CFG(REG2, 0x44)
; Configure signal path to playback
b. CFG(VOLC, 0x00)
; Set Volume to 0dB
c. CFG(R4, 0x07)
; Set Jump register R4 to 0x07, GPIO4 to trigger VM#7
d. CFG(R2, 0x0a)
; Set Jump register R2 to 0x0a, GPIO2 to trigger VM#A
e. Finish
; Exit Voice Macro, stay powered up.
This GPIO_WAKEUP macro sets up the play path as settings in these registers are reset during
power down. It also resets jump registers R4 and R2 to default conditions.
10.2.2 Example: Cycle through a sequence of messages.
In this example a high-to-low transition on GPIO5 will initially trigger VM#3 as defined in the
POI initialization macro. In VM#3 the Voice Prompt “One” is played and jump register R5 set
to VM#4. Thus the next high-to-low transition on GPIO5 will trigger VM#4 and play Voice
Prompt “Two”. Similarly next trigger will play “Three” then “Four” and back to “One”. Notice
the difference in VM#4 where a WAIT_INTERRUPT command has been inserted before the
setting of the jump register. If the GPIO5/SW6 button is pushed rapidly, so that play is
interrupted, “Two” will continue to be repeated. Other Voice Macros, because the jump
register is changed first, will always progress to the next step in sequence.
VM#3: R5_Count_One (GPIO5)
a. CFG(R5, 0x04)
b. Play(One)
c. PD
VM#4:Two
a. Play(Two)
b. Wait Interrupt
c. CFG(R5, 0x05)
d. PD
VM#5: Three
a. CFG(R5, 0x06)
b. Play(Three)
c. PD
VM#6: Four
Jun 15, 2021
; Configure GPIO5 to play VM#4 on next trigger
; Play voice prompt “One”
; Power Down
; Play voice prompt “Two”
; Wait until Play finishes
; Configure GPIO5 to play VM#5 on next trigger
; Power Down
; Configure GPIO5 to play VM#6 on next trigger
; Play voice prompt “Three”
; Power Down
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a. CFG(R5, 0x03)
b. Play(Four)
c. PD
; Configure GPIO5 to play VM# 3 on next trigger
; Play voice prompt “Four “
; Power Down
10.2.3 Example: Looping short sounds. Interrupt to stop playback.
This example demonstrates how to loop short sound samples and use a trigger interrupt to
stop playback. A trigger on GPIO4 will play a series of Voice Prompts until it is interrupted by
another trigger to stop playback. VM#7 was associated with the GPIO4 trigger in the POI
routine. The first action of this VM is to change the trigger VM to VM#8, thus if GPIO4 is retriggered while the Voice Macro is running it will execute the power down voice macro rather
than start the play sequence again.
The next command sets the LRMP bit of REG1, under normal operation the compressor ramps
signal level to zero after a sound sample is played to prevent a DC voltage appearing on the
output. The LRMP bit prevents this from happening while a sample is looping allowing
continuous audio. To loop a sound sample, the audio should be edited such that the last
sample loops smoothly to the first. To do this, create the sample in a sound editor at the
sample rate desired for storage then find the first sample that returns to the initial condition
and cut back audio to one before this sample. Note that tones require different lengths to
fulfill these conditions at a given sample rate and thus loop numbers vary to produce the same
length of output audio.
At the end of the VM REG1 is reset and the trigger is re-enabled back to VM#7 before powering
down.
VM#7: R4_PlayLoop (GPIO4)
a. CFG(R4, 0x08)
; Configure GPIO4 to execute VM# 8 on next trigger.
b. CFG(REG1, 0x20) ; Configure LRMP bit in REG1
c. LOOP_VP(Do,20) ; LOOP “Do” 20 times.
d. LOOP_VP(Re,250) ; LOOP “Re” 250 times.
e. LOOP_VP(Mi,5) ; LOOP “Mi” 5 times.
f. LOOP_VP(Fa,33) ; LOOP “Fa” 33 times.
g. LOOP_VP(So,10) ; LOOP “So” 10 times
h. LOOP_VP(La,10) ; LOOP “La” 10 times
i. LOOP_VP(Si,7)
; LOOP “Si” 7 times.
j. Silence (128 ms) ; Insert 128ms of silence
k. CFG(REG1, 0x00) ; Reset REG1
l. CFG(R4, 0x07)
; Configure GPIO4 to execute VM#7 on next trigger.
m. PD
; Power Down
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VM#8: PD_R4
a. CFG(REG1, 0x00)
b. CFG(R4, 0x07)
c. PD
; Configure Register one to its default value 00
; Configure GPIO4 to execute VM#7 on next trigger.
; Power Down
10.2.4 Example: Uninterruptable Trigger, smooth audio.
In this example a single trigger on GPIO3 will sequence through several messages until all
messages are played the playback cannot be interrupted by any other trigger. The example
also demonstrates how to use begin and end segments to create smooth playback. Each
“note” consists of concatenating three voice prompts, for instance “So_begin” “So” and
“So_end”. The begin and end prompts ramp the audio smoothly to avoid sudden transients
in sound level. The middle, full amplitude, section is created by looping a short sample.
At the beginning of the Voice Macro, all triggers are disabled so that Voice Macro cannot be
interrupted from any source. The NRMP bit of REG1 is set so that concatenation of audio
occurs without any ramp down between prompts. At the end of the macro, interrupts are reenabled and device is powered down.
VM#9: R3_Non-Int_Smooth (GPIO3)
a. CFG(REG_GPIO_AF1, 0x00)
b. CFG(REG1, 0x04)
c. PLAY_VP(So_begin)
d. LOOP_VP(So,10)
e. PLAY_VP(So_end)
f. PLAY_VP(Fa_begin)
g. LOOP_VP(Fa,33)
h. PLAY_VP(Fa_end)
i. PLAY_VP(Mi_begin)
j. LOOP_VP(Mi,5)
k. PLAY_VP(Mi_end)
l. PLAY_VP(Re_begin)
m. LOOP_VP(Re,250)
n. PLAY_VP(Re_end)
o. PLAY_VP(Do_begin)
p. LOOP_VP(Do,20)
q. PLAY_VP(Do_end)
r. Wait Interrupt
s. CFG(REG1, 0x00)
t. CFG(REG_GPIO_AF1, 0x3f)
u. PD
Jun 15, 2021
; Disable all triggers.
; Set NRMP bit
; Play “So_begin”
; Loop “So” 10 times.
; Play “So_end”
; Wait for audio to finish
; Reset NRMP bit
; Re-enable interrupts
; Power down device.
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10.2.5 Example: Continuous Play until re-trigger.
In this example a single trigger on GPIO2 will sequence through several messages with pause
in between each message. Messages are played in a loop indefinitely until another trigger
occurs on GPIO2 to stop playback.
VM0#A: R2_Loop_VM (GPIO2)
a. CFG(R2, 0x0b)
b. PLAY_VP(One)
c. Silence (256 ms)
d. PLAY_VP(two)
e. Silence (256 ms)
f. PLAY_VP(three)
g. Silence (736 ms)
h. PLAY_VP(four)
i. Silence (256 ms)
j. EXE_VM(0xA)
k. Finish
VM0#B: PD_R2
a. CFG(R2, 0x0a)
b. PD
; Set Trigger to VM#B (PD_R2)
; Play “One”
; pause 256ms
; Play “Two”
; Execute VM#A (repeat)
; Reset Trigger to VM#A
; Power Down.
10.2.6 Example: Level Hold Trigger.
In this example holding GPIO1 will play several messages. Releasing GPIO1 will stop the
playback. No other triggers will affect operation.
VM#C: R1_Level_Hold (GPIO1)
a. CFG(REG_GPIO_AF0, 0x02) ; Enable rising edge trigger for GPIO2
b. CFG(REG_GPIO_AF1, 0x02) ; Disable all triggers except GPIO2
c. CFG(R1, 0x0d)
; Set Trigger to VM#D (PD_R1)
d. CFG(REG1, 0x20)
e. LOOP_VP(Re,200)
f. Silence (32 ms)
g. LOOP_VP(Mi,4)
h. Silence (32 ms)
i. LOOP_VP(Fa,20)
j. Silence (32 ms)
k. CFG(REG1, 0x00)
l. PLAY_VP(applause)
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m. PD
VM#D: PD_R1
a. CFG(REG_GPIO_AF0, 0x00)
b. CFG(REG_GPIO_AF1, 0x3f)
c. CFG(REG1, 0x00)
d. CFG(R1, 0x0c)
e. PD
11
; Disable rising edge trigger
; Re-enable all triggers.
; Ensure REG1 reset
; Set trigger to VM#C
; Power Down.
CHANNEL SELECTION AND EXECUTION CONTROL
11.1
SELECT CHANNEL FOR THE PLYABCK
AND MIXING
For any play command such as PLAY_VM or PLAY_VP, the playback occurs in either one
channel or all three channels. In other words, user can either specify one single active channel
for next playback operation, or make the next play operation happen in all three channels.
Channel selection can be achieved by configuring register 0x0C.
To mix two different sound effects from two channels, e.g. channel #0 and channel #1, user
can first configure channel #0 as the active channel by writing 0bxxxxxx00 into register 0x0C,
then send a play command to play the first sound effect; then configure channel #1 as the
active channel by writing 0bxxxxxx01 into register 0x0C, then send another play command to
play the second sound effect. This way sound effect mixing can be achieved.
By Default, play operations will always happen in channel #0.
11.2
EXECUTION CONTROL
The ISD2360 implemented several commands which allow user add fine control in a VM script
execution.
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11.2.1 Conditional Branch and Unconditional Jump
The ISD2360 can do mask branch which judges device’s current pin status and its internal
status register value against the value in mask register, to decide if jump to a memory address
(and start execution from there) or continue executing the next script command inside the
current VM. This gives the possibility of multi-tasking, i.e. let the ISD2360 do something during
the play.
The ISD2360 can also do an absolute jump, which jumps to a memory address and start
execution from there.
The new start address should be a valid command entry address; otherwise it will cause
unknown behavior. The scope for the mask jump and absolute jump is global, i.e. the full range
of the flash size.
11.2.2 Execution Delay / Pause
The ISD2360 has time counter for each channel. So it allows customer add delay during a VM
execution. This adds the convenience for certain operations such as GPIO driving with time
control.
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12 ELECTRICAL CHARACTERISTICS
12.1
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION
SYMBOL
DC Power Supply
CONDITION
MIN
MAX
UNITS
VCCD
VCCD – VSSD
-0.3
+6.0
V
VCCPWM
VCCPWM – VSSPWM
-0.3
+6.0
V
Digital Input Voltage
DVIN
DVIN - VSSD
VSSD – 0.3
VCCD + 0.3
V
Junction Temperature
TJ
-
-40
+125
°C
Storage Temperature
Tst
-
-65
+150
°C
CAUTION: Do not operate at or near the maximum ratings listed for extended period of time.
Exposure to such conditions may adversely influence product reliability and result in failures
not covered by warranty. These devices are sensitive to electrostatic discharge; follow proper
IC Handling Procedures.
12.2
OPERATING CONDITIONS
OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS)
CONDITIONS
VALUES
Operating temperature range (Case temperature)
-40°C to +85°C
Supply voltage (VDD) [1]
+2.4V to +5.5V
Ground voltage (VSS) [2]
0V
Digital input voltage (DVIN)
0V to 5.5V
Voltage applied to any pins
(VSS –0.3V) to (VDD +0.3V)
NOTES:
12.3
[1] V
DD
[2] V
SS
= VCCD = VCCPWM
= VSSD = VSSPWM
AC PARAMETERS
12.3.1 Internal Oscillator
PARAMETER
Sample rate with Internal
Oscillator
Jun 15, 2021
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
𝐹𝑆𝑚𝑎𝑥
-1%
32kHz
+1%
kHz
Vdd = 3V.
At room temperature
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ISD2360
12.3.2 Speaker Outputs
PARAMETER
SYMBOL
Output Power
MIN
TYP[1]
POUT_SPK
SNR, Memory to SPK+/SPK-
SNRMEM_SPK
60
THD, Memory to SPK+/SPK-
THD %
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