MR0A08B
FEATURES
•
•
•
•
•
•
•
•
•
128K x 8 MRAM
3.3 Volt power supply
Fast 35 ns read/write cycle
SRAM compatible timing
Native non-volatility
Unlimited read & write endurance
Data always non-volatile for >20 years at temperature
Commercial and industrial temperatures
All products meet MSL-3 moisture sensitivity level
RoHS-Compliant TSOP2 and BGA packages
BENEFITS
• One memory replaces FLASH, SRAM, EEPROM and
MRAM in system for simpler, more efficient design
• Improves reliability by replacing battery-backed
SRAM
48-ball FBGA
44-pin TSOP2
INTRODUCTION
The MR0A08B is a 1,048,576-bit magnetoresistive random access
memory (MRAM) device organized as 131,072 words of 8 bits. The
MR0A08B offers SRAM compatible 35 ns read/write timing with unlimited endurance.
Data is always non-volatile for greater than 20-years. Data is automatically protected on
power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
The MR0A08B is the ideal memory solution for applications that must permanently store and
retrieve critical data and programs quickly.
The MR0A08B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP
type-2 package, 8 mm x 8 mm, or a 48-pin ball grid array (BGA) package with 0.75 mm ball
centers. (The 32-SOIC package options is obsolete and no longer available for new orders.)
These packages are compatible with similar low-power SRAM products and other non-volatile RAM products.
The MR0A08B provides highly reliable data storage over a wide range of temperatures. The
product is offered with commercial temperature range (0 to +70 °C) and industrial temperature range (-40 to +85 °C).
RoHS
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
TABLE OF CONTENTS
FEATURES..............................................................................................................................................1
BENEFITS................................................................................................................................................1
INTRODUCTION....................................................................................................................................1
BLOCK DIAGRAM AND PIN ASSIGNMENTS........................................................................................4
Figure 1 – MR0A08B Block Diagram....................................................................................................................... 4
Table 1 – Pin Functions................................................................................................................................................ 4
Figure 2 – Pin Diagrams for Available Packages (Top View) 1....................................................................... 5
OPERATING MODES..............................................................................................................................5
Table 2 – Operating Modes........................................................................................................................................ 5
ELECTRICAL SPECIFICATIONS.............................................................................................................6
Table 3 – Absolute Maximum Ratings.................................................................................................................... 6
OPERATING CONDITIONS....................................................................................................................7
Table 4 – Operating Conditions................................................................................................................................ 7
Power Up and Power Down Sequencing........................................................................................8
Figure 3 – Power Up and Power Down Diagram................................................................................................ 8
DC CHARACTERISTICS..........................................................................................................................9
Table 5 – DC Characteristics....................................................................................................................................... 9
Table 6 – Power Supply Characteristics................................................................................................................. 9
TIMING SPECIFICATIONS.................................................................................................................. 10
Table 7 – Capacitance................................................................................................................................................10
Table 8 – AC Measurement Conditions...............................................................................................................10
Figure 4 – Output Load Test Low and High........................................................................................................10
Figure 5 – Output Load Test All Others................................................................................................................10
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
TABLE OF CONTENTS (CONT’D)
Read Mode..................................................................................................................................... 11
Table 9 – Read Cycle Timing....................................................................................................................................11
Figure 6 – Read Cycle 1..............................................................................................................................................12
Figure 7 – Read Cycle 2..............................................................................................................................................12
Write Mode..................................................................................................................................... 13
Table 10 – Write Cycle Timing 1 ( W Controlled )..............................................................................................13
Figure 8 – Write Cycle Timing 1 (W Controlled)................................................................................................14
Table 11 – Write Cycle Timing 2 (E Controlled).................................................................................................15
Figure 9 – Write Cycle Timing 2 (E Controlled).................................................................................................16
Table 12 – Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)..............................................17
Figure 10 – Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)............................................17
ORDERING INFORMATION................................................................................................................ 18
Table 13 – Ordering Part Number System for Parallel I/O MRAM..............................................................18
Table 14 – MR0A08B Ordering Part Numbers 1................................................................................................18
PACKAGE OUTLINE DRAWINGS........................................................................................................ 19
Figure 11 – 44-TSOP2 Package Outline...............................................................................................................19
Figure 12 – 48-BGA Package Outline....................................................................................................................20
Figure 13 – 32-SOIC Package Outline 1...............................................................................................................21
REVISION HISTORY............................................................................................................................ 22
HOW TO CONTACT US........................................................................................................................ 23
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
BLOCK DIAGRAM AND PIN ASSIGNMENTS
Figure 1 – MR0A08B Block Diagram
G
A[16:0]
17
E
W
OUTPUT
ENABLE
BUFFER
OUTPUT ENABLE
ADDRESS
BUFFER
7
10
ROW
DECODER
CHIP
ENABLE
BUFFER
COLUMN
DECODER
8
SENSE
AMPS
128k x 8
BIT
MEMORY
ARRAY
WRITE
ENABLE
BUFFER
8
FINAL
WRITE
DRIVERS
8
OUTPUT
BUFFER
8
WRITE
DRIVER
8
8
DQ[7:0]
WRITE ENABLE
Table 1 – Pin Functions
Signal Name
Function
A
Address Input
E
Chip Enable
W
Write Enable
G
Output Enable
DQ
Data I/O
VDD
Power Supply
VSS
Ground
DC
Do Not Connect
NC
No Connection - Pin 2, 40, 41,43 (TSOP2); Ball C2, C5, D3, F2, F5, G1, G2, G6, H1, H6
(BGA); Pin 30 (SOIC) Reserved For Future Expansion
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Figure 2 – Pin Diagrams for Available Packages (Top View) 1
DC
NC
A0
A1
A2
A3
A4
E
DQ0
DQ1
VDD
VSS
DQ2
DQ3
W
A5
A6
A7
A8
A9
DC
DC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DC
DC
1
32
VDD
NC
DC
NC
NC
A16
A15
G
DQ7
A16
2
31
A15
A14
3
30
NC
A12
4
29
W
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
DQ6
VSS
A4
8
25
A11
VDD
DQ5
DQ4
DC
A3
9
24
G
A2
10
23
A10
A1
11
22
E
A14
A13
A12
A0
12
21
DQ7
DQ0
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
VSS
16
17
DQ3
A11
A10
DC
DC
1
2
3
4
5
6
DC
G
A0
A1
A2
DC
A
NC
DC
A3
A4
E
DC
B
DQ0
NC
A5
A6
NC
DQ4
C
VSS
DQ1
NC
A7
DQ5
VDD
D
VDD
DQ2
DC
A16
DQ6
VSS
E
DQ3
NC
A14
A15
NC
DQ7
F
NC
NC
A12
A13
W
NC
G
NC
A8
A9
A10
A11
NC
H
32 Pin SOIC 1
44 Pin TSOP2
48 Pin FBGA
Note:
1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer
available for new orders.
OPERATING MODES
Table 2 – Operating Modes
E1
G1
W1
Mode
VDD Current
DQ[7:0] 2
H
X
X
Not selected
ISB1, ISB2
Hi-Z
L
H
H
Output disabled
IDDR
Hi-Z
L
L
H
Byte Read
IDDR
DOut
L
X
L
Byte Write
IDDW
Din
Notes:
1. H = high, L = low, X = don’t care
2. Hi-Z = high impedance
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater
than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken o avoid
application of any magnetic field more intense than the maximum field intensity specified in the maximum
ratings. 1
Table 3 – Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply voltage 2,3
VDD
-0.5 to 4.0
V
Voltage on any pin 2,3
VIN
-0.5 to VDD + 0.5
V
Output current per pin
IOUT
±20
mA
PD
0.600
W
Package power dissipation 3
Temperature under bias
MR0A08B (Commercial)
MR0A08BC (Industrial)
Storage Temperature
TBIAS
-10 to 85
-45 to 95
°C
Tstg
-55 to 150
°C
TLead
260
°C
Maximum magnetic field during write
MR0A08B (All Temperatures)
Hmax_write
2000
A/m
Maximum magnetic field during read or standby
Hmax_read
8000
A/m
Lead temperature during solder (3 minute max)
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or
magnetic fields could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability depends on package characteristics and use environment.
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
OPERATING CONDITIONS
Table 4 – Operating Conditions
Parameter
Min
3.0 1
Typical
Max
Unit
Power supply voltage
Symbol
VDD
3.3
3.6
V
Write inhibit voltage
VWI
2.5
2.7
3.0 1
V
Input high voltage
VIH
2.2
-
VDD + 0.3 2
V
Input low voltage
VIL
-0.5 3
-
0.8
V
TA
0
70
°C
-40
85
Temperature under bias
MR0A08B (Commercial)
MR0A08BC (Industrial)
Notes:
1. There is a 2 ms startup time once VDD exceeds VDD,(max). See “Figure 3 – Power Up and Power Down
Diagram” .
2. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
3. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds
VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory
power supplies to stabilize.
The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and
remain high for the startup time. In most systems, this means that these signals should be pulled up with a
resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and
W should hold the signals high with a power-on reset signal for longer than the startup time.
During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be
observed when power returns above VDD(min).
Figure 3 – Power Up and Power Down Diagram
VWI
VDD
BROWNOUT or POWER LOSS
2 ms
STARTUP
READ/WRITE
INHIBITED
2 ms
RECOVER
NORMAL
OPERATION
READ/WRITE
INHIBITED
NORMAL
OPERATION
VIH
VIH
E
W
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
DC CHARACTERISTICS
Table 5 – DC Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
Input leakage current
Ilkg(I)
-
-
±1
μA
Output leakage current
Ilkg(O)
-
-
±1
μA
VOL
-
-
0.4
V
VOH
2.4
-
Output low voltage
(IOL = +4 mA)
(IOL = +100 μA)
VSS + 0.2
Output high voltage
(IOL = -4 mA)
(IOL = -100 μA)
-
V
VDD - 0.2
Table 6 – Power Supply Characteristics
Parameter
AC active supply current - read modes 1
(IOUT= 0 mA, VDD= max)
Symbol
Typical
Max
Unit
IDDR
25
30
mA
55
65
55
70
ISB1
6
7
mA
ISB2
5
6
mA
AC active supply current - write modes 1
(VDD= max)
MR0A08B (Commercial)
MR0A08BC (Industrial)
IDDW
mA
AC standby current
(VDD= max, E = VIH)
no other restrictions on other inputs
CMOS standby current
( E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V )
( VDD = max, f = 0 MHz )
Notes:
1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
TIMING SPECIFICATIONS
Table 7 – Capacitance
Parameter 1
Symbol
Typical
Max
Unit
Address input capacitance
CIn
-
6
pF
Control input capacitance
CIn
-
6
pF
Input/Output capacitance
CI/O
-
8
pF
Notes:
1. f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 8 – AC Measurement Conditions
Parameter
Value
Unit
Logic input timing measurement reference level
1.5
V
Logic output timing measurement reference level
1.5
V
0 or 3.0
V
2
ns
Logic input pulse levels
Input rise/fall time
Output load for low and high impedance parameters
See Figure 4
Output load for all other timing parameters
See Figure 5
Figure 4 – Output Load Test Low and High
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 5 – Output Load Test All Others
3.3 V
590 Ω
Output
5 pF
435 Ω
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Read Mode
Table 9 – Read Cycle Timing
Parameter 1
Symbol
Min
Max
Unit
Read cycle time
tAVAV
35
-
ns
Address access time
tAVQV
-
35
ns
Enable access time 2
tELQV
-
35
ns
Output enable access time
tGLQV
-
15
ns
Output hold from address change
tAXQX
3
-
ns
Enable low to output active 3
tELQX
3
-
ns
Output enable low to output active 3
tGLQX
0
-
ns
Enable high to output Hi-Z 3
tEHQZ
0
15
ns
Output enable high to output Hi-Z 3
tGHQZ
0
10
ns
Notes:
1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
2. Addresses valid before or at the same time E goes low.
3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage.
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Figure 6 – Read Cycle 1
t AVAV
A (ADDRESS)
t AXQX
Q (DATA OUT)
Previous Data Valid
Data Valid
t AVQV
Note: Device is continuously selected (E≤VIL, G≤VIL).
Figure 7 – Read Cycle 2
t AVAV
A (ADDRESS)
t AVQV
E (CHIP ENABLE)
t ELQV
t EHQZ
t ELQX
G (OUTPUT ENABLE)
Q (DATA OUT)
Copyright © 2018 Everspin Technologies
t GHQZ
t GLQV
t GLQX
Data Valid
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Write Mode
Table 10 – Write Cycle Timing 1 ( W Controlled )
Parameter 1
Symbol
Min
Max
Unit
Write cycle time 2
tAVAV
35
-
ns
Address set-up time
tAVWL
0
-
ns
Address valid to end of write (G high)
tAVWH
18
-
ns
Address valid to end of write (G low)
tAVWH
20
-
ns
Write pulse width (G high)
tWLWH
tWLEH
15
-
ns
Write pulse width (G low)
tWLWH
tWLEH
15
-
ns
Data valid to end of write
tDVWH
10
-
ns
Data hold time
tWHDX
0
-
ns
Write low to data Hi-Z 3
tWLQZ
0
12
ns
Write high to output active 3
tWHQX
3
-
ns
Write recovery time
tWHAX
12
-
ns
Notes:
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain
in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given
voltage or temperate, tWLQZ(max) < tWHQX(min)
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Figure 8 – Write Cycle Timing 1 (W Controlled)
t AVAV
A (ADDRESS)
t AVWH
t WHAX
E (CHIP ENABLE)
t WLEH
t WLWH
W (WRITE ENABLE)
t AVWL
t DVWH
D (DATA IN)
t WHDX
DATA VALID
t WLQZ
Q (DATA OUT)
Hi -Z
Hi -Z
t WHQX
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Table 11 – Write Cycle Timing 2 (E Controlled)
Parameter 1
Symbol
Min
Max
Unit
Write cycle time 2
tAVAV
35
-
ns
Address set-up time
tAVEL
0
-
ns
Address valid to end of write (G high)
tAVEH
18
-
ns
Address valid to end of write (G low)
tAVEH
20
-
ns
Enable to end of write (G high)
tELEH
tELWH
15
-
ns
Enable to end of write (G low) 3
tELEH
tELWH
15
-
ns
Data valid to end of write
tDVEH
10
-
ns
Data hold time
tEHDX
0
-
ns
Write recovery time
tEHAX
12
-
ns
Notes:
1.
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or
after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2.
All write cycle timings are referenced from the last valid address to the first transition address.
3.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Figure 9 – Write Cycle Timing 2 (E Controlled)
t AVAV
A (ADDRESS)
t EHAX
t AVEH
t ELEH
E (CHIP ENABLE)
t AVEL
t ELWH
W (WRITE ENABLE)
t DVEH
D (DATA IN)
Data Valid
Hi-Z
Q (DATA OUT)
Copyright © 2018 Everspin Technologies
t EHDX
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Table 12 – Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)
Parameter 1
Min
Max
Unit
Write cycle time 2
Symbol
tAVAV
35
-
ns
Address set-up time
tAVWL
0
-
ns
Address valid to end of write (G high)
tAVWH
tAVWH
18
-
ns
20
-
ns
Address valid to end of write (G low)
Write pulse width
tWLWH
tWLEH
15
-
ns
Data valid to end of write
tDVWH
10
-
ns
Data hold time
tWHDX
0
-
ns
Enable recovery time
tEHAX
-2
-
ns
Write recovery time 3
tWHAX
6
-
ns
Write to enable recovery time 3
tWHEL
12
-
ns
Notes:
1.
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or
after W goes low, the output will remain in a high impedance state. After W, or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. If E goes low at the same time or after W goes low the output will remain in a high impedance state. If E goes high at the
same time or before W goes high the output will remain in a high impedance state. E must be brought high each cycle.
Figure 10 – Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)
t AVAV
A (ADDRESS)
t WHAX
t AVWH
E (CHIP ENABLE)
t EHAX
t WLEH
W (WRITE ENABLE)
t WHEL
t WLWH
t AVWL
t DVWH
t WHDX
D (DATA IN)
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
ORDERING INFORMATION
Table 13 – Ordering Part Number System for Parallel I/O MRAM
MRAM
256 Kb
1 Mb
4 Mb
16 Mb
Example Ordering Part Number
MR
256
0
2
4
Memory Density
MR
0
Type
A
I/O Width
08
Rev.
B
Temp Package Speed
C
MA
35
Packing
R
Grade
A
Async 3.3v
Async 3.3v Vdd and 1.8v Vddq
D
Async 3.3v Vdd and 1.8v Vddq with 2.7v min. Vdd
DL
8-bit
16-bit
Rev A
Rev B
Commercial
0 to 70°C
Industrial
-40 to 85°C
Extended
-40 to 105°C
AEC Q-100 Grade 1 -40 to 125°C
44-TSOP-2
48-FBGA
16-SOIC
32-SOIC
35 ns
45 ns
Tray
Tape and Reel
Engineering Samples
Customer Samples
Mass Production
08
16
A
B
Blank
C
V
M
YS
MA
SC
SO
35
45
Blank
R
ES
Blank
Blank
Table 14 – MR0A08B Ordering Part Numbers 1
Temp Grade
Temp
Package
Shipping
Tray
44-TSOP2
Commercial
0 to +70 °C
Tape and Reel
Tray
48-BGA
Tape and Reel
Tray
32-SOIC 1
Tape and Reel
Tray
44-TSOP2
Industrial
-40 to +85 °C
Tape and Reel
Tray
48-BGA
Tape and Reel
Tray
32-SOIC 1
Tape and Reel
Ordering Part Number
MR0A08BYS35
MR0A08BYS35R
MR0A08BMA35
MR0A08BMA35R
MR0A08BSO35 Obsolete
MR0A08BSO35R Obsolete
MR0A08BCYS35
MR0A08BCYS35R
MR0A08BCMA35
MR0A08BCMA35R
MR0A08BCSO35 Obsolete
MR0A08BCSO35R Obsolete
1 The 32-SOIC package option is obsolete and no longer available. See PCN02895 here.
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
PACKAGE OUTLINE DRAWINGS
Figure 11 – 44-TSOP2 Package Outline
Not To Scale
1.
Dimensions and tolerances per ASME Y14.5M - 1994.
2.
Dimensions in Millimeters.
3.
Dimensions do not include mold protrusion.
4.
Dimension does not include DAM bar protrusions.
5.
DAM Bar protrusion shall not cause the lead width to
exceed 0.58.
44
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Figure 12 – 48-BGA Package Outline
TOP VIEW
0.41
0.31
BOTTOM VIEW
0.32
0.22
SIDE VIEW
Not To Scale
1.
Dimensions in Millimeters.
2.
Dimensions and tolerances per ASME Y14.5M - 1994.
3.
Maximum solder ball diameter measured parallel to DATUM A
4.
DATUM A, the seating plane is determined by the spherical crowns
of the solder balls.
5.
surface of package.
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
Figure 13 – 32-SOIC Package Outline 1
PIN 1 ID
32
17
J
Reference JEDEC MO-119
K
1
16
A
I
G
D
B
Unit
mm - Min
- Max
inch - Min
- Max
E
C
A
20.574
20.878
0.810
0.822
B
1.00
1.50
0.04
0.06
C
0.355
0.508
0.14
0.02
D
0.66
0.81
0.026
0.032
E
0.101
0.254
0.004
0.010
H
F
F
2.286
2.540
0.09
0.10
G
Radius
0.101
Radius
0.0040
H
0.533
1.041
0.021
0.041
I
0.152
0.304
0.006
0.012
J
7.416
7.594
0.292
0.299
K
10.287
10.642
0.405
0.419
Note:
1. The 32-SOIC package is obsolete and shown for legacy reference only. This package option is no longer
available for new orders.
Copyright © 2018 Everspin Technologies
21
MR0A08B Rev. 8.6, 3/2018
MR0A08B
REVISION HISTORY
Revision
0
Date
Description of Change
Sep 12, 2008
Initial Advance Information Release
Revised format; Add Table 3.6 Write Timing Cycle 3; Add Figure 3.6 Write
Timing Cycle 3; Add TSOPII Lead Width Info; Changed to Preliminary from
Product Concept.
Changed from datasheet from Preliminary to Production except where
noted.
1
May 8, 2009
2
June 18, 2009
3
Apr 12, 2011
Added SOIC package option.
4
August 15, 2011
Corrected SOIC Pin 1 to read DC. Updated contact information. Revised
copyright year.
5
Dec 16, 2011
Changed TSOP-II to TSOP2. Changed logo to new EST Logo. Added Industrial Temp Grade option in SOIC package, Table 4.1. Deleted Tape &
Reel pack option for all SOIC packaged parts. Figure 2.1 cosmetic update.
Figure 5.2 BGA package outline drawing revised for ball size.
6
July 9, 2013
MR0A08BCSO35 preliminary status removed. Now MP.
7
September 4, 2013 Added table of dimenstions to the SOIC package outline diagram.
8
October 11, 2013
Added Tape and Reel shipping option for SOIC packged versions. Reformatted to current standards.
8.1
May 18, 2015
Revised How to Contact Us information.
8.2
June 11, 2015
Correction to Japan Sales Office telephone number.
8.3
July 20, 2015
32-SOIC package options Not Recommended for New Designs.
8.4
October 17, 2015
32-SOIC package options are obsolete and no longer available.
8.5
December 9, 2015
Corrections to incorrect package pinouts and replaced missing 48-BGA
package outline drawing.
8.6
March 22, 2018
Updated Contact Us table
Copyright © 2018 Everspin Technologies
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MR0A08B Rev. 8.6, 3/2018
MR0A08B
HOW TO CONTACT US
Home Page:
Everspin Technologies, Inc.
www.everspin.com
Information in this document is provided solely to enable system and
software implementers to use Everspin Technologies products. There are
no express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does Everspin Technologies assume any liability arising out of
the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin
Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technologies does not
convey any license under its patent rights nor the rights of others. Everspin
Technologies products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Everspin Technologies products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even
if such claim alleges that Everspin Technologies was negligent regarding
the design or manufacture of the part. Everspin™ and the Everspin logo
are trademarks of Everspin Technologies, Inc. All other product or service
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85224
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
Filename:
names are the property of their respective owners.
EST00183_MR0A08B_Datasheet_Rev8.6 032218
Copyright © Everspin Technologies, Inc. 2018
Copyright © 2018 Everspin Technologies
23
MR0A08B Rev. 8.6, 3/2018
