HI-1575
MIL-STD-1553 3.3V Dual Transceivers
with Integrated Encoder / Decoders
DESCRIPTION
11
12
13
14
15
16
17
18
19
20
1575PCI
1575PCT
26 - D3
25 - D4
28 - D1
27 - D2
30 - CLK
40 Pin Plastic 6mm x 6mm
Chip-scale package
29 - D0
Activity on both MIL-STD-1553 data buses is continuously
monitored. When the HI-1575 detects a properly encoded
word, a hardware interrupt is generated and the
information is decoded and stored in one of two internal
registers, which may then be read by the host processor.
Bits in the internal Status & Mode Register indicate on
which bus the word was received and whether the word
had a Data or Command Sync.
30 29 D5
28 D6
27 D7
26 GND
25 D8
24 D9
23 D10
22 D11
21 -
R/W
STRB
MR
SYNC
D15
D14
D13
D12
-
A single write cycle is used to transfer a word to the
HI-1575, which encodes the data, adds the selected Sync
and Parity bits, and transmits the word on the chosen
MIL-STD-1553 data bus. Complete MIL-STD-1553
messages may be transmitted by executing multiple write
cycles to the device.
- 1
RCVA 2
BUSA 3
BUSA 4
VDD 5
BUSB 6
BUSB 7
RCVB 8
REG 9
- 10
32 - ERROR
The HI-1575 is a low power CMOS dual transceiver with
on-chip Manchester II Encoder and dual Decoder
designed to meet the requirements of the MIL-STD-1553
specification. The part acts as a "Smart Transceiver",
allowing users to transmit and receive properly encoded
MIL-STD-1553 Command and Data words between a
16-bit host processor and dual MIL-STD-1553 data
buses.
40 39 ERROR
38 CHA/CHB
37 CLK
36 D0
35 D1
34 D2
33 D3
32 D4
31 -
PIN CONFIGURATIONS
31 - CHA/CHB
April 2011
FEATURES
RCVA - 1
24 - D5
BUSA - 2
23 - D6
BUSA - 3
BUSB - 5
BUSB - 6
21 - GND
20 - D8
19 - D9
D12 - 16
D14 - 14
D13 - 15
D15 - 13
MR - 11
17 - D11
SYNC - 12
18 - D10
REG - 8
STRB - 10
RCVB - 7
TQFP package
! Less than 0.5W maximum power dissipation
! 6 mm x 6 mm 40-pin plastic chip-scale
22 - D7
HI-1575PQI
&
HI-1575PQT
VDD - 4
R/W - 9
! Compliant to MIL-STD-1553A & B
! 3.3V single supply operation
! On-chip Encoder and Dual Decoder
! Small footprint available in 32-pin plastic
32 Pin TQFP package
package option
(DS1575 Rev. D)
HOLT INTEGRATED CIRCUITS
www.holtic.com
04/011
HI-1575
PIN DESCRIPTIONS
PIN
(TQFP)
PULL-UP
SYMBOL FUNCTION PULL-DOWN
DESCRIPTION
1
RCVA
Digital output
-
Goes high when MIL-STD-1553 word received on Bus A
2
BUSA
Analog I/O
-
MIL-STD-1533 bus driver A, negative signal
3
BUSA
Analog I/O
-
MIL-STD-1553 bus driver A, positive signal
4
VDD
Power supply
-
+3.3 VDC
5,
BUSB
Analog I/O
-
MIL-STD-1533 bus driver B, negative signal
MIL-STD-1553 bus driver B, positive signal
6
BUSB
Analog I/O
-
7
RCVB
Digital output
-
8
REG
Digital input
12K pull-down
9
R/W
Digital input
12K pull-up
10
STRB
Digital input
12K pull-up
11
MR
Digital input
12K pull-down
Goes high when MIL-STD-1553 word received on Bus B
Selects Status & Mode Register when high, or Data registers when low
Controls data and sync direction during read or write operations
Strobe. Timing input to control register read and write operations
Pulse high to reset the HI-1575
12
SYNC
Digital I/O
12K pull-down
Selects transmit sync type on write, indicates received sync type on read.
13-20, 22-29
D15:D0
Digital I/O
12K pull-down
Data bus. D15 (MSB) corresponds to MIL-STD-1553 bit 4
21
GND
Power supply
-
30
CLK
Digital input
-
31
CHA/CHB
Digital Input
12K pull-down
32
ERROR
Digital output
-
Ground
12 MHz clock
Selects MIL-STD-1553 Bus A or Bus B
Goes high when a received MIL-STD-1553 word has an encoding error
FUNCTIONAL DESCRIPTION
Figure 1 shows a simplified block diagram of the HI-1575.
The MR (Master Reset) input should be pulsed high to
initialize the Manchester II Encoder and Decoders. MR
also clears the Receive Data registers, RXA and RXB,
and sets the Status & Mode register to its default state
as described in figure 2.
The CLK input requires a 12.0 MHz clock signal. CLK is
used to derive the 1.0 us bit period for MIL-STD-1553
data transmission, as well to provide the master clock for
the Manchester II encoder and the decoder's receiver
sampling logic.
STATUS & MODE REGISTER
The HI-1575 is configured by writing bits 0 - 5 of the Status & Mode (SAM) register. Refer to figure 2 for a complete description. SAM bits 0 - 5 are read/write allowing
the user to verify the chip's configuration at any time by
reading the SAM. SAM is accessed by performing a read
or write cycle with the REG input high.
SAM bits 6 - 15 are read-only and are used to provide
status information.
To minimize the number of hardware control inputs, SAM
bit 5 (Channel A/B select) is logically 'OR'ed with the
CHA/CHB input pin. To select between MIL-STD-1553
bus A or B, the user may either tie the CHA/CHB pin low
and select buses using SAM bit 5 (software control), or
program SAM bit 5 to a zero and use the CHA/CHB pin
to select the active bus (hardware control).
Similarly, the SYNC I/O pin may be left open-circuit allowing the transmitter sync to be programmed into SAM
bit 4, or SAM bit 4 can be set to zero and the SYNC pin
used to set the transmitted SYNC type. Note that SYNC
is an I/O pin. It is an input when writing data to the
HI-1575 transmit data register (TX), and an output when
reading data from the HI-1575 receivers (RXA and RXB).
The SYNC pin must not be shorted directly to VDD or
GND. An internal pull-down resistor allow the SYNC pin
to be left open-circuit if the user opts for purely software
control.
TRANSMITTER
Data words to be transmitted on the MIL-STD-1553 data
bus are written to the TX register by pulsing STRB low
while R/W is low and REG is low. The logical OR of the
CHA/CHB input pin and SAM bit 5 (CHAN) during the
write cycle determines whether the word is output on
MIL-STD-1553 bus A or B. Setting CHA/CHB OR CHAN
to a zero selects bus A, and a one selects bus B. The logical OR of the SYNC pin and SAM bit 4 (TXSYNC) during the write cycle defines whether the transmitted word
is a MIL-STD-1553 Command or Data word. Setting
SYNC to a one causes a Command (or Status) sync to
be generated. Setting SYNC to zero selects a Data sync.
Note that the SYNC pin is bidirectional. It should be
treated as an extension to the 16-bit bidirectional
databus (D15:D0) in terms of I/O switching and timing.
The HI-1575 automatically calculates and appends the correct parity bit to the transmitted word. Each word is assigned odd parity as required by MIL-STD-1553.
HOLT INTEGRATED CIRCUITS
2
HI-1575
4
VDD
30
REG
2
8
CHA/CHB
11
5
6
RXA
DATABUS
12
BUSA
BUSB
BUSB
Decoder A
1
RXB
RCVA
3
31
13-20,
22-29
SYNC
BUSA
Encoder
TX
MR
9
SHIFT
R/W
10
SHIFT
STRB
SHIFT
CLK
Decoder B
7
6
10
ERROR
32
STATUS & MODE
RCVB
21
GND
Note: Pin numbers reflect QFP package
FIGURE 1. HI-1575 BLOCK DIAGRAM
To transmit contiguous words, a second write to the TX
register must occur no earlier than 3.5 us and no later
than 18.5 us after the first TX write. SAM bit 15
(SENDDATA) is high during this period and may be used
as a flag to indicate when the HI-1575 is ready to accept
the next data write for contiguous transmission. When
transmitting a message of three or more words, the third
and subsequent write operations should occur every 20.0
us so as to avoid over-writing the previous data before it is
transferred to the transmitter's shift register.
Figure 3 shows a timing diagram for transmit operations.
The transmitter outputs are either direct or transformer
coupled to the MIL-STD-1553 data bus. Both coupling
methods produce a nominal voltage on the main
MIL-STD-1553 bus of 7.5 volts peak-to-peak, line-to-line.
Figure 6 shows bus coupling examples.
One or both transmitters may be disabled by writing a '1'
into SAM register bits 0 or 1 (TXDISA, TXDISB). When disabled, the host interface works as normal, but there is no
output from the BUSA and BUSA (BUSB and BUSB) pins.
RECEIVER
The HI-1575's two receivers continuously monitor both
MIL-STD-1553 data busses. Bi-phase differential data
words are accepted from the MIL-STD-1553 bus through
the same direct or transformer coupled interface as the
transmitter. Each receiver’s differential input stage drives
a filter and threshold comparator that presents data to the
decoders.
The decoder logic checks the incoming word for correct
encoding, bit count and parity. If a valid MIL-STD-1553
word is received, the RCVA or RCVB output goes high
and the 16-bit received word is transferred to the RXA or
RXB register. The HI-1575 ERROR output goes high
whenever an encoding error is detected on either bus. If
a received word has an encoding error, then SAM bits 10
or 14 (ERRORA, ERRORB) are set high, and the
corresponding RCVA or RCVB pin is not asserted.
To minimize the number of pins necessary to interface the
HI-1575, the state of RCVA and RCVB can also be read
from SAM bits 7 and 11.
HOLT INTEGRATED CIRCUITS
3
SE
N
ER DD
R AT
G OR A
AP B
R B
SY
R NC
C B
V
ER B
R
G OR
AP A
R A
SY
R NC
C A
V
N A
ot
u
C se
H d
AN
TX
S
R YN
EN C
R B
EN
TX A
D
TX ISB
D
IS
A
HI-1575
STATUS & MODE REGISTER (SAM)
0
15 14 13 12 11 10 9
MSB
8
7
6
5
4
3
2
1
0
LSB
Bit Name
R/W
0
TXDISA
R/W
0
Writing TXDISA to a '1' disables the transmitter for MIL-STD-1553 bus A
1
TXDISB
R/W
0
Writing TXDISB to a '1' disables the transmitter for MIL-STD-1553 bus B
2
RENA
R/W
1
Setting RENA to a '1' enables the receiver for MIL-STD-1553 bus A. A '0' disables the
receiver causing the HI-1575 to ignore all activity on bus A.
3
RENB
R/W
1
Setting RENB to a '1' enables the receiver for MIL-STD-1553 bus B. A '0' disables the
receiver causing the HI-1575 to ignore all activity on bus B.
4
TXSYNC
R/W
0
The TXSYNC bit is logically ORed with the SYNC input pin during host write cycles to the
Transmit Data Register (TX). If TXSYNC OR SYNC is a '1' the transmitter prefixes the
transmitted word with a MIL-STD-1553 Command Sync. If TXSYNC OR SYNC is a '0'
during a write to TX, then the transmitted word has a MIL-STD-1553 Data Sync.
5
CHAN
R/W
0
The CHAN bit is logically ORed with the CHA/CHB input pin and the result used to Select
between MIL-STD-1553 bus A or B during write transfers to the TX register, or reading data
from the RX registers. When CHAN OR CHA/CHB is a '0' during a transmit operation,
data is transmitted on MIL-STD-1553 bus A. When the result is a '1', MIL-STD-1553
bus B is selected. During HI-1575 data read cycles, if CHAN OR CHA/CHB is a '0', the RXA
register is accessed, and if CHAN OR CHA/CHB is a '1' then the data is read from RXB.
6
-
Read-only
0
Not used. Internally set to '0'.
7
RCVA
Read-only
0
This bit reflects the state of the RCVA output pin. RCVA goes high whenever a new word is
received on MIL-STD-1553 bus A. The received word may be read by the host from the RXA
register. RCVA is reset on reading RXA or if the HI-1575 detects a new word arriving on bus A.
If the data words are contiguous, then RCVA will be high for about 3 us before the new word
resets it. The data is still available in the RXA register and may be retreived any time up until
the RCVA flag goes high again. If the user does not read the data, the word is lost when
the RCVA flag goes high on reception of the next word.
8
RSYNCA
Read-only
0
RSYNCA indicates the Sync of the last MIL-STD-1553 word received on bus A. RSYNCA is a
'0' for a Data sync, and a '1' for a Command Sync. When the RXA register is read, the
RSYNCA value is also output on the SYNC I/O pin.
9
GAPA
Read-only
0
GAPA is a '1' when there is no activity detected on MIL-STD-1553 bus A, for example during an
inter-message gap. GAPA is a '0' whenever the HI-1575 detects bus traffic.
10 ERRORA
Read-only
0
ERRORA goes high when the HI-1575 Manchester decoder receives an incorrectly encoded
word on MIL-STD-1553 bus A
11
Read-only
0
Same function as RCVA but for MIL-STD-1553 bus B.
RCVB
Default Description
12 RSYNCB
Read-only
0
Same function as RSYNCA but for MIL-STD-1553 bus B.
13 GAPB
Read-only
0
Same function as GAPA but for MIL-STD-1553 bus B.
14 ERRORB
Read-only
0
Same function as ERRORA but for MIL-STD-1553 bus B.
15 SENDDATA Read-only
1
SENDDATA goes high approximately 3.5 us after the start of a MIL-STD-1553 word
transmission. SENDATA goes low approximately 18.5 us after the start of a MIL-STD-1553
word transmission. If new a new data word is written to the TX register while SENDDATA is
high, that word will be transmitted contiguously after the currently transmitting word.
FIGURE 2. STATUS AND MODE REGISTER
HOLT INTEGRATED CIRCUITS
4
HI-1575
Write TX,
(MIL-STD-1553 Status word)
Write TX,
(MIL-STD-1553 Data word)
Read SAM,
check SENDDATA=1
D15 - D0
TXDATA
DON’T CARE
SAM
TXDATA
DON’T CARE
R/W
VALID
CHA/CHB
DON’T CARE
SYNC
DON’T CARE
REG
DON’T CARE
VALID
STRB
SYNC
BUSA (B)
SYNC
15
14
13
3
3
2
1
0
P
SYNC
SYNC
15
FIGURE 3. EXAMPLE TRANSMIT OPERATION
Read RXA or RXB,
(MIL-STD-1553 Data word)
Read SAM
BUSA (B)
SYNC
SYNC
15
14
13
12
2
1
0
P
SYNC
SYNC
15
14
13
RCVA (B)
R/W
DON’T CARE
CHA/CHB
DON’T CARE
REG
DON’T CARE
VALID
STRB
D15 - D0
SAM
SYNC
RXA (B)
SYNC
FIGURE 4. EXAMPLE RECEIVE OPERATION
CHAN OR CHA/CHB
0
1
X
REG
0
0
1
Register
Receiver A Data (RXA)
Receiver B Data (RXB)
Status & Mode Register (SAM)
FIGURE 5. HI-1575 REGISTER MAP
HOLT INTEGRATED CIRCUITS
5
12
HI-1575
The host reads the received word from the HI-1575 RXA or
RXB register. The data word is read by pulsing STRB low,
while R/W is high and REG is low. Figure 4 shows an
example receive operation. The SYNC output indicates
whether the word had a Command Sync (SYNC=1) or
Data Sync (SYNC=0). SAM register bits 8 and 12
(RSYNCA and RSYNCB) retain the Sync values for the
last word received on each bus.
MIL-STD-1553 BUS CONNECTION
The HI-1575 includes on-chip MIL-STD-1553 analog
transceivers which are designed to drive the primary
winding of a 1:2.5 turns-ratio MIL-STD-1553 isolation
transformer. Figure 6 shows how the HI-1575 may be
connected to the MIL-STD-1553 data bus as either a
direct coupled stub (Bus A example), or a transformer
coupled stub (Bus B example). Holt Integrated Circuits
offers a wide range of single-core and dual-core coupling
transformers suitable for use with the HI-1575.
SAM bits 2 or 3 (RENA, RENB) can be used to
independently enable or disable each receiver. Writing a
'1' to RENA enables receiver A. A '0' disables the receiver.
RENB performs the same function for the MIL-STD-1553
bus B.
Note that because each receiver is internally connected to
its transmitter, when a MIL-STD-1553 word is transmitted
by the HI-1575 it will also be received on the same
channel. This feature allows the terminal to self-monitor
data transmitted to the MIL-STD-1553 data bus.
3.3 V
VDD
CLK
12.0 MHz
55 Ohms
BUSA
STRB
MIL-STD-1553
BUS A
(Direct Coupled)
R/W
55 Ohms
BUSA
CHA/CHB
1:2.5
REG
Host CPU
D15:D0
SYNC
HI-1575
RCVA
RCVB
52.5 Ohms
BUSB
MIL-STD-1553
BUS B
(Transformer Coupled)
ERROR
MR
52.5 Ohms
BUSB
1:2.5
1:1.4
GND
FIGURE 6. MIL-STD-1553 BUS CONNECTION
Bit Period
Command Word
Data Word
Status Word
1
2
3
SYNC
4
5
6
7
8
TERMINAL ADDRESS
9
R/T
SYNC
SYNC
10 11 12 13 14 15 16 17 18 19 20
SUBADDRESS
/ MODE
DATA WORD
COUNT
P
P
DATA WORD
SYNC
SYNC
TERMINAL ADDRESS
ME
CODE FOR FAILURE MODES
SYNC
FIGURE 7. MIL-STD-1553 WORD FORMATS
HOLT INTEGRATED CIRCUITS
6
TF
P
HI-1575
TIMING DIAGRAMS
BIT PERIOD
BIT PERIOD
BIT PERIOD
t R1
BUSA - BUSA
(BUSB - BUSB)
t R1
COMMAND SYNC
t R1
BUSA - BUSA
(BUSB - BUSB)
t R1
DATA SYNC
t R3
BUSA - BUSA
(BUSB - BUSB)
t R2
t R2
t R3
ONE
t R2
ZERO
ONE
FIGURE 8. MIL-STD-1553 BUS RECEIVER TIMING
MID-SYNC
MID-SYNC
MID-PARITY
MID-SYNC
MID-PARITY
MID-PARITY
1553
BUS
COMMAND
DATA
tFH
WORD WITH ERROR
tFH
tFH
RCVA(B)
tFR
tFR
ERROR
tFR
tRF
tRF
tRF
STRB
(Read RXA)
(Read RXA)
(Read SAM)
FIGURE 9. HI-1575 RECEIVER TIMING
REG
REG
VALID
VALID
tRWH
tRWS
tRRH
tRRS
tSTR
tSTR
STRB
STRB
tDWS
tDRV
tDWH
D15:0
SYNC
VALID
tDRT
VALID
D15:0
SYNC
tCHRS
tCHWS
tCHWH
CHA/CHB
tCHRH
CHA/CHB
tRWRS
tRWWS
tRWRH
tRWWH
R/W
R/W
Figure 10. DATABUS TIMING - WRITE.
Figure 11. DATABUS TIMING - READ
HOLT INTEGRATED CIRCUITS
7
HI-1575
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Supply voltage (VDD)
Logic input voltage range
Receiver differential voltage
Driver peak output current
Power dissipation at 25°C
Solder Temperature
Junction Temperature
Storage Temperature
Supply Voltage
VDD....................................... 3.3V... ±5%
-0.3 V to +5 V
-0.3 V DC to +3.6 V
50 Vp-p
+1.0 A
1.0 W
275°C for 10 sec.
175°C
-65°C to +150°C
Temperature Range
Industrial Screening.........-40°C to +85°C
Hi-Temp Screening........-55°C to +125°C
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation
at the limits is not recommended.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
3.15
3.30
3.45
V
Operating Voltage
VDD
Total Supply Current
ICC1
Not Transmitting
4
10
mA
ICC2
Transmit one channel @
50% duty cycle
225
250
mA
ICC3
Transmit one channel @
100% duty cycle
425
500
mA
0.06
W
0.5
W
Power Dissipation
PD1
Not Transmitting
PD2
Transmit one channel @
100% duty cycle
Min. Input Voltage
(HI)
VIH
Digital inputs
Max. Input Voltage
(LO)
VIL
Digital inputs
Min. Input Current
(HI)
IIH
Digital inputs (without pull-down)
Max. Input Current
(LO)
IIL
Digital inputs (without pull-up)
Pull-up / Pull-down current
IPUD
Digital inputs and data bus
Min. Output Voltage
(HI)
VOH
IOUT = -1.0mA, Digital outputs
Max. Output Voltage
(LO)
VIH
IOUT = 1.0mA, Digital outputs
RECEIVER
0.3
70%
VDD
30%
VDD
20
µA
-20
µA
275
uA
90%
VDD
10%
VDD
(Measured at Point “AD“ in Figure 12 unless otherwise specified)
Input resistance
Input capacitance
RIN
Differential
CIN
Differential
2
5
Common mode rejection ratio
CMRR
40
Input common mode voltage
VICM
-10.0
Detect
VTHD
No Detect
VTHND
Threshold Voltage - Direct-coupled
Theshold Voltage - Transformer-coupled
Detect
VTHD
No Detect
VTHND
Kohm
1 Mhz Sine Wave
(Measured at Point “AD“ in Figure 12)
1.15
1 MHz Sine Wave
(Measured at Point “AT“ in Figure 13)
0.86
pF
dB
+10.0
V-pk
Vp-p
0.28
Vp-p
Vp-p
0.20
Vp-p
6.0
9.0
Vp-p
18.0
27.0
Vp-p
10.0
mVp-p
-90
90
mV
-250
250
mV
TRANSMITTER(Measured at Point “AD” in Figure 12 unless otherwise specified)
Output Voltage
Direct coupled
VOUT
Transformer coupled
VOUT
Output Noise
VON
Output Dynamic Offset Voltage
Direct coupled
VDYN
Transformer coupled
VDYN
35 ohm load
(Measured at Point “AD“ in Figure 12)
70 ohm load
(Measured at Point “AT“ in Figure 13)
Differential, inhibited
35 ohm load
(Measured at Point “AD“ in Figure 12)
70 ohm load
(Measured at Point “AT“ in Figure 13)
HOLT INTEGRATED CIRCUITS
8
HI-1575
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, TA =Operating Temperature Range (unless otherwise specified)
PARAMETER
TRANSMITTER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
(Measured at Point “AD” in Figure 12)
RiseTtime
tr
35 ohm load
100
300
ns
Fall Time
tf
35 ohm load
100
300
ns
RECEIVER (See figures 8 and 9)
Sync Transition Span
tR1
1500
ns
Short Data Transition Span
Long Data Transition Span
tR2
500
ns
tR3
1000
Delay Mid-Parity to Flag Set
tFH
Flag Setup Time to Read
tFR
Flag Reset Delay
tRF
DATA BUS TIMING - WRITE
ns
2500
0
ns
ns
60
ns
(See figure 10)
Strobe STRB Pulse Width
tSTR
50
ns
REG Write Setup Time
tRWS
50
ns
REG Write Hold Time
tRWH
10
ns
Databus / SYNC Write Setup Time
tDWS
50
ns
Databus / SYNC Write Hold Time
tDWH
10
ns
CHA/CHB Write Setup Time
tCHWS
50
ns
CHA/CHB Write Hold Time
tCHWH
10
ns
R/W Write Setup Time
tRWWS
50
ns
R/W Write Hold Time
tRWWH
10
ns
Strobe STRB Pulse Width
tSTR
50
ns
REG Read Setup Time
tRRS
50
ns
REG Read Hold Time
tRRH
10
Data Read to Databus Valid
tDRV
DATA BUS TIMING - READ (See figure 11)
ns
60
ns
60
ns
Data Read to Databus Tri-state
tDRT
0
CHA/CHB Read Setup Time
tCHRS
50
ns
CHA/CHB Read Hold Time
tCHRH
10
ns
R/W Read Setup Time
tRWRS
50
ns
R/W Read Hold Time
tRWRH
10
ns
HI-1575 TRANSMITTER
1:2.5
55 W
BUSA/B
35 W
BUSA/B
Isolation
Transformer
55 W
Point “AD“
55 W
2.5:1
35 W
55 W
Point “AD“
Isolation
Transformer
FIGURE 12. DIRECT COUPLED TEST CIRCUITS
HOLT INTEGRATED CIRCUITS
9
HI-1575 RECEIVER
HI-1575
HI -1575 TRANSMITTER
1:2.5
Point
“AT”
1:1.4
BUSA/B
52.5 W
(.75 Zo)
35 W (.5 Zo)
BUSA/B
52.5 W
(.75 Zo)
Isolation
Transformer
Coupling
Transformer
1.4:1
Point
“AT” 2.5:1
52.5 W
(.75 Zo)
HI-1575 RECEIVER
35 W (.5 Zo)
52.5 W
(.75 Zo)
Coupling
Transformer
Isolation
Transformer
FIGURE 13. TRANSFORMER COUPLED TEST CIRCUITS
HEAT SINKING THE LEADLESS PLASTIC
CHIP CARRIER PACKAGE
The HI-1575PCI/T is packaged in a 40 pin leadless plastic
chip carrier (QFN). This package has a metal heat sink
pad on its bottom surface, which should be soldered to
the printed circuit board for optimum thermal dissipation.
The package heat sink is electrically isolated and may be
soldered to any convenient power plane or ground plane.
Redundant "vias" between the exposed board surface
and buried power or ground plane will enhance thermal
conductivity.
APPLICATIONS NOTE
Holt Applications Note AN-500 provides circuit design
notes regarding the use of Holt MIL-STD-1553 data
communications devices. Layout considerations, as well
as recommended interface and protection components
are included.
HOLT INTEGRATED CIRCUITS
10
HI-1575
THERMAL CHARACTERISTICS
PACKAGE STYLE
CONDITION
qJA
HI-1575PQI / T
32 pin PQFP
Mounted on
circuit board
59.5
°C / W
HI-1575PCI / T
40 pin LPCC
Heat sink pad
soldered
27.5
°C / W
PART NUMBER
ORDERING INFORMATION
HI - 1575 xx x x
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
Blank
100% Matte Tin (Pb-free, RoHS compliant)
F
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
I
NO
T
-55°C TO +125°C
T
NO
M
-55°C TO +125°C
M
YES
PART
NUMBER
PQ
PC
PACKAGE
DESCRIPTION
32 PIN PLASTIC PQFP (32PTQS)
40 PIN CHIP SCALE PACKAGE (40PCS) (PCM not available)
HOLT INTEGRATED CIRCUITS
11
HI-1575
REVISION HISTORY
P/N
DS1575
Rev
Date
D
04/20/11
Description of Change
Added REG input to block diagram. Corrected D.C. Electrical Characteristics Table and
package thickness dimension for the 32PTQS.
HOLT INTEGRATED CIRCUITS
12
PACKAGE DIMENSIONS
32 PIN PLASTIC QUAD FLAT PACK (PQFP)
inches (millimeters)
Package Type: 32PQS
.0057 ± .002
(0.145 ± .06)
.354 BSC SQ
(9.00)
.0315
BSC
(0.80)
.276 BSC SQ
(7.00)
.015 ± .003
(0.375 ± .075)
.024 ± .006
(0.60 ± .15)
.039 ± .002
(1.0 ± .05)
.006 ± .002
(0.14 ± .06) R
See Detail A
0° £ Q £ 7°
.047
max
(1.20)
.004 ± .002
(0.10 ± .05)
.003
R min
(.08)
Detail A
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
40-PIN PLASTIC CHIP-SCALE PACKAGE
millimeters
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
6.00 BSC
Package Type: 40PCS
4.15 ± .15
0.50 BSC
6.00 BSC
Top View
4.15 ± .15
Bottom
View
0.25 typ
0.55 ± .10
See Detail A
1.00 max
0.2 typ
0.90 ± .10
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
13
0.02 typ
Detail A
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