MR4A08BCMA35R

MR4A08B FEATURES 2M x 8 MRAM Memory • +3.3 Volt power supply • Fast 35 ns read/write cycle • SRAM compatible timing • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • RoHS-compliant small footprint BGA and TSOP2 packages • All products meet MSL-3 moisture sensitivity level BENEFITS • One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs • Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR4A08B is a 16,777,216-bit magnetoresistive random access memory (MRAM) device organized as 2,097,152 words of 8 bits. The MR4A08B offers SRAM compatible 35ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by lowvoltage inhibit circuitry to prevent writes with voltage out of specification. The RoHS MR4A08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR4A08B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-II package or 10 mm x 10 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are compatible with similar low-power SRAM products and other non-volatile RAM products. The MR4A08B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial (0 to +70 °C) and industrial (-40 to +85 °C) operating temperature range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 11 5. MECHANICAL DRAWING.......................................................................... 12 6. REVISION HISTORY...................................................................................... 14 How to Reach Us.......................................................................................... 15 Copyright © 2018 Everspin Technologies 1 MR4A08B Rev. 8.7 3/2018 MR4A08B 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT ENABLE BUFFER G A[20:0] 21 ADDRESS BUFFER OUTPUT ENABLE 10 11 ROW DECODER COLUMN DECODER CHIP ENABLE BUFFER E 8 8 OUTPUT BUFFER 8 2M x 8 BIT MEMORY ARRAY WRITE ENABLE BUFFER W SENSE AMPS 8 FINAL WRITE DRIVERS 8 WRITE DRIVER 8 DQ[7:0] WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection Copyright © 2018 Everspin Technologies 2 MR4A08B Rev. 8 .7 3/2018 MR4A08B DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View) DC A20 A A A A A E VDD VSS W A A A A A DC DC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DC A19 DC A A A A G VSS 1 2 3 4 5 6 DC G A A A DC A NC DC A A E DC B DQ NC A A NC DQ C VSS DQ A DQ VDD D VDD DQ DQ VSS E DQ3 NC NC DQ F NC G VDD DC A A A NC A A 20 A DC A A W A A A 19 H DC DC 44 Pin TSOP2 48 Pin FBGA Table 1.2 Operating Modes E1 G1 W1 Mode VDD Current DQ[7:0]2 H X X Not selected ISB1, ISB2 Hi-Z L H H Output disabled IDDR Hi-Z L L H Byte Read IDDR DOut L X L Byte Write IDDW Din 1 H = high, L = low, X = don’t care 2 Hi-Z = high impedance Copyright © 2018 Everspin Technologies 3 MR4A08B Rev. 8.7 3/2018 MR4A08B 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Table 2.1 Absolute Maximum Ratings1 Parameter Symbol Value Unit Supply voltage2 VDD -0.5 to 4.0 V Voltage on any pin2 VIN -0.5 to VDD + 0.5 V Output current per pin IOUT ±20 mA Package power dissipation 3 PD 0.600 W Temperature under bias MR4A08B (Commercial) MR4A08BC (Industrial) TBIAS -10 to 85 -45 to 95 °C Storage Temperature Tstg -55 to 150 °C Lead temperature during solder (3 minute max) TLead 260 °C Hmax_write 8000 A/m Hmax_read 8000 A/m Maximum magnetic field during write MR4A08B (All Temperatures) Maximum magnetic field during read or standby 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. Power dissipation capability depends on package characteristics and use environment. 3 Copyright © 2018 Everspin Technologies 4 MR4A08B Rev. 8 .7 3/2018 MR4A08B Electrical Specifications Table 2.2 Operating Conditions Parameter Symbol Min Typical Max Unit Power supply voltage VDD 3.0 1 3.3 3.6 V Write inhibit voltage VWI 2.5 2.7 3.0 1 V Input high voltage VIH 2.2 - VDD + 0.3 2 V Input low voltage VIL -0.5 3 - 0.8 V Temperature under bias MR4A08B (Commercial) TA MR4A08BC (Industrial) 0 70 -40 85 °C 1. There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below. 2. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA. 3. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA. Power Up and Power Down Sequencing MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 2.1 Power Up and Power Down Diagram VWIDD VDD STARTUP 2 ms READ/WRITE INHIBITED BROWNOUT or POWER LOSS NORMAL OPERATION READ/WRITE INHIBITED 2 ms RECOVER NORMAL OPERATION VIH VIH E W Copyright © 2018 Everspin Technologies 5 MR4A08B Rev. 8.7 3/2018 MR4A08B Electrical Specifications Table 2.3 DC Characteristics Parameter Symbol Min Typical Max Unit Input leakage current Ilkg(I) - - ±1 μA Output leakage current Ilkg(O) - - ±1 μA VOL - - 0.4 V Output low voltage (IOL = +4 mA) (IOL = +100 μA) Output high voltage VSS + 0.2 (IOL = -4 mA) VOH (IOL = -100 μA) 2.4 - - V VDD - 0.2 Table 2.4 Power Supply Characteristics Parameter Symbol AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) Typical Max Unit IDDR 60 68 mA IDDW 152 180 mA ISB1 9 14 mA ISB2 5 9 mA AC active supply current - write modes1 (VDD= max) AC standby current (VDD= max, E = VIH) no other restrictions on other inputs CMOS standby current (E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V) (VDD = max, f = 0 MHz) 1 All active current measurements are measured with one address transition per cycle and at minimum cycle time. Copyright © 2018 Everspin Technologies 6 MR4A08B Rev. 8 .7 3/2018 MR4A08B 3. TIMING SPECIFICATIONS Table 3.1 Capacitance1 Parameter 1 Symbol Typical Max Unit Address input capacitance CIn - 6 pF Control input capacitance CIn - 6 pF Input/Output capacitance CI/O - 8 pF Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3.1 Output load for all other timing parameters See Figure 3.2 f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested. Table 3.2 AC Measurement Conditions Parameter Logic input pulse levels Figure 3.1 Output Load Test Low and High ZD= 50 Ω Output RL = 50 Ω VL = 1.5 V Figure 3.2 Output Load Test All Others 3.3 V 590 Ω Output 5 pF 435 Ω Copyright © 2018 Everspin Technologies 7 MR4A08B Rev. 8.7 3/2018 MR4A08B Timing Specifications Read Mode Table 3.3 Read Cycle Timing1 Parameter Symbol Min Max Unit Read cycle time tAVAV 35 - ns Address access time tAVQV - 35 ns Enable access time2 tELQV - 35 ns Output enable access time tGLQV - 15 ns Output hold from address change tAXQX 3 - ns Enable low to output active3 tELQX 3 - ns Output enable low to output active3 tGLQX 0 - ns Enable high to output Hi-Z3 tEHQZ 0 15 ns Output enable high to output Hi-Z3 tGHQZ 0 10 ns W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2 Addresses valid before or at the same time E goes low. 3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. 1 Figure 3.3A Read Cycle 1 t AVAV A (ADDRESS) t AXQX Q (DATA OUT) Previous Data Valid Data Valid t AVQV Note: Device is continuously selected (E≤VIL, G≤VIL). Figure 3.3B Read Cycle 2 t AVAV A (ADDRESS) t AVQV E (CHIP ENABLE) t ELQV t EHQZ t ELQX G (OUTPUT ENABLE) t GLQX Data Valid Q (DATA OUT) Copyright © 2018 Everspin Technologies t GHQZ t GLQV 8 MR4A08B Rev. 8 .7 3/2018 MR4A08B Timing Specifications Table 3.4 Write Cycle Timing 1 (W Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 18 - ns Address valid to end of write (G low) tAVWH 20 - ns 15 - ns 15 - ns tWLWH Write pulse width (G high) tWLEH tWLWH Write pulse width (G low) tWLEH Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns Write low to data Hi-Z3 tWLQZ 0 12 ns Write high to output active3 tWHQX 3 - ns Write recovery time tWHAX 12 - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 All write cycle timings are referenced from the last valid address to the first transition address. 3 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given voltage or temperature, tWLQZ(max) < tWHQX(min) 1 Figure 3.4 Write Cycle Timing 1 (W Controlled) t AVAV A (ADDRESS) t AVWH t WHAX E (CHIP ENABLE) t WLEH t WLWH W (WRITE ENABLE) t AVWL t DVWH D (DATA IN) t WHDX DATA VALID t WLQZ Q (DATA OUT) Hi -Z Hi -Z t WHQX Copyright © 2018 Everspin Technologies 9 MR4A08B Rev. 8.7 3/2018 MR4A08B Timing Specifications Table 3.5 Write Cycle Timing 2 (E Controlled)1 Parameter Symbol Min Max Unit Write cycle time 2 tAVAV 35 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 18 - ns Address valid to end of write (G low) tAVEH 20 - ns 15 - ns 15 - ns tELEH Enable to end of write (G high) tELWH tELEH Enable to end of write (G low) 3 tELWH Data valid to end of write tDVEH 10 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 All write cycle timings are referenced from the last valid address to the first transition address. 3 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. 1 Figure 3.5 Write Cycle Timing 2 (E Controlled) t AVAV A (ADDRESS) t EHAX t AVEH t ELEH E (CHIP ENABLE) t AVEL t ELWH W (WRITE ENABLE) t DVEH D (DATA IN) Q (DATA OUT) Copyright © 2018 Everspin Technologies t EHDX Data Valid Hi-Z 10 MR4A08B Rev. 8 .7 3/2018 MR4A08B 4. ORDERING INFORMATION Figure 4.1 Part Numbering System MR 4 A 08 B C YS 35 R Carrier (Blank = Tray, R = Tape & Reel) Speed (35 ns) Package (YS = TSOP2, MA = FBGA) Temperature Range (Blank= Commercial (0 to +70°C), C= Industrial (-40 to +85°C) Revision Data Width (08 = 8-Bit) Type (A = Asynchronous) Density (4 =16Mb) Magnetoresistive RAM (MR) Table 4.1 Available Parts Grade Temp Range Package 44-TSOP2 Commercial 0 to +70°C 48-BGA 44-TSOP2 Industrial -40 to +85°C 48-BGA Copyright © 2018 Everspin Technologies 11 Shipping Container Tray Tape and Reel Tray Tape and Reel Tray Part Number MR4A08BYS35 MR4A08BYS35R MR4A08BMA35 MR4A08BMA35R MR4A08BCYS35 Tape and Reel MR4A08BCYS35R Tray Tape and Reel MR4A08BCMA35 MR4A08BCMA35R MR4A08B Rev. 8.7 3/2018 MR4A08B 5. MECHANICAL DRAWING Figure 5.1 TSOP2 Print Version Not To Scale 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protrusion. 4. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58. Copyright © 2018 Everspin Technologies 12 MR4A08B Rev. 8 .7 3/2018 MR4A08B Mechanical Drawings Figure 5.2 FBGA BOTTOM VIEW TOP VIEW (DATUM B) PIN A1 INDEX PIN A1 INDEX 6 5 4 3 2 1 A (DATUM A) B C D E F G H SEATING PLANE SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS ø 0.35mm Ref Min Nominal Max A 1.19 1.27 1.35 A1 0.22 0.27 0.32 b D E D1 E1 DE SE e 0.31 0.36 0.41 Ref aaa bbb ddd eee fff 10.00 BSC 10.00 BSC Not To Scale 5.25 BSC 3.75 BSC 1. Dimensions in Millimeters. 0.375 BSC 2. The ‘e’ represents the basic solder ball grid pitch. 0.75 BSC 3. ‘b’ is measurable at the maximum solder ball diameter in a plane parallel to datum C. Tolerance of, from and position 4. Dimension ‘ddd’ is measured parallel to primary datum C. 5. Primary datum C (seating plane) is defined by the crowns of the solder balls. 6. Package dimensions refer to JEDEC MO-205 Rev. G. 0.375 BSC 0.10 0.10 0.10 0.15 0.08 Copyright © 2018 Everspin Technologies 13 MR4A08B Rev. 8.7 3/2018 MR4A08B 6. REVISION HISTORY Revision Date Description of Change 1 2 May 29, 2009 July 27, 2009 Establish Speed and Power Specifications Increase BGA Package to 11 mm x 11 mm 3 May 5, 2010 Changed speed marking and timing specs to 35 ns part. Changed BGA package to 10 mm x 10mm 4 5 Aug 10, 2011 March 1, 2012 6 September 20, 2013 Replaced missing VOH specification line in Table 2.3. 7 April 25, 2014 AEC-Q100 removed until qualified product is available. 8 September 17, 2014 48-BGA package options moisture sensitivity level upgraded to MSL-5. 8.1 May 19, 2015 Revised Everspin contact information. 8.2 June 11, 2015 Corrected Japan Sales Office telephone number. 8.3 July 29, 2015 Minor correction to the ‘ddd’ tolerance value for the BGA Package (Note 4.) 8.4 March 11, 2016 The BGA package moisture sensitivity level rating is changed to MSL-6 in Table 4.1. 8.5 November 22, 2016 The BGA package moisture sensitivity level rating is changed to MSL-5 in Table 4.1. 8.6 May 9, 2017 The BGA package moisture sensitivity level is upgraded to MSL-3 8.7 March 23, 2018 Updated the Contact Us table Max. magnetic field during write (Hmax_write ) increased to 8000 A/m. Added preliminary information on AEC-Q100 Grade 1. Copyright © 2018 Everspin Technologies 14 MR4A08B Rev. 8 .7 3/2018 MR4A08B 7. HOW TO CONTACT US Everspin Technologies, Inc. How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © 2018 Everspin Technologies, Inc. Filename: EST00356_MR4A08B_Datasheet_Rev8.7032318 Copyright © 2018 Everspin Technologies 15 MR4A08B Rev. 8.7 3/2018