74HCT9046APW,118

74HCT9046A PLL with band gap controlled VCO Rev. 7 — 29 February 2016 Product data sheet 1. General description The 74HCT9046A. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits                Operation power supply voltage range from 4.5 V to 5.5 V Low power consumption Complies with JEDEC standard no. 7A Inhibit control for ON/OFF keying and for low standby power consumption center frequency up to 17 MHz (typical) at VCC = 5.5 V Choice of two phase comparators:  PC1: EXCLUSIVE-OR  PC2: Edge-triggered JK flip-flop No dead zone of PC2 Charge pump output on PC2, whose current is set by an external resistor Rbias center frequency tolerance 10 % Excellent Voltage Controlled Oscillator (VCO) linearity Low frequency drift with supply voltage and temperature variations On-chip band gap reference Glitch free operation of VCO, even at very low frequencies Zero voltage offset due to operational amplifier buffering ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V 74HCT9046A Nexperia PLL with band gap controlled VCO 3. Applications  FM modulation and demodulation where a small center frequency tolerance is essential  Frequency synthesis and multiplication where a low jitter is required (e.g. video picture-in-picture)  Frequency discrimination  Tone decoding  Data synchronization and conditioning  Voltage-to-frequency conversion  Motor-speed control 4. Ordering information Table 1. Ordering information Type number 74HCT9046AD Package Temperature range Name Description Version 40 C to +125 C plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT9046APW 40 C to +125 C 74HCT9046A Product data sheet SO16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © SOT403-1 Nexperia B.V. 2017. All rights reserved 2 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 5. Block diagram IRXW & ILQ &$  9&& &% 9&2B287 &203B,1 6,*B,1      $ 3&B287  3&3B287 5  5 3+$6( &203$5$725  9&2  3&B287 3+$6( &203$5$725  5%  5  5 5ELDV    '(0B287 9&2B,1 ,1+   *1' *1' 5 5 & 5V Fig 1. PEG Block diagram 6. Functional diagram  &203B,1  6,*B,1  5% 3&B287 3&3B287  3&B287  ĭ 3// $ ĭ    &$  &%  5   5 9&2B,1  ,1+ 9&2B287  9&2 '(0B287  &203B,1 6,*B,1  &$  &% Logic symbol 74HCT9046A Product data sheet    5  5 '(0B287   5% 9&2B287   9&2B,1  ,1+ PEG Fig 2. 3&B287 3&3B287 3&B287 PEG Fig 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 3 of 44 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x  &$  Nexperia 74HCT9046A Product data sheet IRXW & ILQ   &% 9&2B287 &203B,1  6,*B,1 3& 3&B287 3&3B287   9UHI  5 5 9&2 5 ORJLF  9UHI  ' 4 XS 3&3 &3 5 4 5' Rev. 7 — 29 February 2016 All information provided in this document is subject to legal disclaimers. 5 ORJLF   '(0B287 ' 3&B287  4 &3 9UHI 56 9UHI 4 5' GRZQ &+$5*( 3803  5 5 & 5%  %$1' *$3 9&2B,1 ,1+   5ELDV 9UHI Fig 4. Logic diagram 5  5ELDV PEG 74HCT9046A 4 of 44 PLL with band gap controlled VCO  74HCT9046A Nexperia PLL with band gap controlled VCO 7. Pinning information 7.1 Pinning +&7$ *1'   9&& 3&B2873&3B287   5% &203B,1   6,*B,1 9&2B287   3&B287 ,1+   5 &$   5 &%   '(0B287 *1'   9&2B,1 DDH Fig 5. Pin configuration 7.2 Pin description Table 2. Pin description Symbol Pin Description GND 1 ground (0 V) of phase comparators PC1_OUT/PCP_OUT 2 phase comparator 1 output or phase comparator pulse output COMP_IN 3 comparator input VCO_OUT 4 VCO output INH 5 inhibit input C1A 6 capacitor C1 connection A C1B 7 capacitor C1 connection B GND 8 ground (0 V) VCO VCO_IN 9 VCO input DEM_OUT 10 demodulator output R1 11 resistor R1 connection R2 12 resistor R2 connection PC2_OUT 13 phase comparator 2 output; current source adjustable with Rbias SIG_IN 14 signal input RB 15 bias resistor (Rbias) connection VCC 16 supply voltage 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 5 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 8. Functional description The 74HCT9046A is a phase-locked-loop circuit that comprises a linear VCO and two different phase comparators (PC1 and PC2) with a common signal input amplifier and a common comparator input, see Figure 1. The signal input can be directly coupled to large voltage signals (CMOS level), or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 74HCT9046A forms a second-order loop PLL. The principle of this phase-locked-loop is based on the familiar 74HCT4046A. However extra features are built-in, allowing very high-performance phase-locked-loop applications. This is done, at the expense of PC3, which is skipped in this 74HCT9046A. The PC2 is equipped with a current source output stage here. Further a band gap is applied for all internal references, allowing a small center frequency tolerance. The details are summed up in Section 8.1. If one is familiar with the 74HCT4046A already, it will do to read this section only. 8.1 Differences with respect to the familiar 74HCT4046A • A center frequency tolerance of maximum 10 %. • The on board band gap sets the internal references resulting in a minimal frequency shift at supply voltage variations and temperature variations. • The value of the frequency offset is determined by an internal reference voltage of 2.5 V instead of VCC  0.7 V; In this way the offset frequency will not shift over the supply voltage range. • A current switch charge pump output on pin PC2_OUT allows a virtually ideal performance of PC2; The gain of PC2 is independent of the voltage across the low-pass filter; Further a passive low-pass filter in the loop achieves an active performance. The influence of the parasitic capacitance of the PC2 output plays no role here, resulting in a true correspondence of the output correction pulse and the phase difference even up to phase differences as small as a few nanoseconds. • Because of its linear performance without dead zone, higher impedance values for the filter, hence lower C-values, can be chosen; correct operation will not be influenced by parasitic capacitances as in case of the voltage source output using the 74HCT4046A. • No PC3 on pin RB but instead a resistor connected to GND, which sets the load/unload currents of the charge pump (PC2). • Extra GND pin 1 to allow an excellent FM demodulator performance even at 10 MHz and higher. • Combined function of pin PC1_OUT/PCP_OUT. If pin RB is connected to VCC (no bias resistor Rbias) pin PC1_OUT/PCP_OUT has its familiar function viz. output of PC1. If at pin RB a resistor (Rbias) is connected to GND it is assumed that PC2 has been chosen as phase comparator. Connection of Rbias is sensed by internal circuitry and this changes the function of pin PC1_OUT/PCP_OUT into a lock detect output (PCP_OUT) with the same characteristics as PCP_OUT of pin 1 of the 74HCT4046A. 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 6 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO • The inhibit function differs. For the 74HCT4046A a HIGH-level at the inhibit input (pin INH) disables the VCO and demodulator, while a LOW-level turns both on. For the 74HCT9046A a HIGH-level on the inhibit input disables the whole circuit to minimize standby power consumption. 8.2 VCO The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external resistor R1 (between pins R1 and GND) or two external resistors R1 and R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required (see Figure 4). The high input impedance of the VCO simplifies the design of the low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. The DEM_OUT voltage equals that of the VCO input. If DEM_OUT is used, a series resistor (Rs) should be connected from pin DEM_OUT to GND; if unused, DEM_OUT should be left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator input (pin COMP_IN), or connected via a frequency divider. The output signal has a duty cycle of 50 % (maximum expected deviation 1 %), if the VCO input is held at a constant DC level. A LOW-level at the inhibit input (pin INH) enables the VCO and demodulator, while a HIGH-level turns both off to minimize standby power consumption. 8.3 Phase comparators The signal input (pin SIG_IN) can be directly coupled to the self-biasing amplifier at pin SIG_IN, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings. 8.3.1 Phase Comparator 1 (PC1) This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50 % duty cycle to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: V CC V DEM_OUT = ----------   SIG_IN –  COMP_IN   where: VDEM_OUT is the demodulator output at pin DEM_OUT VDEM_OUT = VPC1_OUT (via low-pass) V CC The phase comparator gain is: K p = ----------  V  r   The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin DEM_OUT (VDEM_OUT), is the resultant of the phase differences of signals (SIG_IN) and the comparator input (COMP_IN) as shown in Figure 6. The average of VDEM_OUT is equal to 0.5VCC when there is no signal or noise at SIG_IN and with this input the VCO oscillates at the center frequency (f0). Typical waveforms for the PC1 loop locked at f0 are shown in Figure 7. This figure also shows the 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 7 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO actual waveforms across the VCO capacitor at pins C1A and C1B (VC1A and VC1B) to show the relation between these ramps and the VCO_OUT voltage. The frequency capture range (2f0) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of the input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration remains locked even with very noisy input signals. Typical behavior of this type of phase comparator is that it may lock to input frequencies close to the harmonics of the VCO center frequency. PEG 9&& 9'(0B287$9 9&&  R  R ĭ3&B,1  R V CC V DEM_OUT = V PCI_OUT = ----------  SIG_IN –  COMP_IN   PC_IN =   SIG_IN –  COMP_IN  Fig 6. 74HCT9046A Product data sheet Phase comparator 1; average output voltage as a function of input phase difference All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 8 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 6,*1B,1 &203B,1 9&2B287 3&B287 9&& 9&2B,1 *1' 9&$ &$ 9&% &% PEG Fig 7. Typical waveforms for PLL using phase comparator 1; loop-locked at f0 8.3.2 Phase Comparator 2 (PC2) This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty cycles of SIG_IN and COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state output stage with sink and source transistors acting as current sources, henceforth called charge pump output of PC2. The circuit functions as an up-down counter (see Figure 4) where SIG_IN causes an up-count and COMP_IN a down count. The current switch charge pump output allows a virtually ideal performance of PC2, due to appliance of some pulse overlap of the up and down signals, see Figure 8a. The pump current Icp is independent from the supply voltage and is set by the internal band gap reference of 2.5 V. 2.5 I cp = 17  ------------  A  R bias Where Rbias is the external bias resistor between pin RB and ground. The current and voltage transfer function of PC2 are shown in Figure 9. The phase comparator gain is: I cp K P = ---------  A  r  2 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 9 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 9 && XS ,FS 9&& 3&B287 ,FS XS & 3&B287 5 GRZQ 9&B287 ,FS GRZQ ǻĭ ĭ3&B,1 SXOVHRYHUODSRI DSSUR[LPDWHO\QV PEG a. At every , even at zero  both switches are closed simultaneously for a short period (typically 15 ns). Fig 8. & PEG b. Comparable voltage-controlled switch The current switch charge pump output of PC2 9&& ,FS 9'(0B287$9  ,FSî5 9&&  ,FS  ʌ  ĭ3&B,1   ʌ ʌ DDN a. Current transfer I cp pump current --------- PC_IN 2  ĭ3&B,1 ʌ DDN b. Voltage transfer. This transfer can be observed at PC2_OUT by connecting a resistor (R = 10 k) between PC2_OUT and 0.5VCC. 5 V DEM_OUT = V PC2_OUT = ------ PC_IN 4  PC_IN =   SIG_IN –  COMP_IN  Fig 9. Phase comparator 2 current and voltage transfer characteristics When the frequencies of SIG_IN and COMP_IN are equal but the phase of SIG_IN leads that of COMP_IN, the up output driver at PC2_OUT is held ‘ON’ for a time corresponding to the phase difference (PC_IN). When the phase of SIG_IN lags that of COMP_IN, the down or sink driver is held ‘ON’. 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 10 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO When the frequency of SIG_IN is higher than that of COMP_IN, the source output driver is held ‘ON’ for most of the input signal cycle time and for the remainder of the cycle time both drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency, then it is the sink driver that is held ‘ON’ for most of the cycle. Subsequently the voltage at the capacitor (C2) of the low-pass filter connected to PC2_OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high-impedance. Also in this condition the signal at the phase comparator pulse output (PCP_OUT) has a minimum output pulse width equal to the overlap time, so can be used for indicating a locked condition. Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both output drivers are OFF for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of the low-pass filter. With no signal present at SIG_IN the VCO adjust, via PC2, to its lowest frequency. By using current sources as charge pump output on PC2, the dead zone or backlash time could be reduced to zero. Also, the pulse widening due to the parasitic output capacitance plays no role here. This enables a linear transfer function, even in the vicinity of the zero crossing. The differences between a voltage switch charge pump and a current switch charge pump are shown in Figure 11. 6,*B,1 &203B,1 9&2B287 QVW\SLFDO 83 3&B,1 '2:1 &855(17$7 3&B287 KLJKLPSHGDQFH2))VWDWH ]HURFXUUHQW 3&B2879&2B,1 3&3B287 PEG The pulse overlap of the up and down signals (typically 15 ns). Fig 10. Timing diagram for PC2 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 11 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO   9&2B,1  9&2B,1          SKDVHHUURUQV      SKDVHHUURUQV DDN  DDN (1) Due to parasitic capacitance on PC2_OUT. (2) Backlash time (dead zone). a. Response with traditional voltage-switch charge-pump PC2_OUT (74HCT4046A). b. Response with current switch charge-pump PC2_OUT as applied in the 74HCT9046A. Fig 11. The response of a locked-loop in the vicinity of the zero crossing of the phase error The design of the low-pass filter is somewhat different when using current sources. The external resistor R3 is no longer present when using PC2 as phase comparator. The current source is set by Rbias. A simple capacitor behaves as an ideal integrator now, because the capacitor is charged by a constant current. The transfer function of the voltage switch charge pump may be used. In fact it is even more valid, because the transfer function is no longer restricted for small changes only. Further the current is independent from both the supply voltage and the voltage across the filter. For one that is familiar with the low-pass filter design of the 74HCT4046A a relation may show how Rbias relates with a fictive series resistance, called R3'. This relation can be derived by assuming first that a voltage controlled switch PC2 of the 74HCT4046A is connected to the filter capacitance C2 via this fictive R3' (see Figure 8b). Then during the PC2 output pulse the charge current equals: V CC – V C2  0  I cp = ------------------------------R3' 2.5 With the initial voltage VC2(0) at: 0.5VCC = 2.5 V, I cp = ------R3' As shown before the charge current of the current switch of the 74HCT9046A is: 2.5 I cp = 17  -----------R bias Hence: R bias R3‘ = ------------    17 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 12 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO Using this equivalent resistance R3' for the filter design the voltage can now be expressed as a transfer function of PC2; assuming ripple (fr = fi) is suppressed, as: 5 K PC2 = ------  V  r  4 Again this illustrates the supply voltage independent behavior of PC2. 8.4 Loop filter component selection Examples of PC2 combined with a passive filter are shown in Figure 12 and 13. Figure 12 shows that PC2 with only a C2 filter behaves as a high-gain filter. For stability the damped version of Figure 13 with series resistance R4 is preferred. Practical design values for Rbias are between 25 k and 250 k with R3' = 1.5 k to 15 k for the filter design. Higher values for R3' require lower values for the filter capacitance which is very advantageous at low values of the loop natural frequency n. $ ,FS )MȦ ,FS  ,1387 5ELDV &  $IJ  287387  $IJ DDN a. Simple loop filter for PC2 without damping R bias  1 = ------------  C2 = R3'  C2 17  Ȧ DDN DDN b. Amplitude characteristic 1 1 F  j  = ----------------------------  ----------1  A + j 1 j 1 c. Pole zero diagram A = DC gain limit, due to leakage Fig 12. Simple loop filter for PC2 without damping 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 13 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO $ ,FS )MȦ ,FS  5ELDV 287387  $IJ 2   IJ  5 ,1387 P  &  $IJ  $IJ   DDN Ȧ DDN a. Simple loop filter for PC2 with damping b. Amplitude characteristic 1 + j 2 F  j  = ---------------------------1  A + j 1 R bias  1 = ------------  C2 = R3‘  C2 17 DDN c. Pole zero diagram A = DC gain limit, due to leakage  2 = R4  C2 Fig 13. Simple loop filter for PC2 with damping 9. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK Conditions Min Max 0.5 +7 V Unit VI < 0.5 V or VI > VCC + 0.5 V - 20 mA output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA 0.5 V < VO < VCC + 0.5 V IO output current - 25 mA ICC supply current - +50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C [1] Ptot derates linearly with 8 mW/K above 70 C. [2] Ptot derates linearly with 5.5 mW/K above 60 C. 74HCT9046A Product data sheet SO16 package [1] - 500 mW TSSOP16 package [2] - 500 mW All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 14 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 10. Recommended operating conditions Table 4. Operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate Min Typ Max Unit 4.5 5.0 5.5 V 0 - VCC V 0 - 40 pin INH; VCC = 4.5 V - VCC V +125 C 139 ns/V 1.67 11. Static characteristics Table 5. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit pins SIG_IN and COMP_IN; 3.15 2.4 - V - 2.1 1.35 V IO = 20 A 4.4 4.5 - V IO = 4.0 mA 3.98 4.32 - V IO = 20 A - 0 0.1 V IO = 4.0 mA - 0.15 0.26 V - - 30 A Tamb = 25 C Phase comparator section VIH HIGH-level input voltage VIL LOW-level input voltage VCC = 4.5 V; DC coupled pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled VOH VOL II HIGH-level output voltage LOW-level output voltage input leakage current pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL pins SIG_IN and COMP_IN; VCC = 5.5 V; VI = VCC or GND IOZ OFF-state output current pin PC2_OUT; VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND - - 0.5 A RI input resistance SIG_IN and COMP_IN; - 250 - k 25 - 250 k VCC = 4.5 V; VI at self-bias operating point; VI = 0.5 V; see Figure 14, 15 and 16 Rbias bias resistance VCC = 4.5 V Icp charge pump current VCC = 4.5 V; Rbias = 40 k VIH HIGH-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled 2.0 1.6 - V VIL LOW-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled - 1.2 0.8 V 0.53 1.06 2.12 mA VCO section 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 15 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = 20 A 4.4 4.5 - V IO = 4.0 mA 3.98 4.32 - V pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A - 0 0.1 V IO = 4.0 mA - 0.15 0.26 V pins C1A and C1B; VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA - - 0.40 V II input leakage current pins INH and VCO_IN; VCC = 5.5 V; VI = VCC or GND - - 0.1 A R1 resistor 1 VCC = 4.5 V 3 - 300 k R2 resistor 2 VCC = 4.5 V 3 - 300 k C1 capacitor 1 VCC = 4.5 V 40 - no limit pF VVCO_IN voltage on pin VCO_IN over the range specified for R1 VCC = 4.5 V 1.1 - 3.4 V VCC = 5.0 V 1.1 - 3.9 V VCC = 5.5 V 1.1 - 4.4 V 50 - 300 k Demodulator section Rs series resistance VCC = 4.5 V; at Rs > 300 k the leakage current can influence VDEM_OUT Voffset offset voltage VCO_IN to VDEM_OUT; VCC = 4.5 V; VI = VVCO_IN = 0.5VCC; values taken over Rs range; see Figure 17 - 20 - mV Rdyn dynamic resistance DEM_OUT; VCC = 4.5 V; VDEM_OUT = 0.5VCC - 25 -  ICC supply current disabled; VCC = 5.5 V; pin INH at VCC - - 8.0 A ICC additional supply current pin INH; VI = VCC  2.1 V; VCC = 4.5 V; other inputs at VCC or GND; - 100 360 A CI input capacitance - 3.5 - pF 3.15 - - V - - 1.35 V General Tamb = 40 C to +85 C Phase comparator section VIH HIGH-level input voltage pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled VIL LOW-level input voltage pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 16 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH HIGH-level output voltage pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL VOL LOW-level output voltage Min Typ Max Unit IO = 20 A 4.4 - - V IO = 4.0 mA 3.84 - - V pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A - - 0.1 V IO = 4.0 mA - - 0.33 V - - 38 A - - 5.0 A II input leakage current SIG_IN and COMP_IN; IOZ OFF-state output current PC2_OUT; VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND VIH HIGH-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled 2.0 - - V VIL LOW-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled - - 0.8 V VOH HIGH-level output voltage pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A 4.4 - - V IO = 4.0 mA 3.84 - - V IO = 20 A - - 0.1 V IO = 4.0 mA - - 0.33 V pins C1A and C1B; VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA - - 0.47 V pins INH and VCO_IN; - - 1.0 A VCC = 5.5 V; VI = VCC or GND VCO section VOL II LOW-level output voltage input leakage current pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL VCC = 5.5 V; VI = VCC or GND General ICC supply current disabled; VCC = 5.5 V; pin INH at VCC - - 80.0 A ICC additional supply current per input pin; VI = VCC  2.1 V; VCC = 4.5 V; other inputs at VCC or GND; - - 450 A 3.15 - - V - - 1.35 V Tamb = 40 C to +125 C Phase comparator section VIH HIGH-level input voltage pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled VIL LOW-level input voltage pins SIG_IN and COMP_IN; VCC = 4.5 V; DC coupled 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 17 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO Table 5. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max VOH HIGH-level output voltage pins PCP_OUT and PCn_OUT; Unit IO = 20 A 4.4 - - V IO = 4.0 mA 3.7 - - V IO = 20 A - - 0.1 V IO = 4.0 mA - - 0.4 V - - 45 A - - VCC = 4.5 V; VI = VIH or VIL VOL LOW-level output voltage pins PCP_OUT and PCn_OUT; VCC = 4.5 V; VI = VIH or VIL II input leakage current pins SIG_IN and COMP_IN; VCC = 5.5 V; VI = VCC or GND 10.0 A OFF-state output current pin PC2_OUT; VCC = 5.5 V; VI = VIH or VIL; VO = VCC or GND VIH HIGH-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled 2.0 - - V VIL LOW-level input voltage pin INH; VCC = 4.5 V to 5.5 V; DC coupled - - 0.8 V VOH HIGH-level output voltage pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A 4.4 - - V IO = 4.0 mA 3.7 - - V IOZ VCO section VOL II LOW-level output voltage input leakage current pin VCO_OUT; VCC = 4.5 V; VI = VIH or VIL IO = 20 A - - 0.1 V IO = 4.0 mA - - 0.4 V pins C1A and C1B; VCC = 4.5 V; VI = VIH or VIL; IO = 4.0 mA - - 0.54 V pins INH and VCO_IN; - - 1.0 A 160.0 A VCC = 5.5 V; VCC or GND General ICC supply current disabled; VCC = 5.5 V; pin INH at VCC - - ICC additional supply current per input pin; VI = VCC  2.1 V; VCC = 4.5 V; other inputs at VCC or GND; - - 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © 490 A Nexperia B.V. 2017. All rights reserved 18 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PEG ,, PJD  5, Nȍ ǻ9,   9&&  9  VHOIELDVRSHUDWLQJSRLQW  9&&  9, Fig 14. Typical input resistance curve at SIG_IN and COMP_IN PJD  9 9&& 9 9&& 9,9 9&& Fig 15. Input resistance at SIG_IN; COMP_IN with VI = 0.5 V at self-bias point PJD  9RIIVHW P9  9 ,, —$  9&&  9  9  9&&  9   9 9&& 9,9 9&&   9&&  9&& 9&& 99&2B,19 ___ Rs = 50 k - - - Rs = 300 k Fig 16. Input current at SIG_IN; COMP_IN with VI = 0.5 V at self-bias point 74HCT9046A Product data sheet Fig 17. Offset voltage at demodulator output as a function of VCO_IN and Rs All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 19 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 12. Dynamic characteristics Table 6. Dynamic characteristics[1] GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol Parameter Conditions Min Typ Max Unit - 23 40 ns - 35 68 ns Tamb = 25 C Phase comparator section tpd propagation delay SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V; see Figure 18 SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V; see Figure 18 ten enable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 - 30 56 ns tdis disable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 - 36 65 ns tt transition time VCC = 4.5 V; see Figure 18 - 7 15 ns - 50 - mV 10 - +10 peak-to-peak input voltage pin SIGN_IN or COMP_IN; VCC = 4.5 V; AC coupled; fi = 1 MHz [4] f frequency deviation VCC = 5.0 V; VVCO_IN = 3.9 V; R1 = 10 k; R2 = 10 k; C1 = 1 nF [5] f0 center frequency VCC = 4.5 V; duty cycle = 50 %; VVCO_IN = 0.5VCC; R1 = 4.3 k; R2 =  ; C1 = 40 pF; see Figure 23 and 31 11.0 15.0 - MHz VCC = 5 V; duty cycle = 50 %; VVCO_IN = 0.5VCC; R1 = 3 k; R2 =  ; C1 = 40 pF; see Figure 23 and 31 - 16.0 - MHz - 0.4 - % - 50 - % - 20 - pF - - 50 ns - - 85 ns Vi(p-p) VCO section f/f relative frequency variation VCC = 4.5 V; R1 = 100 k; R2 =  ; C1 = 100 pF; see Figure 24 and 25  duty cycle VCO_OUT; VCC = 4.5 V [6] % General CPD [2][3] power dissipation capacitance Tamb = 40 C to +85 C Phase comparator section tpd propagation delay SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V; see Figure 18 SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V; see Figure 18 ten enable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 - - 70 ns tdis disable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 - - 81 ns tt transition time VCC = 4.5 V; see Figure 18 - - 19 ns 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 20 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO Table 6. Dynamic characteristics[1] …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol Parameter Conditions frequency variation with temperature VCC = 4.5 V; VVCO_IN = 0.5VCC; recommended range: R1 = 10 k; R2 = 10 k; C1 = 1 nF; see Figure 20, 21 and 22 Min Typ Max Unit - 0.06 - %/K - - 60 ns - - 102 ns VCO section f/T [7] Tamb = 40 C to +125 C Phase comparator section propagation delay tpd SIG_IN, COMP_IN to PC1_OUT; VCC = 4.5 V; see Figure 18 SIG_IN, COMP_IN to PCP_OUT; VCC = 4.5 V; see Figure 18 ten enable time SIG_IN, COMP_IN to PC2_OUT; VCC = 4.5 V; see Figure 19 - - 84 ns tdis disable time SIG_IN, COMP_IN to PC2_OUT; - - 98 ns - - 22 ns VCC = 4.5 V; see Figure 19 tt transition time VCC = 4.5 V; see Figure 18 [1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH; tt is the same as tTLH and tTHL. [2] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; (CL  VCC2  fo) = sum of outputs. [3] Applies to the phase comparator section only (pin INH = HIGH). For power dissipation of the VCO and demodulator sections, see Figure 26, 27 and 28. [4] This is the (peak to peak) input sensitivity. [5] This is the center frequency tolerance. [6] This is the frequency linearity. [7] This is the frequency stability with temperature change. 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 21 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 90 6,*B,1&203B,1 LQSXWV W3+/ 3&3B2873&B287 RXWSXWV W3/+ 90 W7+/ W7/+ PEG VM = 0.5VCC; VI = GND to VCC. Fig 18. Waveforms showing input (SIG_IN and COMP_IN) to output (PCP_OUT and PC1_OUT) propagation delays and the output transition times 6,*B,1 LQSXW 90 &203B,1 LQSXW 90 W3+= W3=+ W3=/ W3/=  3&B287 RXWSXW 90  PJD VM = 0.5VCC; VI = GND to VCC. Fig 19. Waveforms showing the enable and disable times for PC2_OUT 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 22 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PEG  ǻI  ǻI  PEG       9&&  9&&   9 9   9 9         7DPEƒ& a. R1 = 3 k; R2 =  ; C1 = 100 pF.         7DPEƒ& b. R1 = 10 k; R2 =  ; C1 = 100 pF. Fig 20. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter PEG  9&& ǻI  9 9  ǻI  PEG    9&&   9               7DPEƒ& a. R1 = 300 k; R2 =  ; C1 = 100 pF.     9     7DPEƒ& b. R1 =  ; R2 = 3 k; C1 = 100 pF. Fig 21. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 23 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PEG  PEG  ǻI  ǻI      9&&  9&& 9  9  9 9         7DPEƒ& a. R1 =  ; R2 = 10 k; C1 = 100 pF.         7DPEƒ& b. R1 =  ; R2 = 300 k; C1 = 100 pF. Fig 22. Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 24 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PEG  PEG  I9&2 I9&2 0+] N+]  9&& 9  9 9&& 9   9          a. R1 = 4.3 k; C1 = 39 pF. b. PEG  I9&2 PEG 9&2 +] 9&& 9  R1 = 4.3 k; C1 = 100 nF.  I N+] 9&& 9       IUHTXHQF\       99&2B,19 c. R1 = 300 k; C1 = 39 pF. 9  9 IUHTXHQF\   99&2B,19 99&2B,19  99&2B,19 d. R1 = 300 k; C1 = 100 nF. Fig 23. Graphs showing VCO frequency as a function of the VCO input voltage (VVCO_IN) 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 25 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PEG  PJD I 0+] & —) 9 9 I9&2  &  S)  I 9 I I   I 9 PLQ 9 9  PD[ 9&& f1 + f2 f‘ 0 = -------------2 f‘ 0 – f 0 linearity = ----------------  100 % f0 Fig 24. Definition of VCO frequency linearity: V = 0.5 V over the VCC range 9&& 3' :   PEG  9&& 9 & S) : 9 & —)   5Nȍ Fig 25. Frequency linearity as a function of R1, C1 and VCC 3' 9 & —)   R2 =   and V = 0.5 V PEG    99&2B,19  9 & S)  9 & S) 9 9 & —) 9 & S)      5Nȍ  R2 =   Product data sheet     5Nȍ  R1 =   Fig 26. Power dissipation as a function of R1 74HCT9046A  Fig 27. Power dissipation as a function of R2 All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 26 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PEG   3'(0 : 9&& 9 9       5VNȍ   Fig 28. Typical power dissipation as a function of Rs 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 27 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 13. Application information This information is a guide for the approximation of values of external components to be used with the 74HCT9046A in a phase-locked-loop system. Values of the selected components should be within the ranges shown in Table 7. Table 7. Survey of components Component Value R1 between 3 k and 300 k R2 between 3 k and 300 k R1 + R2 parallel value > 2.7 k C1 > 40 pF Table 8. Design considerations for VCO section Subject Phase comparator Design consideration VCO frequency without extra offset PC1, PC2 VCO frequency characteristic. With R2 =  and R1 within the range 3 k < R1 < 300 k, the characteristics of the VCO operation will be as shown in Figure 29a. (Due to R1, C1 time constant a small offset remains when R2 =  ). PC1 Selection of R1 and C1. Given f0, determine the values of R1 and C1 using Figure 31. PC2 Given fmax and f0 determine the values of R1 and C1 using Figure 31; use Figure 33 to obtain 2fL and then use this to calculate fmin. PC1, PC2 VCO frequency characteristic. With R1 and R2 within the ranges 3 k < R1 < 300 k < R2 < 300 k, the characteristics of the VCO operation is as shown in Figure 29b. PC1, PC2 Selection of R1, R2 and C1. Given f0 and fL determine the value of product R1C1 by using Figure 33. Calculate foff from the equation foff = f0  1.6fL. Obtain the values of C1 and R2 by using Figure 32. Calculate the value of R1 from the value of C1 and the product R1C1. PC1 VCO adjusts to f0 with PC_IN = 90 and VVCO_IN = 0.5VCC PC2 VCO adjusts to foffset with PC_IN = 360 and VVCO_IN = minimum VCO frequency with extra offset PLL conditions with no signal at pin SIG_IN 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 28 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PJD I 9&2 I PD[ I I / GXHWR 5& I PLQ 9 9&& 9&& 9 9&& 9&2B,1 a. Operating without offset; f0 = center frequency; 2fL = frequency lock range. PJD I 9&2 I PD[ I GXHWR 5& I/ I PLQ I RII I/ GXHWR 5& 9 9&& 9&& 9 9&& 9&2B,1 b. Operating with offset; f0 = center frequency; 2fL = frequency lock range. Fig 29. Frequency characteristic of VCO 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 29 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 13.1 Filter design considerations for PC1 and PC2 of the 74HCT9046A Figure 30 shows some examples of passive and active filters to be used with the phase comparators of the 74HCT9046A. Transfer functions of phase comparators and filters are given in Table 9. Table 9. Transfer functions of phase comparators and filters Phase comparator Explanation Figure Filter type Transfer function PC1 V CC K PC1 = ---------- V/r  Figure 30a passive filter without damping 1 F  j  = --------------------1 + j 1 1 = R3  C2; 2 = R4  C2; 3 = R4  C3; A = 105 = DC gain amplitude Figure 30b passive filter with damping 1 + j 2 F  j  = ------------------------------------1 + j   1 +  2  Figure 30c active filter with damping 1 + j 2 1 + j 2 F  j  = ---------------------------  --------------------1/A + j 1 j 1 5 K PC + ------V/r 4 Figure 30d passive filter with damping 1 + j 2 1 + j 2 F  j  = -----------------------------  --------------------1  A + j 1 j 1 PC2 1 = R3’  C2; 2 = R4  C2; Figure 30e 3 = R4  C3; R3' = Rbias/17; Rbias = 25 k to 250 k Table 10. A = 105 = DC gain amplitude active filter with damping 1 + j 2 1 + j 2 F  j  = ---------------------------  --------------------1/A + j 1 j 1 A = 105 = DC gain amplitude General design considerations Subject Phase comparator Design consideration PLL locks on harmonics at center frequency PC1 yes PC2 no Noise rejection at signal input PC1 high PC2 low PC1 fr = 2fi; large ripple content at PC_IN = 90 PC2 fr = fi; small ripple content at PC_IN = 0 AC ripple content when PLL is locked 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 30 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO $03/,78'( &+$5$&7(5,67,& 3& &,5&8,7 32/(=(52 ',$*5$0 ) MȦ 5 ;  IJ  IJ  &  D ) MȦ 5  IJ  &  IJ  2  IJ  5  IJ  IJ  & ;  IJ IJ E $ &  IJ  & 5  IJ   $ IJ  5 $ 2  IJ  ;  $ IJ  2  IJ  ;  $ IJ  2  IJ  ;  $ IJ  F 3& $ 5  IJ   IJ  5 $5 $ IJ  & G $ &  IJ  &  IJ  5 5 $ $ IJ  H PEG Fig 30. Passive and active filters for 74HCT9046A 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 31 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO PEG  I +]                        &S) (1) VCC = 5.5 V; R1 = 3 k. (2) VCC = 4.5 V; R1 = 3 k. (3) VCC = 5.5 V; R1 = 10 k. (4) VCC = 4.5 V; R1 = 10 k. (5) VCC = 5.5 V; R1 = 150 k. (6) VCC = 4.5 V; R1 = 150 k. (7) VCC = 5.5 V; R1 = 300 k. (8) VCC = 4.5 V; R1 = 300 k. R2 =  ; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 C. Fig 31. Typical value of VCO center frequency (f0) as a function of C1 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 32 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO IRII +] PEG                     &S) (1) VCC = 4.5 V to 5.5 V; R1 = 3 k. (2) VCC = 4.5 V to 5.5 V; R1 = 10 k. (3) VCC = 4.5 V to 5.5 V; R1 = 150 k. (4) VCC = 4.5 V to 5.5 V; R1 = 300 k. R1 =  ; VVCO_IN = 0.5VCC; INH = GND; Tamb = 25 C. Fig 32. Typical value of frequency offset as a function of C1 I/ +] PEG       9&&     9 9              5&V 2f L K v = --------------------------------------- 2  r  s  V  V VCO_IN range VVCO_IN = 1.1 V to (VCC  1.1) V Fig 33. Typical frequency lock range 2fL as a function of the product R1 and C1 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 33 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 13.2 PLL design example The frequency synthesizer used in the design example shown in Figure 34 has the following parameters: Output frequency: 2 MHz to 3 MHz Frequency steps: 100 kHz Settling time: 1 ms Overshoot: < 20 % The open loop gain is: H(s)  G(s) = K p  K f  K o  K n and the closed loop: u Kp  Kf  Ko  Kn ------- = ---------------------------------------------------i 1 + Kp  Kf  Ko  Kn where: Kp = phase comparator gain Kf = low-pass filter transfer gain Ko = Kv/s VCO gain Kn = 1n divider ratio The programmable counter ratio Kn can be found as follows: f OUT 2 MHz N min = ----------- = -------------------- = 20 f step 100 kHz f OUT 3 MHz N max = ----------- = --------------------- = 30 f step 100 kHz The VCO is set by the values of R1, R2 and C1; R2 = 10 k (adjustable). The values can be determined using the information in Table 8. With f0 = 2.5 MHz and fL = 500 kHz this gives the following values (VCC = 5.0 V): R1 = 30 k R2 = 30 k C1 = 100 pF The VCO gain is: 2f L  2 1 MHz 6 K v = ------------------------------------------ = -----------------  2  2.24  10 r  s  V  V CC – 1.1  – 1.1 2.8 The gain of the phase comparator PC2 is: 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 34 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 5 K p = ------------ = 0.4 V  r 4 Using PC2 with the passive filter as shown in Figure 34 results in a high gain loop with the same performance as a loop with an active filter. Hence loop filter equations as for a high gain loop should be used. The current source output of PC2 can be simulated then with a fictive filter resistance: R bias R3‘ = -----------17 The transfer functions of the filter is given by: 1 + s 2 K f = ----------------s 2 Where:  1 = R3‘  C2  2 = R4  C2 The characteristic equation is: 1 + K p  K f  K o  K n This results in: 1 + s 2 K v 1 + K p  ----------------- ------ K n = 0  s 1  s or: 2 2 s + sK p K v K n ----- + K p K v K n   1 = 0 1 This can be written as: 2 2 s + 2 n s +   n  = 0 with the natural frequency n defined as: n = Kp  Kv  Kn ------------------------------1 and the damping value given as:  = 0.5   2   n In Figure 35 the output frequency response to a step of input frequency is shown. The overshoot and settling time percentages are now used to determine n. From Figure 35 it can be seen that the damping ratio  = 0.707 will produce an overshoot of less than 20 % and settle to within 5 % at nt = 5. The required settling time is 1 ms. This results in: 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 35 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO 5 5 3  n = --- = ------------- = 5  10 r  s t 0.001 Rewriting the equation for natural frequency results in: Kp  Kv  Kn  1 = ------------------------------2  n  The maximum overshoot occurs at Nmax = 30; hence Kn = 130: 6 0.4  2.24  10 - = 0.0012  1 = -------------------------------------2 5000  30 When C2 = 470 nF, it follows: 1 0.0012 - = 2550  R3‘ = ------- = ------------------------–9 C2 470  10 Hence the current source bias resistance R bias = 17  2550 = 43 k With  = 0.707 (0.5  2  n) it follows: 0.707  2 = ------------------------- = 0.00028 0.5  5000 2 0.00028 - = 600  R4 = ------- = ------------------------–9 C2 470  10 For extra ripple suppression a capacitor C3 can be connected in parallel with R4, with an extra 3 = R4  C3. For stability reasons 3 should be < 0.12, hence C3 < 0.1C2 or C3 = 39 nF. 74HCT9046A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 29 February 2016 © Nexperia B.V. 2017. All rights reserved 36 of 44 74HCT9046A Nexperia PLL with band gap controlled VCO .S N+] 26&,//$725 +&8 ',9,'(%