XS1-L02A-QF124-C5-THS

XS1-L02A-QF124 Datasheet 2012/10/12 XMOS © 2012, All Rights Reserved Document Number: X1189, XS1-L02A-QF124 Datasheet 1 Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Features . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . Signal Description . . . . . . . . . . Block Diagram . . . . . . . . . . . . Product Overview . . . . . . . . . . DC and Switching Characteristics . Package Information . . . . . . . . Ordering Information . . . . . . . . Development Tools . . . . . . . . . Addendum: XMOS USB Interface . . Device Errata . . . . . . . . . . . . . Associated Design Documentation Related Documentation . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 7 8 15 19 20 20 20 21 22 22 23 TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/. XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation that the information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used without written permission. Company and product names mentioned in this document are the trademarks or registered trademarks of their respective owners. X1189, XS1-L02A-QF124 Datasheet 1 2 Features · Dual-Tile Multicore Microcontroller with Advanced Multi-Core RISC Architecture • Up to 1000 MIPS shared between up to 16 real-time logical cores • Each logical core has: — Guaranteed throughput of between 1/4 and 1/8 of tile MIPS — 16x32bit dedicated registers • 159 high-density 16/32-bit instructions — All have single clock-cycle execution (except for divide) — 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions · Programmable I/O • 84 general-purpose I/O pins, configurable as input or output • Port sampling rates of up to 60 MHz with respect to an external clock • 64 channel ends for communication with other cores, on or off-chip · Memory • 128KB internal single-cycle SRAM (max 64KB per tile) for code and data storage • 16KB internal OTP (max 8KB per tile) for application boot code · JTAG Module for On-Chip Debug · Security Features • Programming lock disables debug and prevents read-back of memory contents • AES bootloader ensures secrecy of IP held on external flash memory · Ambient Temperature Range • Commercial qualification: 0 °C to 70 °C • Industrial qualification: -40 °C to 85 °C · Speed Grade • 5: 500 MIPS • 4: 400 MIPS · Power Consumption • Active Mode — 400 mA at 500 MHz (typical) — 320 mA at 400 MHz (typical) • Standby Mode — 28 mA • Sleep Mode — Programmable PCU module puts device into sleep mode — Wakeup on external signal or timeout · 124-pin dual-row QFN package 0.5 mm pitch X1189, XS1-L02A-QF124 Datasheet A65 X0D20 A64 X0D19 A63 X0D18 A62 X0D23 A61 X0D17 A60 X0D16 A59 X0D15 A58 X0D14 A57 X0D13 A56 X0D22 A55 X0D12 A54 X0D24 X0D42 B54 X0D41 B53 X0D40 B52 X0D39 B51 X0D38 B50 X0D37 B49 X0D36 B48 X0D33 B47 X0D32 B46 X0D31 B45 X0D30 B44 VDD B43 A52 GND A51 VDDIO VDDIO A2 X0D35 A3 B1 VDDIO VDDIO B42 A50 X1D11 X0D34 A4 B2 PCU_WAKE X0D29 B41 A49 X1D10 X0D02 A5 B3 PCU_GATE X0D28 B40 A48 X1D09 X0D03 A6 B4 PCU_VDDIO X0D27 B39 A47 X1D08 X0D04 A7 B5 PCU_VDD X0D26 B38 A46 X1D07 X0D05 A8 B6 PCU_CLK DEBUG_N B37 A45 X1D06 X0D06 A9 B7 CLK MODE[3] B36 A44 X1D05 X0D07 A10 B8 RST_N MODE[2] B35 A43 X1D04 X0D08 A11 B9 TDO MODE[1] B34 A42 X1D03 X0D09 A12 B10 TCK MODE[0] B33 A41 X1D02 X0D10 A13 B11 TMS OTP_VCC B32 A40 X1D01 X0D11 A14 B12 TDI X1D39 B31 A39 X1D00 X0D00 A15 B13 TRST_N X1D38 B30 A38 PLL_AVDD X0D01 A16 B14 VDDIO VDDIO B29 A37 PLL_AGND GND B16 X1D26 B17 X1D27 B18 X1D28 B19 X1D29 B20 X1D30 B21 X1D31 B22 X1D32 B23 X1D33 B24 X1D34 B25 X1D35 B26 X1D36 B27 X1D37 B28 VDD X1D12 A21 X1D22 A22 X1D13 A23 X1D14 A24 X1D15 A25 X1D16 A26 X1D17 A27 X1D23 A28 X1D18 A29 X1D19 A30 X1D20 A31 X1D21 A32 X1D25 A33 VDD A34 B15 VDD VDD A19 A18 GND A36 VDDIO X1D24 A20 VDDIO A17 X1189, A53 VDD A66 X0D21 X0D43 B55 A68 VDD A1 GND A67 X0D25 Pin Configuration VDD B56 2 3 A35 MODE[4] XS1-L02A-QF124 Datasheet 3 4 Signal Description Module Signal Function Type Active Properties PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger Input, OT=Output Tristate, S=Switchable RS =Required for SPI boot (§5.6), RU =Required for USB-enabled devices (§10) Power PLL JTAG PCU GND Digital ground GND — VDD Digital tile power PWR — VDDIO Digital I/O power PWR — PLL_AGND Analog ground for PLL PWR — PLL_AVDD Analog PLL power PWR — PCU_VDD PCU tile power PWR — PCU_VDDIO PCU I/O supply PWR — OTP_VCC OTP power supply PWR — RST_N Global reset input Input Low CLK PLL reference clock Input — PD, ST MODE[4:0] Boot mode select Input — PU, ST TDI Test data input Input — PU, ST TDO Test data output Output — PD, OT TMS Test mode select Input — PU, ST TRST_N Test reset input Input Low TCK Test clock Input — PU, ST DEBUG_N Multi-chip debug I/O Low PU PCU_WAKE Wakeup reset Input — PD, ST PCU_GATE Power control gate control Output — OT PCU_CLK Clock input Input — PD, ST P1A0 I/O — PDS , RS P1B0 I/O — PDS , RS X0D00 Tile 0 I/O X0D01 XLA4o 5b X0D02 XLA3o 5b P4A0 P8A0 P16A0 P32A20 I/O — PDS , RU X0D03 XLA2o 5b P4A1 P8A1 P16A1 P32A21 I/O — PDS , RU X0D04 XLA1o 2b/5b P4B0 P8A2 P16A2 P32A22 I/O — PDS , RU X0D05 XLA0o 2b/5b P4B1 P8A3 P16A3 P32A23 I/O — PDS , RU X0D06 XLA0i 2b/5b P4B2 P8A4 P16A4 P32A24 I/O — PDS , RU X0D07 XLA1i 2b/5b P4B3 P8A5 P16A5 P32A25 I/O — PDS , RU X0D08 XLA2i 5b P4A2 P8A6 P16A6 P32A26 I/O — PDS , RU X0D09 XLA3i 5b P4A3 P8A7 P16A7 P32A27 I/O — PDS , RU X0D10 XLA4i 5b P1C0 I/O — PDS , RS X0D11 P1D0 I/O — PDS , RS X0D12 P1E0 I/O — PDS , RU P1F0 I/O — PDS , RU X0D13 XLB4o 5b X0D14 XLB3o 5b P4C0 P8B0 P16A8 P32A28 I/O — PDS , RU X0D15 XLB2o 5b P4C1 P8B1 P16A9 P32A29 I/O — PDS , RU X0D16 XLB1o 2b/5b P4D0 P8B2 P16A10 I/O — PDS , RU X0D17 XLB0o 2b/5b P4D1 P8B3 P16A11 I/O — PDS , RU (continued) X1189, XS1-L02A-QF124 Datasheet Module Tile 0 I/O 5 Name Function Type Active Properties X0D18 XLB0i 2b/5b P4D2 P8B4 P16A12 I/O — PDS , RU X0D19 XLB1i 2b/5b P4D3 P8B5 P16A13 I/O — PDS , RU X0D20 XLB2i 5b P4C2 P8B6 P16A14 P32A30 I/O — PDS , RU X0D21 XLB3i 5b P4C3 P8B7 P16A15 P32A31 I/O — PDS , RU X0D22 XLB4i 5b P1G0 I/O — PDS , RU X0D23 P1H0 I/O — PDS , RU X0D24 P1I0 I/O — PDS X0D25 P1J0 I/O — PDS X0D26 P4E0 P8C0 P16B0 I/O — PDS , RU X0D27 P4E1 P8C1 P16B1 I/O — PDS , RU X0D28 P4F0 P8C2 P16B2 I/O — PDS , RU X0D29 P4F1 P8C3 P16B3 I/O — PDS , RU X0D30 P4F2 P8C4 P16B4 I/O — PDS , RU X0D31 P4F3 P8C5 P16B5 I/O — PDS , RU X0D32 P4E2 P8C6 P16B6 I/O — PDS , RU X0D33 P4E3 P8C7 P16B7 I/O — PDS , RU X0D34 P1K0 I/O — PDS X0D35 P1L0 I/O — PDS X0D36 P1M0 P8D0 P16B8 I/O — PDS X0D37 P1N0 P8D1 P16B9 I/O — PDS , RU X0D38 P1O0 P8D2 P16B10 I/O — PDS , RU X0D39 P1P0 P8D3 P16B11 I/O — PDS , RU X0D40 P8D4 P16B12 I/O — PDS , RU X0D41 P8D5 P16B13 I/O — PDS , RU X0D42 P8D6 P16B14 I/O — PDS , RU X0D43 P8D7 P16B15 I/O — PUS , RU P1A0 I/O — PDS P1B0 I/O — PDS X1D00 Tile 1 I/O X1D01 XLA4o 5b X1D02 XLA3o 5b P4A0 P8A0 P16A0 P32A20 I/O — PDS , RU X1D03 XLA2o 5b P4A1 P8A1 P16A1 P32A21 I/O — PDS , RU X1D04 XLA1o 2b/5b P4B0 P8A2 P16A2 P32A22 I/O — PDS , RU X1D05 XLA0o 2b/5b P4B1 P8A3 P16A3 P32A23 I/O — PDS , RU X1D06 XLA0i 2b/5b P4B2 P8A4 P16A4 P32A24 I/O — PDS , RU X1D07 XLA1i 2b/5b P4B3 P8A5 P16A5 P32A25 I/O — PDS , RU X1D08 XLA2i 5b P4A2 P8A6 P16A6 P32A26 I/O — PDS , RU X1D09 XLA3i 5b P4A3 P8A7 P16A7 P32A27 I/O — PDS , RU X1D10 XLA4i 5b P1C0 I/O — PDS X1D11 P1D0 I/O — PDS X1D12 P1E0 I/O — PDS , RU P1F0 I/O — PDS , RU X1D13 XLB4o 5b X1D14 XLB3o 5b P4C0 P8B0 P16A8 P32A28 I/O — PDS , RU X1D15 XLB2o 5b P4C1 P8B1 P16A9 P32A29 I/O — PDS , RU X1D16 XLB1o 2b/5b P4D0 P8B2 P16A10 I/O — PDS , RU (continued) X1189, XS1-L02A-QF124 Datasheet Module Tile 1 I/O X1189, 6 Name Function Type Active Properties X1D17 XLB0o 2b/5b P4D1 P8B3 P16A11 I/O — PDS , RU X1D18 XLB0i 2b/5b P4D2 P8B4 P16A12 I/O — PDS , RU X1D19 XLB1i 2b/5b P4D3 P8B5 P16A13 I/O — PDS , RU X1D20 XLB2i 5b P4C2 P8B6 P16A14 P32A30 I/O — PDS , RU X1D21 XLB3i 5b P4C3 P8B7 P16A15 P32A31 I/O — PDS , RU X1D22 XLB4i 5b P1G0 I/O — PDS , RU X1D23 P1H0 I/O — PDS , RU X1D24 P1I0 I/O — PDS X1D25 P1J0 I/O — PDS X1D26 P4E0 P8C0 P16B0 I/O — PDS , RU X1D27 P4E1 P8C1 P16B1 I/O — PDS , RU X1D28 P4F0 P8C2 P16B2 I/O — PDS , RU X1D29 P4F1 P8C3 P16B3 I/O — PDS , RU X1D30 P4F2 P8C4 P16B4 I/O — PDS , RU X1D31 P4F3 P8C5 P16B5 I/O — PDS , RU X1D32 P4E2 P8C6 P16B6 I/O — PDS , RU X1D33 P4E3 P8C7 P16B7 I/O — PDS , RU X1D34 P1K0 I/O — PDS X1D35 P1L0 I/O — PDS X1D36 P1M0 P8D0 P16B8 I/O — PDS X1D37 P1N0 P8D1 P16B9 I/O — PDS , RU X1D38 P1O0 P8D2 P16B10 I/O — PDS , RU X1D39 P1P0 P8D3 P16B11 I/O — PDS , RU XS1-L02A-QF124 Datasheet Block Diagram Core 7 6 Clock Blocks 10 Timers 4 Locks X1189, ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ PLL 4A 4A Port 8B Port 8C 4E 1G 1H ¶ 1I ¶ 1J ¶ 1K 1L 1M 1N 1O 1P ¶ ¶ ¶ ¶ ¶ ¶ · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · X1D00 X1D01 X1D02 X1D03 X1D08 X1D09 X1D04 X1D05 X1D06 X1D07 X1D10 X1D11 X1D12 X1D13 X1D14 X1D15 X1D20 X1D21 X1D16 X1D17 X1D18 X1D19 X1D22 X1D23 X1D24 X1D25 X1D26 X1D27 X1D32 X1D33 X1D28 X1D29 X1D30 X1D31 X1D34 X1D35 X1D36 X1D37 X1D38 X1D39 6 Clock Blocks 64KB SRAM 64KB SRAM 7 Synchronizers TDI TCK TMS TRST_N DEBUG_N PLL_AVDD PLL_AGND CLK RST_N MODE[4:0] PCU_WAKE PCU_GATE PCU_CLK PCU_VDD PCU_VDDIO OTP_VCC VDD VDDIO GND Port 4D 4C Core 7 ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ Port 8D Core 6 Port 16B Core 6 XLE Core 5 Port 4F 4E 32 Channel Ends Switch XLG Core 4 XLF Switch XLG · · · · Core 3 Core 5 XLH Port 8C Port 16B 1K 1L 1M 1N 1O 1P Port 8D · · · · · · Core 4 · · · · · · · · 32 Channel Ends Port 8B XLF 4C Port 4D Core 3 4C 1G · 1H · 1I · 1J XLA Core 2 4C Core 2 1C 1D ¶ 1E ¶ 1F Port 16A Port 16A 1C · 1D · 1E 1F Core 1 Port 4B Port 8A XLH XLE Port 8A 4A Port 4B 4A Core 1 ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ XLB 1A ¶ 1B Core 0 Core 0 4E · · · · · · · · · · · 1A 1B Port 4F · · · · · · · · · · 4E ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ XLA X0D00 X0D01 X0D02 X0D03 X0D04 X0D05 X0D06 X0D07 X0D08 X0D09 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D23 X0D24 X0D25 X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D34 X0D35 X0D36 X0D37 X0D38 X0D39 X0D40 X0D41 X0D42 X0D43 XLB 4 7 10 Timers 4 Locks 7 Synchronizers JTAG JTAG Boot ROM Boot ROM Security Register Security Register PCU 8KB OTP 8KB OTP X0 X1 TDO PLL XS1-L02A-QF124 Datasheet 5 8 Product Overview The XMOS XS1-L02A-QF124 is a powerful device that provides a simple design process and highly-flexible solution to many applications. The device consists of two xCORE Tiles, each comprising a flexible multicore microcontroller with tightly integrated I/O and on-chip memory. The processors run mutiple tasks simultaneously using logical cores, each of which is guaranteed a slice of processing power and can execute computational code, control software and I/O interfaces. Logical cores use channels to exchange data within a tile or across tiles. The tiles are connected via an integrated switch network, which uses a proprietary physical layer protocol, and which can also be used to add additional resources to a design. The I/O pins are driven using intelligent ports that can serialize data, interpret strobe signals and wait for scheduled times or events, making the device ideal for real-time control applications. The device can be configured using a set of software components that are rapidly customized and composed. XMOS provides source code libraries for many standard components. The device can be programmed using high-level languages such as C/C++ and XMOS-originated extensions to C, called XC, that simplify the control over concurrency, I/O and time. The XMOS toolchain includes compilers, a simulator, debugger and static timing analyzer. The combination of real-time software, a compiler and timing analyzer enables the programmer to close timings on components of the design without a detailed understanding of the hardware characteristics. 5.1 Logical cores, Synchronizers and Locks Each xCORE Tile has up to eight active logical cores, which issue instructions down a shared four-stage pipeline. Instructions from the active cores are issued round-robin. If up to four logical cores are active, each core is allocated a quarter of the processing cycles. If more than four logical cores are active, each core is allocated at least 1/n cycles (for n cores). Figure 1 shows the guaranteed core performance depending on the number of cores used. Speed Grade Figure 1: Core performance Minimum MIPS per core (for n cores) 1 2 3 4 5 6 7 8 400 MHz 100 100 100 100 80 67 57 50 500 MHz 125 125 125 125 100 83 71 63 There is no way that the performance of a logical core can be reduced below these predicted levels. Because cores may be delayed on I/O, however, their unused processing cycles can be taken by other cores. This means that for more than four logical cores, the performance of each core is often higher than the predicted minimum. X1189, XS1-L02A-QF124 Datasheet 5.2 9 Channel Ends, Links and Switch Logical cores communicate using point-to-point connections formed between two channel ends. Between tiles, channel communications are implemented over xConnect Links and routed through switches. The links operate in either 2bit/direction or 5bit/direction mode, depending on the amount of bandwidth required. Circuit switched, streaming and packet switched data can both be supported efficiently. Streams provide the fastest possible data rates between xCORE Tiles (up to 250 MBit/s), but each stream requires a single link to be reserved between switches on two tiles. All packet communications can be multiplexed onto a single link. Information on the supported routing topologies that can be used to connect multiple devices together can be found in the XS1-L Link Performance and Design Guide, X2999. 5.3 Ports and Clock Blocks Ports provide an interface between the logical cores and I/O pins. All pins of a port provide either output or input. Signals in different directions cannot be mapped onto the same port. The operation of each port is synchronized to a clock block. A clock block can be connected to an external clock input, or it can be run from the divided reference clock. A clock block can also output its signal to a pin. On reset, each port is connected to clock block 0, which runs from the xCORE Tile reference clock. The ports and links are multiplexed, allowing the pins to be configured for use by ports of different widths or links. If an xConnect Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their specified width, even if they share pins with another port. 5.4 Timers Timers are 32-bit counters that are relative to the xCORE Tile reference clock. A timer is defined to tick every 10 ns. This value is derived from the reference clock, which is configured to tick at 100 MHz by default. 5.5 PLL The PLL creates a high-speed clock that is used for the switch, tile, and reference clock. The PLL multiplication value is selected through the two MODE pins, and can be changed by software to speed up the tile or use less power. The MODE pins are set as shown in Figure 2: Figure 2 also lists the values of OD, F and R, which are the registers that define the ratio of the tile frequency to the oscillator frequency: Fcor e = Fosc × X1189, F +1 1 1 × × 2 R+1 OD + 1 XS1-L02A-QF124 Datasheet Figure 2: PLL multiplier values and MODE pins Oscillator Frequency 5-13 MHz 13-20 MHz 20-48 MHz 48-100 MHz 10 MODE 1 0 0 0 1 1 1 0 0 1 Tile Frequency 130-399.75 MHz 260-400.00 MHz 167-400.00 MHz 196-400.00 MHz PLL Ratio 30.75 20 8.33 4 PLL settings OD F R 1 122 0 2 119 0 2 49 0 2 23 0 OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and 1 260MHz ≤ Fosc × F +1 × R+1 ≤ 1.3GHz. The OD, F , and R values can be modified 2 by writing to the digital node PLL configuration register. The MODE pins must be held at a static value until the third rising edge of the system clock following the deassertion of the system reset. For 500 MHz parts, once booted, the PLL must be reprogrammed to provide this tile frequency. The XMOS tools perform this operation by default. Further details on configuring the clock can be found in the XS1-L Clock Frequency Control document, X1433. 5.6 Boot ROM The xCORE Tile boot procedure is illustrated in Figure 3. In normal usage, MODE[4:2] controls the boot source according to the table in Figure 4. If bit 5 of the security register (see §5.7.1) is set, the device boots from OTP. Start Boot ROM Primary boot Security Register Bit [5] set No Yes OTP Figure 3: Boot procedure X1189, Copy OTP contents to base of SRAM Execute program Boot according to boot source pins XS1-L02A-QF124 Datasheet 11 MODE[4] MODE[3] MODE[2] Boot Source X 0 0 None: Device waits to be booted via JTAG X 0 1 Reserved 0 1 0 X0 boots from link B, X1 from channel end 0 via X0 X0 boots from SPI, X1 from channel end 0 via X0 0 Figure 4: Boot source pins 1 1 PinA Signal Description X0D00 MISO Master In Slave Out X0D01 SS Slave Select X0D10 SCLK Clock X0D11 MOSI Master Out Slave In 1 1 0 X0 and X1 independently enable link B and internal links (E, F, G, H), and boot from channel end 0 1 1 1 Both tiles boot from SPI independently A The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. An SPI boot program can be burned into OTP and used at any time. 5.7 OTP Each xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with a security register that configures system wide security features. The OTP holds data in 2k rows x 32-bit configuration which can be used to implement secure bootloaders and store encryption keys. Data for the security register is loaded from the OTP on power up. All additional data in OTP is copied from the OTP to SRAM and executed first on the processor. 5.7.1 Security Register The security register enables the following security features: · Secure Boot: The xCORE Tile is forced to boot from address 0 of the OTP, allowing the xCORE Tile boot ROM to be bypassed (see §5.6). This feature can be used to implement a secure bootloader which loads an encrypted image from external flash, decrypts and CRC checks it with the processor, and discontinues the boot process if the decryption or CRC check fails. XMOS provides a default secure bootloader that can be written to the OTP along with secret decryption keys. · Disable JTAG: The JTAG interface is disabled, making it impossible for the tile state or memory content to be accessed via the JTAG interface. · Disable Link access: Other tiles are forbidden access to the processor state via the system switch. Disabling both JTAG and Link access transforms an xCORE Tile into a “secure island” with other tiles free for non-secure user application code. · Disable Global Debug access: Disables access to the DEBUG_N pin. X1189, XS1-L02A-QF124 Datasheet 12 · OTP Master and Sector Lock: Further access to the OTP is prevented by setting the master lock. Locks can also be applied to each of the four OTP sectors individually. These security features provide a strong level of protection and are sufficient for providing strong IP security. 5.8 SRAM Each xCORE Tile integrates a single 64 KB SRAM bank for both instructions and data. All internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one tile clock cycle. There is no dedicated external memory interface, although data memory can be expanded through appropriate use of the ports. 5.9 JTAG The JTAG module can be used for loading programs, boundary scan testing, incircuit source-level debugging and programming the OTP memory. X0 X1 BS TAP TDI TDI TDO CHIP TAP TDI TDO BS TAP TDI TDO CHIP TAP TDI TDO TDO TCK TMS Figure 5: JTAG chain structure TRST_N DEBUG_N The JTAG chain structure is illustrated in Figure 5. Directly after reset, two TAP controllers are present in the JTAG chain for each xCORE Tile: the boundary scan TAP and the chip TAP. The boundary scan TAP is a standard 1149.1 compliant TAP that can be used for boundary scan of the I/O pins. The chip TAP provides access into the xCORE Tile, switch and OTP for loading code and debugging. The TRST_N pin must be asserted low during and after power up for 100 ns. If JTAG is not required, the TRST_N pin can be tied to ground to hold the JTAG module in reset. The DEBUG_N pin is used to synchronize the debugging of multiple xCORE Tiles. This pin can operate in both output and input mode. In output mode and when configured to do so, DEBUG_N is driven low by the device when the processor hits a debug break point. Prior to this point the pin will be tri-stated. In input mode and when configured to do so, driving this pin low will put the xCORE Tile into debug mode. Software can set the behavior of the xCORE Tile based on this pin. X1189, XS1-L02A-QF124 Datasheet 13 This pin should have an external pull up of 4K7-47K Ω or left not connected in single core applications. The JTAG device identification register can be read by using the IDCODE instruction. Its contents are specified in Figure 6. Figure 6: IDCODE return value Bit31 Device Identification Register Version 0 0 0 Bit0 Part Number 0 0 0 0 0 0 0 0 0 0 0 0 Manufacturer Identity 0 0 0 0 0 0 0 1 0 0 1 2 1 0 0 0 6 1 1 1 0 0 3 1 1 3 The JTAG usercode register can be read by using the USERCODE instruction. Its contents are specified in Figure 7. The OTP User ID field is read from bits [22:31] of the security register on xCORE Tile 0 (all zero on unprogrammed devices). Figure 7: USERCODE return value Bit31 Usercode Register OTP User ID 0 0 0 0 0 0 5.10 0 0 0 Bit0 Unused 0 0 0 0 0 0 Silicon Revision 0 0 1 2 0 1 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCU The PCU can be used to isolate the core voltage of the device and reapply it under a controlled condition known as sleep mode. In sleep mode, all data in the SRAM is lost. The device recovers into functional mode under the control of an external PCU_WAKE signal or an internal timer. If the PCU is not required, PCU_WAKE should be left unconnected, PCU_GATE should be left unconnected and PCU_CLK must be tied to CLK. 5.11 Power Supplies The device has the following types of power supply pins: · VDD pins for the xCORE Tile tile · VDDIO pins for the I/O lines · PLL_AVDD pins for the PLL · PCU_VDD and PCU_VDDIO pins for the PCU · OTP_VCC pins for the OTP Several pins of each type are provided to minimize the effect of inductance within the package, all of which must be connected. The power supplies must be brought up monotonically and input voltages must not exceed specification at any time. The VDD supply must ramp from 0 V to its final value within 10 ms to ensure correct startup. The VDDIO supply must ramp to its final value before VDD reaches 0.4 V. X1189, XS1-L02A-QF124 Datasheet 14 The PLL_AVDD supply should be separated from the other noisier supplies on the board. The PLL requires a very clean power supply, and a low pass filter (for example, a 2.2 Ω resistor and 100 nF multi-layer ceramic capacitor) is recommended on this pin. The PCU_VDD supply must be connected to the VDD supply. The PCU_VDDIO supply must be connected to the VDDIO supply. The OTP_VCC supply should be connected to the VDDIO supply. The following ground pins are provided: · PLL_AGND for PLL_AVDD · GND for all other supplies All ground pins must be connected directly to the board ground. The VDD and VDDIO supplies should be decoupled close to the chip by several 100 nF low inductance multi-layer ceramic capacitors between the supplies and GND (for example, 4x100nF 0402 low inductance MLCCs per supply rail). The ground side of the decoupling capacitors should have as short a path back to the GND pins as possible. A bulk decoupling capacitor of at least 10 uF should be placed on each of these supplies. RST_N is an active-low asynchronous-assertion global reset signal. Following a reset, the PLL re-establishes lock after which the device boots up according to the boot mode (see §5.6). RST_N and must be asserted low during and after power up for 100 ns. X1189, XS1-L02A-QF124 Datasheet 6 15 DC and Switching Characteristics 6.1 Operating Conditions Symbol Parameter MIN TYP MAX UNITS VDD Tile DC supply voltage 0.95 1.00 1.05 V VDDIO I/O supply voltage 3.00 3.30 3.60 V PLL_AVDD PLL analog supply 0.95 1.00 1.05 V PCU_VDD PCU tile DC supply voltage 0.95 1.00 1.05 V PCU_VDDIO PCU I/O DC supply voltage 3.00 3.30 3.60 V OTP_VCC OTP supply voltage 3.00 3.30 3.60 V Cl xCORE Tile I/O load capacitance Ambient operating temperature (Commercial) Ta Figure 8: Operating conditions Ambient operating temperature (Industrial) Tj Junction temperature Tstg Storage temperature 6.2 Figure 9: DC characteristics 25 pF 0 70 °C -40 85 °C 125 °C -65 150 °C Notes DC Characteristics Symbol Parameter MIN MAX UNITS Notes V(IH) Input high voltage 2.00 TYP 3.60 V A V(IL) Input low voltage -0.30 0.70 V A V(OH) Output high voltage V B, C V(OL) Output low voltage V B, C R(PU) Pull-up resistance 35K Ω D R(PD) Pull-down resistance 35K Ω D 2.70 0.60 A All pins except power supply pins. B Ports 1A, 1D, 1E, 1H, 1I, 1J, 1K and 1L are nominal 8 mA drivers, the remainder of the general-purpose I/Os are 4 mA. C Measured with 4 mA drivers sourcing 4 mA, 8 mA drivers sourcing 8 mA. D Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be used to pull external circuitry. 6.3 Figure 10: ESD stress voltage X1189, ESD Stress Voltage Symbol Parameter HBM Human body model MM Machine model MAX UNITS -2.00 MIN TYP 2.00 KV -200 200 V Notes XS1-L02A-QF124 Datasheet 6.4 Figure 11: Reset timing 16 Reset Timing Symbol Parameters MIN T(RST) Reset pulse width 5 T(INIT) Initialization time TYP MAX UNITS Notes us 150 µs A A Shows the time taken to start booting after RST_N has gone high. 6.5 Figure 12: xCORE Tile currents Power Consumption Symbol Parameter I(DDCQ) Quiescent VDD current PD Tile power dissipation IDD I(ADDPLL) UNITS Notes 28 mA A, B, C 450 µW/MIPS A, D, E, F Active VDD current (Speed Grade 4) 320 600 mA A, G Active VDD current (Speed Grade 5) 400 600 mA A, H mA I PLL_AVDD current MIN TYP MAX 14 A B C D E F G Use for budgetary purposes only. Assumes typical tile and I/O voltages with no switching activity. Includes PLL current. Assumes typical tile and I/O voltages with nominal switching activity. Assumes 1 MHz = 1 MIPS. PD(TYP) value is the usage power consumption under typical operating conditions. Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 400 MHz, average device resource usage. H Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 500 MHz, average device resource usage. I PLL_AVDD = 1.0 V The tile power consumption of the device is highly application dependent and should be used for budgetary purposes only. More detailed power analysis can be found in the XS1-L Power Consumption document, X2999. X1189, XS1-L02A-QF124 Datasheet 6.6 17 Clock Symbol Parameter MIN TYP MAX UNITS f Frequency 4.22 20 100 MHz SR Slew rate 0.10 TJ(LT) Long term jitter (pk-pk) 2 % A f(MAX) Processor clock frequency (Speed Grade 4) 400 MHz B Processor clock frequency (Speed Grade 5) 500 MHz B Figure 13: Clock Notes V/ns A Percentage of CLK period. B Assumes typical tile and I/O voltages with nominal activity. Further details can be found in the XS1-L Clock Frequency Control document, X1433. 6.7 Figure 14: I/O AC characteristics xCORE Tile I/O AC Characteristics Symbol Parameter MIN TYP MAX UNITS T(XOVALID) Input data valid window 8 T(XOINVALID) Output data invalid window 9 T(XIFMAX) Rate at which data can be sampled with respect to an external clock Notes ns ns 60 MHz The input valid window parameter relates to the capability of the device to capture data input to the chip with respect to an external clock source. It is calculated as the sum of the input setup time and input hold time with respect to the external clock as measured at the pins. The output invalid window specifies the time for which an output is invalid with respect to the external clock. Note that these parameters are specified as a window rather than absolute numbers since the device provides functionality to delay the incoming clock with respect to the incoming data. Information on interfacing to high-speed synchronous interfaces can be found in the XS1 Port I/O Timing document, X5821. 6.8 Figure 15: Link performance xConnect Link Performance Symbol Parameter MAX UNITS Notes B(2blinkP) 2b link bandwidth (packetized) MIN TYP 87 MBit/s A, B B(5blinkP) 5b link bandwidth (packetized) 217 MBit/s A, B B(2blinkS) 2b link bandwidth (streaming) 100 MBit/s B B(5blinkS) 5b link bandwidth (streaming) 250 MBit/s B A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header and payload. B 7.5 ns symbol time. X1189, XS1-L02A-QF124 Datasheet 18 The asynchronous nature of links means that the relative phasing of CLK clocks is not important in a multi-clock system, providing each meets the required stability criteria. 6.9 Figure 16: JTAG timing JTAG Timing Symbol Parameter f(TCK_D) TCK frequency (debug) MIN TYP MAX UNITS 18 MHz 10 MHz f(TCK_B) TCK frequency (boundary scan) T(SETUP) TDO to TCK setup time 5 ns A T(HOLD) TDO to TCK hold time 5 ns A T(DELAY) TCK to output delay ns B 15 Notes A Timing applies to TMS and TDI inputs. B Timing applies to TDO output from negative edge of TCK. All JTAG operations are synchronous to TCK apart from the global asynchronous reset TRST_N. X1189, XS1-L02A-QF124 Datasheet 7 Package Information X1189, 19 XS1-L02A-QF124 Datasheet 20 7.1 Part Marking Manufacturing date code Qualification/Speed grade (optional) MCYYWWFN QS Figure 17: Part marking scheme 8 LLLLLL.LL Lot code Ordering Information Figure 18: Orderable part numbers Product Code XS1–L02A–QF124–C4 XS1–L02A–QF124–C5 XS1–L02A–QF124–I4 XS1–L02A–QF124–I5 Marking MCYYWWL2 MCYYWWL2 C5 MCYYWWL2 I4 MCYYWWL2 I5 Qualification Commercial Commercial Industrial Industrial XS1–L02A–QF124-C5-THS * MCYYWWL2 TH5 Commercial Speed Grade 400 MHz 500 MHz 400 MHz 500 MHz 500 MHz * MOQ and signed license agreement with XMOS required for access to Thesycon USB Audio Class 2.0 Production Driver (XS1-L2 Windows). 9 Development Tools XMOS provides a comprehensive suite of development tools. Source files, timing scripts and a board design file are input to the compiler toolchain which produces a binary executable. This executable file can be simulated, loaded onto the device and debugged over JTAG, programmed into flash memory on the board or written to OTP memory on the device. The tools can also encrypt the flash image and write the decrpytion key securely to OTP memory. The tools can be driven from either a graphical development environment or the command line and are supported on Windows, Linux and MacOS X. The tools are available at no cost from xmos.com/downloads. Information on using the tools is provided in a separate user guide, X1013. X1189, XS1-L02A-QF124 Datasheet 21 10 Addendum: XMOS USB Interface XMOS provides a low-level USB interface for connecting the device to a USB transceiver using the UTMI+ Low Pin Interface (ULPI). The ULPI signals must be connected to the pins named in Figure 19. Note also that some ports on the same tile are used internally and are not available for use when the USB driver is active (they are available otherwise). Pin Pin Signal Pin XnD02 XnD12 ULPI_STP XnD26 XnD03 XnD13 ULPI_NXT XnD27 XnD04 XnD14 ULPI_DATA[0] XnD28 XnD15 ULPI_DATA[1] XnD29 XnD16 ULPI_DATA[2] XnD30 XnD17 ULPI_DATA[3] XnD31 XnD08 XnD18 ULPI_DATA[4] XnD32 XnD09 XnD19 ULPI_DATA[5] XnD33 XnD20 ULPI_DATA[6] XnD21 ULPI_DATA[7] XnD37 XnD22 ULPI_DIR XnD38 XnD23 ULPI_CLK XnD39 XnD05 XnD06 XnD07 Figure 19: ULPI signals provided by the XMOS USB driver 11 Signal Unavailable when USB active XnD40 XnD41 Signal Unavailable when USB active Unavailable when USB active XnD42 XnD43 Device Errata This section describes minor operational differences from the data sheet and recommended workarounds. As device and documentation issues become known, this section will be updated the document revised. To guarantee a logic low is seen on the pins RST_N, DEBUG_N, MODE[4:0], TRST_N, TMS, TCK and TDI, the driving circuit should present an impedance of less than 100 Ω to ground. Usually this is not a problem for CMOS drivers driving single inputs. If one or more of these inputs are placed in parallel, however, additional logic buffers may be required to guarantee correct operation. For static inputs tied high or low, the relevant input pin should be tied directly to GND or VDDIO. X1189, XS1-L02A-QF124 Datasheet 12 22 Associated Design Documentation Document Title Information Document Number XS1-L Hardware Design Checklist Board design checklist X6277 Device Package User Guide Land pattern, solder paste, ground recommendations X4979 Estimating Power Consumption For XS1-L Devices Power consumption X4271 Programming XC on XMOS Devices Timers, ports, clocks, cores and channels X9577 XMOS Tools User Guide Compilers, assembler and linker/mapper X1013 Timing analyzer and debugger Flash and OTP programming utilities · Example schematic diagrams detailing minimal system configurations are available from http://www.xmos.com/support/silicon. 13 Related Documentation Document Title Information Document Number The XMOS XS1 Architecture ISA manual X7879 XS1 Port I/O Timing Port timings X5821 XS1-L System Specification Link, switch and system information X2725 XS1-L Link Performance and Design Guidelines Link timings X2999 XS1-L Clock Frequency Control Advanced clock control X1433 XS1-L Active Power Conservation Low-power mode during idle X5512 X1189, XS1-L02A-QF124 Datasheet 14 Revision History The page numbers in this section refer to this document. Rev. X1189L–10/12 1. Renamed XCore to xCORE Tile, and Thread to Core. 2. Instruction description updated - page 2. 3. Updated PL section - page 9. Rev. X1189K–05/12-B 1. Block diagram updated: pins listed sequentially, 4-bit ports updated - page 7. Rev. X1189J–05/12 1. Input voltage use for 1-bit ports updated footnote on page 15. 2. Pull up/down information updated for JTAG/MODE pins on page 4. 3. Updated use of TRST_N on page 12. 4. Clarified tables of pins used by USB Interface on page 20. 5. OTP section updated and moved before SRAM on page 12. Rev. X1189I–03/12 1. Removed “Volatile” from Memory description on page 2. Rev. X1189H–05/11 1. Changed XMOS Link references to XLA format in Signal Description on page 4. Rev. X1189G–01/11 1. Replaced “Port Pin Table” with “Signal Description” on page 4. 2. Updated “ULPI” on page 20 with set of disabled signals. 3. Removed “Device Configuration”. 4. Added “Associated Design Documentation” on page 22. 5. Renamed OTP_VDDIO to OTP_VCC. 6. Renamed DEBUG to DEBUG_N. 7. Updated Figure 12 on page 16 by adding max value for IDD. 8. Removed Preliminary designation for all characterization data. Rev. X1189F–06/10 1. Updated “Errata” on page 21 to correct pin A35. 2. Updated “USB ULPI Mode” on page 20 to correct pin A23. Rev. X1189E–05/10 1. Added “USB ULPI Mode” on page 20. 2. Added C5, I4 and I5 parts. X1189, 23 XS1-L02A-QF124 Datasheet 24 Rev. X1189D–03/10 1. 2. 3. 4. Added “Power Supply Sequencing”. Added Figure 4 on page 11. Changed from ‘Preliminary’ to ‘Release’. Editorial updates. Rev. X1189C–01/10-B 1. Added “Precedence” on page 9. 2. Added “Power Control Unit” on page 13. 3. Added “SPI Interface’ on page 11. Rev. X1189B–01/10 1. Added “Package Marking” on page 20. 2. Updated “Miscellaneous Control Signals”. 3. Added ring position to pin table. Rev. X1189A–12/09 1. Initial revision. Copyright © 2012, All Rights Reserved. Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. X1189,