XS1-G04B-FB512-C4

XS1-G04B-FB512 Datasheet 2012/10/15 XMOS © 2012, All Rights Reserved Document Number: X1066, XS1-G04B-FB512 Datasheet 1 Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 Features . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . Signal Description . . . . . . . . . . Block Diagram . . . . . . . . . . . . Product Overview . . . . . . . . . . DC and Switching Characteristics . Package Information . . . . . . . . Ordering Information . . . . . . . . Development Tools . . . . . . . . . Addendum: XMOS USB Interface . . Associated Design Documentation Related Documentation . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4 11 13 20 23 24 24 24 25 26 27 TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. 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X1066, XS1-G04B-FB512 Datasheet 1 2 Features · Quad-Tile Multicore Microcontroller with Advanced Multi-Core RISC Architecture • Up to 1600 MIPS shared between up to 32 real-time logical cores • Each logical core has: — Guaranteed throughput of between 1/4 and 1/8 of tile MIPS — 16x32bit dedicated registers • 159 high-density 16/32-bit instructions — All have single clock-cycle execution (except for divide) — 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions · Programmable I/O • 256 general-purpose I/O pins, configurable as input or output • Port sampling rates of up to 60 MHz with respect to an external clock • 128 channel ends for communication with other cores, on or off-chip · Memory • 256KB internal single-cycle SRAM (max 64KB per tile) for code and data storage • 32KB internal OTP (max 8KB per tile) for application boot code · JTAG Module for On-Chip Debug · Security Features • Programming lock disables debug and prevents read-back of memory contents • AES bootloader ensures secrecy of IP held on external flash memory · Ambient Temperature Range • Commercial qualification: 0 °C to 70 °C • Industrial qualification: -40 °C to 85 °C · Speed Grade • 400 MHz part: 400 MIPS · 512-pin PBGA package 0.8 mm pitch X1066, XS1-G04B-FB512 Datasheet 2 3 Pin Configuration 1 2 3 4 5 6 7 8 A IO VDD IO VDD X0D61 X0D63 X0D65 VSS X0D67 B IO VDD IO VDD NC X0D62 X0D64 VSS X0D66 C NC X0D58 IO VDD X0D37 X0D39 X0D41 D X0D57 X0D56 X0D35 IO VDD X0D36 X0D38 E X0D55 X0D54 X0D33 X0D34 IO VDD X0D13 X0D15 X0D17 VSS X0D19 X0D21 X0D23 X3D23 F VSS VSS X0D31 X0D32 X0D11 IO VDD X0D12 X0D14 X0D16 X0D18 X0D20 X0D22 X3D22 G X0D53 X0D52 VSS X0D30 X0D09 X0D10 IO VDD SS_PLL_ BYPASS SS_ BYPASS_ PLL_ LOCK VDD VDD SS_ RESET SS_OTP_ VREF VDD H X0D51 X0D50 X0D29 VSS X0D07 9 10 11 12 13 14 15 X0D69 NC IO VDD NC NC NC NC X0D68 X0D70 IO VDD NC NC NC NC VSS X0D43 NC NC IO VDD NC NC X0D40 VSS X0D42 NC NC NC NC 16 17 18 19 20 21 22 23 24 VSS NC X3D69 X3D67 IO VDD X3D65 X3D63 X3D61 VSS VSS VSS X3D70 X3D68 X3D66 IO VDD X3D64 X3D62 NC VSS VSS VSS NC NC X3D43 IO VDD X3D41 X3D39 X3D37 VSS X3D58 NC NC NC X3D42 IO VDD X3D40 X3D38 X3D36 VSS X3D35 X3D56 X3D57 X3D21 X3D19 IO VDD X3D17 X3D15 X3D13 VSS X3D34 X3D33 X3D54 X3D55 X3D20 X3D18 X3D16 X3D14 X3D12 VSS X3D11 X3D32 X3D31 IO VDD IO VDD VDD VDD SS_OTP_ PWR_UP VSS X3D10 X3D09 X3D30 IO VDD X3D52 X3D53 X3D50 X3D51 X0D08 SS_CLK SS_XC0_ BS[0] X3D08 X3D07 IO VDD X3D29 SS_XC0_ BS[1] J X0D49 NC X0D27 X0D28 VSS X0D06 SS_PLL_ LOCK X3D06 IO VDD X3D28 X3D27 NC X3D49 K IO VDD IO VDD X0D25 X0D26 X0D05 X0D04 VDD VSS VSS VSS VSS VSS VSS VDD X3D04 X3D05 X3D26 X3D25 VSS VSS L NC NC IO VDD X0D24 X0D03 X0D02 VDD VSS VSS VSS VSS VSS VSS VDD X3D02 X3D03 X3D24 NC SS_XC_ CFG[0] SS_XC1_ BS[0] X0D00 SS_EXT_ OSC_ CONFIG VSS VSS VSS VSS VSS VSS SS_ DEBUG X3D00 X3D01 NC NC SS_XC_ CFG[1] SS_XC1_ BS[1] VSS VSS VSS VSS VSS VSS M NC NC NC NC X0D01 N NC NC NC NC X1D01 X1D00 SS_EXT_ OSC_ HS_ MODE P NC NC VSS X1D24 X1D03 X1D02 VDD VSS VSS VSS VSS VSS VSS VDD R VSS VSS X1D25 X1D26 X1D05 X1D04 VDD VSS VSS VSS VSS VSS VSS T U X1D49 X1D51 NC X1D50 X1D27 X1D29 X1D28 IO VDD IO VDD X1D07 X1D06 SS_PLL_ TEST X1D08 SS_PLL_ AGND NC NC X2D02 X2D03 X2D24 NC SS_XC0_ SS_XC1_ BS[3] BS[3] VDD X2D04 X2D05 X2D26 X2D25 IO VDD IO VDD SS_ TEST_ ENA X2D06 VSS X2D28 X2D27 NC X2D49 SS_TCK X2D08 X2D07 VSS X2D29 X2D50 X2D51 V X1D53 X1D52 IO VDD X1D30 X1D09 X1D10 VSS SS_PLL_ AVDD VDD VDD SS_TMS SS_TDO VDD VDD SS_TDI SS_TRST IO VDD X2D10 X2D09 X2D30 VSS X2D52 X2D53 W IO VDD IO VDD X1D31 X1D32 X1D11 VSS X1D12 X1D14 X1D16 X1D18 X1D20 X1D22 X2D22 X2D20 X2D18 X2D16 X2D14 X2D12 IO VDD X2D11 X2D32 X2D31 VSS VSS Y X1D55 X1D54 X1D33 X1D34 VSS X1D13 X1D15 X1D17 IO VDD X1D19 X1D21 X1D23 X2D23 X2D21 X2D19 VSS X2D17 X2D15 X2D13 IO VDD X2D34 X2D33 X2D54 X2D55 AA X1D57 X1D56 X1D35 VSS X1D36 X1D38 X1D40 IO VDD X1D42 NC NC NC NC NC NC X2D42 VSS X2D40 X2D38 X2D36 IO VDD X2D35 X2D56 X2D57 AB NC X1D58 VSS X1D37 X1D39 X1D41 IO VDD X1D43 NC NC VSS NC NC IO VDD NC NC X2D43 VSS X2D41 X2D39 X2D37 IO VDD X2D58 NC AC VSS VSS NC X1D62 X1D64 IO VDD X1D66 X1D68 X1D70 VSS NC NC NC NC IO VDD X2D70 X2D68 X2D66 VSS X2D64 X2D62 NC IO VDD IO VDD AD VSS VSS X1D61 X1D63 X1D65 IO VDD X1D67 X1D69 NC VSS NC NC NC NC IO VDD NC X2D69 X2D67 VSS X2D65 X2D63 X2D61 IO VDD IO VDD X1066, SS_OTP_ VPP X2D01 SS_XC0_ SS_XC1_ BS[2] BS[2] SS_ X2D00 RESERVED XS1-G04B-FB512 Datasheet 3 4 Signal Description Module Signal Function Type Active Properties PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger Input, OT=Output Tristate, S=Switchable RS =Required for SPI boot (§5.6), RU =Required for USB-enabled devices (§10) Power PLL JTAG VSS Digital ground GND — VDD Digital tile power PWR — IO VDD Digital I/O power PWR — SS_PLL_AGND Analog ground for PLL GND — SS_PLL_AVDD Analog PLL power PWR — SS_OTP_VPP OTP programming voltage PWR — SS_RESET Global reset input Input — SS_CLK PLL reference clock Input — PD, ST SS_PLL_BYPASS PLL bypass Input — PD SS_EXT_OSC_CONFIG Oscillator config Input — PD SS_EXT_OSC_HS_MODE Oscillator high-speed mode Input — PD SS_XC0_BS[3:0] Boot status (tile 0) I/O — PU SS_XC1_BS[3:0] Boot status (tile 1) I/O — PU SS_TDI Test data input Input — PU, ST SS_TDO Test data output Output — PD SS_TMS Test mode select Input — PU, ST SS_TRST Test reset input Input — PU, ST SS_TCK Test clock Input — PU, ST SS_DEBUG Multi-chip debug I/O — PU P1A0 I/O — PDS , RS P1B0 I/O — PDS , RS X0D00 Tile 0 I/O X0D01 X0LA4i 5b X0D02 X0LA3i 5b P4A0 P8A0 P16A0 P32A20 I/O — PDS , RU X0D03 X0LA2i 5b P4A1 P8A1 P16A1 P32A21 I/O — PDS , RU X0D04 X0LA1i 2b/5b P4B0 P8A2 P16A2 P32A22 I/O — PDS , RU X0D05 X0LA0i 2b/5b P4B1 P8A3 P16A3 P32A23 I/O — PDS , RU X0D06 X0LA0o 2b/5b P4B2 P8A4 P16A4 P32A24 I/O — PDS , RU X0D07 X0LA1o 2b/5b P4B3 P8A5 P16A5 P32A25 I/O — PDS , RU X0D08 X0LA2o 5b P4A2 P8A6 P16A6 P32A26 I/O — PDS , RU X0D09 X0LA3o 5b P4A3 P8A7 P16A7 P32A27 I/O — PDS , RU X0D10 X0LA4o 5b P1C0 I/O — PDS , RS X0D11 P1D0 I/O — PDS , RS X0D12 P1E0 I/O — PDS , RU P1F0 I/O — PDS , RU X0D13 X0LB4i 5b X0D14 X0LB3i 5b P4C0 P8B0 P16A8 P32A28 I/O — PDS , RU X0D15 X0LB2i 5b P4C1 P8B1 P16A9 P32A29 I/O — PDS , RU X0D16 X0LB1i 2b/5b P4D0 P8B2 P16A10 I/O — PDS , RU X0D17 X0LB0i 2b/5b P4D1 P8B3 P16A11 I/O — PDS , RU X0D18 X0LB0o 2b/5b P4D2 P8B4 P16A12 I/O — PDS , RU (continued) X1066, XS1-G04B-FB512 Datasheet Module Tile 0 I/O 5 Name Function Type Active Properties X0D19 X0LB1o 2b/5b P4D3 P8B5 P16A13 I/O — PDS , RU X0D20 X0LB2o 5b P4C2 P8B6 P16A14 P32A30 I/O — PDS , RU X0D21 X0LB3o 5b P4C3 P8B7 P16A15 P32A31 I/O — PDS , RU X0D22 X0LB4o 5b P1G0 I/O — PDS , RU X0D23 P1H0 I/O — PDS , RU X0D24 P1I0 I/O — PDS X0D25 P1J0 I/O — PDS X0D26 P4E0 P8C0 P16B0 I/O — PDS , RU X0D27 P4E1 P8C1 P16B1 I/O — PDS , RU X0D28 P4F0 P8C2 P16B2 I/O — PDS , RU X0D29 P4F1 P8C3 P16B3 I/O — PDS , RU X0D30 P4F2 P8C4 P16B4 I/O — PDS , RU X0D31 P4F3 P8C5 P16B5 I/O — PDS , RU X0D32 P4E2 P8C6 P16B6 I/O — PDS , RU X0D33 P4E3 P8C7 P16B7 I/O — PDS , RU X0D34 P1K0 I/O — PDS X0D35 P1L0 I/O — PDS X0D36 P1M0 P8D0 P16B8 I/O — PDS X0D37 P1N0 P8D1 P16B9 I/O — PDS , RU X0D38 P1O0 P8D2 P16B10 I/O — PDS , RU X0D39 P1P0 P8D3 P16B11 I/O — PDS , RU X0D40 P8D4 P16B12 I/O — PDS , RU X0D41 P8D5 P16B13 I/O — PDS , RU X0D42 P8D6 P16B14 I/O — PDS , RU X0D43 P8D7 P16B15 I/O — PUS , RU X0D49 X0LC4i 5b P32A0 I/O — PDS X0D50 X0LC3i 5b P32A1 I/O — PDS X0D51 X0LC2i 5b P32A2 I/O — PDS X0D52 X0LC1i 2b/5b P32A3 I/O — PDS X0D53 X0LC0i 2b/5b P32A4 I/O — PDS X0D54 X0LC0o 2b/5b P32A5 I/O — PDS X0D55 X0LC1o 2b/5b P32A6 I/O — PDS X0D56 X0LC2o 5b P32A7 I/O — PDS X0D57 X0LC3o 5b P32A8 I/O — PDS X0D58 X0LC4o 5b P32A9 I/O — PDS X0D61 X0LD4i 5b P32A10 I/O — PDS X0D62 X0LD3i 5b P32A11 I/O — PDS X0D63 X0LD2i 5b P32A12 I/O — PDS X0D64 X0LD1i 2b/5b P32A13 I/O — PDS X0D65 X0LD0i 2b/5b P32A14 I/O — PDS X0D66 X0LD0o 2b/5b P32A15 I/O — PDS X0D67 X0LD1o 2b/5b P32A16 I/O — PDS X0D68 X0LD2o 5b P32A17 I/O — PDS (continued) X1066, XS1-G04B-FB512 Datasheet Module Tile 0 I/O 6 Name Function Type Active Properties X0D69 X0LD3o 5b P32A18 I/O — PDS X0D70 X0LD4o 5b P32A19 I/O — PDS P1A0 I/O — PDS P1B0 I/O — PDS X1D00 Tile 1 I/O X1D01 X1LA4o 5b X1D02 X1LA3o 5b P4A0 P8A0 P16A0 P32A20 I/O — PDS , RU X1D03 X1LA2o 5b P4A1 P8A1 P16A1 P32A21 I/O — PDS , RU X1D04 X1LA1o 2b/5b P4B0 P8A2 P16A2 P32A22 I/O — PDS , RU X1D05 X1LA0o 2b/5b P4B1 P8A3 P16A3 P32A23 I/O — PDS , RU X1D06 X1LA0i 2b/5b P4B2 P8A4 P16A4 P32A24 I/O — PDS , RU X1D07 X1LA1i 2b/5b P4B3 P8A5 P16A5 P32A25 I/O — PDS , RU X1D08 X1LA2i 5b P4A2 P8A6 P16A6 P32A26 I/O — PDS , RU X1D09 X1LA3i 5b P4A3 P8A7 P16A7 P32A27 I/O — PDS , RU X1D10 X1LA4i 5b P1C0 I/O — PDS X1D11 P1D0 I/O — PDS X1D12 P1E0 I/O — PDS , RU P1F0 I/O — PDS , RU X1D13 X1LB4o 5b X1D14 X1LB3o 5b P4C0 P8B0 P16A8 P32A28 I/O — PDS , RU X1D15 X1LB2o 5b P4C1 P8B1 P16A9 P32A29 I/O — PDS , RU X1D16 X1LB1o 2b/5b P4D0 P8B2 P16A10 I/O — PDS , RU X1D17 X1LB0o 2b/5b P4D1 P8B3 P16A11 I/O — PDS , RU X1D18 X1LB0i 2b/5b P4D2 P8B4 P16A12 I/O — PDS , RU X1D19 X1LB1i 2b/5b P4D3 P8B5 P16A13 I/O — PDS , RU X1D20 X1LB2i 5b P4C2 P8B6 P16A14 P32A30 I/O — PDS , RU X1D21 X1LB3i 5b P4C3 P8B7 P16A15 P32A31 I/O — PDS , RU X1D22 X1LB4i 5b P1G0 I/O — PDS , RU X1D23 P1H0 I/O — PDS , RU X1D24 P1I0 I/O — PDS X1D25 P1J0 I/O — PDS X1D26 P4E0 P8C0 P16B0 I/O — PDS , RU X1D27 P4E1 P8C1 P16B1 I/O — PDS , RU X1D28 P4F0 P8C2 P16B2 I/O — PDS , RU X1D29 P4F1 P8C3 P16B3 I/O — PDS , RU X1D30 P4F2 P8C4 P16B4 I/O — PDS , RU X1D31 P4F3 P8C5 P16B5 I/O — PDS , RU X1D32 P4E2 P8C6 P16B6 I/O — PDS , RU X1D33 P4E3 P8C7 P16B7 I/O — PDS , RU X1D34 P1K0 I/O — PDS , RU X1D35 P1L0 I/O — PDS , RU X1D36 P1M0 P8D0 P16B8 I/O — PDS , RU X1D37 P1N0 P8D1 P16B9 I/O — PDS , RU X1D38 P1O0 P8D2 P16B10 I/O — PDS , RU X1D39 P1P0 P8D3 P16B11 I/O — PDS , RU P8D4 P16B12 I/O — PDS , RU X1D40 (continued) X1066, XS1-G04B-FB512 Datasheet Module Tile 1 I/O Name 7 Type Active Properties X1D41 Function P8D5 P16B13 I/O — PDS , RU X1D42 P8D6 P16B14 I/O — PDS , RU X1D43 P8D7 P16B15 I/O — PUS , RU X1D49 X1LC4o 5b P32A0 I/O — PDS X1D50 X1LC3o 5b P32A1 I/O — PDS X1D51 X1LC2o 5b P32A2 I/O — PDS X1D52 X1LC1o 2b/5b P32A3 I/O — PDS X1D53 X1LC0o 2b/5b P32A4 I/O — PDS X1D54 X1LC0i 2b/5b P32A5 I/O — PDS X1D55 X1LC1i 2b/5b P32A6 I/O — PDS X1D56 X1LC2i 5b P32A7 I/O — PDS X1D57 X1LC3i 5b P32A8 I/O — PDS X1D58 X1LC4i 5b P32A9 I/O — PDS X1D61 X1LD4o 5b P32A10 I/O — PDS X1D62 X1LD3o 5b P32A11 I/O — PDS X1D63 X1LD2o 5b P32A12 I/O — PDS X1D64 X1LD1o 2b/5b P32A13 I/O — PDS X1D65 X1LD0o 2b/5b P32A14 I/O — PDS X1D66 X1LD0i 2b/5b P32A15 I/O — PDS X1D67 X1LD1i 2b/5b P32A16 I/O — PDS X1D68 X1LD2i 5b P32A17 I/O — PDS X1D69 X1LD3i 5b P32A18 I/O — PDS X1D70 X1LD4i 5b P32A19 I/O — PDS P1A0 I/O — PDS P1B0 I/O — PDS X2D00 Tile 2 I/O X2D01 X2LA4i 5b X2D02 X2LA3i 5b P4A0 P8A0 P16A0 P32A20 I/O — PDS , RU X2D03 X2LA2i 5b P4A1 P8A1 P16A1 P32A21 I/O — PDS , RU X2D04 X2LA1i 2b/5b P4B0 P8A2 P16A2 P32A22 I/O — PDS , RU X2D05 X2LA0i 2b/5b P4B1 P8A3 P16A3 P32A23 I/O — PDS , RU X2D06 X2LA0o 2b/5b P4B2 P8A4 P16A4 P32A24 I/O — PDS , RU X2D07 X2LA1o 2b/5b P4B3 P8A5 P16A5 P32A25 I/O — PDS , RU X2D08 X2LA2o 5b P4A2 P8A6 P16A6 P32A26 I/O — PDS , RU X2D09 X2LA3o 5b P4A3 P8A7 P16A7 P32A27 I/O — PDS , RU X2D10 X2LA4o 5b P1C0 I/O — PDS X2D11 P1D0 I/O — PDS X2D12 P1E0 I/O — PDS , RU P1F0 I/O — PDS , RU X2D13 X2LB4i 5b X2D14 X2LB3i 5b P4C0 P8B0 P16A8 P32A28 I/O — PDS , RU X2D15 X2LB2i 5b P4C1 P8B1 P16A9 P32A29 I/O — PDS , RU X2D16 X2LB1i 2b/5b P4D0 P8B2 P16A10 I/O — PDS , RU X2D17 X2LB0i 2b/5b P4D1 P8B3 P16A11 I/O — PDS , RU X2D18 X2LB0o 2b/5b P4D2 P8B4 P16A12 I/O — PDS , RU X2D19 X2LB1o 2b/5b P4D3 P8B5 P16A13 I/O — PDS , RU (continued) X1066, XS1-G04B-FB512 Datasheet Module Tile 2 I/O 8 Name Function Type Active Properties X2D20 X2LB2o 5b P4C2 P8B6 P16A14 P32A30 I/O — PDS , RU X2D21 X2LB3o 5b P4C3 P8B7 P16A15 P32A31 I/O — PDS , RU X2D22 X2LB4o 5b P1G0 I/O — PDS , RU X2D23 P1H0 I/O — PDS , RU X2D24 P1I0 I/O — PDS X2D25 P1J0 I/O — PDS X2D26 P4E0 P8C0 P16B0 I/O — PDS , RU X2D27 P4E1 P8C1 P16B1 I/O — PDS , RU X2D28 P4F0 P8C2 P16B2 I/O — PDS , RU X2D29 P4F1 P8C3 P16B3 I/O — PDS , RU X2D30 P4F2 P8C4 P16B4 I/O — PDS , RU X2D31 P4F3 P8C5 P16B5 I/O — PDS , RU X2D32 P4E2 P8C6 P16B6 I/O — PDS , RU X2D33 P4E3 P8C7 P16B7 I/O — PDS , RU X2D34 P1K0 I/O — PDS X2D35 P1L0 I/O — PDS X2D36 P1M0 P8D0 P16B8 I/O — PDS X2D37 P1N0 P8D1 P16B9 I/O — PDS , RU X2D38 P1O0 P8D2 P16B10 I/O — PDS , RU X2D39 P1P0 P8D3 P16B11 I/O — PDS , RU X2D40 P8D4 P16B12 I/O — PDS , RU X2D41 P8D5 P16B13 I/O — PDS , RU X2D42 P8D6 P16B14 I/O — PDS , RU X2D43 P8D7 P16B15 I/O — PUS , RU X2D49 X2LC4i 5b P32A0 I/O — PDS X2D50 X2LC3i 5b P32A1 I/O — PDS X2D51 X2LC2i 5b P32A2 I/O — PDS X2D52 X2LC1i 2b/5b P32A3 I/O — PDS X2D53 X2LC0i 2b/5b P32A4 I/O — PDS X2D54 X2LC0o 2b/5b P32A5 I/O — PDS X2D55 X2LC1o 2b/5b P32A6 I/O — PDS X2D56 X2LC2o 5b P32A7 I/O — PDS X2D57 X2LC3o 5b P32A8 I/O — PDS X2D58 X2LC4o 5b P32A9 I/O — PDS X2D61 X2LD4i 5b P32A10 I/O — PDS X2D62 X2LD3i 5b P32A11 I/O — PDS X2D63 X2LD2i 5b P32A12 I/O — PDS X2D64 X2LD1i 2b/5b P32A13 I/O — PDS X2D65 X2LD0i 2b/5b P32A14 I/O — PDS X2D66 X2LD0o 2b/5b P32A15 I/O — PDS X2D67 X2LD1o 2b/5b P32A16 I/O — PDS X2D68 X2LD2o 5b P32A17 I/O — PDS X2D69 X2LD3o 5b P32A18 I/O — PDS (continued) X1066, XS1-G04B-FB512 Datasheet 9 Module Name Function Tile 2 I/O X2D70 X2LD4o 5b X3D00 Tile 3 I/O Type Active Properties I/O — PDS P1A0 I/O — PDS P1B0 I/O — PDS P32A19 X3D01 X3LA4o 5b X3D02 X3LA3o 5b P4A0 P8A0 P16A0 P32A20 I/O — PDS , RU X3D03 X3LA2o 5b P4A1 P8A1 P16A1 P32A21 I/O — PDS , RU X3D04 X3LA1o 2b/5b P4B0 P8A2 P16A2 P32A22 I/O — PDS , RU X3D05 X3LA0o 2b/5b P4B1 P8A3 P16A3 P32A23 I/O — PDS , RU X3D06 X3LA0i 2b/5b P4B2 P8A4 P16A4 P32A24 I/O — PDS , RU X3D07 X3LA1i 2b/5b P4B3 P8A5 P16A5 P32A25 I/O — PDS , RU X3D08 X3LA2i 5b P4A2 P8A6 P16A6 P32A26 I/O — PDS , RU X3D09 X3LA3i 5b P4A3 P8A7 P16A7 P32A27 I/O — PDS , RU X3D10 X3LA4i 5b P1C0 I/O — PDS X3D11 P1D0 I/O — PDS X3D12 P1E0 I/O — PDS , RU P1F0 I/O — PDS , RU X3D13 X3LB4o 5b X3D14 X3LB3o 5b P4C0 P8B0 P16A8 P32A28 I/O — PDS , RU X3D15 X3LB2o 5b P4C1 P8B1 P16A9 P32A29 I/O — PDS , RU X3D16 X3LB1o 2b/5b P4D0 P8B2 P16A10 I/O — PDS , RU X3D17 X3LB0o 2b/5b P4D1 P8B3 P16A11 I/O — PDS , RU X3D18 X3LB0i 2b/5b P4D2 P8B4 P16A12 I/O — PDS , RU X3D19 X3LB1i 2b/5b P4D3 P8B5 P16A13 I/O — PDS , RU X3D20 X3LB2i 5b P4C2 P8B6 P16A14 P32A30 I/O — PDS , RU X3D21 X3LB3i 5b P4C3 P8B7 P16A15 P32A31 I/O — PDS , RU X3D22 X3LB4i 5b P1G0 I/O — PDS , RU X3D23 P1H0 I/O — PDS , RU X3D24 P1I0 I/O — PDS X3D25 P1J0 I/O — PDS X3D26 P4E0 P8C0 P16B0 I/O — PDS , RU X3D27 P4E1 P8C1 P16B1 I/O — PDS , RU X3D28 P4F0 P8C2 P16B2 I/O — PDS , RU X3D29 P4F1 P8C3 P16B3 I/O — PDS , RU X3D30 P4F2 P8C4 P16B4 I/O — PDS , RU X3D31 P4F3 P8C5 P16B5 I/O — PDS , RU X3D32 P4E2 P8C6 P16B6 I/O — PDS , RU X3D33 P4E3 P8C7 P16B7 I/O — PDS , RU X3D34 P1K0 I/O — PDS X3D35 P1L0 I/O — PDS X3D36 P1M0 P8D0 P16B8 I/O — PDS X3D37 P1N0 P8D1 P16B9 I/O — PDS , RU X3D38 P1O0 P8D2 P16B10 I/O — PDS , RU X3D39 P1P0 P8D3 P16B11 I/O — PDS , RU X3D40 P8D4 P16B12 I/O — PDS , RU X3D41 P8D5 P16B13 I/O — PDS , RU (continued) X1066, XS1-G04B-FB512 Datasheet Module Tile 3 I/O Reserved X1066, Name 10 Type Active Properties X3D42 Function P8D6 P16B14 I/O — PDS , RU X3D43 P8D7 P16B15 I/O — PUS , RU X3D49 X3LC4o 5b P32A0 I/O — PDS X3D50 X3LC3o 5b P32A1 I/O — PDS X3D51 X3LC2o 5b P32A2 I/O — PDS X3D52 X3LC1o 2b/5b P32A3 I/O — PDS X3D53 X3LC0o 2b/5b P32A4 I/O — PDS X3D54 X3LC0i 2b/5b P32A5 I/O — PDS X3D55 X3LC1i 2b/5b P32A6 I/O — PDS X3D56 X3LC2i 5b P32A7 I/O — PDS X3D57 X3LC3i 5b P32A8 I/O — PDS X3D58 X3LC4i 5b P32A9 I/O — PDS X3D61 X3LD4o 5b P32A10 I/O — PDS X3D62 X3LD3o 5b P32A11 I/O — PDS X3D63 X3LD2o 5b P32A12 I/O — PDS X3D64 X3LD1o 2b/5b P32A13 I/O — PDS X3D65 X3LD0o 2b/5b P32A14 I/O — PDS X3D66 X3LD0i 2b/5b P32A15 I/O — PDS X3D67 X3LD1i 2b/5b P32A16 I/O — PDS X3D68 X3LD2i 5b P32A17 I/O — PDS X3D69 X3LD3i 5b P32A18 I/O — PDS X3D70 X3LD4i 5b P32A19 I/O — PDS SS_PLL_LOCK Reserved (do not connect) Output — PD SS_BYPASS_PLL_LOCK Reserved (tie to VSS) Input — PD SS_PLL_TEST Reserved (do not connect) Input — SS_OTP_VREF Reserved (do not connect) Output — SS_OTP_PWR_UP Reserved (do not connect) Output — SS_TEST_ENA Reserved (tie to VSS) Input — PD SS_XC_CFG[1:0] Reserved (tie to VSS) Input — PD SS_RESERVED Reserved (do not connect) Output — NC Not connected I/O — XS1-G04B-FB512 Datasheet Boot ROM Core 1 Core 1 Boot ROM ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ 4A 4C 4C Port 4D Port 8B 4C 8KB OTP 4E Port 4F 6 Clock Blocks 4E Core 4 Port 8C Security Register Port 32A Core 3 Port 16B 32 Channel Ends Switch Core 4 Switch 6 Clock Blocks Switch Core 3 Port 8D Core 5 Core 5 10 Timers 4 Locks Core 6 Core 6 4 Locks 7 Synchronizers Core 7 Core 7 7 Synchronizers 1K 1L 1M 1N 1O 1P ¶ ¶ ¶ ¶ ¶ ¶ X3LC 10 Timers ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ X3LD · · · · Security Register 32 Channel Ends 4E Port 16B Port 4F Port 8C 4E Port 32A 1G 1H 1I 1J ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · X3D00 X3D01 X3D02 X3D03 X3D04 X3D05 X3D06 X3D07 X3D08 X3D09 X3D10 X3D11 X3D12 X3D13 X3D14 X3D15 X3D16 X3D17 X3D18 X3D19 X3D20 X3D21 X3D22 X3D23 X3D24 X3D25 X3D26 X3D27 X3D28 X3D29 X3D30 X3D31 X3D32 X3D33 X3D34 X3D35 X3D36 X3D37 X3D38 X3D39 X3D40 X3D41 X3D42 X3D43 X3D49 X3D50 X3D51 X3D52 X3D53 X3D54 X3D55 X3D56 X3D57 X3D58 X3D61 X3D62 X3D63 X3D64 X3D65 X3D66 X3D67 X3D68 X3D69 X3D70 X3 JTAG PLL SS_OTP_VPP VDD IO VDD VSS X1 and X2 shown on following page X1066, Port 16A Port 16A 4C Port 8B Port 4D Core 2 Core 2 X0 SS_PLL_BYPASS SS_EXT_OSC_CONFIG SS_EXT_OSCHS_MODE SS_CLK SS_XC0_BS SS_XC1_BS SS_RESET SS_PLL_AVDD SS_PLL_AGND 1C 1D 1E 1F X3LA 64KB SRAM 8KB OTP · · · · · · · · ¶ Port 4B Port 4B 1F 1G · 1H · 1I · 1J 1A 1B 4A Core 0 Port 8A Core 0 4A X0LA 1C · 1D · 1E · 1K · 1L · 1M · 1N · 1O · 1P · · · · · · · · · · · · · · · · · · · · 64KB SRAM Port 8A 4A 1B Port 8D · · · · · · · · · · · 1A X0LB · · · · · · · · · · X0LC X0D00 ¶ X0D01 ¶ X0D02 ¶ X0D03 ¶ X0D04 ¶ X0D05 ¶ X0D06 ¶ X0D07 ¶ X0D08 ¶ X0D09 ¶ X0D10 ¶ X0D11 ¶ X0D12 ¶ X0D13 ¶ X0D14 ¶ X0D15 ¶ X0D16 ¶ X0D17 ¶ X0D18 ¶ X0D19 ¶ X0D20 ¶ X0D21 ¶ X0D22 ¶ X0D23 ¶ X0D24 ¶ X0D25 ¶ X0D26 ¶ X0D27 ¶ X0D28 ¶ X0D29 ¶ X0D30 ¶ X0D31 ¶ X0D32 ¶ X0D33 ¶ X0D34 ¶ X0D35 ¶ X0D36 ¶ X0D37 ¶ X0D38 ¶ X0D39 ¶ X0D40 ¶ X0D41 ¶ X0D42 ¶ X0D43 ¶ X0D49 ¶ X0D50 ¶ X0D51 ¶ X0D52 ¶ X0D53 ¶ X0D54 ¶ X0D55 ¶ X0D56 ¶ X0D57 ¶ X0D58 ¶ X0D61 ¶ X0D62 ¶ X0D63 ¶ X0D64 ¶ X0D65 ¶ X0D66 ¶ X0D67 ¶ X0D68 ¶ X0D69 ¶ X0D70 ¶ X3LB Block Diagram X0LD 4 11 SS_TDO SS_TDI SS_TCK SS_TMS SS_TRST SS_DEBUG XS1-G04B-FB512 Datasheet 12 X0 and X3 shown on previous page X2 X1 X1066, Core 1 Boot ROM 1C 1D 1E 1F ¶ ¶ 4A X2LA Core 1 Port 16A Port 16A 4C X2LB Port 4D Port 8B Port 4D Port 8B Core 2 Core 2 8KB OTP 4C 4C 8KB OTP Core 5 Core 5 10 Timers 4 Locks Core 6 Core 6 4 Locks 7 Synchronizers Core 7 Core 7 7 Synchronizers 4E ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ 1K 1L 1M 1N 1O 1P ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ X2LD X2LC 10 Timers Port 4F 4E 6 Clock Blocks Port 8C Core 4 Port 32A Security Register Port 16B Switch Core 3 32 Channel Ends Core 4 Switch 6 Clock Blocks Switch Core 3 Port 8D · · · · Security Register 32 Channel Ends Port 16B 4E Port 4F Port 8C 4E Port 32A 1G 1H 1I 1J X1LC · · · · · · · · ¶ Port 4B Boot ROM Port 8A 64KB SRAM 4C 1F 1G · 1H · 1I · 1J 1A 1B 4A 4A Port 4B Core 0 Port 8A Core 0 4A X1LA 1C · 1D · 1E · 1K · 1L · 1M · 1N · 1O · 1P · · · · · · · · · · · · · · · · · · · · 64KB SRAM Port 8D · · · · · · · · · · 1B X1LB · · · · · · · · · · · 1A X1LD X1D00 ¶ X1D01 ¶ X1D02 ¶ X1D03 ¶ X1D04 ¶ X1D05 ¶ X1D06 ¶ X1D07 ¶ X1D08 ¶ X1D09 ¶ X1D10 ¶ X1D11 ¶ X1D12 ¶ X1D13 ¶ X1D14 ¶ X1D15 ¶ X1D16 ¶ X1D17 ¶ X1D18 ¶ X1D19 ¶ X1D20 ¶ X1D21 ¶ X1D22 ¶ X1D23 ¶ X1D24 ¶ X1D25 ¶ X1D26 ¶ X1D27 ¶ X1D28 ¶ X1D29 ¶ X1D30 ¶ X1D31 ¶ X1D32 ¶ X1D33 ¶ X1D34 ¶ X1D35 ¶ X1D36 ¶ X1D37 ¶ X1D38 ¶ X1D39 ¶ X1D40 ¶ X1D41 ¶ X1D42 ¶ X1D43 ¶ X1D49 ¶ X1D50 ¶ X1D51 ¶ X1D52 ¶ X1D53 ¶ X1D54 ¶ X1D55 ¶ X1D56 ¶ X1D57 ¶ X1D58 ¶ X1D61 ¶ X1D62 ¶ X1D63 ¶ X1D64 ¶ X1D65 ¶ X1D66 ¶ X1D67 ¶ X1D68 ¶ X1D69 ¶ X1D70 ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ ¶ · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · X2D00 X2D01 X2D02 X2D03 X2D04 X2D05 X2D06 X2D07 X2D08 X2D09 X2D10 X2D11 X2D12 X2D13 X2D14 X2D15 X2D16 X2D17 X2D18 X2D19 X2D20 X2D21 X2D22 X2D23 X2D24 X2D25 X2D26 X2D27 X2D28 X2D29 X2D30 X2D31 X2D32 X2D33 X2D34 X2D35 X2D36 X2D37 X2D38 X2D39 X2D40 X2D41 X2D42 X2D43 X2D49 X2D50 X2D51 X2D52 X2D53 X2D54 X2D55 X2D56 X2D57 X2D58 X2D61 X2D62 X2D63 X2D64 X2D65 X2D66 X2D67 X2D68 X2D69 X2D70 XS1-G04B-FB512 Datasheet 5 13 Product Overview The XMOS XS1-G04B-FB512 is a powerful device that provides a simple design process and highly-flexible solution to many applications. The device consists of four xCORE Tiles, each comprising a flexible multicore microcontroller with tightly integrated I/O and on-chip memory. The processors run mutiple tasks simultaneously using logical cores, each of which is guaranteed a slice of processing power and can execute computational code, control software and I/O interfaces. Logical cores use channels to exchange data within a tile or across tiles. The tiles are connected via an integrated switch network, which uses a proprietary physical layer protocol, and which can also be used to add additional resources to a design. The I/O pins are driven using intelligent ports that can serialize data, interpret strobe signals and wait for scheduled times or events, making the device ideal for real-time control applications. The device can be configured using a set of software components that are rapidly customized and composed. XMOS provides source code libraries for many standard components. The device can be programmed using high-level languages such as C/C++ and XMOS-originated extensions to C, called XC, that simplify the control over concurrency, I/O and time. The XMOS toolchain includes compilers, a simulator, debugger and static timing analyzer. The combination of real-time software, a compiler and timing analyzer enables the programmer to close timings on components of the design without a detailed understanding of the hardware characteristics. 5.1 Logical cores, Synchronizers and Locks Each xCORE Tile has up to eight active logical cores, which issue instructions down a shared four-stage pipeline. Instructions from the active cores are issued round-robin. If up to four logical cores are active, each core is allocated a quarter of the processing cycles. If more than four logical cores are active, each core is allocated at least 1/n cycles (for n cores). Figure 1 shows the guaranteed core performance depending on the number of cores used. Figure 1: Core performance Speed Grade 400 MHz Minimum MIPS per core (for n cores) 1 2 3 4 5 6 7 8 100 100 100 100 80 67 57 50 There is no way that the performance of a logical core can be reduced below these predicted levels. Because cores may be delayed on I/O, however, their unused processing cycles can be taken by other cores. This means that for more than four logical cores, the performance of each core is often higher than the predicted minimum. 5.2 Channel Ends, Links and Switch Logical cores communicate using point-to-point connections formed between two channel ends. Between tiles, channel communications are implemented over X1066, XS1-G04B-FB512 Datasheet 14 xConnect Links and routed through switches. The links operate in either 2bit/direction or 5bit/direction mode, depending on the amount of bandwidth required. Circuit switched, streaming and packet switched data can both be supported efficiently. Streams provide the fastest possible data rates between xCORE Tiles (up to 250 MBit/s), but each stream requires a single link to be reserved between switches on two tiles. All packet communications can be multiplexed onto a single link. A total of eight 5bit links are available between every pair of cores. Information on the supported routing topologies that can be used to connect multiple devices together can be found in the XS1-G Link Performance and Design Guide, X7561. 5.3 Ports and Clock Blocks Ports provide an interface between the logical cores and I/O pins. All pins of a port provide either output or input. Signals in different directions cannot be mapped onto the same port. The operation of each port is synchronized to a clock block. A clock block can be connected to an external clock input, or it can be run from the divided reference clock. A clock block can also output its signal to a pin. On reset, each port is connected to clock block 0, which runs from the xCORE Tile reference clock. The ports and links are multiplexed, allowing the pins to be configured for use by ports of different widths or links. If an xConnect Link is enabled, the pins of the underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their specified width, even if they share pins with another port. 5.4 Timers Timers are 32-bit counters that are relative to the xCORE Tile reference clock. A timer is defined to tick every 10 ns. This value is derived from the reference clock, which is configured to tick at 100 MHz by default. 5.5 PLL The PLL is used to generate all on-chip clocks. SS_CLK is the reference clock input. It should be supplied with a clock with monotonic rising edges and should be stable before SS_RESET is taken high. Many standard clock frequencies can be used with appropriate settings configured into the PLL. At boot time, before the PLL can be reconfigured, the PLL multiplier is set using the pins specified in the table in Figure 2. The PLL increases the clock frequency to the tile frequency used to run the processor data path and the switch. Clock frequencies of betweeen 20 MHz and 25 MHz are not supported. Further details on configuring the clock can be found in the XS1-G Clock Frequency Control document, X3221. X1066, XS1-G04B-FB512 Datasheet 15 SS_PLL_ SS_EXT_OSC_ SS_EXT_OSC_ PLL multi- CLK Input Boot Freq- Figure 2: PLL boot modes BYPASS CONFIG HS_MODE plier ratio (MHz) ency (MHz) 0 0 X 20 12.5–20 250–400 0 1 0 5 25–50 125–250 0 1 1 2.5 50–100 125–250 1 X X 0.5