74CBTLV16211DGG;11

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74CBTLV16211 24-bit bus switch Rev. 7 — 9 November 2016 Product data sheet 1. General description The 74CBTLV16211 provides a dual 12-bit high-speed bus switch with separate output enable inputs (1OE, 2OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is HIGH. To ensure the high-impedance OFF-state during power-up or power-down, 1OE and 2OE should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Supply voltage range from 2.3 V to 3.6 V  High noise immunity  Complies with JEDEC standard:  JESD8-5 (2.3 V to 2.7 V)  JESD8-B/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  CDM AEC-Q100-011 revision B exceeds 1000 V  5  switch connection between two ports  Rail to rail switching on data I/O ports  CMOS low power consumption  Latch-up performance exceeds 250 mA per JESD78B Class I level A  IOFF circuitry provides partial Power-down mode operation  TSSOP56 packages: SOT364-1 and SOT481-2  Specified from 40 C to +85 C and 40 C to +125 C 74CBTLV16211 NXP Semiconductors 24-bit bus switch 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV16211DGG 40 C to +125 C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74CBTLV16211DGV 40 C to +125 C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 4.4 mm SOT481-2 4. Functional diagram 2( 2( $  $  $  $  $  $  $  $  $  $  $  $   %  %  %  %  %  %  %  %  %  %  %  % $  $  $  $  $  $  $  $  $  $  $  $   %  %  %  %  %  %  %  %  %  %  %  %   DDL Fig 1. Logic symbol Q$Q Q%Q Q2( DDL Fig 2. Logic diagram (one switch) 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 2 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 5. Pinning information 5.1 Pinning QF   2( $   2( $   % $   % $   % $   % $   % *1'   *1' $   % $   % $   % $   % $   % $  $   % &%7/9  % $   % 9&&   % $   % *1'   *1' $   % $   % $   % $   % $   % $   % $   % $   % $   % DDL Fig 3. Pin configuration (SOT364-1 and SOT481-2) 5.2 Pin description Table 2. Pin description Symbol Pin Description n.c. 1 not connected 1A0 to 1A11 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 independent input or output 2A0 to 2A11 15, 16, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28 independent input or output GND 8, 19, 38, 49 ground (0 V) VCC 17 supply voltage 2B0 to 2B11 41, 40, 39, 37, 36, 35, 34, 33, 32, 31, 30, 29 independent input or output 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 3 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch Table 2. Pin description …continued Symbol Pin Description 1B0 to 1B11 54, 53, 52, 51, 50, 48, 47, 46, 45, 44, 43, 42 independent input or output 2OE 55 output enable input (active-LOW) 1OE 56 output enable input (active-LOW) 6. Functional description Table 3. Function table[1] Output enable input OE Function switch L ON-state H OFF-state [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +4.6 V [1] 0.5 +4.6 V [1] 0.5 VCC + 0.5 V VI input voltage VSW switch voltage enable and disable mode IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.5 V 50 - mA VSW = 0 V to VCC ISW switch current - 128 mA ICC supply current - +100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 600 mW total power dissipation Ptot Tamb = 40 C to +125 C [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP56 packages: above 55 C the value of Ptot derates linearly with 8.0 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW switch voltage Tamb ambient temperature t/V [1] Conditions enable and disable mode input transition rise and fall rate VCC = 2.3 V to 3.6 V [1] Min Max Unit 2.3 3.6 V 0 3.6 V 0 VCC V 40 +125 C 0 200 ns/V Applies to control signal levels. 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 4 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - V LOW-level input VCC = 2.3 V to 2.7 V voltage VCC = 3.0 V to 3.6 V - - 0.7 - 0.7 V - - 0.9 - 0.9 V II input leakage current - - 1.0 - 20 A IS(OFF) OFF-state VCC = 3.6 V; see Figure 4 leakage current - - 1 - 20 A IS(ON) ON-state VCC = 3.6 V; see Figure 5 leakage current - - 1 - 20 A IOFF power-off VI or VO = 0 V to 3.6 V; leakage current VCC = 0 V - - 10 - 50 A ICC supply current VI = GND or VCC; IO = 0 A; VSW = GND or VCC; VCC = 3.6 V - - 10 - 50 A ICC additional supply current pin nOE; VI = VCC  0.6 V; VSW = GND or VCC; VCC = 3.6 V - - 300 - 2000 A CI input capacitance pin nOE; VCC = 3.3 V; VI = 0 V to 3.3 V - 0.9 - - - pF CS(OFF) OFF-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 5.2 - - - pF CS(ON) ON-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 14.3 - - - pF HIGH-level input voltage VIH VIL pin nOE; VI = GND to VCC; VCC = 3.6 V [1] All typical values are measured at Tamb = 25 C. [2] One input at 3 V, other inputs at VCC or GND. [2] 9.1 Test circuits 9&& 9&& Q2( 9,+ ,V $ 9O Q%Q Q$Q Q2( 9,/ ,V ,V $ $ *1' 92 9O DDP Product data sheet *1' 92 VI = VCC or GND and VO = open circuit. Test circuit for measuring OFF-state leakage current (one channel) 74CBTLV16211 Q%Q DDP VI = VCC or GND and VO = GND or VCC. Fig 4. Q$Q Fig 5. Test circuit for measuring ON-state leakage current (one channel) All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 5 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 9.2 ON resistance Table 7. Resistance RON At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6. Symbol Parameter RON Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 64 mA; VI = 0 V - 4.2 8.0 - 15.0  ISW = 24 mA; VI = 0 V - 4.2 8.0 - 15.0  ISW = 15 mA; VI = 1.7 V - 8.4 40 - 60.0  ISW = 64 mA; VI = 0 V - 4.0 7.0 - 11.0  ISW = 24 mA; VI = 0 V - 4.0 7.0 - 11.0  ISW = 15 mA; VI = 2.4 V - 6.2 15 - 25.5  ON resistance VCC = 2.3 V to 2.7 V; see Figure 7 to Figure 9 [2] VCC = 3.0 V to 3.6 V; see Figure 10 to Figure 12 [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. 9.3 ON resistance test circuit and graphs DDL  521 ȍ  96: 9  9&&  Q2( 9,/   Q$Q 9O Q%Q *1'   ,6:        9,9 DDP (1) Tamb = 125 C. RON = VSW / ISW. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 6. Test circuit for measuring ON resistance (one channel) 74CBTLV16211 Product data sheet Fig 7. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 15 mA All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 6 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch DDL  521 ȍ DDL  521 ȍ                            9,9 (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 8. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 24 mA DDL   9,9 521 ȍ Fig 9. ON resistance as a function of input voltage; VCC = 2.5 V; ISW = 64 mA DDL  521 ȍ                      9,9 (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 10. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 15 mA Product data sheet   9,9 (1) Tamb = 125 C. 74CBTLV16211  Fig 11. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 24 mA All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 7 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch DDL  521 ȍ               9,9 (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 12. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 15 Symbol Parameter Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - - 0.13 - 0.2 ns - - 0.2 - 0.31 ns 1.0 2.0 7.0 1.0 7.8 ns 1.0 1.7 6.2 1.0 6.8 ns VCC = 2.3 V to 2.7 V 1.0 2.6 7.2 1.0 8.1 ns VCC = 3.0 V to 3.6 V 1.0 3.0 7.7 1.0 8.8 ns propagation delay nAn to nBn or nBn to nAn; see Figure 13 tpd [2][3] VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V enable time ten nOE to nAn or nBn; see Figure 14 [4] VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V disable time tdis nOE to nAn or nBn; see Figure 14 [5] [1] All typical values are measured at Tamb = 25 C and at nominal VCC. [2] The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance). [3] tpd is the same as tPLH and tPHL. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPHZ and tPLZ. 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 8 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 11. Waveforms 9, LQSXW 90 90 9 W3+/ W3/+ 92+ 90 RXWSXW 90 92/ DDL Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 13. The data input (nAn or nBn) to output (nBn or nAn) propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VI tr = tf VM VX VY 2.3 V to 2.7 V 0.5VCC VCC  2.0 ns 0.5VCC VOL + 0.15 V VOH  0.15 V 3.0 V to 3.6 V 0.5VCC VCC  2.0 ns 0.5VCC VOL + 0.3 V VOH  0.3 V 9, Q2(LQSXW 90 *1' W3/= W3=/ 9&& RXWSXW /2:WR2)) 2))WR/2: 90 9; 92/ W3+= 92+ W3=+ 9< RXWSXW +,*+WR2)) 2))WR+,*+ 90 *1' VZLWFK HQDEOHG VZLWFK GLVDEOHG VZLWFK HQDEOHG DDN Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 14. Enable and disable times 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 9 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 9, W:  QHJDWLYH SXOVH 90 9 WI WU WU WI 9,  SRVLWLYH SXOVH 9 90  90 90  W: 9(;7 9&& 9, * 5/ 92 '87 57 5/ &/ DDH Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 15. Test circuit for measuring switching times Table 10. Test data Supply voltage Load VCC CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 2.3 V to 2.7 V 30 pF 500  open GND 2VCC 3.0 V to 3.6 V 50 pF 500  open GND 2VCC 74CBTLV16211 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 10 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 11.1 Additional dynamic characteristics Table 11. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf 2.5 ns. Symbol Parameter f(3dB) [1] Tamb = 25 C Conditions 3 dB frequency response VCC = 3.3 V; RL = 50 ; see Figure 16 [1] Unit Min Typ Max - 458 - MHz fi is biased at 0.5VCC. 11.2 Test circuits 9&& 9&& Q2( 9,/ 5/ Q%Q IL Q$Q *1' G% DDD nOE connected to GND; Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Fig 16. Test circuit for measuring the frequency response when channel is in ON-state 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 11 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 12. Package outline 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ( ' $ ; F +( \ Y 0 $ =   4 $ $  $ SLQLQGH[ $ ș /S /  GHWDLO;  Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 17. Package outline SOT364-1 (TSSOP56) 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 12 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ( ' $ ; F \ +( Y 0 $ =   $ $ $  $ SLQLQGH[ ș /S /  GHWDLO;  Z 0 ES H   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S Y Z \ = ș PP                          R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627  02  (8523($1 352-(&7,21 ,668('$7(  Fig 18. Package outline SOT481-2 (TSSOP56) 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 13 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 13. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74CBTLV16211 v.7 20161109 Product data sheet - 74CBTLV16211 v.6 - 74CBTLV16211 v.5 Modifications: 74CBTLV16211 v.6 Modifications: • Section 11.1 and Section 11.2 added. 20111215 • Product data sheet Legal pages updated. 74CBTLV16211 v.5 20101230 Product data sheet - 74CBTLV16211 v.4 74CBTLV16211 v.4 20100816 Product data sheet - 74CBTLV16211 v.3 74CBTLV16211 v.3 20100112 Product data sheet - 74CBTLV16211 v.2 74CBTLV16211 v.2 20090826 Product data sheet - 74CBTLV16211 v.1 74CBTLV16211 v.1 20080620 Product data sheet - - 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 14 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. 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All rights reserved. 15 of 17 74CBTLV16211 NXP Semiconductors 24-bit bus switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74CBTLV16211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 9 November 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 16 of 17 NXP Semiconductors 74CBTLV16211 24-bit bus switch 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 9.1 9.2 9.3 10 11 11.1 11.2 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional dynamic characteristics . . . . . . . . 11 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 November 2016 Document identifier: 74CBTLV16211