74HCT166DB,118

74HC166; 74HCT166 8-bit parallel-in/serial out shift register Rev. 5 — 9 August 2021 Product data sheet 1. General description The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Synchronous parallel-to-serial applications Synchronous serial input for easy expansion Input levels: • For 74HC166: CMOS level • For 74HCT166: TTL level Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package 74HC166D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HCT166D 74HC166PW 74HCT166PW SOT403-1 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 4. Functional diagram 1 PE DS 2 D0 3 D1 4 D2 5 D3 10 D4 11 D5 12 D6 14 D7 9 Fig. 1. 15 6 7 15 9 1 2 3 Q7 4 13 SRG8 ≥1 C1/2 M2 R 2,1D 2,1D 2,1D 5 10 MR 11 CP CE 7 6 12 14 13 aaa-008816 aaa-008817 Logic symbol Fig. 2. 2 15 1 9 7 6 PE 3 D0 4 D1 5 D2 10 D3 D4 11 IEC logic symbol 12 14 D5 D6 D7 DS MR CP CE 8-BIT PARALLEL/SERIAL-IN/ SERIAL-OUT SHIFT REGISTER Q7 13 aaa-008818 Fig. 3. Functional diagram 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 2 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register D0 D1 D2 D3 D4 D5 D6 D7 PE DS CP CE S S S S S S S S FF CP 1 FF CP 2 FF CP 3 FF CP 4 FF CP 5 FF CP 6 FF CP 7 CP R RD R RD R RD R RD R RD R RD R RD R RD FF 8 MR Q7 aaa-008819 Fig. 4. Logic diagram 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 3 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 5. Pinning information 5.1. Pinning 74HC166 74HCT166 DS 1 16 VCC D0 2 15 PE D1 3 14 D7 D2 4 13 Q7 D3 5 12 D6 CE 6 11 D5 CP 7 10 D4 GND 8 9 74HC166 74HCT166 MR DS 1 16 VCC D0 2 15 PE D1 3 14 D7 D2 4 13 Q7 D3 5 12 D6 CE 6 11 D5 CP 7 10 D4 GND 8 MR aaa-033055 aaa-033054 Fig. 5. 9 Pin configuration for SOT109-1 (SO16) Fig. 6. Pin configuration for SOT403-1 (TSSOP16) 5.2. Pin description Table 2. Pin description Symbol Pin Description DS 1 serial data input D0 to D7 2, 3, 4, 5, 10, 11, 12, 14 parallel data inputs CE 6 clock enable input (active LOW) CP 7 clock input (LOW-to-HIGH edge-triggered) GND 8 ground (0 V) MR 9 asynchronous master reset (active LOW) Q7 13 serial output from the last stage PE 15 parallel enable input (active LOW) VCC 16 positive supply voltage 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 4 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition; X = don’t care; ↑ = LOW-to-HIGH clock transition. Operating modes Inputs parallel load serial shift hold "do nothing" Qn registers Output PE CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 I I ↑ X I L L to L L I I ↑ X h H H to H H h I ↑ l X L q0 to q5 q6 h I ↑ h X H q0 to q5 q6 X H X X X q0 q1 to q6 q7 CP mode control inputs CE MR DS shift/ load D0 H L D1 D2 H L D3 parallel inputs D4 H L D5 output D6 H D7 H Q7 H serial shift H L H L L H H serial shift inhibit clear Fig. 7. load aaa-008820 Typical clear, shift, load, inhibit, and shift sequences 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 5 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter Min Max VCC supply voltage -0.5 +7 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V [1] - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current -0.5 V < VO < VCC + 0.5 V [1] - ±20 mA - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Conditions Tamb = -40 °C to +125 °C [2] Unit The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC166 74HCT166 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 - +125 -40 - +125 °C Δt/ΔV input transition rise and fall rate VCC supply voltage VI VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V 74HC166 VIH VIL HIGH-level input voltage LOW-level input voltage 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 6 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register Symbol Parameter VOH VOL HIGH-level output voltage LOW-level output voltage Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V VI = VIH or VIL VI = VIH or VIL - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 μA CI input capacitance - 3.5 - - - - - pF 74HCT166 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V VOL LOW-level output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 4.5 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL; VCC = 4.5 V II input leakage current VI = VCC or GND; VCC = 4.5 V - - ±0.1 - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 4.5 V - - 8.0 - 80 - 160 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V Dn and DS inputs - 35 126 - 157.5 - 171.5 μA CP and CE inputs - 80 288 - 360 - 392 μA MR input - 40 144 - 180 - 196 μA PE input - 60 216 - 270 - 294 μA - 3.5 - - - - - pF CI input capacitance 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 7 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Fig. 11 Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 50 150 - 190 - 225 ns VCC = 4.5 V - 18 30 - 38 - 45 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns VCC = 2.0 V - 47 160 - 200 - 240 ns VCC = 4.5 V - 17 32 - 40 - 48 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 27 - 34 - 41 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 100 25 - 125 - 150 - ns VCC = 4.5 V 20 9 - 25 - 30 - ns VCC = 6.0 V 17 7 - 21 - 26 - ns VCC = 2.0 V 0 -19 - 0 - 0 - ns VCC = 4.5 V 0 -7 - 0 - 0 - ns VCC = 6.0 V 0 -6 - 0 - 0 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 100 33 - 125 - 150 - ns VCC = 4.5 V 20 12 - 25 - 30 - ns VCC = 6.0 V 17 10 - 21 - 26 - ns 74HC166 tpd propagation CP to Q7; see Fig. 8 delay VCC = 2.0 V [1] MR to Q7; see Fig. 9 tt tW transition time pulse width output; see Fig. 8 [2] CP input HIGH or LOW; see Fig. 8 MR input LOW; see Fig. 9 trec tsu recovery time set-up time MR to CP; see Fig. 9 Dn, CE to CP; see Fig. 10 PE to CP; see Fig. 10 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 8 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register Symbol Parameter th hold time Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 2 -8 - 2 - 2 - ns VCC = 4.5 V 2 -3 - 2 - 2 - ns VCC = 6.0 V 2 -2 - 2 - 2 - ns VCC = 2.0 V 0 -28 - 0 - 0 - ns VCC = 4.5 V 0 -10 - 0 - 0 - ns VCC = 6.0 V 0 -8 - 0 - 0 - ns VCC = 2.0 V 6 19 - 4.8 - 4 - MHz VCC = 4.5 V 30 57 - 24 - 20 - MHz Dn, CE to CP; see Fig. 10 PE to CP; see Fig. 10 fmax maximum frequency CP input; see Fig. 8 VCC = 5.0 V; CL = 15 pF - 63 - - - - - MHz 35 68 - 28 - 24 - MHz - 41 - - - - - pF - 23 40 - 50 - 60 ns - 20 - - - - - ns VCC = 4.5 V - 22 40 - 50 - 60 ns VCC = 5.0 V; CL = 15 pF - 19 - - - - - ns - 7 15 - 19 - 22 ns 20 9 - 25 - 30 - ns 25 11 - 31 - 38 - ns 0 -7 - 0 - 0 - ns 16 8 - 20 - 24 - ns 30 15 - 38 - 45 - ns 0 -3 - 0 - 0 - ns 0 -13 - 0 - 0 - ns 25 45 - 20 - 17 - MHz - 50 - - - - - MHz VCC = 6.0 V CPD power per package; dissipation VI = GND to VCC capacitance [3] 74HCT166 tpd propagation CP to Q7; see Fig. 8 delay VCC = 4.5 V [1] VCC = 5.0 V; CL = 15 pF MR to Q7; see Fig. 9 tt tW transition time output; see Fig. 8 [2] pulse width CP input HIGH or LOW; see Fig. 8 VCC = 4.5 V VCC = 4.5 V MR input LOW; see Fig. 9 VCC = 4.5 V trec tsu recovery time MR to CP; see Fig. 9 set-up time Dn, CE to CP; see Fig. 10 VCC = 4.5 V VCC = 4.5 V PE to CP; see Fig. 10 VCC = 4.5 V th hold time Dn, CE to CP; see Fig. 10 VCC = 4.5 V PE to CP; see Fig. 10 VCC = 4.5 V fmax maximum frequency CP input; see Fig. 8 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 9 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register Symbol Parameter CPD [1] [2] [3] Conditions 25 °C power per package; dissipation VI = GND to VCC - 1.5 V capacitance -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max - 41 - - - - - [3] pF tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi + Σ (CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; 2 Σ (CL x VCC x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 10.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPHL VOH tPLH 90 % 90 % VM Q7 output 10 % VOL 10 % tTHL tTLH aaa-008821 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum frequency VI VM MR input GND tW trec VI VM CP input GND tPHL VOH VM Q7 output VOL aaa-008822 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 10 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register VI see note (1) CE input VM GND tsu VI PE input th tsu th tsu th VM GND tsu VI th tsu stable VM Dn input GND tsu VI th stable VM DS input GND tsu VI CP input GND th th tW VM condition: MR = HIGH aaa-008823 The shaded areas indicate when the input is permitted to change for predictable output performance Measurement points are given in Table 8. (1) CE may change only from HIGH-to-LOW while CP is LOW Fig. 10. Set-up and hold times Table 8. Measurement points Type Input Output VI VM VM 74HC166 VCC 0.5VCC 0.5VCC 74HCT166 3V 1.3 V 1.3 V 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 11 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI VCC VO DUT RT RL S1 open CL 001aad983 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig. 11. Test circuit for measuring switching times Table 9. Test data Type Input S1 position Load VI tr, tf CL RL tPHL, tPLH 74HC166 VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HCT166 3V 6 ns 15 pF, 50 pF 1 kΩ open 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 12 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 12. Package outline SOT109-1 (SO16) 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 13 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 13. Package outline SOT403-1 (TSSOP16) 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 14 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT166 v.5 20210809 Product data sheet - 74HC_HCT166 v.4 Modifications: • • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HCT166PW (SOT403-1/TSSOP16) added. Type numbers 74HC166DB and 74HCT166DB (SOT338-1/SSOP16) removed. Section 2 updated. Section 7: Derating values for Ptot total power dissipation have been updated. 74HC_HCT166 v.4 20151228 Modifications: • 74HC_HCT166 v.3 20130911 Modifications: • • • 74HC_HCT166_CNV v.2 74HC_HCT166 Product data sheet Product data sheet - 74HC_HCT166 v.3 Type numbers 74HC166N and 74HCT166N (SOT38-4) removed. Product data sheet - 74HC_HCT166_CNV v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Family data added, see Section 9 December 1990 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 - © Nexperia B.V. 2021. All rights reserved 15 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 16 / 17 74HC166; 74HCT166 Nexperia 8-bit parallel-in/serial out shift register Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 4 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................6 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit...................................... 10 11. Package outline........................................................ 13 12. Abbreviations............................................................ 15 13. Revision history........................................................15 14. Legal information......................................................16 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 9 August 2021 74HC_HCT166 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 August 2021 © Nexperia B.V. 2021. All rights reserved 17 / 17