NJU8711V-TE2

NJU8711 3V Operation Switching Driver for Class D Amplifier PACKAGE OUTLINE GENERAL DESCRIPTION The NJU8711 is a Switching Driver for class D Amplifier including BEEP and BPZ (Bipolar Zero) output circuits. It converts 1bit digital signal input, such as PWM or PDM signal, to analog signal output with simple external LC low-pass filter. The NJU8711 realizes very high power-efficiency by class D operation. Therefore, It is suitable for portable audio set and others. NJU8711V PIN CONFIGURATION FEATURES 2-channel 1bit Audio Signal Input Standby(Hi-Z), BPZ Control Internal BPZ Charger Beep Function Operating Voltage : 2.0V to 3.6V CMOS Technology Package Outline : SSOP10 EN1 MCK VDD BEEP EN2 1 2 3 4 5 10 9 8 7 6 OUT2 IN2 VSS IN1 OUT1 BLOCK DIAGRAM VDD VSS BPZ Output OUT1 IN1 BEEP OUT2 IN2 Output Control MCK Ver.2004-06-02 EN1 BPZ Output EN2 -1- NJU8711 TERMINAL DESCRIPTION No. 3 8 SYMBOL VDD VSS I/O - 2 MCK I 1 5 7 9 EN1 EN2 IN1 IN2 4 BEEP I 6 10 OUT1 OUT2 O I I Function Power Supply, VDD=3V Power GND, VSS=0V Master Clock Input Terminal The condition of the data input terminal is fetched with the rising edge of this signal. Output Control Terminal Output circuit is selected by the condition of this terminal. Audio Signal Input Terminal 1-bit Audio Signal inputs into this terminal. Beep Signal Input Terminal Beep signal inputs into this terminal. Output Terminal • When Output Terminal selects Audio Signal, IN1 terminal input data outputs from OUT1 terminal and IN2 terminal input data outputs from OUT2 terminal. • When Output Terminal selects Beep Signal, BEEP terminal input data outputs from OUT1 and OUT2 terminals. INPUT TERMINAL STRUCTURE VDD Input Terminal Inside Circuit VSS -2- Ver.2004-06-02 NJU3555 NJU8711 FUNCTIONAL DESCRIPTION (1) Signal Output PWM signals of L channel and R output from OUT1 and OUT2 terminals respectively. These signals are converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from VDD and VSS are required high response power supply against voltage fluctuation like as switching regulator because Output T.H.D is effected by power supply stability. (2) Master Clock Master clock (MCK) synchronizes the Audio signal inputs (IN1 and IN2). The setup time and the hold time should be kept in the AC characteristics because IN1 and IN2 are fetched with the rising edge of MCK. MCK requires jitter-free or jitter as small as possible because the jitter downs S/N ratio. OUT1 and OUT2 occur the pop noise when MCK is stopped in operation without standby mode. Therefore, the standby mode should be set before MCK stop. (3) Output Control Output circuit is selected by the conditions of EN1 and EN2 terminals. EN2 EN1 0 0 Standby(High impedance) 0 1 Audio Signal Output 1 0 BPZ Output 1 1 Beep Signal Output Output State of OUT1 & OUT2 (4) Beep Function The beep signal must be input before the rising edge of EN2 signal and must be stopped after the falling edge of EN2 signal. EN1 EN2 MCK BEEP Audio Signal Output Ver.2004-06-02 Beep Signal Output Audio Signal Output -3- NJU8711 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATING UNIT Supply Voltage VDD -0.3 to +4.0 V Input Voltage Vin -0.3 to VDD+0.3 V Operating Temperature Topr -40 to +85 °C Storage Temperature Tstg -40 to +125 °C PD 280 mW Power Dissipation SSOP10 Note 1) All voltage values are specified as VSS=0V. Note 2) If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electrical characteristics conditions will cause malfunction and poor reliability. Note 3) Decoupling capacitors should be connected between VDD-VSS due to the stabilized operation. ELECTRICAL CHARACTERISTICS (Ta=25°C, VDD=3.0V, VSS=0.0V, Load Impedance=16Ω, fS=44.1kHz, unless otherwise noted) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT VDD Supply Voltage VDD 2.0 3.0 3.6 V BPZ Driving Voltage VBPZ VDD /2-0.2 VDD /2 VDD /2+0.2 V Output Driver High side Resistance RH VOUT=VDD-0.1V - 1.5 2 Ω Output Driver Low side Resistance RL VOUT=0.1V - 1.5 2 Ω High side Current IBH VOUT=VDD-1V 100 250 600 uA Low side Current IBL VOUT=1V 100 250 600 uA - - 1 uA - 1 2 mA VIH 0.7VDD - VDD V VIL 0 - 0.3VDD V ILK - - ±1 uA Beep Beep Operating Current At Standby IST Operating Current At no input signal IDD Stopping MCK, IN1, IN2, BEEP No-load operating IN1, IN2=32fS MCK=256fS Input Voltage Input Leakage Current Note 4) When VDD Supply Voltage is lower than typical voltage, a pop noise may occur in output change between BPZ and Audio Signal. Therefore, please consider and check the circuit carefully against pop noise. -4- Ver.2004-06-02 NJU3555 NJU8711 TIMING CHARACTERISTICS • Audio Signal Input tMCKH tMCKL MCK tMCKI IN1, IN2 tDS PARAMETER SYMBOL tDH (Ta=25°C, VDD=3.0V, VSS=0.0V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT MCK Frequency fMCKI 8 - 25 MHz MCK Pulse Width (H) tMCKH 12 - - ns MCK Pulse Width (L) tMCKL 12 - - ns IN1,IN2 Setup Time tDS 20 - - ns IN1,IN2 Hold Time tDH 20 - - ns Note 5) tMCKI shows the cycle of the MCK signal. • Output Control Signal Input EN1,EN2 tUP PARAMETER SYMBOL tDN (Ta=25°C, VDD=3.0V, VSS=0.0V, unless otherwise noted) CONDITIONS MIN. TYP. MAX. UNIT Rise Time tUP - - 100 ns Fall Time tDN - - 100 ns Note 6) All timings are based on 30% and 70% voltage level of VDD. Ver.2004-06-02 -5- NJU8711 APPLICATION CIRCUIT Stereo OTL application example 1 Output Control 5 Master Clock 2 BEEP EN1 OUT2 10 100uH VDD VSS 2.2uF 100uF 3 7 9 Beep Signal 4 1 Output Control 5 Master Clock 2 •A915BY-220M is manufactured by TOKO, INC. For further information, please refer to its technical papers. A915BY-220M IN1 OUT1 6 22uH IN2 BEEP EN1 NJU8711 Audio Signal Switching Regulator 8 1 channel BTL application example • 1kΩ Headphone 220uF A915BY-101M EN2 MCK 16Ω 1kΩ 4 100uH 22uH OUT2 10 8Ω Speaker A915BY-220M EN2 VDD MCK 1.5uF Beep Signal IN2 1.5uF 9 OUT1 6 0.22uF Audio Signal 220uF A915BY-101M IN1 0.22uF 7 •A915BY-220M is manufactured by TOKO, INC. For further information, please refer to its technical papers. NJU8711 • VSS 2.2uF 100uF 3 Switching Regulator 8 Note 7) De-coupling capacitors must be connected between each power supply pin and GND pin. Note 8) The power supply for VDD requires fast driving response performance such as a switching regulator for THD. Note 9) The bigger capacitor value of external AC-coupling capacitors realize better low frequency response characteristics. In addition, ESR(Equivalent Series Resistance) should be low. Note 10) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please consider and check the circuit carefully to fit your application. -6- Ver.2004-06-02 NJU3555 NJU8711 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. Ver.2004-06-02 -7-