Table of Contents
1
2
3
4
DESCRIPTION .................................................................................................................................................2
PINOUT ............................................................................................................................................................. 3
PIN DESCRIPTIONS .......................................................................................................................................4
ELECTRICAL CHARACTERISTICS .............................................................................................................6
4.1
4.2
4.3
AC Characteristics (Bridge Tied Load) .........................................................................................................6
AC Characteristics (Single Ended) ...............................................................................................................7
DC Characteristics .......................................................................................................................................8
CONDITIONS: PVDDX = 18V RLOAD = 8OHMS, F_PWM = 300KHZ .....................................................................8
CONDITIONS: PVDDX = 18V RLOAD = 8OHMS, F_PWM = 300KHZ .....................................................................9
4.4
4.5
5
6
7
Absolute Maximum Ratings ..........................................................................................................................9
Recommended Operating Conditions ..........................................................................................................9
TYPICAL OPERATING CHARACTERISTICS ........................................................................................... 10
TYPICAL OPERATING CHARACTERISTICS ........................................................................................... 15
SPECIAL FEATURE DESCRIPTION.......................................................................................................... 19
7.1
Device Fault Detection ............................................................................................................................... 19
7.1.1
Thermal Overload Detection ............................................................................................................... 19
7.1.2
Short Circuit Detection ........................................................................................................................ 19
7.1.3
Supply under Voltage Detection .......................................................................................................... 19
7.2
8
Power up and Power down Control ............................................................................................................ 19
APPLICATION INFORMATION ................................................................................................................... 20
Differential BTL Application with Modulation Filters ............................................................................................ 20
Single Ended Application with Modulation Filters ............................................................................................... 21
8.1
Component Selection ................................................................................................................................. 23
8.1.1
Bypass Capacitors .............................................................................................................................. 23
8.1.2
Bootstrap Circuit (BSTxx) .................................................................................................................... 23
8.1.3
3V and 5V LDOs ................................................................................................................................. 23
8.2
9
Layout considerations ................................................................................................................................ 23
OPERATION ................................................................................................................................................... 23
9.1
Power Supplies .......................................................................................................................................... 23
9.2
System Power Up and Power Down Sequence ......................................................................................... 23
9.2.1
Power Up ............................................................................................................................................ 23
9.2.2
Recommended Power up Sequence................................................................................................... 24
9.2.3
Power Down ........................................................................................................................................ 24
9.2.4
Recommended Power down Sequence .............................................................................................. 24
9.3
Error Reporting ........................................................................................................................................... 24
9.4
Device Exception Handling System ........................................................................................................... 25
9.4.1
Device Standby and Reset .................................................................................................................. 25
10
11
9.4.2
Thermal Information ............................................................................................................................ 25
9.4.3
Slew Rate Configuration ..................................................................................................................... 25
PACKAGE DIMENSIONS ............................................................................................................................. 26
ORDERING INFORMATION ........................................................................................................................ 27
NAU83P20YG Datasheet Rev1.8
Page 1 of 28
October 2014
NAU83P20 Data sheet
NAU83P20
20W Stereo Class-D Audio Amplifier
1 Description
The NAU83P20 is single supply, 20W, high efficiency, Class-D audio power stage for driving Stereo
bridge-tied speakers. Operating from a single VDD 8V-24V supply, the design includes under-voltage,
over-current and over-temperature detection.
NAU83P20 is available in the QFN 48 package.
Key Features
Applications
Class D power 2x20W into 8Ohms (10% THD)
Typical power efficiency of 90%
105dB SNR
Slew control
3V LDO to power PWM controller
Supports multiple output configurations:
2-CH Bridged outputs (20Wx2)
4-CH single ended outputs (10Wx4)
2-CH single ended + 1-CH bridged (10Wx2
+ 20Wx1)
Fault Detection:
Over-Temperature
Under-Voltage
Over-Current
STBYB
LCD TV’s
TV sound bars
Car Audio
Portable Media “Boom Boxes”
Home entertainment systems
VDD
PWM1A
Control
Gate
Driver
Control
Gate
Driver
Control
Gate
Driver
Control
Gate
Driver
PWM Receiver
PWM1B
PWM2A
PWM Receiver
PWM2B
Under Voltage
Over Current
Over Temp
Fault
5V LDO
Current / Thermal
Detection
3V LDO
VSS
NAU83P20
Figure 1: NAU83P20 Block Diagram
emPowerAudio™
NAU83P20 20W Class D
PWM1B
NC
PWM1A
BST2A
PVSS2
PVSS2
OUT2A
OUT2A
PVDD2
PVDD2
OUT2B
OUT2B
48
32
47
31
46
30
45
29
44
28
43
27
42
26
41
25
40
28
39
27
38
26
37
25
2 Pinout
FAULTB
1
36
24
PVSS2
TWARNB
2
35
23
PVSS2
ENSLEWB
3
34
22
BST2B
4
33
21
VDDHV
REGVSS
5
32
24
NC
REG3V
6
31
23
REGVSS
PWM2A
PWM2B
7
30
22
REG5V
8
29
21
SDLATB
OTEMPB
9
5
28
20
NC
OCURRB
10
6
27
19
BST1B
UVOLTB
11
26
18
PVSS1
RESET
12
25
17
PVSS1
15
11
16
12
17
13
18
14
19
15
20
16
21
13
22
14
23
15
24
16
BST1A
PVSS1
PVSS1
OUT1A
OUT1A
PVDD1
PVDD1
OUT1B
OUT1B
14
10
NC
NC
13
9
NAU83P20
48-lead QFN
RoHS
VREF
STBYB
Part Number
Dimension
Package
Package
Material
NAU83P20YG
7 x 7 mm
48-QFN
Green
NAU83P20YG Datasheet Rev1.8
Page 3 of 28
January 12, 2015
NAU83P20 20W Class D
3 Pin Descriptions
Pin #
Name
Type
1
FAULTB
Digital Output
Device Error Signal. Active Low if Over current, Under
Voltage or Over temperature faults occur.
2
TWARNB
Digital Output
Over Temperature Warning Signal. Active Low if device
internal temperature is 120°C
3
ENSLEWB
Digital Input
Enable Slew rate control on the output drivers. Change
Slew Rate of PWM Output
4
STBYB
Digital Input
Standby Bar, Disables all 4 PWM Outputs.
5
REGVSS
Supply
6
REG3V
Supply Output
7
PWM2A
PWM Input
Channel 2A Pulse Width Modulation Signal Input
8
PWM2B
PWM Input
Channel 2B Pulse Width Modulation Signal Input
9
OTEMPB
Digital Output
Over Temperature Fault Signal. Active Low if device
internal temperature is 145°C.
10
OCURRB
Digital Output
Over Current Fault Signal. Active Low if current drawn
from any of the output drivers is > 6 A.
11
UVOLTB
Digital Output
Under Voltage Fault Signal. Active Low if the supply
voltage is under 4.75V.
12
RESET
Digital Input
13
VREF
I
Internal Reference Voltage
14
N/C
-
No Connect
15
N/C
-
No Connect
16
BST1A
Supply
Channel 1A High Side Bootstrap Supply
17
PVSS1
Supply
Channel 1 Power Ground
18
PVSS1
Supply
Channel 1 Power Ground
19
OUT1A
PWM Output
Channel 1A Pulse Width Modulation Signal Output
20
OUT1A
PWM Output
Channel 1A Pulse Width Modulation Signal Output
21
PVDD1
Supply
Channel 1 Power Supply
22
PVDD1
Supply
Channel 1 Power Supply
23
OUT1B
PWM Output
Channel 1B Pulse Width Modulation Signal Output
24
OUT1B
PWM Output
Channel 1B Pulse Width Modulation Signal Output
25
PVSS1
Supply
Channel 1 Power Ground
26
PVSS1
Supply
Channel 1 Power Ground
27
BST1B
Supply
Channel 1B High Side Bootstrap Supply
28
N/C
-
29
SDLATB
Digital Output
Device Shutdown Latch Signal, This signal will latch low,
if the Over current fault occurs. This flag is cleared by
RESET.
30
REG5V
Supply Output
5V Regulator Supply Output
31
REGVSS
Supply
NAU83P20YG Datasheet Rev1.8
Functionality
3V Regulator Ground
3V Regulator Supply Output
Reset, Resets SDLATB
No Connect
5V Regulator Ground
Page 4 of 28
January 12, 2015
NAU83P20 20W Class D
32
N/C
-
No Connect
33
VDDHV
Supply
Supply for Regulators
34
BST2B
Supply
Channel 2B High Side Bootstrap Supply
35
PVSS2
Supply
Channel 2 Power Ground
36
PVSS2
Supply
Channel 2 Power Ground
37
OUT2B
PWM Output
Channel 2B Pulse Width Modulation Signal Output
38
OUT2B
PWM Output
Channel 2B Pulse Width Modulation Signal Output
39
PVDD2
Supply
Channel 2 Power Supply
40
PVDD2
Supply
Channel 2 Power Supply
41
OUT2A
PWM Output
Channel 2A Pulse Width Modulation Signal Output
42
OUT2A
PWM Output
Channel 2A Pulse Width Modulation Signal Output
43
PVSS2
Supply
Channel 2 Power Ground
44
PVSS2
Supply
Channel 2 Power Ground
45
BST2A
Supply
Channel 2A High Side Bootstrap Supply
46
PWM1A
PWM Input
47
N/C
-
48
PWM1B
PWM Input
Channel 1A Pulse Width Modulation Signal Input
No Connect
Channel 1B Pulse Width Modulation Signal Input
Table 1: NAU83P20 Pin description
NAU83P20YG Datasheet Rev1.8
Page 5 of 28
January 12, 2015
NAU83P20 20W Class D
4 Electrical Characteristics
4.1
AC Characteristics (Bridge Tied Load)
Conditions: PVDDx = 18V, Rload = 8 Ohms, Audio Frequency = 1KHz, AES17 filter, F_PWM = 300KHz, Slew
disabled, Ambient temp = 25C. NAU82011 are used as input device unless otherwise stated
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Power Delivered
Power Output per
Channel
Total Harmonic
Po
ZL = 8Ω + 68µH
PVDDx = 18V
20
THD + N = 10%
PVDDx = 12V
9
ZL = 8Ω + 68µH
PVDDx = 18V
18
THD + N = 1%
PVDDx = 12V
8
Po=10W (Half
Power)
PVDDx = 18V
0.15
Po=4.5W(Half
Power)
PVDDx = 12V
0.08
%
W
Distortion + Noise
THD+
N
Output Integrated
Noise*
Vn
A-Weighted
50
uVrms
Signal to Noise
Ratio*
SNR
A-Weighted
105
dB
Dynamic Range*
DNR
A-Weighted Input=60dbFS
105
dB
Power
Dissipation Due
to Idle Losses
PD
Po=0W, 4 channels
switching
0.6
W
* Using a signal generator with the same input applied to all channels
NAU83P20YG Datasheet Rev1.8
Page 6 of 28
January 12, 2015
NAU83P20 20W Class D
4.2
AC Characteristics (Single Ended)
Conditions: PVDDx = 18V, Rload = 8 Ohms, Audio Frequency = 1KHz, AES17 filter, F_PWM = 300KHz,
Ambient temp = 25C NAU82011 are used as input device unless otherwise stated.
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Power Delivered
Power Output per
Channel
Po
ZL = 8Ω + 68µH
PVDDx = 18V
10
THD + N = 10%
PVDDx = 12V
4.5
ZL = 8Ω + 68µH
PVDDx = 18V
9
THD + N = 1%
PVDDx = 12V
4
Po=10W (Half
Power)
PVDDx = 18V
0.2
Po=4.5W(Half
Power)
PVDDx = 12V
0.2
%
W
Total Harmonic
Distortion + Noise
THD+
N
Output Integrated
Noise
Vn
A-Weighted
50
uVrms
Signal to Noise
Ratio*
SNR
A-Weighted
105
dB
Dynamic Range*
DNR
A-Weighted Input=60dbFS
105
dB
Power
Dissipation Due
to Idle Losses
PD
Po=0W, 4 channels
switching
0.6
W
*Using a signal generator with the same input applied to all channels
NAU83P20YG Datasheet Rev1.8
Page 7 of 28
January 12, 2015
NAU83P20 20W Class D
Electrical Characteristics (continued)
4.3
DC Characteristics
Conditions: PVDDX = 18V Rload = 8Ohms, F_PWM = 300KHz
Parameter
Half-bridge supply
Internal Supply for Regulators
Symbol
Comments/Conditions
Min
Typ
Max
Units
PVDDX
VDDHV
8
18
24
V
8
18
24
V
STBYB= 1
Quiescent Current
Consumption
IQUI
Input at 50% duty
cycle with output filter
60
mA
13
mA
STBYB= 0
Input at 50% duty
cycle with output filter
I/O Detection
Under voltage detection limit,
falling
Vuvp
Under voltage detection limit,
rising
Vuvp
Over temperature warning
OTW
125
ºC
Over temperature Error
OTE
150
ºC
Over temperature Hysteresis
OTW HYST
30
ºC
Overcurrent Limit detection
IOC
4.5
A
Overcurrent Response Time
IOCT
1
us
High-level input voltage
VIH
2
V
Low-level input voltage
VIL
PWM1A/1B/2A/2B,
STBY
0.8
V
IIkg
PWM1A/1B/2A/2B,
STBY
Input leakage Current, High
Input leakage Current, Low
NAU83P20YG Datasheet Rev1.8
5.5
V
7
Page 8 of 28
V
100
-10
10
January 12, 2015
uA
NAU83P20 20W Class D
Conditions: PVDDX = 18v Rload = 8Ohms, F_PWM = 300KHz
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
Internal Voltage Regulator and Current Consumption
Regulator output
REG3V
Supply Current 3 VREG
4.4
I (Load)
3
V
With 100ohm Load:
REG3V typ. 3.3V
30
mA
Standby mode no
Switching
6.5
mA
Absolute Maximum Ratings
Parameter
Min
Max
Units
Supply
-0.50
25
V
Industrial operating temperature
-40
+85
°C
Storage temperature range
-65
+150
°C
Junction temperature range
-40
+150
°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods. Exposure to such
conditions may adversely influence product reliability and result in failures not covered by warranty.
4.5
Recommended Operating Conditions
Parameter
Supply range
Symbol
PVDD1,2
Digital Input Supply
Voltage
REG3V
Test Condition
DC supply voltage
DC supply voltage
Min
24
V
3
3.3
3.6
V
DC Ground
PWM frame rate
Fpwm
192
Tj
0
RL(SE)
Load Impedance
Output filter: L =10µH, C= 470nF
Output AD modulation switching
frequency >350Khz
RL(PBTL)
Lo(BTL)
0
V
384
432
Khz
125
ºC
6-8
3-4
3-4
Minimum output inductance
under short circuit condition
Units
18
VSS
RL(BTL)
Max
8
Ground
Junction
Temperature
Typical
Ω
Ω
Ω
200
nH
Lo(SE)
200
nH
Lo(PBTL)
200
nH
Output Filter
inductance
NAU83P20YG Datasheet Rev1.8
Page 9 of 28
January 12, 2015
NAU83P20 20W Class D
5 Typical Operating Characteristics
5.1
BTL
10
1
Po=0.5W
0.1
Po=2.5W
Po=5W
0.01
0.001
20
200
2000
20000
THD+N vs Frequency, Vcc=8V, Rl= 8 BTL
10
1
Po=0.5W
0.1
Po=1W
Po=5W
0.01
0.001
20
200
2000
20000
THD+N vs Frequency, Vcc=12V, Rl= 8 BTL
NAU83P20YG Datasheet Rev1.8
Page 10 of 28
January 12, 2015
NAU83P20 20W Class D
10
1
Po=1W
0.1
Po=5W
Po=10W
0.01
0.001
20
200
2000
20000
THD+N vs Frequency, Vcc=18V, Rl= 8 BTL
10
1
f=20Hz
f=1kHz
f=10kHz
0.1
0.01
0.01
0.1
1
10
100
THD+N vs Output Power Vcc=8V, Rl= 8 BTL
NAU83P20YG Datasheet Rev1.8
Page 11 of 28
January 12, 2015
NAU83P20 20W Class D
10
1
f=20Hz
f=1kHz
f=10kHz
0.1
0.01
0.01
0.1
1
10
100
THD+N vs Output Power Vcc=12V, Rl= 8 BTL
10
1
f=20Hz
f=1kHz
f=10kHz
0.1
0.01
0.01
0.1
1
10
100
THD+N vs Output Power Vcc=8V, Rl= 8 BTL
NAU83P20YG Datasheet Rev1.8
Page 12 of 28
January 12, 2015
NAU83P20 20W Class D
-20
-30
-40
-50
Left to Right
-60
Right to Left
-70
-80
-90
-100
20
200
2000
20000
Crosstalk vs Frequency Vcc=18V Rl=4 Po=0.25W SE
Efficency vs
Output Power
100
90
80
70
60
8V
50
12V
40
18V
30
20
10
0
0
5
10
15
20
25
30
F=1kHz Rl=8 BTL
NAU83P20YG Datasheet Rev1.8
Page 13 of 28
January 12, 2015
NAU83P20 20W Class D
3
Supply Current vs
Total Output Power
2.5
2
8V
1.5
12V
18V
1
0.5
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44
F=1kHz Rl=8 BTL
40
Output Power vs
Supply Voltage
35
30
25
10% Left
20
10% Right
1% Left
15
1% Right
10
5
0
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
F=1kHz Rl=8 SE
NAU83P20YG Datasheet Rev1.8
Page 14 of 28
January 12, 2015
NAU83P20 20W Class D
6 Typical Operating Characteristics
6.1
SE
0
-10
20
200
2000
20000
-20
-30
-40
Left to Right
-50
Right to Left
-60
-70
-80
-90
-100
Crosstalk vs Frequency, Vcc=18V Rl=4 Po=0.25W SE
10
1
Po=0.5W
0.1
Po=1W
Po=2.5W
0.01
0.001
20
200
2000
20000
THD+N vs Frequency, Vcc=12V Rl=4 SE
NAU83P20YG Datasheet Rev1.8
Page 15 of 28
January 12, 2015
NAU83P20 20W Class D
10
1
Po=0.5W
0.1
Po=2.5W
Po=5W
0.01
0.001
20
200
2000
20000
THD+N vs Frequency, Vcc=18V Rl=4 SE
10
1
12V
18V
0.1
0.01
0.1
1
10
100
THD+N vs Output Power, F=1kHz Rl=4 SE
NAU83P20YG Datasheet Rev1.8
Page 16 of 28
January 12, 2015
NAU83P20 20W Class D
18
15
12
1%
9
10%
6
3
0
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Output Power vs Supply Voltage , F=1kHz Rl=8 SE
3
2.5
2
18V
1.5
12V
8V
1
0.5
0
0
10
20
30
40
50
Supply Current vs Output Power, F=1kHz Rl=4 SE
NAU83P20YG Datasheet Rev1.8
Page 17 of 28
January 12, 2015
NAU83P20 20W Class D
0
-20
-40
-60
-80
-100
8
10
12
14
16
18
20
22
24
A-Weighted Noise vs Supply Voltage, F=1kHz Rl=4 SE
NAU83P20YG Datasheet Rev1.8
Page 18 of 28
January 12, 2015
NAU83P20 20W Class D
7 Special Feature Description
The NAU83P20, in addition to high efficiency, also provides the following protection features.
7.1
Device Fault Detection
The NAU83P20 includes device fault detection for three operating scenarios. They are
1. Thermal Overload
2. Short circuit
3. Supply under voltage
7.1.1 Thermal Overload Detection
When the device internal junction temperature reaches 125°C, the NAU83P20 will force the TWARNB digital
output low. If the temperature continues to rise to 150°C, the NAU83P20 will force the OTEMPB digital output
low. When the device cools down and a safe operating temperature of 125°C has been reached, the
TWARNB and OTEMPB digital outputs will return to their default states, high.
7.1.2 Short Circuit Detection
If a short circuit condition is detected on any of the output drivers the NAU83P20 will force the OCURRB
digital output low. The OCURRB digital output will remain low until the short circuit condition has been
removed. The short circuit threshold is 4.5A.
7.1.3 Supply under Voltage Detection
If the supply voltage drops under 5.5 V, the NAU83P20 will force the UVOLTB digital output low. UVOLTB
digital output will remain low until the supply voltage returns to a level > 7V.
7.2
Power up and Power down Control
When the PVDD supply voltage ramps up, the 3V and the 5V LDOs also power up. The STBYB pin only
controls the operation of the 4 half bridge drivers. When STBYB is low, the 4 half bridge drivers are in the high
impedance state. STBYB is high, enables the 4 half bridge drivers. The recommended power up sequence is
to hold the STBYB pin low, apply the PVDD supply, wait until the 3V and 5V LDO’s are stable, apply
STBYB=1 and then start driving the PWM input signals.
NAU83P20YG Datasheet Rev1.8
Page 19 of 28
January 12, 2015
NAU83P20 20W Class D
8 Application Information
Differential BTL Application with Modulation Filters
VREF
PVDD
PVDD1
+
0.1uF/16V
BST1A
0.033uF
50V
OUT1A
10nF
50V
10uH
10uH
PWM1A
PWM1B
PWM2A
PWM2B
0.1uF/50V
10uF/50V
220uF/50V
3.3
0.47uF
50V
0.47uF
50V
3.3
OUT1B
BST1B
REG3V
10nF
50V
0.033uF
50V
PVSS1
0.1uF/16V
PVDD2
REG5V
PVDD
+
0.1uF/16V
FAULTB
TWARNB
OTEMPB
BST2A
0.033uF
50V
OUT2A
10uH
OCURRB
UVOLTB
10uH
SDLATB
OUT2B
STBYB
RESET
0.1uF/50V
10uF/50V
220uF/50V
0.47uF
50V
0.47uF
50V
10nF
50V
3.3
10nF
50V
3.3
0.033uF
50V
BST2B
VDDHV
0.1uF/16V
PVSS2
NAU83P20
NAU83P20YG Datasheet Rev1.8
Page 20 of 28
January 12, 2015
NAU83P20 20W Class D
Single Ended Application with Modulation Filters
VREF
PVDD
PVDD1
+
0.1uF/16V
BST1A
0.1uF/50V
10uF/50V
220uF/50V
0.033uF
50V
OUT1A
10nF
50V
22uH
3.3
PVDD
PWM1A
PWM1B
PWM2A
PWM2B
OUT1B
10Kohms
10Kohms
330uF
330uF
BST1B
REG3V
PVSS1
0.1uF/16V
REG5V
PVDD2
PVDD
+
0.1uF/16V
FAULTB
TWARNB
OTEMPB
BST2A
OUT2A
0.1uF/50V
10uF/50V
220uF/50V
0.033uF
50V
10nF
50V
22uH
3.3
OCURRB
UVOLTB
PVDD
SDLATB
OUT2B
STBYB
RESET
NAU83P20YG Datasheet Rev1.8
10Kohms
BST2B
VDDHV
0.1uF/16V
10Kohms
330uF
330uF
PVSS2
Page 21 of 28
January 12, 2015
NAU83P20 20W Class D
Sub-Woofer Application with Modulation Filters
VREF
PVDD
PVDD1
0.1uF/50V
10uF/50V
220uF/50V
+
0.1uF/16V
BST1A
0.033uF
50V
10nF
50V
3.3
22uH
OUT1A
PVDD
10Kohms
330uF
PWM1A
PWM1B
PWM2A
PWM2B
10Kohms
330uF
OUT1B
0.033uF
50V
10nF
50V
3.3
22uH
BST1B
PVDD
REG3V
0.1uF/16V
10Kohms
10Kohms
PVSS1
REG5V
330uF
330uF
0.1uF/16V
PVDD2
+
FAULTB
TWARNB
OTEMPB
BST2A
OCURRB
0.033uF
50V
10uH
OUT2A
UVOLTB
0.47uF
50V
0.47uF
50V
SDLATB
OUT2B
STBYB
RESET
BST2B
0.033uF
50V
PVDD
0.1uF/50V
10uF/50V
220uF/50V
10nF
50V
3.3
10nF
50V
3.3
10uH
VDDHV
0.1uF/16V
PVSS2
NAU83P20
NAU83P20YG Datasheet Rev1.8
Page 22 of 28
January 12, 2015
NAU83P20 20W Class D
8.1
Component Selection
8.1.1 Bypass Capacitors
Bypass capacitors are required to remove the ac ripple on the PVDDx pins. The value of these capacitors
depends on the length of the PVDDx trace. In most cases, 10uF and 0.1uF are sufficient to ensure optimum
performance. In addition, 220uF capacitors should be added to remove the additional ripple on the high
current PVDDx inputs.
8.1.2 Bootstrap Circuit (BSTxx)
In order for the bootstrap circuit to function correctly, a ceramic capacitor must be added between BSTx and
OUTx. In applications with PWM switching frequencies of 300kHz a 0.22uF capacitor is recommended. If the
application involves a higher or lower PWM switching frequency, the capacitor size may need to be
decreased or increased respectively.
8.1.3 3V and 5V LDOs
In order for the internal regulators to function more efficiently, a 0.1uF capacitor needs to be placed between
the REG3V, REG5V pins and ground.
8.2
Layout considerations
Good PCB layout and grounding techniques are essential to get the good audio performance. It is
recommended to use low resistance traces for the outputs as these devices are driving low impedance loads.
The resistance of the traces has a significant effect on the output power delivered to the load. In order to
dissipate more heat, use wide traces for the power and ground lines.
9 Operation
9.1
Power Supplies
The NAU83P20 requires one 8-24V supply in order to operate. The boost voltage supplies required by the
high-side gate driver is realized by mostly built-in circuitry requiring only a few external capacitors. The power
supply should be low output impedance and low noise.
In order to provide high quality electrical and audio characteristics the output stages are identical but
independent half-bridges. Each half-bridge has separate bootstrap power supply pin and voltage regulator for
efficient gate drive operation. The supply for the common logic circuits is derived from internal voltage
regulators, which translate the VDDHV pin supply, allowing for single supply operation.
In order for the bootstrap circuit to function correctly, a ceramic capacitor is added between the BSTxx and
the OUTxx pins. When the output of the power stage is low, the capacitor is charged and when the output is
high, the capacitor potential is shifted above the output potential providing a full rail to rail output. Refer to
Section 7 for recommended capacitor values.
9.2
System Power Up and Power Down Sequence
9.2.1 Power Up
It is recommended that the STBYB be held low to tri-state the output drivers until the PVDDx voltage rises
above the under voltage detection threshold of 7V. Holding STBYB in a low state while powering up also
helps to ensure that the bootstrap capacitors are fully charged before the chip begins operation.
NAU83P20YG Datasheet Rev1.8
Page 23 of 28
January 12, 2015
NAU83P20 20W Class D
9.2.2 Recommended Power up Sequence
1.
2.
3.
4.
5.
6.
7.
With PVDDx Low
Hold STBYB LOW
Apply Power to PVDDx
Wait 10ms for the chip to power up
Apply input modulation signal at 50% duty cycle
Hold STBYB HIGH
The device will begin to modulate
9.2.3 Power Down
The device will remain fully powered on as long as PVDDx remain above the under voltage detection
threshold. It is recommended to hold STBY low during power down; this will prevent clicks and pops.
9.2.4 Recommended Power down Sequence
1.
2.
3.
4.
5.
9.3
With STBYB and PVDDx High
Hold STBYB Low tri-stating the drivers
Wait 10ms while the drivers tri-state
Remove all input signals
Remove power from PVDDx
Error Reporting
The FAULTB pin is an active-low, open-drain output. The over temperature, over current, and under voltage
pins are active-low, open-drain outputs. The function of these pins is to report errors in the chip to the PWM
controller, micro controller, or other system control device.
Pin
Causes
FAULTB
Any low transition on
(FAULTB= 0)
OTEMPB, OCRURB, UVOLTB
OTEMPB
(FAULTB= 1)
OCURRB
(FAULTB)
Device junction temperature above
145°C
The Current limit is set at 4.5A
UVOLTB
(FAULTB=1)
PVDDx has fallen below the minimal
5.5V required for chip operation
NAU83P20YG Datasheet Rev1.8
Page 24 of 28
January 12, 2015
NAU83P20 20W Class D
9.4
Device Exception Handling System
The NAU83P20 has several error reporting signals used for device fault detection. The system has been
designed so that it can be easily integrated into a system that will be able to adjust operating parameters in
order to allow the device to operate within its specified limits.
There are six signals related to the exception handling system, which are output to device pins:
1.
2.
3.
4.
5.
6.
Fault (FAULTB)
Temperature Warning (TWARNB)
Over Temperature (OTEMPB)
Over Current (OCURRB)
Under Voltage (UVOLTB)
Shutdown Latch (SDLATB)
All 6 signal pins are open drain, active low outputs.
9.4.1 Device Standby and Reset
The STBYB pin controls the half-bridges. Setting STBYB low forces the half-bridges into a high impedance
state. The device will also be in a low current state. The STBYB pin can also be used for hard muting the
power stage.
For stand-alone fault protection, it is possible to tie the FAULTB pin to STBYB. In this configuration any fault
detection reported by the FAULTB pin going low will force STBYB low, therefore, minimizing any possible
damage to the device from over-current or over-temperature issues.
In BTL modes driving the STBYB pin low will enable weak pull down of the half-bridge circuits causing the
bootstrap capacitors to charge.
RESET pin resets the SDLATB pin.
9.4.2 Thermal Information
The QFN-48 package is intended to be interfaced with an exposed heat-sink pad on the underside of the
PCB. This can be accomplished by passing plugged thermal vias from pin 49 (exposed pad) of the package
through all of the PCB layers to an exposed metal layer on the opposite side. If additional thermal
management is required, a heat sink can be attached to this exposed metal layer allowing for additional heat
dissipation.
9.4.3 Slew Rate Configuration
The ENSLEWB pin is used to change the slew rate of the output drivers. There are 2 settings:
1. ENSLEWB = 0 (Default) :
2. ENBSLEWB = 1
:
NAU83P20YG Datasheet Rev1.8
Output Driver Slew rate = 5ns
Output Driver Slew rate = 2ns
Page 25 of 28
January 12, 2015
NAU83P20 20W Class D
10 Package Dimensions
48-lead plastic QFN 48L; 7X7mm2, 0.8mm thickness, 0.5mm lead pitch
COPLANARITY
SYMBOL
MIN
NOM
MAX
TOTAL THICKNESS
A
0.80
0.85
0.90
STAND OFF
A1
0.00
0.04
0.05
MOLD THICKNESS
A2
---
0.65
0.67
L/F THICKNESS
A3
0.203 REF
LEAD WIDTH
b
0.20
BODY SIZE
D
7.0 BSC
E
7.0 BSC
LEAD PITCH
e
0.5 BSC
LEAD LENGTH
L
0.30
0.25
0.40
PACKAGE EDGE TOLERANCE
aaa
0.10
MOLD FLATNESS
bbb
0.10
COPLANARITY
ccc
0.08
LEAD OFFSET
ddd
0.10
EXPOSED PAD OFFSET
eee
0.10
NAU83P20YG Datasheet Rev1.8
Page 26 of 28
0.30
0.50
January 12, 2015
NAU83P20 20W Class D
11 Ordering Information
Nuvoton Part Number Description
NAU83P20YG
Package Material:
G=Green Package
Package Type:
Y = QFN package
NAU83P20YG Datasheet Rev1.8
Page 27 of 28
January 12, 2015
NAU83P20 20W Class D
Version History
VERSION
DATE
PAGE
NAU83P20
Datasheet
Rev1.0
Jan., 2013
NA
DESCRIPTION
Revision1.0
Change block diagram Input labels to PWM##
1,
Update Single Chip Pin-out Diagram
2,
NAU83P20
Datasheet
Rev1.1
Update Single Chip Pin description
3,4,
April, 2013
Change Fault Protection to Fault Detection and update
action description.
10
12
Remove OC_ADJ and STTIMER descriptions. These
are not available.
15
Update Package drawing to QFN48 Saw Type.
16
Change Pkg type designator to Y = QFN
NAU83P20
Datasheet
Rev1.3
Oct., 2013
2
Package material changed from Pb-free to Green
7
Remove Over Current Resistor
12
Update Signal Ended configuration circuit
14
Updated recommended power up/down sequence
All
NAU83P20
Datasheet
Rev1.4
August,25,14
All
AC/DC parameters were updated, Changed pin-out by
deleting a test pin. Made changes to Application
diagrams.
Rev 1.6
Oct, 14, 2014
All
Updated application diagrams, added table contents
Rev 1.7
Oct, 24, 2014
10-18
Updated Performance Graphs
Rev1.8
January
21,2015
26
Updates package information.
Table 1: Version History
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or
equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other
applications intended to support or sustain life. Furthermore, Nuvoton products are not intended for
applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales.
NAU83P20YG Datasheet Rev1.8
Page 28 of 28
January 12, 2015
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