XC7SET32GV,125

XC7SET32 2-input OR gate Rev. 2 — 13 January 2022 Product data sheet 1. General description XC7SET32 is a high-speed Si-gate CMOS device. It provides a 2-input OR function. 2. Features • • • • • • • Symmetrical output impedance High noise immunity Low power dissipation TTL input levels Balanced propagation delays ESD protection: • HBM JESD22-A114E: exceeds 2000 V • MM JESD22-A115-A: exceeds 200 V • CDM JESD22-C101C: exceeds 1000 V Specified from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version XC7SET32GW -40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 XC7SET32GV -40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753 4. Marking Table 2. Marking codes Type number Marking code [1] XC7SET32GW gG XC7SET32GV g32 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. XC7SET32 Nexperia 2-input OR gate 5. Functional diagram 1 B 2 A 4 Y B 1 ≥1 Y A mna165 mna164 Fig. 1. 4 2 Logic symbol Fig. 2. IEC logic symbol Fig. 3. mna166 Logic diagram 6. Pinning information 6.1. Pinning XC7SET32 B 1 A 2 GND 3 5 VCC 4 Y 001aak116 Fig. 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A) 6.2. Pin description Table 3. Pin description Symbol Pin Description B 1 data input A 2 data input GND 3 ground (0 V) Y 4 data output VCC 5 supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Output Inputs A B Y L L L L H H H L H H H H XC7SET32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 2 / 10 XC7SET32 Nexperia 2-input OR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +7.0 V VI input voltage -0.5 +7.0 V IIK input clamping current VI < -0.5 V IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V IO output current -0.5 V < VO < VCC + 0.5 V ICC -20 - mA - ±20 mA - ±25 mA supply current - 75 mA IGND ground current -75 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] [1] Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT753 (SC-74A) package: Ptot derates linearly with 3.8 mW/K above 85 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Typ Max Unit 4.5 5.0 5.5 V input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature -40 +25 +125 °C Δt/ΔV input transition rise and fall rate - - 20 VCC supply voltage VI XC7SET32 Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 © ns/V Nexperia B.V. 2022. All rights reserved 3 / 10 XC7SET32 Nexperia 2-input OR gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH VI = VIH or VIL; VCC = 4.5 V HIGH-level output voltage IO = -50 μA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.8 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V IO = 8.0 mA - - 0.36 - 0.44 - 0.55 V VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 μA IO = -8.0 mA VI = VIH or VIL; VCC = 4.5 V LOW-level output voltage IO = 50 μA VOL II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.0 - 10 - 40 μA ΔICC additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 1.5 10 - 10 - 10 pF 11. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V. For waveform see Fig. 5. For test circuit see Fig. 6. Symbol Parameter 25 °C CPD -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max CL = 15 pF - 3.3 6.9 1.0 8.0 1.0 9.0 ns CL = 50 pF - 4.8 7.9 1.0 9.0 1.0 10 ns - 17 - - - - - pF propagation A and B to Y; VCC = 4.5 V to 5.5 V delay tpd [1] [2] [3] Conditions power per buffer; CL = 50 pF; dissipation f = 1 MHz; capacitance VI = GND to VCC [1] [2] [3] tpd is the same as tPLH and tPHL. Typical values are measured at VCC = 5.0 V. CPD is used to determine the dynamic power dissipation PD (μW). 2 2 PD = CPD × VCC × fi + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V. XC7SET32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 4 / 10 XC7SET32 Nexperia 2-input OR gate 11.1. Waveform and test circuit VM A, B input tPHL tPLH VM Y output mna167 Measurement points are given in Table 9. Fig. 5. The input (A and B) to output (Y) propagation delays Table 9. Measurement points Input Output VI VM VM GND to 3.0 V 1.5 V 0.5 × VCC VCC PULSE GENERATOR VI DUT VO RT CL mna101 Test data is given in Table 10. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig. 6. Test circuit for measuring switching times Table 10. Test data Input Load VI tr, tf CL 3.0 V ≤ 3.0 ns 15 pF, 50 pF XC7SET32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 Test tPLH, tPHL © Nexperia B.V. 2022. All rights reserved 5 / 10 XC7SET32 Nexperia 2-input OR gate 12. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm D SOT353-1 E B A X c (5x) y HE v M A e1 5 4 pin 1 index A 1 2 A1 3 A3 θ Lp w M B bp (5x) e A2 detail X e 0 3 mm scale Dimensions (mm are the original dimensions) Unit mm max min A A1 A2 A3 1.1 0.8 0.1 0 1.0 0.8 0.15 bp c 0.30 0.25 0.15 0.08 D(1) E(1) 2.2 1.8 1.35 0.65 1.15 e e1 HE Lp v w y θ 1.3 2.4 1.8 0.46 0.26 0.3 0.1 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. Outline version SOT353-1 Fig. 7. References IEC JEDEC JEITA MO-203 SC-88A sot353-1_po European projection Issue date 21-12-15 21-12-16 Package outline SOT353-1 (TSSOP5) XC7SET32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 6 / 10 XC7SET32 Nexperia 2-input OR gate Plastic surface-mounted package; 5 leads SOT753 D B E y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT753 Fig. 8. JEITA EUROPEAN PROJECTION ISSUE DATE 02-04-16 06-03-16 SC-74A Package outline SOT753 (SC-74A) XC7SET32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 7 / 10 XC7SET32 Nexperia 2-input OR gate 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes XC7SET32 v.2 20220113 Product data sheet - Modifications: • • • • XC7SET32 v.1 XC7SET32 Product data sheet XC7SET32 v.1 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 8: Derating values for Ptot total power dissipation updated. Fig. 7: Package outline drawing SOT353-1 (TSSOP5) has changed. 20090903 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 - © Nexperia B.V. 2022. All rights reserved 8 / 10 XC7SET32 Nexperia 2-input OR gate 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 9 / 10 XC7SET32 Nexperia 2-input OR gate Contents 1. General description...................................................... 1 2. Features.........................................................................1 3. Ordering information....................................................1 4. Marking.......................................................................... 1 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 2 7. Functional description................................................. 2 8. Limiting values............................................................. 3 9. Recommended operating conditions..........................3 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................4 11.1. Waveform and test circuit.......................................... 5 12. Package outline.......................................................... 6 13. Abbreviations.............................................................. 8 14. Revision history..........................................................8 15. Legal information........................................................9 © Nexperia B.V. 2022. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 13 January 2022 XC7SET32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 January 2022 © Nexperia B.V. 2022. All rights reserved 10 / 10