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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT367
Hex buffer/line driver; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state
74HC/HCT367
The 74HC/HCT367 are hex non-inverting buffer/line
drivers with 3-state outputs. The 3-state outputs (nY) are
controlled by the output enable inputs (1OE, 2OE).
FEATURES
• Non-inverting outputs
• Output capability: bus driver
• ICC category: MSI
A HIGH on nOE causes the outputs to assume a high
impedance OFF-state.
GENERAL DESCRIPTION
The “367” is identical to the “368” but has non-inverting
outputs.
The 74HC/HCT367 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
tPHL/ tPLH
propagation delay nA to nY
CI
input capacitance
CPD
power dissipation capacitance per buffer
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
HCT
8
11
ns
3.5
3.5
pF
30
32
pF
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state
74HC/HCT367
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 15
1OE, 2OE
output enable inputs (active LOW)
2, 4, 6, 10, 12, 14
1A to 6A
data inputs
3, 5, 7, 9, 11, 13
1Y to 6Y
data outputs
8
GND
ground (0 V)
16
VCC
positive supply voltage
Fig.1 Pin configuration.
December 1990
Fig.2 Logic symbol.
3
Fig.3 IEC logic symbol.
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state
74HC/HCT367
FUNCTION TABLE
INPUTS
OUTPUTS
nOE
nA
nY
L
L
H
L
H
X
L
H
Z
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state
74HC/HCT367
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
UNIT V
WAVEFORMS
CC
(V)
max.
tPHL/ tPLH
propagation delay
nA to nY
28
10
8
95
19
16
120
24
20
145
29
25
ns
2.0
4.5
6.0
Fig.6
tPZH/ tPZL
3-state output enable time
nOE to nY
44
16
13
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.7
tPHZ/ tPLZ
3-state output disable time
nOE to nY
55
20
16
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.7
tTHL/ tTLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
December 1990
5
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state
74HC/HCT367
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
1OE
2OE
nA
1.00
0.90
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
UNIT V
WAVEFORMS
CC
(V)
max.
tPHL/ tPLH
propagation delay
nA to nY
14
25
31
38
ns
4.5
Fig.6
tPZH/ tPZL
3-state output enable time
nOE to nY
16
35
44
53
ns
4.5
Fig.7
tPHZ/ tPLZ
3-state output disable time
nOE to nY
21
35
44
53
ns
4.5
Fig.7
tTHL/ tTLH
output transition time
5
12
15
18
ns
4.5
Fig.6
December 1990
6
Philips Semiconductors
Product specification
Hex buffer/line driver; 3-state
74HC/HCT367
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
7
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