74LVT16240ADL,112

74LVT16240A 3.3 V 16-bit inverting buffer/driver; 3-state Rev. 4 — 1 October 2018 Product data sheet 1. General description The 74LVT16240A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an inverting 16-bit buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling four of the 3-state outputs. 2. Features and benefits • • • • • • • • • • • 16-bit bus interface 3-state buffers Output capability: +64 mA/–32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: • JESD78B Class II exceeds 500 mA ESD protection: • HBM: JESD22-A114F exceeds 2000 V • MM: JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package 74LVT16240ADGG Temperature range Name Description Version -40 °C to +85 °C plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 TSSOP48 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 4. Functional diagram 47 46 44 43 1 1A0 1Y0 1A1 1Y1 1A2 1Y2 1A3 1Y3 2 41 3 40 5 38 6 1OE 37 48 2A0 2Y0 2A1 2Y1 2A2 2Y2 2A3 2Y3 8 9 11 1OE 2OE 25 3OE 24 4OE 12 2OE 1A0 1A1 1A2 36 35 3A0 3A1 3Y0 3Y1 13 14 30 29 4A0 4A1 4Y0 4Y1 1A3 19 2A0 2A1 2A2 20 2A3 33 3A2 3Y2 16 27 4A2 4Y2 3A0 22 3A1 3A2 32 3A3 3Y3 17 26 4A3 4Y3 3A3 23 4A0 4A1 25 Fig. 1. 3OE Logic symbol 74LVT16240A Product data sheet 24 1 48 4A2 4OE 4A3 aaa-029128 Fig. 2. EN1 EN2 EN3 EN4 47 46 1 2 1 3 44 5 43 6 41 40 1 8 2 9 38 11 37 12 36 35 1 3 13 14 33 16 32 17 30 29 1 4 19 20 27 22 26 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 2 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 5. Pinning information 5.1. Pinning 74LVT16240A 1OE 1 48 2OE 1Y0 2 47 1A0 1Y1 3 46 1A1 GND 4 45 GND 1Y2 5 44 1A2 1Y3 6 43 1A3 VCC 7 42 VCC 2Y0 8 41 2A0 2Y1 9 40 2A1 GND 10 39 GND 2Y2 11 38 2A2 2Y3 12 37 2A3 3Y0 13 36 3A0 3Y1 14 35 3A1 GND 15 34 GND 3Y2 16 33 3A2 3Y3 17 32 3A3 VCC 18 31 VCC 4Y0 19 30 4A0 4Y1 20 29 4A1 GND 21 28 GND 4Y2 22 27 4A2 4Y3 23 26 4A3 4OE 24 25 3OE aaa-029130 Fig. 3. Pin configuration SOT362-1 (TSSOP48) 74LVT16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 3 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE, 3OE, 4OE 1, 48, 25, 24 output enable inputs (active LOW) 1A0, 1A1, 1A2, 1A3 47, 46, 44, 43 data inputs 2A0, 2A1, 2A2, 2A3 41, 40, 38, 37 data inputs 3A0, 3A1, 3A2, 3A3 36, 35, 33, 32 data inputs 4A0, 4A1, 4A2, 4A3 30, 29, 27, 26 data inputs 1Y0, 1Y1, 1Y2, 1Y3 2, 3, 5, 6 data outputs 2Y0, 2Y1, 2Y2, 2Y3 8, 9, 11, 12 data outputs 3Y0, 3Y1, 3Y2, 3Y3 13, 14, 16, 17 data outputs 4Y0, 4Y1, 4Y2, 4Y3 19, 20, 22, 23 data outputs GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Output Input nOE nAn nYn L L H L H L H X Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current VI < 0 V IOK output clamping current VO < 0 V IO output current Tstg storage temperature Tj junction temperature [1] [2] Conditions Min Max Unit -0.5 +4.6 V [1] -0.5 +7.0 V [1] -0.5 +7.0 V -50 - mA -50 - mA output in LOW-state - 128 mA output in HIGH-state -64 - mA -65 +150 °C - +150 °C [2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 74LVT16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 4 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate outputs enabled in free air Min Typ Max Unit 2.7 - 3.6 V 0 - 5.5 V -40 - +85 °C - - 10 ns/V Min Typ[1] Max Unit 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VIK input clamping voltage VCC = 2.7 V; IIK = -18 mA - -0.85 -1.2 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = -100 μA VCC - 0.2 VCC - V VCC = 2.7 V; IOH = -8 mA 2.4 2.5 - V VCC = 3.0 V; IOH = -32 mA VOL 2.0 2.3 - V LOW-level output voltage VCC = 2.7 V; IOL = 100 μA - 0.07 0.2 V VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 64 mA - 0.4 0.55 V IOH HIGH-level output current - - -32 mA IOL LOW-level output current - - 32 mA - - 64 mA - 0.4 10 μA - ±0.1 ±1 μA 1 μA current duty cycle ≤ 50%; f ≥ 1kHz II input leakage current all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND data pins VCC = 3.6 V; VI = VCC [2] - 0.1 VCC = 3.6 V; VI = 0 V [2] - -0.4 -5 μA - 0.1 ±100 μA IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V IBHL bus hold LOW current nAn input; VCC = 3 V; VI = 0.8 V 75 135 - μA IBHH bus hold HIGH current nAn input; VCC = 3 V; VI = 2.0 V -75 -135 - μA IBHLO bus hold LOW overdrive current nAn input; VCC = 3.6 V; VI = 0 V to 3.6 V [3] 500 - - μA IBHHO bus hold HIGH overdrive current nAn input; VCC = 3.6 V; VI = 0 V to 3.6 V [3] - - -500 μA ICEX output high leakage current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V - 50 125 μA IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care - 1 ±100 μA 74LVT16240A Product data sheet [4] All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 5 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state Symbol Parameter Conditions IOZ OFF-state output current VCC = 3.6 V; VI = VIL or VIH ICC supply current Min Typ[1] Max Unit output HIGH: VO = 3.0 V - 0.5 5 μA output LOW: VO = 0.5 V - 0.5 -5 μA outputs HIGH - 0.07 0.12 mA outputs LOW - 4.0 6 mA [5] - 0.07 0.12 mA [6] - 0.1 0.2 mA VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs disabled ΔICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC - 0.6 V and other inputs at VCC or GND CI input capacitance nOE; VI = 0 V or 3 V - 3 - pF CO output capacitance Outputs disabled; VO = 0 V or 3.0 V - 9 - pF [1] [2] [3] [4] [5] [6] All typical values are at VCC = 3.3 V and Tamb = 25 °C. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. Measured with outputs pulled up to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 6. Symbol Parameter Conditions Min tPLH LOW to HIGH propagation delay nAn to nYn; see Fig. 4 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tPHL HIGH to LOW propagation delay OFF-state to HIGH propagation delay VCC = 2.7 V VCC = 2.7 V OFF-state to LOW propagation delay nOE to nYn; see Fig. 5 HIGH to OFF-state propagation delay nOE to nYn; see Fig. 5 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tPHZ VCC = 2.7 V VCC = 3.3 V ± 0.3 V tPLZ LOW to OFF-state propagation delay - - 4.0 ns 0.5 1.8 3.2 ns - - 4.0 ns 0.5 2.0 3.2 ns - - 5.0 ns 1.0 2.3 4.0 ns - - 4.8 ns 1.0 2.1 4.4 ns - - 5.0 ns 1.0 3.2 4.5 ns - - 4.8 ns 1.0 3.0 4.4 ns nOE to nYn; see Fig. 5 VCC = 2.7 V VCC = 3.3 V ± 0.3 V [1] Unit nOE to nYn; see Fig. 5 VCC = 3.3 V ± 0.3 V tPZL Max nAn to nYn; see Fig. 4 VCC = 3.3 V ± 0.3 V tPZH Typ[1] Typical values are at VCC = 3.3 V and Tamb = 25 °C. 74LVT16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 6 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 10.1. Waveforms and test circuit VI nAn input VM VM GND tPHL tPLH VOH VM nYn output VM VOL aaa-029131 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 4. Input (nAn) to output (nYn) propagation delay VI VM nOE input GND tPLZ tPZL 3.0 V nYn output VM VX VOL tPHZ VOH tPZH VY nYn output VM GND aaa-028621 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 5. Enable and disable times of 3-state outputs Table 8. Measurement points Input Output VCC VM VM VX VY 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LVT16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 7 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state VI negative pulse tW 90 % 90 % VM 10 % 0V tf tr tr tf VI positive pulse 0V VM VEXT VCC G 90 % VM VI VM 10 % DUT RT 10 % tW RL VO CL RL mna616 001aac221 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig. 6. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6V open 74LVT16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 8 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 11. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 Fig. 7. References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Package outline TSSOP48 (SOT362-1) 74LVT16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 9 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge MIL Military MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT16240A v.4 20181001 Product data sheet - 74LVT16240A v.3 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVT16240ADL (SOT370-1) removed. 74LVT16240A v.3 20030221 Modifications: • • 74LVT16240A v.2 19980219 Product specification - 74LVT16240A v.1 74LVT16240A v.1 19941215 Product specification - - 74LVT16240A Product data sheet Product data sheet - 74LVT16240A v.2 Table 1 corrected: removed ‘North America’ column. Fig. 2 modified to correct pin names All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 10 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVT16240A Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 11 / 12 74LVT16240A Nexperia 3.3 V 16-bit inverting buffer/driver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 7 11. Package outline.......................................................... 9 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 1 October 2018 74LVT16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 12 / 12