74LVC16240ADL,118

74LVC16240A 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state Rev. 5 — 25 April 2019 Product data sheet 1. General description The 74LVC16240A is a 16-bit inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package 74LVC16240ADGG Temperature range Name Description Version -40 °C to +125 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 4. Functional diagram 1A0 1A1 1A2 1A3 1OE 2A0 2A1 2A2 2A3 2OE Fig. 1. 47 2 46 3 44 5 43 6 1Y0 3A0 1Y1 3A1 1Y2 3A2 1Y3 3A3 1 3OE 41 8 40 9 38 11 37 12 2Y0 4A0 2Y1 4A1 2Y2 4A2 2Y3 4A3 48 4OE 36 13 35 14 33 16 32 17 3Y0 3Y1 3Y2 3Y3 25 30 19 29 20 27 22 26 23 4Y0 4Y1 4Y2 4Y3 24 001aaa439 Logic symbol 1OE 2OE 3OE 4OE 1A0 1A1 1A2 1A3 2A0 2A1 2A2 2A3 3A0 3A1 3A2 3A3 4A0 4A1 4A2 4A3 1 48 25 24 47 46 1EN 2EN 3EN 4EN 1 1 2 3 44 5 43 6 41 8 40 1 2 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 29 1 4 19 20 27 22 26 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 001aaa442 Fig. 2. IEC logic symbol 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 2 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 5. Pinning information 5.1. Pinning 74LVC16240A 1OE 1 48 2OE 1Y0 2 47 1A0 1Y1 3 46 1A1 GND 4 45 GND 1Y2 5 44 1A2 1Y3 6 43 1A3 VCC 7 42 VCC 2Y0 8 41 2A0 2Y1 9 40 2A1 GND 10 39 GND 2Y2 11 38 2A2 2Y3 12 37 2A3 3Y0 13 36 3A0 3Y1 14 35 3A1 GND 15 34 GND 3Y2 16 33 3A2 3Y3 17 32 3A3 VCC 18 31 VCC 4Y0 19 30 4A0 4Y1 20 29 4A1 GND 21 28 GND 4Y2 22 27 4A2 4Y3 23 26 4A3 4OE 24 25 3OE 001aaa440 Fig. 3. Pin configuration SOT362-1 (TSSOP48) 5.2. Pin description Table 2. Pin description Name Pin Description 1OE, 2OE, 3OE, 4OE 1, 48, 25, 24 output enable input (active LOW) GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 supply voltage 1Y0, 1Y1, 1Y2, 1Y3 2, 3, 5, 6 data output 2Y0, 2Y1, 2Y2, 2Y3 8, 9, 11, 12 data output 3Y0, 3Y1, 3Y2, 3Y3 13, 14, 16, 17 data output 4Y0, 4Y1, 4Y2, 4Y3 19, 20, 22, 23 data output 1A0, 1A1, 1A2, 1A3 47, 46, 44, 43 data input 2A0, 2A1, 2A2, 2A3 41, 40, 38, 37 data input 3A0, 3A1, 3A2, 3A3 36, 35, 33, 32 data input 4A0, 4A1, 4A2, 4A3 30, 29, 27, 26 data input 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 3 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state Output Input nOE nAn nYn L L H L H L H X Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage output HIGH or LOW state [2] -0.5 output 3-state [2] -0.5 +6.5 V IO output current - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V -40 - +125 °C [1] [2] [3] VI < 0 V [1] VO = 0 V to VCC Tamb = -40 °C to +125 °C [3] mA VCC + 0.5 V The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions supply voltage functional VI input voltage VO output voltage Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 3.6 V - - 10 ns/V 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 4 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage VOH VOL Conditions -40 °C to +85 °C VCC = 1.2 V VCC = 1.65 V to 1.95 V Unit Min Typ [1] Max Min Max 1.08 - - 1.08 - V 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC - 0.2 - - VCC - 0.3 - V IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V HIGH-level output VI = VIH or VIL voltage IO = -100 μA; VCC = 1.65 V to 3.6 V LOW-level output voltage -40 °C to +125 °C 0.35VCC V VI = VIH or VIL II input leakage current VCC = 3.6 V; VI = 5.5 V or GND - ±0.1 ±5 - ±20 μA IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND - 0.1 ±5 - ±20 μA IOFF power-off leakage VCC = 0 V; VI or VO = 5.5 V current - 0.1 ±10 - ±20 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 20 - 80 μA ΔICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 500 - 5000 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 5 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 6. Symbol Parameter tpd propagation delay Conditions -40 °C to +85 °C nAn to nYn; see Fig. 4 enable time 12.0 - - - ns 5.1 11.0 1.0 11.7 ns VCC = 2.3 V to 2.7 V 0.5 2.7 5.5 0.5 6.1 ns VCC = 2.7 V 1.0 2.7 5.2 1.0 6.5 ns VCC = 3.0 V to 3.6 V 1.0 2.3 4.2 1.0 5.5 ns - 18.0 - - - ns VCC = 1.65 V to 1.95 V 1.5 6.6 12.8 1.5 13.5 ns VCC = 2.3 V to 2.7 V 1.0 3.8 6.8 1.0 7.5 ns VCC = 2.7 V 1.5 3.5 5.8 1.5 7.5 ns 1.0 3.0 5.0 1.0 6.5 ns - 11.0 - - - ns VCC = 1.65 V to 1.95 V 2.9 4.7 9.2 2.9 9.7 ns VCC = 2.3 V to 2.7 V 1.0 2.6 5.0 1.0 5.6 ns VCC = 2.7 V 1.5 3.5 5.1 1.5 6.5 ns VCC = 3.0 V to 3.6 V 1.5 3.2 4.9 1.5 6.5 ns - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 4.8 - - - pF VCC = 2.3 V to 2.7 V - 8.3 - - - pF VCC = 3.0 V to 3.6 V - 11.4 - - - pF nOE to nYn; see Fig. 5 [2] nOE to nYn; see Fig. 5 [2] tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per input; VI = GND to VCC [4] [3] [4] Max - VCC = 1.2 V [1] [2] Min 1.0 VCC = 3.0 V to 3.6 V disable time Max VCC = 1.65 V to 1.95 V VCC = 1.2 V tdis Typ [1] [2] VCC = 1.2 V ten Min -40 °C to +125 °C Unit Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching 2 Σ(CL × VCC × fo) = sum of the outputs 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 6 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 10.1. Waveforms and test circuit VI nAn input VM VM GND tPHL VOH tPLH 90 % 90 % VM nYn output VM 10 % VOL 10 % tTHL tTLH mgu781 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. The input nAn to output nYn propagation delays VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled mna362 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. 3-state enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.2 V 0.5 × VCC 0.5 × VCC VOL + 0.1 V VOH - 0.1 V 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC VOL + 0.1 V VOH - 0.1 V 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.1 V VOH - 0.1 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 7 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 8 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 11. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 Fig. 7. References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Package outline SOT362-1 (TSSOP48) 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 9 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC16240A v.5 20190425 Product data sheet - Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVC16240ADL (SOT370-1) removed. Package outline drawing SOT362-1 (TSSOP48) updated. Typo corrected in Section 5.2. 74LVC16240A v.4 20111103 Modifications: • • • 74LVC16240A v.4 Product data sheet - 74LVC16240A v.3 The format of this document has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges. 74LVC16240A v.3 20040305 Product specification - 74LVC16240A v.2 74LVC16240A v.2 19970729 Product specification - 74LVC16240A v.1 74LVC16240A v.1 19951226 Product specification - - 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 10 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVC16240A Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 11 / 12 74LVC16240A Nexperia 16-bit buffer/line driver with 5V tolerant inputs/outputs; inverting; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................4 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 7 11. Package outline.......................................................... 9 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 April 2019 74LVC16240A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 25 April 2019 © Nexperia B.V. 2019. All rights reserved 12 / 12