74LVCH16541ADGG,51

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74LVCH16541A 16-bit buffer/line driver; 3-state Rev. 3 — 15 February 2012 Product data sheet 1. General description The 74LVCH16541A is a 16-bit buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs (1OEn and 2OEn). A HIGH on nOEn causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits            5 Volt tolerant inputs and outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels High-impedance outputs when VCC = 0 V All data inputs have bus hold Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V)  JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C. 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVCH16541ADGG 40 to +125 C TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm 74LVCH16541ADL 40 to +125 C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 4. Functional diagram 1OE1 1OE2 1 48 2OE1 24 25 2OE2 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 & 1A0 47 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 & 47 1A1 1 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 2 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Y0 1A2 1Y1 2A0 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 1Y5 2A5 1Y6 2A6 1Y7 2A7 36 13 35 14 33 16 32 17 30 19 29 20 27 22 26 23 2Y0 2Y1 2Y2 1Y2 1A3 1Y3 2Y3 1Y4 1Y5 1A4 2Y4 1Y6 1Y7 1A5 2Y5 2Y0 2Y1 1A6 2Y6 2Y2 2Y3 1A7 2Y4 2Y7 2Y5 2Y6 1OE1 2Y7 1OE2 1 48 2OE1 24 25 2OE2 mna056 mna057 Fig 1. 1Y0 EN IEC logic symbol Fig 2. Logic diagram VCC data input to internal circuit mna004 Fig 3. Bus hold circuit 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 2 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 1OE1 1 48 1OE2 1Y0 2 47 1A0 1Y1 3 46 1A1 GND 4 45 GND 1Y2 5 44 1A2 1Y3 6 43 1A3 VCC 7 42 VCC 1Y4 8 41 1A4 1Y5 9 40 1A5 GND 10 39 GND 1Y6 11 38 1A6 1Y7 12 2Y0 13 16541 37 1A7 36 2A0 2Y1 14 35 2A1 GND 15 34 GND 2Y2 16 33 2A2 2Y3 17 32 2A3 VCC 18 31 VCC 2Y4 19 30 2A4 2Y5 20 29 2A5 GND 21 28 GND 2Y6 22 27 2A6 2Y7 23 26 2A7 2OE1 24 25 2OE2 mna055 Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Name Pin Description 1OE1 1 output enable input (active LOW) 1OE2 48 output enable input (active LOW) 2OE1 24 output enable input (active LOW) 2OE2 25 output enable input (active LOW) GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V) VCC 7, 18, 31, 42 positive supply voltage 1Y[0:7] 2, 3, 5, 6, 8, 9, 11, 12 data output 2Y[0:7] 13, 14, 16, 17, 19, 20, 22, 23 data output 1A[0:7] 47, 46, 44, 43, 41, 40, 38, 37 data input 2A[0:7] 36, 35, 33, 32, 30, 29, 27, 26 data input 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 3 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 6. Functional description Table 3. Function table[1] Input Output nOE1 nOE2 nAn nYn L L L L L L H H X H X Z H X X Z [1] H = HIGH voltage level L = LOW voltage level X = don’t care Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage IIK input clamping current VI < 0 IOK output clamping current VO > VCC or VO < 0 output voltage VO [1] Min Max Unit 0.5 +6.5 V 0.5 +6.5 V 50 - mA mA - 50 output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA 100 mA IO output current VO = 0 V to VCC ICC supply current - IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K. 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 4 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 8. Recommended operating conditions Table 5. Recommended operating operations Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Max Unit 1.65 3.6 V functional 1.2 - V 0 5.5 V output HIGH or LOW state 0 VCC V output 3-state or VCC = 0 V 0 5.5 V Tamb ambient temperature in free air 40 +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 3.6 V 0 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input VCC = 1.2 V voltage VCC = 1.65 V to 1.95 V HIGH-level output voltage LOW-level output voltage input leakage current 74LVCH16541A Product data sheet 40 C to +125 C Max Min Unit Max - - 1.08 - V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - - 0.12 - 0.12 V - - 0.35  VCC - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = 100 A; VCC = 1.65 V to 3.6 V VCC  0.2 VCC - VCC  0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V LOW-level input VCC = 1.2 V voltage VCC = 1.65 V to 1.95 V 1.08 Typ[1] VI = VIH or VIL IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A VCC = 3.6 V; VI = 5.5 V or GND[2] All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 5 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min Typ[1] 40 C to +125 C Max Min Unit Max IOZ OFF-state VI = VIH or VIL; VCC = 3.6 V; output current[2] VO = 5.5 V or GND - ±0.1 5 - 20 A IOFF power-off leakage supply VCC = 0 V; VI or VO = 5.5 V - ±0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 20 - 80 A ICC additional supply current per input pin; VCC = 1.65 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF IBHL bus hold LOW current [3][4] VCC = 1.65; VI = 0.58 V 10 - - 10 - A VCC = 2.3; VI = 0.7 V 30 - - 25 - A IBHH IBHLO IBHHO [1] bus hold HIGH current [3][4] bus hold LOW overdrive current [3][5] bus hold HIGH overdrive current [3][5] VCC = 3.0; VI = 0.8 V 75 - - 60 - A VCC = 1.65; VI = 1.07 V 10 - - 10 - A VCC = 2.3; VI = 1.7 V 30 - - 25 - A VCC = 3.0; VI = 2.0 V 75 - - 60 - A VCC = 1.95 V 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A VCC = 1.95 V 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. [3] For data inputs only; control inputs do not have a bus hold circuit. [4] The specified sustaining current at the data inputs holds the input below the specified VI level. [5] The specified overdrive current at the data input forces the data input to the opposite logic input state. 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 6 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter propagation delay tpd enable time ten Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - 10 - - - ns VCC = 1.65 V to 1.95 V 1.8 4.7 10.4 1.8 12.0 ns VCC = 2.3 V to 2.7 V 1.5 2.6 5.2 1.5 6.0 ns nAn to nYn; see Figure 5 [2] VCC = 1.2 V VCC = 2.7 V 1.0 2.5 5.0 1.0 6.5 ns VCC = 3.0 V to 3.6 V 1.0 2.2 4.2 1.0 5.5 ns - 17 - - - ns nOEn to nYn; see Figure 6 [2] VCC = 1.2 V VCC = 1.65 V to 1.95 V 1.5 5.5 14.6 1.5 16.8 ns VCC = 2.3 V to 2.7 V 1.0 3.2 7.7 1.0 8.9 ns VCC = 2.7 V 1.5 3.4 6.9 1.5 9.0 ns 1.0 2.6 5.6 1.0 7.0 ns - 9.0 - - - ns 2.6 7.3 9.2 2.6 10.6 ns VCC = 2.3 V to 2.7 V 1.0 4.1 5.2 1.0 6.0 ns VCC = 2.7 V 1.5 4.6 6.5 1.5 8.5 ns VCC = 3.0 V to 3.6 V 1.5 4.5 5.5 1.5 7.0 ns - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 8.5 - - - pF VCC = 2.3 V to 2.7 V - 12.1 - - - pF VCC = 3.0 V to 3.6 V - 15.3 - - - pF VCC = 3.0 V to 3.6 V disable time tdis nOEn to nYn; see Figure 6 [2] VCC = 1.2 V VCC = 1.65 V to 1.95 V tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per input; VI = GND to VCC [4] [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 7 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 11. Waveforms VI nAn input VM VM GND tPLH tPHL VOH VM nYn output VM VOL mna171 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Input nAn to output nYn propagation delays VI nOEn input VM GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPZL VM VX tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND tPZH VY VM outputs enabled outputs enabled outputs disabled col015 Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 8. 3-state enable and disable times Measurement points Supply voltage VM VCC Input VI VX VY 0.5  VCC VCC VOL + 0.15 V VOH  0.15 V 1.65 V to 1.95 V 0.5  VCC VCC VOL + 0.15 V VOH  0.15 V 2.3 V to 2.7 V 0.5  VCC VCC VOL + 0.15 V VOH  0.15 V 2.7 V 1.5 V 2.7 V VOL + 0.3 V VOH  0.3 V 3.0 V to 3.6 V 1.5 V 2.7 V VOL + 0.3 V VOH  0.3 V 1.2 V 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 8 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Table 9. Test circuit for measuring switching times Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC  2 ns 30 pF 1 k open 2  VCC GND 1.65 V to 1.95 V VCC  2 ns 30 pF 1 k open 2  VCC GND 2.3 V to 2.7 V VCC  2 ns 30 pF 500  open 2  VCC GND 2.7 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 9 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 Fig 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Package outline SOT362-1 (TSSOP48) 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 10 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 Fig 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Package outline SOT370-1 (SSOP48) 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 11 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVCH16541A v.3 20120215 Product data sheet - 74LVCH16541A v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges. 74LVCH16541A v.2 20040218 Product specification - 74LVCH16541A v.1 74LVCH16541A v.1 19980519 Product specification - - 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 12 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVCH16541A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 13 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVCH16541A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 15 February 2012 © NXP B.V. 2012. All rights reserved. 14 of 15 74LVCH16541A NXP Semiconductors 16-bit buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 February 2012 Document identifier: 74LVCH16541A