74ALVC32PW,112

74ALVC32 Quad 2-input OR gate Rev. 5 — 30 April 2021 Product data sheet 1. General description The 74ALVC32 is a quad 2-input OR gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8B (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC32D -40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74ALVC32PW -40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74ALVC32BQ -40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 74ALVC32 Nexperia Quad 2-input OR gate 4. Functional diagram 1 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 4 1Y 3 5 2Y 6 9 3Y 8 4Y 11 10 12 3 ≥1 6 ≥1 8 ≥1 11 13 mna243 mna242 Fig. 1. ≥1 Logic symbol Fig. 2. IEC logic symbol A Y B Fig. 3. mna241 Logic diagram (one gate) 5. Pinning information 5.1. Pinning 12 4A 4 11 4Y 2B 5 2Y 6 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 8 3 2A 1B 2B 5 10 3B 2Y 6 9 GND 7 8 Product data sheet 10 3B 9 3A aaa-032404 (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND 3Y Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) 74ALVC32 GND(1) 13 4B Transparent top view 3A aaa-032403 Fig. 4. 1Y 7 14 VCC 2 3Y 1 1B GND 1A 1 74ALVC32 1A terminal 1 index area 14 VCC 74ALVC32 Fig. 5. Pin configuration SOT762-1 (DHVQFN14) All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 2 / 12 74ALVC32 Nexperia Quad 2-input OR gate 5.2. Pin description Table 2. Pin description Symbol Pin Description nA 1, 4, 9, 12 data input nB 2, 5, 10, 13 data input nY 3, 6, 8, 11 data output VCC 14 supply voltage GND 7 ground (0 V) 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input nA Input nB Output nY L L L L H H H L H H H H 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +4.6 V IIK input clamping current -50 - VI input voltage [1] -0.5 +4.6 V IOK output clamping current VO > VCC or VO < 0 V VO output voltage output HIGH or LOW state - ±50 mA [1] -0.5 VCC + 0.5 V output 3-state -0.5 +4.6 V power-down mode; VCC = 0 V -0.5 +4.6 V - ±50 mA VI < 0 V IO output current ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] VO = 0 V to VCC mA Tamb = -40 °C to +85 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 74ALVC32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 3 / 12 74ALVC32 Nexperia Quad 2-input OR gate 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 1.65 3.6 V VI input voltage 0 3.6 V VO output voltage output HIGH or LOW state 0 VCC V output 3-state 0 3.6 V power-down mode; VCC = 0 V 0 3.6 V -40 +85 °C Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 3.6 V 0 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage Conditions Tamb = -40 °C to +85 °C VCC = 1.65 V to 1.95 V Min Typ[1] Max 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC - 0.2 - - V IO = -6 mA; VCC = 1.65 V 1.25 1.51 - V IO = -12 mA; VCC = 2.3 V 1.8 2.10 - V IO = -18 mA; VCC = 2.3 V 1.7 2.01 - V IO = -12 mA; VCC = 2.7 V 2.2 2.53 - V IO = -18 mA; VCC = 3.0 V 2.4 2.76 - V IO = -24 mA; VCC = 3.0 V 2.2 2.68 - V 0.35 × VCC V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 3.6 V VOL Unit LOW-level output voltage VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 V IO = 6 mA; VCC = 1.65 V - 0.11 0.3 V IO = 12 mA; VCC = 2.3 V - 0.17 0.4 V IO = 18 mA; VCC = 2.3 V - 0.25 0.6 V IO = 12 mA; VCC = 2.7 V - 0.16 0.4 V IO = 18 mA; VCC = 3.0 V - 0.23 0.4 V IO = 24 mA; VCC = 3.0 V - 0.30 0.55 V VCC = 3.6 V; VI = 3.6 V or GND - ±0.1 ±5 μA II input leakage current IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 3.6 V - ±0.1 ±10 μA ICC supply current - 0.2 10 μA 74ALVC32 Product data sheet VCC = 3.6 V; VI = VCC or GND; IO = 0 A All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 4 / 12 74ALVC32 Nexperia Quad 2-input OR gate Symbol Parameter Conditions ΔICC additional supply current CI input capacitance [1] Tamb = -40 °C to +85 °C Unit Min Typ[1] Max - 5 750 μA - 3.5 - pF per input pin; VCC = 3.0 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7. Symbol tpd Conditions propagation delay CPD [1] [2] [3] Parameter power dissipation capacitance Tamb = -40 °C to +85 °C Unit Min Typ[1] Max VCC = 1.65 V to 1.95 V 1.0 2.8 4.7 ns VCC = 2.3 V to 2.7 V 1.0 2.0 3.1 ns VCC = 2.7 V 1.0 2.2 2.9 ns VCC = 3.0 V to 3.6 V 1.0 2.0 2.8 ns - 25 - pF nA, nB to nY; see Fig. 6 [2] per gate; VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 °C tpd is the same as tPHL and tPLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching 2 Σ(CL x VCC x fo) = sum of the outputs 10.1. Waveforms and test circuit VI VM nA, nB input GND t PHL nY output t PLH VM mna244 Measurement points are given in Table 8. Fig. 6. Inputs nA, nB to output nY propagation delay times Table 8. Measurement points Supply voltage VCC Input VI VM 1.65 V to 1.95 V VCC 0.5VCC 2.3 V to 2.7 V VCC 0.5VCC 2.7 V 2.7 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 74ALVC32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 5 / 12 74ALVC32 Nexperia Quad 2-input OR gate VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 7. Test circuit for measuring switching times Table 9. Test data Supply voltage VCC Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2 x VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 x VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 74ALVC32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 6 / 12 74ALVC32 Nexperia Quad 2-input OR gate 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 8. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74ALVC32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 7 / 12 74ALVC32 Nexperia Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 Fig. 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Package outline SOT402-1 (TSSOP14) 74ALVC32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 8 / 12 74ALVC32 Nexperia Quad 2-input OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 10. Package outline SOT762-1 (DHVQFN14) 74ALVC32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 9 / 12 74ALVC32 Nexperia Quad 2-input OR gate 12. Abbreviations Table 10. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC32 v.5 20210340 Product data sheet - 74ALVC32 v.4 Modifications: • • 74ALVC32 v.4 20200928 Modifications: • • • • • 74ALVC32 v.3 Section 2: Reference to JESD36 removed. Table 4: Derating values for Ptot total power dissipation updated (errata). • - Product data sheet - 20071210 Product data sheet 74ALVC32 v.1 20021115 Product specification - Product data sheet 74ALVC32 v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 74ALVC32 v.2 74ALVC32 74ALVC32 v.3 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 2 updated. Table 4: Derating values for Ptot total power dissipation have been updated. Package outline drawing of SOT762-1 (Fig. 10) updated. 20140120 • Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 74ALVC32 v.1 - © Nexperia B.V. 2021. All rights reserved 10 / 12 74ALVC32 Nexperia Quad 2-input OR gate 14. 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 11 / 12 74ALVC32 Nexperia Quad 2-input OR gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 3 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................4 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms and test circuit........................................ 5 11. Package outline.......................................................... 7 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 April 2021 74ALVC32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 12 / 12