74LVC2G02GD,125

74LVC2G02 Dual 2-input NOR gate Rev. 14 — 21 July 2021 Product data sheet 1. General description The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • • Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic Overvoltage tolerant inputs to 5.5 V High noise immunity ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C 74LVC2G02 Nexperia Dual 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G02DP -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G02DC -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74LVC2G02GT -40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm 74LVC2G02GF -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm SOT1089 74LVC2G02GN -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm SOT1116 74LVC2G02GS -40 °C to +125 °C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT1203 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC2G02DP V02 74LVC2G02DC V02 74LVC2G02GT V02 74LVC2G02GF VB 74LVC2G02GN VB 74LVC2G02GS VB [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1A 1Y 1B 2A 1 2Y 2B 001aah780 Fig. 1. Logic symbol 74LVC2G02 Product data sheet 001aah781 Fig. 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 B Y A Fig. 3. mna105 Logic diagram (one gate) © Nexperia B.V. 2021. All rights reserved 2 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate 6. Pinning information 6.1. Pinning 74LVC2G02 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 74LVC2G02 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aab643 Transparent top view 001aab642 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig. 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 (XSON8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Output Input nA nB nY L L H X H L H X L 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 3 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Max Unit -0.5 +6.5 V [1] -0.5 +6.5 V Active mode [1] -0.5 VCC + 0.5 V Power-down mode; VCC = 0 V [1] -0.5 +6.5 V -50 - mA IIK input clamping current VI < 0 V IOK output clamping current VO < 0 V or VO > VCC - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 250 mW [1] [2] Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT505-2 (TSSOP8) package: Ptot derates linearly with 4.6 mW/K above 96 °C. For SOT765-1 (VSSOP8) package: Ptot derates linearly with 4.9 mW/K above 99 °C. For SOT833-1 (XSON8) package: Ptot derates linearly with 3.1 mW/K above 68 °C. For SOT1089 (XSON8) package: Ptot derates linearly with 4.0 mW/K above 88 °C. For SOT1116 (XSON8) package: Ptot derates linearly with 4.2 mW/K above 90 °C. For SOT1203 (XSON8) package: Ptot derates linearly with 3.6 mW/K above 81 °C. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate Conditions Active mode Power-down mode; VCC = 0 V 74LVC2G02 Product data sheet Min Max Unit 1.65 5.5 V 0 5.5 V 0 VCC V 0 5.5 V -40 +125 °C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 4 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - VCC = 2.7 V to 3.6 V - VCC = 4.5 V to 5.5 V - Tamb = -40 °C to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 1.65 V to 1.95 V 0.7 V - 0.8 V - 0.3 × VCC V VCC - 0.1 - - V IO = -4 mA; VCC = 1.65 V 1.2 1.53 - V IO = -8 mA; VCC = 2.3 V 1.9 2.13 - V IO = -12 mA; VCC = 2.7 V 2.2 2.50 - V IO = -24 mA; VCC = 3.0 V 2.3 2.60 - V IO = -32 mA; VCC = 4.5 V 3.8 4.10 - V VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V VOL LOW-level output voltage 0.35 × VCC V VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - ±0.1 ±1 μA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±2 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 μA ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 μA CI input capacitance - 2.5 - pF 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 5 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate Symbol Parameter Conditions Min Typ[1] Max Unit 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - VCC = 2.7 V to 3.6 V - VCC = 4.5 V to 5.5 V - Tamb = -40 °C to +125 °C VIH HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage VCC = 1.65 V to 1.95 V 0.7 V - 0.8 V - 0.3 × VCC V VCC - 0.1 - - V IO = -4 mA; VCC = 1.65 V 0.95 - - V IO = -8 mA; VCC = 2.3 V 1.7 - - V IO = -12 mA; VCC = 2.7 V 1.9 - - V IO = -24 mA; VCC = 3.0 V 2.0 - - V IO = -32 mA; VCC = 4.5 V 3.4 - - V IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 5.5 V VOL LOW-level output voltage 0.35 × VCC V VI = VIH or VIL - - 0.80 V II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - ±1 μA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±2 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 4 μA ΔICC additional supply current per pin; VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 500 μA [1] All typical values are measured at Tamb = 25 °C. 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 6 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Fig. 7. Symbol Parameter tpd propagation delay CPD [1] [2] [3] Conditions power dissipation capacitance -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.65 V to 1.95 V 1.2 3.8 8.9 1.2 11.2 ns VCC = 2.3 V to 2.7 V 0.8 2.4 5.4 0.8 6.8 ns VCC = 2.7 V 0.8 3.2 6.0 0.8 7.5 ns VCC = 3.0 V to 3.6 V 0.6 2.4 4.9 0.6 6.2 ns VCC = 4.5 V to 5.5 V 0.6 1.8 4.3 0.6 5.5 ns - 14 - - - pF nA, nB to nY; see Fig. 6 [2] per gate; VI = GND to VCC [3] Typical values are measured at nominal VCC and at Tamb = 25 °C. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of outputs. 11.1. Waveforms and test circuit VI VM nA, nB input GND t PHL t PLH VOH nY output VM 001aae972 VOL Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Input (nA, nB) to output (nY) propagation delays Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 x VCC 0.5 x VCC 2.3 V to 2.7 V 0.5 x VCC 0.5 x VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 x VCC 0.5 x VCC 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 7 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 10. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig. 7. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VEXT Load VCC VI tr, tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 8 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 pin 1 index (A3) A1 θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig. 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 9 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v w y 0.2 0.08 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 Fig. 9. References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Package outline SOT765-1 (VSSOP8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 10 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig. 10. Package outline SOT833-1 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 11 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 x 0.5 mm SOT1089 E terminal 1 index area D A A1 detail X (4×)(2) e L (8×)(2) b 4 5 e1 1 terminal 1 index area 8 L1 X 0 0.5 scale Dimensions Unit mm max nom min 1 mm A(1) 0.5 A1 b D E e e1 L L1 0.04 0.20 1.40 1.05 0.35 0.40 0.15 1.35 1.00 0.55 0.35 0.30 0.35 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1089 sot1089_po References IEC JEDEC JEITA European projection Issue date 10-04-09 10-04-12 MO-252 Fig. 11. Package outline SOT1089 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 12 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1.0 x 0.35 mm 1 2 SOT1116 b 4 3 (4×)(2) L L1 e 8 7 e1 6 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e max 0.35 0.04 0.20 1.25 1.05 nom 0.15 1.20 1.00 0.55 min 0.12 1.15 0.95 e1 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1116_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1116 Fig. 12. Package outline SOT1116 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 13 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203 b 1 2 3 (4×)(2) 4 L L1 e 8 7 6 e1 e1 5 e1 (8×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.40 1.05 0.35 0.40 nom 0.15 1.35 1.00 0.55 0.35 0.30 0.35 min 0.12 1.30 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1203_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1203 Fig. 13. Package outline SOT1203 (XSON8) 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 14 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G02 v.14 20210721 Product data sheet - Modifications: • • • 74LVC2G02 v.13 20180420 Modifications: • • • 74LVC2G02 v.13 Type number 74LVC2G02GM (SOT902-2/XQFN8) removed. Section 1 and Section 2 updated. Section 8: Derating values for Ptot total power dissipation updated. Product data sheet - 74LVC2G02 v.12 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVC2G02GD (SOT996-2) removed. 74LVC2G02 v.12 20161212 Modifications: • 74LVC2G02 v.11 20130408 Modifications: • 74LVC2G02 v.10 20120622 Modifications: • 74LVC2G02 v.9 20111130 Modifications: • 74LVC2G02 v.8 20101020 74LVC2G02 v.7 Product data sheet - 74LVC2G02 v.11 Table 7: The maximum limits for leakage current and supply current have changed. Product data sheet - 74LVC2G02 v.10 For type number 74LVC2G02GD XSON8U has changed to XSON8. Product data sheet - 74LVC2G02 v.9 For type number 74LVC2G02GM the SOT code has changed to SOT902-2. - 74LVC2G02 v.8 Product data sheet - 74LVC2G02 v.7 20080606 Product data sheet - 74LVC2G02 v.6 74LVC2G02 v.6 20080222 Product data sheet - 74LVC2G02 v.5 74LVC2G02 v.5 20070904 Product data sheet - 74LVC2G02 v.4 74LVC2G02 v.4 20060515 Product data sheet - 74LVC2G02 v.3 74LVC2G02 v.3 20050201 Product specification - 74LVC2G02 v.2 74LVC2G02 v.2 20040915 Product specification - 74LVC2G02 v.1 74LVC2G02 v.1 20031015 Product specification - - 74LVC2G02 Product data sheet Product data sheet Legal pages updated. All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 15 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate 15. Legal information injury, death or severe property or environmental damage. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 16 / 17 74LVC2G02 Nexperia Dual 2-input NOR gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................7 11.1. Waveforms and test circuit........................................ 7 12. Package outline.......................................................... 9 13. Abbreviations............................................................ 15 14. Revision history........................................................15 15. Legal information......................................................16 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 21 July 2021 74LVC2G02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 14 — 21 July 2021 © Nexperia B.V. 2021. All rights reserved 17 / 17